LDPC code encoding method and communication device

Abstract

The present application provides a method and communication device for encoding LDPC codes, which can meet the requirement of the IR-HARQ mechanism to increase the number of redundant bits through retransmission to reduce the channel coding rate, and can improve the decoding performance of LDPC codes. The method uses a check matrix of the LDPC code as a basic matrix and expands it to obtain a mother matrix that is compatible with multiple code rates. When performing LDPC encoding, the transmitting device reads the check matrix corresponding to the required code rate from the mother matrix, and performs LDPC encoding on the information bit sequence based on the read check matrix. By using check matrices of different sizes to perform LDPC encoding on the information bit sequence, different numbers of redundant bits can be obtained.

Description

Technical Field

[0001] The present application relates to the field of channel coding, and more specifically, to a method and communication device for encoding LDPC codes. Background Art

[0002] In the field of channel coding, low-density parity check (LDPC) codes are the most mature and widely used channel coding scheme. LDPC codes offer performance close to the Shannon limit and possess numerous advantages. Consequently, IEEE protocols such as 802.11n, 802.11ac, and 802.11ax propose LDPC codes as the standard channel coding scheme for wireless local area networks (WLANs). 802.11ac / ax currently incorporates 12 parity check matrices for LDPC codes, with three code lengths, each supporting four code rates. The transmitting device selects the appropriate parity check matrix from these 12 based on the target code length and code rate for LDPC coding.

[0003] To further improve communication system throughput, the next-generation WLAN standard 802.11be proposes the introduction of the incremental redundancy-hybrid automatic repeat request (IR-HARQ) mechanism based on 802.11ax. The IR-HARQ mechanism aims to increase redundant bits through retransmissions, thereby reducing the channel coding rate and improving the decoding success rate at the receiver, resulting in better decoding results.

[0004] However, the above coding schemes adopted by the current WLAN standards cannot meet the requirement of continuously increasing redundant bits through retransmission in the IR-HARQ mechanism, thereby reducing the channel coding rate. Summary of the Invention

[0005] The present application provides a method and communication device for encoding LDPC codes, which can meet the requirements of the IR-HARQ mechanism for increasing redundant bits through retransmission to reduce the channel coding rate, thereby improving the decoding performance of the LDPC codes.

[0006] In a first aspect, the present application provides a method for encoding an LDPC code, the method comprising: performing low-density parity check (LDPC) encoding on an information bit sequence according to a first check matrix to obtain a first codeword of a first code rate, wherein the first check matrix is ​​obtained by reading i rows and j columns from a mother matrix, the mother matrix comprises a basic matrix, an extended matrix, a first fixed matrix, and a second fixed matrix, the basic matrix is ​​located at the upper left corner of the mother matrix, the extended matrix is ​​located at the lower left corner of the mother matrix, the first fixed matrix is ​​located at the upper right corner of the mother matrix, and the second fixed matrix is ​​located at the lower right corner of the mother matrix, the basic matrix and the first fixed matrix have the same number of rows, the extended matrix and the second fixed matrix have the same number of rows, the extended matrix and the second fixed matrix have the same number of columns, i=p+k, j=q+k, p and q are the number of rows and columns of the basic matrix, respectively, k≥0, and i, j, p, q, and k are all integers; and sending the first codeword.

[0007] In the technical solution of the present application, a check matrix of the LDPC code is used as a basic matrix and expanded to obtain a mother matrix that is compatible with multiple code rates. The check matrices of different sizes read from the mother matrix correspond to different code rates. When performing LDPC encoding, the transmitting device reads the check matrix corresponding to the required code rate from the mother matrix, and performs LDPC encoding on the information bit sequence according to the read check matrix. In the IR-HARQ mechanism, a check matrix corresponding to a lower code rate (relative to the code rate of the first transmission) is read during retransmission to encode the information bit sequence, so that a larger number of redundant bits can be obtained, thereby reducing the channel coding rate.

[0008] It is understandable that, as the channel coding rate is reduced, the decoding success rate of the receiving device is improved, thereby reducing the number of retransmissions and reducing the retransmission delay.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: receiving retransmission indication information; performing LDPC encoding on the information bit sequence according to a second check matrix to obtain a second codeword of a second code rate, wherein the second check matrix is ​​obtained by reading w rows and z columns from the mother matrix, w=p+h, z=q+h, h>k, wherein w, z and h are all positive integers; and sending the second codeword.

[0010] In a second aspect, the present application provides a method for decoding an LDPC code, the method comprising: receiving a first channel receive sequence from a transmitting end device; decoding a first LLR sequence corresponding to the first channel receive sequence according to a first check matrix, wherein the first check matrix is ​​obtained by reading i rows and j columns from a mother matrix, the mother matrix comprises a basic matrix, an extended matrix, a first fixed matrix and a second fixed matrix, the basic matrix is ​​located at the upper left corner of the mother matrix, the extended matrix is ​​located at the lower left corner of the mother matrix, and the first fixed matrix is ​​located at the upper right corner of the mother matrix. corner position, the second fixed matrix is ​​located at the lower right corner position of the mother matrix, the number of rows of the basic matrix and the first fixed matrix is ​​equal, the number of rows of the extended matrix and the second fixed matrix is ​​equal, the number of columns of the extended matrix is ​​equal to the number of columns of the basic matrix, the number of columns of the first fixed matrix and the second fixed matrix is ​​equal, i=p+k,j=q+k,p and q are the number of rows and columns of the basic matrix respectively, k≥0, i, j, p, q, k are all integers; if the first LLR sequence is successfully decoded according to the first parity check matrix, a decoding result is output.

[0011] In combination with the second aspect, in certain implementations of the second aspect, the method further includes: in a case where decoding of the first LLR sequence fails according to the first check matrix, sending retransmission indication information to the transmitting device; receiving a second channel receive sequence from the transmitting device; decoding the merged LLR sequence according to the second check matrix, wherein the merged LLR sequence is obtained by merging the second LLR sequence corresponding to the second channel receive sequence and the first LLR sequence, and the second check matrix is ​​obtained by reading w rows and z columns from the mother matrix, w=p+h, z=q+h, h>k, and w, z and h are all positive integers.

[0012] In certain implementations of the first aspect or the second aspect, the code rate corresponding to the basic matrix is ​​1 / 2, and the mother matrix is ​​shown in the following formula:

[0013]

[0014] Among them, H(1 / 2) is the mother matrix, H MC (1 / 2) is the basic matrix, H IR (1 / 2) is the expansion matrix, the H IR The size of (1 / 2) is r rows and 24 columns, 1 / 2 represents the code rate, 0 12×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 12×r represents a zero matrix with a size of 12 rows and r columns, the I r×rH represents the identity matrix with size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; MC (1 / 2) See instructions.

[0015] In one implementation, H IR (1 / 2) Read r rows and 24 columns from the first matrix. The size of the first matrix is ​​100 rows and 24 columns. H IR The r rows of (1 / 2) are any r rows among the 100 rows of the first matrix, and the first matrix can be represented by Table A.

[0016] In another implementation, H IR (1 / 2) Read r rows and 24 columns from the second matrix. The size of the second matrix is ​​100 rows and 24 columns. H IR The r rows of (1 / 2) are any r rows among the 100 rows of the second matrix, and the second matrix can be represented by Table B.

[0017] In certain implementations of the first aspect or the second aspect, the code rate corresponding to the basic matrix is ​​2 / 3, and the mother matrix is ​​shown in the following formula:

[0018]

[0019] Among them, H(2 / 3) is the mother matrix, H MC (2 / 3) is the basic matrix, H IR (2 / 3) is the expansion matrix, the H IR The size of (2 / 3) is r rows and 8 columns, 2 / 3 represents the bit rate, 0 8×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 8×r Represents an all-zero matrix with a size of 8 rows and r columns, the I r×r H represents the identity matrix with size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; MC (2 / 3) See instructions.

[0020] In one implementation, H IR (2 / 3) Read r rows and 24 columns from the third matrix. The size of the third matrix is ​​100 rows and 24 columns. H IR The r rows of (2 / 3) are any r rows among the 100 rows of the third matrix, and the third matrix can be represented by Table C.

[0021] In another implementation, H IR (2 / 3) Read r rows and 24 columns from the fourth matrix. The size of the fourth matrix is ​​100 rows and 24 columns. H IRThe r rows of (2 / 3) are any r rows among the 100 rows of the fourth matrix, and the fourth matrix can be represented by Table D.

[0022] In certain implementations of the first aspect or the second aspect, the code rate corresponding to the basic matrix is ​​3 / 4, and the mother matrix is ​​shown in the following formula:

[0023]

[0024] Among them, H(3 / 4) is the mother matrix, H MC (3 / 4) is the basic matrix, H IR (3 / 4) is the expansion matrix, H IR The size of (3 / 4) is r rows and 24 columns, 3 / 4 represents the bit rate, 0 6×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 6×r represents a zero matrix with 6 rows and r columns, the I r×r H represents the identity matrix with size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; MC (3 / 4) See instructions.

[0025] In one implementation, H IR (3 / 4) Read r rows and 24 columns from the fifth matrix. The size of the fifth matrix is ​​100 rows and 24 columns. H IR The r rows of (2 / 3) are any r rows among the 100 rows of the fifth matrix, and the fifth matrix can be represented by Table E.

[0026] In one implementation, H IR (3 / 4) Read r rows and 24 columns from the sixth matrix. The size of the sixth matrix is ​​100 rows and 24 columns. H IR The r rows of (2 / 3) are any r rows among the 100 rows of the sixth matrix, and the sixth matrix can be represented by Table F.

[0027] In certain implementations of the first aspect or the second aspect, the code rate corresponding to the basic matrix is ​​5 / 6, and the mother matrix is ​​shown in the following formula:

[0028]

[0029] Among them, H(5 / 6) is the mother matrix, H MC (5 / 6) is the basic matrix, H IR (5 / 6) is the expansion matrix, the H IR The size of (5 / 6) is r rows and 24 columns, 5 / 6 represents the bit rate, 0 4×r is the first fixed matrix, I r×ris the second fixed matrix, the 0 4×r Represents a zero matrix with a size of 4 rows and r columns, the I r×r H represents the identity matrix with size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; MC (5 / 6) See instructions.

[0030] In one implementation, H IR (5 / 6) Read r rows and 24 columns from the seventh matrix. The size of the seventh matrix is ​​100 rows and 24 columns. H IR The r rows of (5 / 6) are any r rows among the 100 rows of the seventh matrix, and the seventh matrix can be represented by Table G.

[0031] In another implementation, H IR (5 / 6) Read r rows and 24 columns from the eighth matrix. The eighth matrix size is 100 rows and 24 columns. H IR The r rows of (5 / 6) are any r rows among the 100 rows of the eighth matrix, and the eighth matrix can be represented by Table H.

[0032] In the above, Table A corresponds to Table 1 in the specification, Table B corresponds to Table 4, Table C corresponds to Table 5, Table D corresponds to Table 6, Table E corresponds to Table 7, Table F corresponds to Table 8, Table G corresponds to Table 9, and Table H corresponds to Table 10.

[0033] In a third aspect, the present application provides a communication device for executing the method in the first aspect or any possible implementation of the first aspect. Specifically, the communication device includes corresponding units for executing the method in the first aspect or any possible implementation of the first aspect.

[0034] In one implementation, the communication device may include a memory and a processor, wherein the memory is used to store a computer program or instructions, and the processor reads and executes the computer program or instructions from the memory, so that the method of the first aspect or any possible implementation thereof is implemented.

[0035] Optionally, the memory and processor may be physically independent units, or may be integrated together.

[0036] In another implementation, the communication device includes an input interface circuit, a logic circuit, and an output interface circuit. The input interface circuit is configured to obtain an information bit sequence to be encoded; the logic circuit is configured to execute the LDPC encoding method of the first aspect or any possible implementation thereof to obtain a codeword of a corresponding code rate; and the output interface circuit is configured to output the codeword.

[0037] Optionally, the input interface circuit and the output interface circuit can be integrated together and referred to as an interface circuit.

[0038] In a fourth aspect, the present application provides a communication device for executing the method in the second aspect or any possible implementation of the second aspect. Specifically, the communication device includes a corresponding unit for executing the method in the second aspect or any possible implementation of the second aspect.

[0039] In one implementation, the communication device may include a memory and a processor, wherein the memory is used to store a computer program or instructions, and the processor reads and executes the computer program or instructions from the memory, so that the method of the second aspect or any possible implementation thereof is implemented.

[0040] Optionally, the memory and processor may be physically independent units, or may be integrated together.

[0041] In another implementation, the communication device includes an input interface circuit, a logic circuit, and an output interface circuit. The input interface circuit is configured to obtain an information bit sequence to be encoded; the logic circuit is configured to execute the LDPC encoding method of the second aspect or any possible implementation thereof to obtain a codeword of a corresponding code rate; and the output interface circuit is configured to output the codeword.

[0042] Optionally, the input interface circuit and the output interface circuit can be integrated together and referred to as an interface circuit.

[0043] In a fifth aspect, the present application provides a communication device comprising an interface circuit and a processor, wherein the interface circuit is used to receive computer code or instructions and transmit them to the processor, and the processor runs the computer code or instructions, and the method in the first aspect or any implementation thereof is implemented.

[0044] In a sixth aspect, the present application provides a communication device comprising an interface circuit and a processor, wherein the interface circuit is used to receive computer code or instructions and transmit them to the processor, and the processor runs the computer code or instructions, and the method in the second aspect or any implementation thereof is implemented.

[0045] In a seventh aspect, the present application provides a communication device comprising at least one processor, wherein the at least one processor is coupled to at least one memory, wherein the at least one memory is used to store a computer program or instruction, and the at least one processor is used to call and run the computer program or instruction from the at least one memory, so that the method in the first aspect or any possible implementation thereof is implemented.

[0046] In an eighth aspect, the present application provides a communication device comprising at least one processor, wherein the at least one processor is coupled to at least one memory, wherein the at least one memory is used to store a computer program or instruction, and the at least one processor is used to call and run the computer program or instruction from the at least one memory, so that the method in the first aspect or any possible implementation thereof is implemented.

[0047] In a ninth aspect, the present application provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed on a computer, the method in the first aspect or any possible implementation thereof is implemented.

[0048] In a tenth aspect, the present application provides a computer-readable storage medium having computer instructions stored therein. When the computer instructions are executed on a computer, the method in the above-mentioned second aspect or any possible implementation thereof is implemented.

[0049] In an eleventh aspect, the present application provides a computer program product comprising computer codes or instructions. When the computer codes or instructions are executed on a computer, the method in the above-mentioned first aspect or any possible implementation thereof is implemented.

[0050] In a twelfth aspect, the present application provides a computer program product, comprising computer code or instructions. When the computer code or instructions are run on a computer, the method in the above-mentioned first aspect or any possible implementation thereof is implemented.

[0051] In a thirteenth aspect, the present application provides a wireless communication system, comprising the communication device of the seventh aspect and the communication device of the eighth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is the check matrix H of the LDPC code.

[0053] Figure 2 is the Tanner graph of the check matrix H of the LDPC code.

[0054] Figure 3 (a) and (b) are system architecture diagrams applicable to the embodiments of the present application.

[0055] Figure 4 This is a flow chart of a method 400 for encoding an LDPC code provided in the present application.

[0056] Figure 5 For H MC An example of a check matrix obtained by expanding (5 / 6).

[0057] Figure 6This is an example of the LDPC code encoding method provided in this application.

[0058] Figure 7 This is a flowchart of the encoding and decoding of the LDPC code provided by this application.

[0059] Figure 8 The figure shows the performance curve of an embodiment of the present application at various compatible bit rates.

[0060] Figure 9 The figure shows the performance curve of another embodiment of the present application at various compatible bit rates.

[0061] Figure 10 This is a schematic block diagram of a communication device 600 provided in this application.

[0062] Figure 11 This is a schematic block diagram of a communication device 800 provided in this application. DETAILED DESCRIPTION

[0063] The technical solution in this application will be described below with reference to the accompanying drawings.

[0064] In the field of channel coding, low-density parity check (LDPC) codes are the most mature and widely used channel coding scheme. LDPC codes offer performance close to the Shannon limit and numerous advantages, such as good bit error performance without the need for deep interleaving, good frame error rate performance, and support for parallel decoding, resulting in low decoding latency. Consequently, IEEE protocols such as 802.11n, 802.11ac, and 802.11ax have proposed LDPC codes as the standard channel coding scheme for wireless local area networks (WLANs).

[0065] 802.11be, the next-generation WLAN standard following 802.11ax, introduces the Hybrid Automatic Repeat Request (HARQ) mechanism to further improve system throughput. In HARQ, if the receiver incorrectly decodes data sent by the transmitter, it saves the incorrectly received data and requests the transmitter to retransmit it. The receiver then combines the retransmitted data with the previously saved data before decoding it. This process provides a certain degree of diversity gain, reducing the number of retransmissions and latency.

[0066] HARQ mechanisms can be divided into two types: chase combining (CC) and incremental redundancy (IR-HARQ). In a simple HARQ mechanism, the receiver directly discards incorrectly received packets. However, while these incorrectly received packets cannot be correctly decoded independently, they still contain some useful information. In CC-HARQ, the CC process utilizes this information to store incorrectly received packets in memory and combine them with retransmitted packets for decoding, thereby improving transmission efficiency. In the IR HARQ mechanism, the transmitter sends information bits and some redundant bits in the initial transmission and additional redundant bits in the retransmission. If the initial transmission is not correctly decoded, the transmitter retransmits more redundant bits to reduce the channel code rate, thereby improving the decoding success rate. If the receiver still cannot correctly decode the packet after combining the redundant bits from the first retransmission, the transmitter retransmits again. As the number of retransmissions increases, the number of redundant bits increases, and the signal-to-code rate decreases, resulting in better decoding results.

[0067] If the next generation WLAN standard introduces the IR HARQ mechanism, it will need to be supported by an LDPC coding scheme that is compatible with multiple rates so that new incremental redundancy bits can be introduced during retransmission.

[0068] In order to facilitate understanding of the solution of the present application, the relevant concepts of LDPC codes are first introduced.

[0069] An LDPC code is a linear block code whose parity check matrix is ​​a sparse matrix. The number of zero elements in the parity check matrix of an LDPC code far exceeds the number of non-zero elements. In other words, the row and column weights of the parity check matrix are very small compared to the code length of the LDPC code. An LDPC code with an information bit sequence length equal to k and a code length equal to n can be uniquely identified by its parity check matrix.

[0070] In 1981, Tanner represented the codewords of LDPC codes in the form of a graph. This graph is now called a Tanner graph. The Tanner graph corresponds one-to-one with the check matrix. The Tanner graph consists of two types of vertices: one type of vertex represents the codeword bits, called variable nodes, and the other type of vertex is the check node, which represents the check constraint relationship. Each check node represents a check constraint relationship. Figure 1 and Figure 2 Provide explanation.

[0071] See also Figure 1 , Figure 1 is the check matrix H of the LDPC code. Figure 1 In {V i} represents a variable node set, {C i} represents the check node set. Each row of the check matrix H represents a check equation, and each column represents a codeword bit. Figure 1 In the equation, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the bit node and the check node involved to obtain the Tanner graph.

[0072] See also Figure 2 , Figure 2 is the Tanner graph of the check matrix H of the LDPC code. Figure 2 As shown, the Tanner graph represents the check matrix of the LDPC code. For example, for a check matrix H with a size of m rows and n columns, the Tanner graph contains two types of nodes, namely n bit nodes and m check nodes. The n bit nodes correspond to the n columns of the check matrix H, and the m check nodes correspond to the m rows of the check matrix H. The cycle in the Tanner graph is composed of vertices connected to each other. The cycle uses one of the vertices in this group of vertices as both the starting point and the end point, and only passes through each node once. The length of the cycle is defined as the number of connections it contains, and the girth of the graph can also be called the size of the graph, which is defined as the minimum cycle length in the graph, such as Figure 2 In the figure, the girth is 6, such as Figure 2 As shown by the black line in Chinese.

[0073] The LDPC codes used in the IEEE 802.11ac and 802.11ax standards are quasi-cyclic low-density parity check (QC-LDPC) codes. QC-LDPC codes are a type of structured LDPC code. Due to the unique structure of their parity check matrix, encoding can be implemented using a simple feedback shift register, reducing the coding complexity of LDPC codes.

[0074] IEEE 802.11ac and 802.11ax adopt a total of 12 LDPC code parity check matrices, supporting three code lengths: 648, 1296, and 1944. Each code length supports four different code rates: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The parity bit portion of these 12 parity check matrices has the same structure.

[0075] For example, the parity check matrix H for an LDPC code with a code length of 1944 and a code rate of 5 / 6 in 802.11ac is as follows:

[0076]

[0077] It can be seen that the size of H is 4 rows and 24 columns. Each element of the matrix represents a square matrix of order z=N / 24. The 0 in the matrix represents a square matrix of size z×z with all zeros. z i represents a cyclic permutation matrix, i represents a cyclic shift value, where 0≤i≤z-1, and i is an integer. In addition, "-" in the matrix represents an all-zero matrix, and "0" represents an identity matrix.

[0078] For example, P z 1 As shown below:

[0079]

[0080] When encoding an LDPC code in a WLAN, the transmitter selects a corresponding check matrix from the 12 check matrices according to a target code length and a target code rate, wherein the 12 check matrices are different from each other.

[0081] To improve WLAN transmission reliability, the IEEE 802.11be standard introduces the IR-HARQ mechanism, building on the previous 802.11ax standard. To achieve higher throughput, the IR-HARQ mechanism requires the introduction of rate-compatible LDPC codes in WLANs to generate incremental redundancy bits during retransmissions. The receiver then gains performance by combining the initially received bits with the retransmitted incremental redundancy bits.

[0082] The following is a technical solution provided in conjunction with this application.

[0083] The technical solution of the present application is mainly applicable to wireless communication systems, which can comply with the wireless communication standards of the Third Generation Partnership Project (3GPP) or other wireless communication standards, such as the 802 series (for example, 802.11, 802.15, or 802.20) of the Institute of Electrical and Electronics Engineers (IEEE).

[0084] See also Figure 3 , Figure 3 (a) and (b) are system architecture diagrams applicable to embodiments of the present application. The wireless communication system includes at least one network device and one or more terminal devices. The at least one network device and one or more terminal devices communicate using wireless communication technology. For example, Figure 3 (a) shows communication between a network device and a single terminal device. Figure 3(b) shows a network device communicating with multiple terminal devices. Optionally, the communication between the above network device and the terminal device may include downlink transmission of signals sent by the network device to the terminal device, and uplink transmission of signals sent by the terminal device to the network device, which is not limited in this article.

[0085] The terminal devices involved in the embodiments of the present application are also called user equipment (UE), terminal, mobile phone, tablet computer, laptop computer, wearable device (for example, smart watch, smart bracelet, smart helmet, smart glasses, etc.), and other devices with wireless access capabilities, such as smart cars, various Internet of Things (IoT) devices, including various smart home devices (for example, smart meters and smart appliances) and smart city devices (for example, security or monitoring equipment, smart road traffic facilities), terminal devices in 5G systems or later communication systems, etc.

[0086] The network device involved in the embodiments of the present application may be a base station, which is sometimes also referred to as a wireless access point (AP), a transmission reception point (TRP) or a transmission node (TP). Optionally, the base station may be a generalized node B (gNB) in a fifth generation (5G) system or an evolved node B (eNB) in a long term evolution (LTE) system. In addition, depending on the physical form or transmission power of the base station, the base station can be divided into a macro base station or a micro base station. A micro base station is sometimes also referred to as a small base station or a small cell. In addition, the network device may also be a network node constituting a gNB or TRP, such as a building baseband unit (BBU), a centralized unit (CU) or a distributed unit (DU).

[0087] See also Figure 4 , Figure 4 This is a flow chart of a method 400 for encoding an LDPC code provided in the present application.

[0088] Optionally, method 400 can be performed by a transmitting device, or by a chip or circuit system disposed within the transmitting device. The circuit system can be, for example, an integrated circuit or a logic circuit. The chip can be, for example, a system on a chip (SoC) chip or a baseband modem chip, which is not limited herein. The following description uses a transmitting device as an example. The transmitting device can be a terminal device or a network device. It should be understood that the transmitting device in the embodiments of the present application is also an encoding device.

[0089] 410. The transmitting device performs LDPC encoding on the information bit sequence according to the first check matrix to obtain a first codeword of a first code rate.

[0090] The first check matrix is ​​obtained by reading i rows and j columns from the mother matrix. The mother matrix includes a base matrix, an extended matrix, a first fixed matrix, and a second fixed matrix. The base matrix is ​​located in the upper left corner of the mother matrix, the extended matrix is ​​located in the lower left corner of the mother matrix, the first fixed matrix is ​​located in the upper right corner of the mother matrix, and the second fixed matrix is ​​located in the lower right corner of the mother matrix. The number of columns of the base matrix is ​​equal to the number of columns of the extended matrix, and the number of columns of the first fixed matrix is ​​equal to the number of columns of the second fixed matrix. The number of rows of the base matrix is ​​equal to the number of rows of the first fixed matrix, and the number of rows of the extended matrix is ​​equal to the number of rows of the second fixed matrix.

[0091] Specifically, the first fixed matrix is ​​an all-zero matrix, and the second fixed matrix is ​​a unit matrix.

[0092] In other words, the mother matrix is ​​a larger matrix from which parity check matrices of different sizes can be read. Parity check matrices of different sizes correspond to different code rates.

[0093] The first check matrix is ​​obtained by reading i rows and j columns from the mother matrix, i=p+k, j=q+k, p and q are the number of rows and columns of the basic matrix respectively, k≥0, i, j, p, q, k are all integers;

[0094] Optionally, when k = 0, the first check matrix is ​​the base matrix. When k > 0, the first check matrix includes the base matrix, which is obtained by extending the base matrix rightward by k columns and then downward by k rows, where k > 0 and k is an integer. For example, k = 1, 2, 4, 50, etc.

[0095] Different parity check matrices read from the mother matrix correspond to different code rates. For example, when reading the base matrix from the mother matrix, the base matrix is ​​the first parity check matrix, and in this case, the first parity check matrix corresponds to the highest code rate. When reading the entire mother matrix, the mother matrix is ​​the first parity check matrix, and in this case, the first parity check matrix corresponds to the lowest code rate.

[0096] For the convenience of description, the corresponding code rate when the first check matrix is ​​the basic matrix is ​​referred to as the maximum code rate, and the corresponding code rate when the first check matrix is ​​the mother matrix is ​​referred to as the minimum code rate.

[0097] The parity check matrix corresponding to any code rate between the maximum code rate and the minimum code rate can be read from the mother matrix. Alternatively, when k takes different values, the first parity check matrix is ​​used to encode the information bit sequence to obtain the first codeword of different code rates.

[0098] 420. The transmitting device sends the first codeword.

[0099] After performing LDPC encoding on the information bit sequence to obtain a first codeword, the transmitting device sends the first codeword.

[0100] In an embodiment of the present application, by expanding the basic matrix, check matrices corresponding to different code rates are obtained. Since these check matrices for different code rates are expanded on the basis of keeping the basic matrix fixed, using these check matrices for LDPC coding can not only be compatible with multiple code rates, but also obtain diversity gain, thereby improving coding performance.

[0101] In an embodiment of the present application, for LDPC codes with a code length of 1944 and code rates of 1 / 2, 2 / 3, 3 / 4 and 5 / 6, the check matrix (i.e., the basic matrix) is expanded to obtain a mother matrix. The highest code rates that the mother matrix can support are 1 / 2, 2 / 3, 3 / 4 and 5 / 6, which are the maximum code rates mentioned above. The minimum code rates that the mother matrix can support are 12 / 124=0.097, 16 / 124=0.129, 18 / 124=0.145, and 20 / 124=0.161, which are the minimum code rates mentioned above. Several examples of mother matrices are given below.

[0102] For the sake of simplicity, the parity check matrices of LDPC codes with a code length of 1944 and code rates of 1 / 2, 2 / 3, 3 / 4, and 5 / 6 used in WLAN are first given.

[0103] (1)

[0104]

[0105] H MC (1 / 2) as an example, H MC(1 / 2) is a matrix with 12 rows and 24 columns, where each element in the matrix represents a square matrix of order z=N / 24. 0 represents a square matrix of all zeros of size z×z. Each item i in the matrix represents a z×z cyclic permutation matrix, where i represents the cyclic shift value. For example, if N=1944, then z=1944 / 24=81. The element with i=0 in the matrix represents the unit matrix of size 81×81. For another example, the element with i=1 represents a cyclic shift matrix of size 81×81:

[0106]

[0107] (2)

[0108]

[0109] (3)

[0110]

[0111] (4)

[0112]

[0113] Here, the check matrix H MC (2 / 3), H MC (3 / 4) and H MC The meaning of the elements in (5 / 6) and the H introduced above MC The meanings of the elements in (1 / 2) are the same and will not be repeated here.

[0114] In this embodiment of the present application, the position of the base matrix is ​​first fixed, and then it is expanded row by row and column by column. Each time a column is expanded to the right, a row is expanded downward simultaneously, and the optimal performance of the LDPC code is sought, achieving the optimal performance at the current code rate, to obtain an expanded matrix. Next, the expanded matrix is ​​expanded to the right again by a row and downward by a column, and the optimal performance of the LDPC code is sought, achieving the optimal performance at the current code rate, and so on, gradually expanding to obtain the mother matrix.

[0115] For example, H MC (5 / 6) corresponds to a code rate of 5 / 6. If you want to MC (5 / 6) is extended to obtain a lower code rate, which is used to increase the incremental redundancy bits in the retransmission process of the IR-HARQ mechanism. Then, H can be MC (5 / 6) for expansion.

[0116] For example, if you need to change the bit rate from H MC (5 / 6) The corresponding 5 / 6 is reduced to 4 / 7, or, you need toMC (5 / 6) and then add 324 incremental redundant bits, then it is necessary to convert H into H(5 / 6) MC (5 / 6) Expand several columns to the right and several rows downward. The check matrix obtained after expansion is as follows: Figure 5 shown.

[0117] See also Figure 5 , Figure 5 For H MC An example of a check matrix obtained by expanding (5 / 6). Figure 5 As shown, the upper left corner of the matrix is ​​the matrix H MC (5 / 6), H MC (5 / 6) Expand 4 columns to the right and at the same time H MC (5 / 6) Expand 4 lines downwards and get Figure 5 The mother matrix is ​​shown. Figure 5 Each blank grid in represents an all-zero matrix of size 81×81, and the upper left corner of the mother matrix is ​​a matrix H of size 4×24 MC (5 / 6), the upper right corner is the first fixed matrix, which is a 4×4 all-zero matrix. The lower left corner of the mother matrix is ​​the matrix H IR (5 / 6), the lower right corner of the mother matrix is ​​the second fixed matrix, which is a unit matrix of size 4×4.

[0118] The size of the matrix obtained after expansion is 8×28, such as Figure 5 As mentioned above, the code length is N=1944, and the H MC (5 / 6) is expanded, and each element in the expanded matrix is ​​a cyclic shift matrix of size 81×81. Therefore, Figure 5 The matrix shown is expanded to obtain the mother matrix, and the actual size of the mother matrix should be 648×2268.

[0119] The above is H MC (5 / 6) is expanded, so that the code rate corresponding to the check matrix is ​​reduced from 5 / 6 to 4 / 7. If a check matrix corresponding to a code rate other than 4 / 7 is required, the transmitting device can read the matrix of the corresponding size from the upper left corner of the mother matrix H(5 / 6) as the check matrix.

[0120] For example, if in addition to H MC In addition to the codeword bits of the LDPC code corresponding to (5 / 6), 81·v incremental redundant bits need to be generated. Figure 5 A matrix of size (4+v)×(24+v) is read from the mother matrix H(5 / 6) as a check matrix, where v is a positive integer.

[0121] The above check matrix H corresponding to the code rate of 5 / 6 MC (5 / 6) As an example, the expansion process from the basic matrix to the mother matrix is ​​introduced. The expansion process of the basic matrix corresponding to other code rates is also based on the same design concept.

[0122] The following describes the expanded mother matrices for the parity check matrices of code rates 1 / 2, 2 / 3, 3 / 4, and 5 / 6, respectively.

[0123] In one embodiment, the basic matrix with a code rate of 1 / 2 is expanded, and the expanded mother matrix is ​​shown in formula (1):

[0124]

[0125] In formula (1), H(1 / 2) is the mother matrix, H MC (1 / 2) is the basic matrix, H IR (1 / 2) is the expansion matrix, the H IR The size of (1 / 2) is r rows and 24 columns, 1 / 2 represents the code rate, 0 12×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 12×r represents a zero matrix with a size of 12 rows and r columns, the I r×r Represents the identity matrix of size r rows and r columns, r ≥ 1, r is an integer. MC (1 / 2) See above.

[0126] It should be noted that H(1 / 2) represents a mother matrix, which means that the mother matrix is ​​obtained by expanding a check matrix with a code rate of 1 / 2 as a basic matrix.

[0127] Table 1 below represents a matrix with a size of 100 rows and 24 columns, which is referred to as the first matrix below. IR (1 / 2) is obtained by reading r rows and 24 columns from the first matrix, where the r rows are any r rows among the 100 rows of the first matrix. In other words, reading r rows and 24 columns from the 100 rows of the first matrix shown in Table 1 is H IR (1 / 2).

[0128] It should be understood that when r rows of the first matrix are read, the elements of the 24 columns corresponding to the r rows in the first matrix are also uniquely determined, and the matrix thus constructed is H IR (1 / 2).

[0129] Among them, Table 1 is as follows:

[0130] Table 1

[0131]

[0132]

[0133]

[0134] In Table 1, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the first matrix, the nth element (a, b) from left to right in the mth row of the first matrix represents that the cyclic shift coefficient of the cyclic shift matrix in the (a+n)th column in the mth row of the first matrix is ​​b, and the remaining positions of the first matrix are all zero matrices, n∈{1,2,3,4,5},m,n,a and b are all positive integers.

[0135] It should be understood that the row weight of the m-th row of the first matrix represents the number of elements “1” in the m-th row of the first matrix.

[0136] For example, the value of the first element from the top to the bottom of the first column in Table 1 is 5, indicating that the row weight of the first row of the first matrix is ​​5. The first element from the left to the right of the first row is (0, 22), indicating that the cyclic shift value of the cyclic shift matrix in the (0+1)th column of the first row of the first matrix is ​​22. The elements of the remaining columns of the first row of the first matrix represent an all-zero matrix.

[0137] For another example, in Table 1, the 10th element from the top of the first column is 4, indicating that the row weight of the 10th row of the first matrix is ​​5. The third element from the left to the right of the 10th row is (8, 78), indicating that the cyclic shift value of the (8+3)th column of the first matrix is ​​78. That is, the cyclic shift value of the cyclic shift matrix of the 11th column in the 10th row of the first matrix is ​​78. The elements of the remaining columns in the 10th row of the first matrix represent an all-zero matrix.

[0138] Optionally, in one embodiment, H MC (1 / 2) is expanded to the right by 100 columns and downward by 100 rows. The resulting mother matrix is ​​shown in formula (2):

[0139]

[0140] In formula (2), H(1 / 2) is the mother matrix, H MC (1 / 2) represents the basic matrix with size 12 rows and 24 columns, see above. IR (1 / 2) is the expansion matrix, 1 / 2 represents the bit rate, 0 12×100 is the first fixed matrix, I 12×100 is the second fixed matrix. Specifically, 0 12×100 represents an all-zero matrix with a size of 12 rows and 100 columns, I 100×100Represents the identity matrix of size 100 rows and 100 columns.

[0141] It can be understood that when r=100 in formula (1), formula (2) is obtained, and H in formula (2) is IR (1 / 2) As shown in Table 1, its size is 100 rows and 24 columns.

[0142] Optionally, when 1≤r<100, the H with a size of r rows and 24 columns can be determined according to Table 1. IR (1 / 2), further according to H MC (1 / 2), 0 12×r and I r×r , we can get a mother matrix with a size of (12+100) rows and (24+100) columns. Specifically, H IR The r rows of (1 / 2) can be obtained by reading r rows and 24 columns from Table 1.

[0143] In one embodiment, r rows and 24 columns are read from Table 1 in ascending order of row index, as H IR (1 / 2), wherein the r rows are r rows with consecutive row indices in the first matrix.

[0144] For example, when r=4, 4 rows and 24 columns are read from the first matrix shown in Table 1 as H IR (1 / 2), the 4 rows are the 1st to 4th rows of the first matrix, as shown in Table 2:

[0145] Table 2

[0146]

[0147] For example, when r=50, H IR (1 / 2) is a 50×24 matrix. Read the 50 rows and 24 columns of the first matrix in ascending order of row index, and get H IR (1 / 2). The 50 rows are the 1st to 50th rows of the first matrix. At this time, H IR (1 / 2) as shown in Table 3:

[0148] Table 3

[0149]

[0150]

[0151] Alternatively, in another embodiment, according to other reading rules, r rows are read from Table 1 as H IR For example, 4 rows are randomly read from the 100 rows in Table 1, or 4 rows are randomly read from the rows with even indexes, etc.

[0152] Alternatively, in another embodiment, the following Table 4 represents a matrix with a size of 100 rows and 24 columns, hereinafter referred to as the second matrix. Read r rows and 24 columns from the second matrix to obtain H IR (1 / 2), wherein the r rows are any r rows among the 100 rows of the second matrix. Table 4 is as follows:

[0153] Table 4

[0154]

[0155]

[0156]

[0157] In Table 4, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the second matrix, the nth element (a, b) from left to right in the mth row of the second matrix represents that the cyclic shift coefficient of the cyclic shift matrix in the (a+n)th column in the mth row of the second matrix is ​​b, and the remaining positions of the second matrix are all all-zero matrices, n∈{1,2,3,4,5}, m, a, and b are all positive integers.

[0158] In another embodiment, H MC (2 / 3) is expanded as the basic matrix, and the resulting mother matrix can be shown as formula (3):

[0159]

[0160] Among them, H(2 / 3) is the mother matrix, H MC (2 / 3) is the basic matrix, H IR (2 / 3) is the expansion matrix, the H IR The size of (2 / 3) is r rows and 8 columns, 2 / 3 represents the bit rate, 0 8×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 8×r Represents an all-zero matrix with a size of 8 rows and r columns, the I r×r H represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, and r is an integer. MC (2 / 3) See above.

[0161] Optionally, H IR (2 / 3) can be obtained by reading r rows from Table 5 or Table 6.

[0162] In one implementation, r rows are read from Table 5 or Table 6 in descending order of row index. In other embodiments, r rows are read from Table 5 or Table 6 to obtain the H IR(2 / 3).

[0163] Table 5

[0164]

[0165]

[0166]

[0167] In Table 5, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the third matrix, the nth element (a, b) from left to right in the mth row of the third matrix represents that the cyclic shift coefficient of the cyclic shift matrix in the (a+n)th column in the mth row of the third matrix is ​​b, and the remaining positions of the third matrix are all all-zero matrices, n∈{1,2,3,4,5,6,7}, m, a, and b are all positive integers.

[0168] Table 6

[0169]

[0170]

[0171]

[0172]

[0173] In Table 6, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the fourth matrix, the nth element (a, b) from left to right in the mth row of the fourth matrix represents that the cyclic shift coefficient of the cyclic shift matrix in the (a+n)th column in the mth row of the fourth matrix is ​​b, and the remaining positions of the fourth matrix are all all-zero matrices, n∈{1,2,3,4,5}, m, a, and b are all positive integers.

[0174] Optionally, in one embodiment, H MC (2 / 3) is expanded to the right by 100 columns and downward by 100 rows. The resulting mother matrix is ​​shown in formula (4):

[0175]

[0176] Among them, H MC (2 / 3) can be the third matrix as shown in Table 5, or the fourth matrix as shown in Table 6,

[0177] Its size is 100 rows and 24 columns.

[0178] Optionally, in one embodiment, H MC (3 / 4) is expanded as the basic matrix, and the resulting mother matrix is ​​shown in formula (5):

[0179]

[0180] In formula (1), H(3 / 4) is the mother matrix, H MC (3 / 4) is the basic matrix, H IR (3 / 4) is the expansion matrix, the H IR The size of (3 / 4) is r rows and 24 columns, 3 / 4 represents the bit rate, 0 12×r is the first fixed matrix, I r×r is the second fixed matrix. 6×r represents a zero matrix with a size of 12 rows and r columns, the I r×r Represents the identity matrix of size r rows and r columns, r ≥ 1, r is an integer. MC (3 / 4) See above.

[0181] Table 7 below represents a matrix with a size of 100 rows and 24 columns, which is referred to as the fifth matrix below. Read r rows and 24 columns from the fifth matrix to obtain H IR (3 / 4) wherein the r rows are any r rows among the 100 rows.

[0182] Optionally, the r rows are the first 50 rows of the 100 rows of the fifth matrix.

[0183] Among them, Table 7 is as follows:

[0184] Table 7

[0185]

[0186]

[0187]

[0188] In Table 7, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the fifth matrix, the nth element (a, b) from left to right in the mth row of the fifth matrix represents that the cyclic shift coefficient of the cyclic shift matrix in the (a+n)th column in the mth row of the fifth matrix is ​​b, and the remaining positions of the fifth matrix are all all-zero matrices, n∈{1,2,3,4,5,6,7,8,9}, m, a, and b are all positive integers.

[0189] Table 8

[0190]

[0191]

[0192]

[0193]

[0194] In Table 8, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the sixth matrix, the nth element (a, b) from left to right in the mth row of the sixth matrix represents that the cyclic shift coefficient of the cyclic shift matrix in the (a+n)th column in the mth row of the sixth matrix is ​​b, and the remaining positions of the sixth matrix are all all-zero matrices, n∈{1,2,3,4,5}, m, a, and b are all positive integers.

[0195] Optionally, in one embodiment, H IR (3 / 4) is expanded to the right by 100 columns and downward by 100 rows. The resulting mother matrix is ​​shown in formula (6):

[0196]

[0197] Among them, H(3 / 4) is the mother matrix, H MC (3 / 4) is the basic matrix, H IR (3 / 4) is the expansion matrix, 3 / 4 represents the bit rate, 0 6×100 and I 100×100 is a fixed matrix, 0 6×100 Represents an all-zero matrix of size 6 rows and 100 columns, I 100×100 Represents the identity matrix of size 100 rows and 100 columns, H IR (3 / 4) can be the fifth matrix represented by Table 7, or the sixth matrix represented by Table 8.

[0198] Optionally, in one embodiment, H MC (5 / 6) is expanded as the basic matrix, and the resulting mother matrix can be shown as formula (7):

[0199]

[0200] Among them, H(5 / 6) is the mother matrix, H MC (5 / 6) is the basic matrix, H IR (5 / 6) is the expansion matrix, the H IR The size of (5 / 6) is r rows and 24 columns, 5 / 6 represents the bit rate, 0 12×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 4×r represents a zero matrix with a size of 12 rows and r columns, the I r×r Represents the identity matrix of size r rows and r columns, r ≥ 1, r is an integer. MC (5 / 6) See above.

[0201] Table 9 below represents a matrix with 100 rows and 24 columns, which is called the seventh matrix. Read r rows from the 100 rows of the seventh matrix to get H IR (5 / 6).

[0202] Among them, Table 9 is as follows:

[0203] Table 9

[0204]

[0205]

[0206]

[0207] In Table 9, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the seventh matrix, the nth element (a, b) from left to right in the mth row of the seventh matrix represents that the cyclic shift coefficient of the cyclic shift matrix in the (a+n)th column in the mth row of the seventh matrix is ​​b, and the remaining positions of the seventh matrix are all all-zero matrices, n∈{1,2,3,4,5,6,7,8,9,10,11}, m,n,a and b are all positive integers.

[0208] Alternatively, in another embodiment, the following Table 10 represents a matrix with a size of 100 rows and 24 columns, which is called the eighth matrix. Read r rows and 24 columns from the 100 rows of the eighth matrix to obtain H IR (5 / 6). Optionally, the r columns are any r rows of the eighth matrix. Optionally, the r rows are the 1st to the rth rows of the eighth matrix.

[0209] Among them, Table 10 is as follows:

[0210] Table 10

[0211]

[0212]

[0213]

[0214] In Table 10, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the eighth matrix, the nth element (a, b) from left to right in the mth row of the eighth matrix represents that the cyclic shift coefficient of the cyclic shift matrix in the (a+n)th column in the mth row of the eighth matrix is ​​b, and the remaining positions of the eighth matrix are all all-zero matrices, n∈{1,2,3,4,5,6,7,8,9,10,11}, m,n,a and b are all positive integers.

[0215] Optionally, in one embodiment, H MC(5 / 6) is expanded to the right by 100 columns and downward by 100 rows. The resulting mother matrix is ​​shown in formula (8):

[0216]

[0217] In formula (2), H(5 / 6) is the mother matrix, H MC (5 / 6) represents the basic matrix with a size of 12 rows and 24 columns, H IR (5 / 6) is the expansion matrix, 5 / 6 represents the bit rate, 0 4×100 is the first fixed matrix, I 100×100 is the second fixed matrix. Specifically, 0 12×100 represents an all-zero matrix with a size of 12 rows and 100 columns, I 100×100 H represents the identity matrix with size 100 rows and 100 columns. IR (5 / 6) may be the seventh matrix as shown in Table 9, or may be the eighth matrix as shown in Table 10.

[0218] The above describes the mother matrix provided by this application. Based on the mother matrix obtained by different code rate expansion, in the IR-HARQ mechanism, by retransmitting incremental redundancy bits, the channel coding rate can be reduced to improve the reception success rate of the receiving device. The following examples illustrate this.

[0219] See also Figure 6 , Figure 6 This is an example of the LDPC code encoding method provided in this application.

[0220] 601. A transmitting device performs LDPC encoding on an information bit sequence according to a first check matrix to obtain a first codeword of a first code rate.

[0221] Among them, the first check matrix is ​​obtained by reading i rows and j columns from the mother matrix, i=p+k, j=q+k, p and q are the number of rows and columns of the basic matrix respectively, k≥0, i, j, p, q, k are all integers.

[0222] Alternatively, the mother matrix can be based on H MC (1 / 2) expanded H(1 / 2), based on H MC (2 / 3) expanded H(2 / 3), based on H MC (3 / 4) extended H(3 / 4), or based on H MC Any one of H(5 / 6) obtained by expanding (5 / 6) is not limited.

[0223] Here, H(5 / 6) shown in formula (7) is used as the mother matrix, where H IR(5 / 6) is obtained by reading r rows and 24 columns from the eighth matrix represented by Table 10. The r rows are the 1st to the rth rows of the eighth matrix.

[0224] For example, the first check matrix is ​​obtained from 4 rows and 24 columns, that is, p = 4, q = 24, k = 0, and the first check matrix H MC (5 / 6) It can be seen that the first code rate of the first codeword obtained by using the first check matrix to perform LDPC encoding on the information bit sequence is 5 / 6.

[0225] 602. The transmitting device sends the first codeword.

[0226] 603. The transmitting device receives first retransmission indication information from the receiving device.

[0227] 604. The transmitting device performs LDPC encoding on the information bit sequence according to the second check matrix to obtain a second codeword of a second code rate.

[0228] The second check matrix is ​​obtained by reading w rows and z columns from the mother matrix, where w=p+h, z=q+h, h>k, and w, z and h are all positive integers.

[0229] In the present application, the first check matrix and the second check matrix are read from the same mother matrix.

[0230] For example, w rows and z columns are read from H(5 / 6), where p = 4, q = 24, and h = 50. That is, 54 rows and 74 columns are read from the eighth matrix to obtain a second parity check matrix. LDPC encoding is performed on the information bit sequence using the second parity check matrix to obtain a second codeword.

[0231] 605. The transmitting device sends the second codeword.

[0232] exist Figure 6 In the illustrated process, the first codeword may be the first transmission of data, and the second codeword may be the first retransmission of data. It will be appreciated that if the receiving end still cannot correctly decode the data based on the first received data and the retransmitted data, the receiving end device may request the transmitting end device to retransmit a second time. Furthermore, method 600 may also include steps 606-608.

[0233] 606. The transmitting device receives second retransmission indication information from the receiving device.

[0234] 607. The transmitting device performs LDPC encoding on the information bit sequence according to the third check matrix to obtain a third codeword of a third code rate.

[0235] The third check matrix is ​​read from the mother matrix. The size of the third check matrix can be (p+y) rows and (q+y) columns, where y>h and y is an integer. In addition, the (p+y) rows are rows 1 to (p+y) of the eighth matrix.

[0236] For example, if p = 4, q = 24, and y = 100, then 104 rows and 124 columns are read from the eighth matrix to obtain a third parity check matrix. The third parity check matrix is ​​used to perform LDPC encoding on the information bit sequence to obtain a third codeword. The code rate of the third codeword is 20 / 124.

[0237] It should be understood that the third check matrix, the second check matrix and the first check matrix are read from the same mother matrix.

[0238] It can be seen that as the number of retransmissions increases, the number of check bits continues to increase and the channel coding rate continues to decrease, thereby improving the decoding success rate of the receiving device.

[0239] 608. The transmitting device sends the third codeword.

[0240] Below Figure 6 The process shown is described as an example.

[0241] For example, in step 601, the transmitting device reads a first parity check matrix from the mother matrix and performs LDPC encoding on an information bit sequence of length K to obtain M1 parity check bits. The length of the first codeword sent by the transmitting device is N, where N = K + M1. That is, the first codeword includes the K information bits and the M1 parity check bits.

[0242] If the receiving device does not correctly decode the received codeword corresponding to the first codeword, it requests the transmitting device to retransmit. In step 604, the transmitting device reads a second parity check matrix from the mother matrix and uses the second parity check matrix to perform LDPC encoding on the K information bits to obtain the M1 parity check bits. Furthermore, the (K+M1) bits are encoded based on the rows and columns expanded by the second parity check matrix relative to the first parity check matrix to obtain M2 parity check bits. The receiving device retransmits the M2 parity check bits. That is, the M2 parity check bits are the second codeword.

[0243] Optionally, in another implementation, after the transmitting device sends the first codeword, it stores the M1 check bits. If the first codeword is not correctly decoded, the transmitting device retransmits. Specifically, the transmitting device performs LDPC encoding on the (K+M1) bits according to a second parity check matrix to obtain the M2 check bits. The transmitting device sends the M2 check bits.

[0244] In an embodiment of the present application, after a transmission fails, the transmitting device can increase the number of redundant bits by reading a check matrix corresponding to a lower code rate from the mother matrix and using the check matrix corresponding to the lower code rate to encode the information bit sequence, thereby reducing the code rate of the encoded codeword and improving the success rate of decoding by the receiving device.

[0245] Similarly, as the number of retransmissions increases, the channel coding rate continues to decrease until the receiving device successfully decodes the data, or until the set maximum number of retransmissions is reached.

[0246] It can be understood that the transmitting device reads the check matrix corresponding to the lower code rate from the mother matrix, which is actually a process of continuously expanding the basic matrix to obtain a matrix that not only completely contains the basic matrix but also expands to the right to obtain more columns and expands downward to obtain more rows.

[0247] For example, taking the mother matrix shown in equations (1)-(8) above as an example, when the transmitting device only reads the basic matrix as the check matrix, the code rate of the codeword obtained by the transmitting device through LDPC encoding of the information bit sequence is the largest. For example, the code rate corresponding to the basic matrix in equation (1) or equation (2) is 1 / 2, the code rate corresponding to the basic matrix in equation (3) or equation (4) is 2 / 3, the code rate corresponding to the basic matrix in equation (5) or equation (6) is 3 / 4, and the code rate corresponding to the basic matrix in equation (7) or equation (8) is 5 / 6. When the transmitting device reads the entire mother matrix as the check matrix, the code rate of the codeword obtained by the transmitting device through LDPC encoding of the information bit sequence is the smallest. For example, the code rate corresponding to the mother matrix of formula (2) is 12 / 124=0.097, the code rate corresponding to the mother matrix of formula (4) is 16 / 124=0.129, the code rate corresponding to the mother matrix of formula (6) is 18 / 124=0.145, and the code rate corresponding to the mother matrix of formula (8) is 20 / 124=0.161.

[0248] It should be understood that the mother matrix provided in this application is also applicable to decoding of a receiving device.

[0249] For each transmission (first transmission or retransmission), the receiving device uses the same check matrix as the sending end for decoding. Figure 7 Provide explanation.

[0250] See also Figure 7 , Figure 7 This is a flowchart of the encoding and decoding of the LDPC code provided by this application.

[0251] Optionally, the operations or processing performed by the receiving device in method 700 may be performed by the receiving device, or by a chip or circuit system disposed within the receiving device. The circuit system may be, for example, an integrated circuit or a logic circuit. The chip may be, for example, a system on a chip (SoC) chip or a baseband modem chip, etc., which are not limited herein. The following description uses the receiving device as an example.

[0252] The receiving device can be a terminal device or a network device. It should be understood that the receiving device in the embodiments of the present application is also an encoding device. For example, in uplink transmission, the sending device is a terminal device and the receiving device is a network device. In downlink transmission, the sending device is a network device and the receiving device is a terminal device.

[0253] 710. The transmitting device performs LDPC encoding on the information bit sequence according to the first check matrix to obtain a first codeword.

[0254] 720. The transmitting device sends a first codeword.

[0255] The receiving device receives a first channel receiving sequence from the transmitting device.

[0256] Among them, steps 710-720 refer to the above Figure 6 Steps 601-602 in the above are not described in detail here.

[0257] 730. The receiving end device determines a first log-likelihood ratio (LLR) sequence corresponding to the first channel reception sequence, and decodes the first LLR sequence according to a first parity check matrix.

[0258] The first check matrix is ​​obtained by reading i rows and j columns from the mother matrix. The mother matrix includes a basic matrix, an extended matrix, a first fixed matrix, and a second fixed matrix. The basic matrix is ​​located at the upper left corner of the mother matrix, the extended matrix is ​​located at the lower left corner of the mother matrix, the first fixed matrix is ​​located at the upper right corner of the mother matrix, and the second fixed matrix is ​​located at the lower right corner of the mother matrix. The basic matrix and the extended matrix have the same number of columns, and the first fixed matrix and the second fixed matrix have the same number of columns. The basic matrix has the same number of rows as the first fixed matrix, and the extended matrix and the second fixed matrix have the same number of rows. i = p + k, j = q + k, p and q are the number of rows and columns of the basic matrix respectively, k ≥ 0, and i, j, p, q, and k are all integers.

[0259] 740. If the decoding is successful, the receiving device outputs the decoding result.

[0260] Optionally, if the receiving device makes a decoding error, the receiving device sends retransmission indication information to the sending device to request the sending device to retransmit, as shown in steps 750-770 below.

[0261] In addition, if decoding fails, the receiving device saves the first LLR sequence to be combined with a subsequently received retransmitted LLR sequence for decoding.

[0262] 750. The receiving device sends retransmission indication information to the transmitting device. The transmitting device receives the retransmission indication information from the receiving device.

[0263] 760. The transmitting device performs LDP encoding on the information bit sequence according to the second check matrix to obtain a second codeword.

[0264] 770. The transmitting device sends a second codeword.

[0265] Correspondingly, the receiving end device receives the second channel receiving sequence.

[0266] Steps 760-770 can be found in Figure 6 Steps 604-605 in the above are not described in detail here.

[0267] 780. The receiving end device determines a second LLR sequence corresponding to the second channel reception sequence, and decodes the combined LLR sequence according to the second parity check matrix.

[0268] The combined LLR sequence is obtained by combining the first LLR sequence and the retransmitted second LLR sequence. Specifically, the first LLR sequence and the second LLR sequence are combined bit by bit. The LLR values ​​at the same position index in the second LLR sequence and the first LLR sequence are combined, while the LLR values ​​at different index positions are retained.

[0269] For example, the length of the first LLR sequence is 6, and the index positions are 1, 2, 3, 4, and 5, and the corresponding LLR values ​​are LLR 11 ,LLR 12, LLR 13, LLR 14, LLR 15 The length of the second LLR sequence is 6, and the index positions are 3, 4, 5, 6, and 7, and the corresponding LLR values ​​are LLR 23 ,LLR 24 , LLR 25 , LLR 26 ,LLR 27 Therefore, the combined LLR sequence is {LLR 11 ,LLR 12, LLR 13 +LLR23, LLR 14 +LLR 24, LLR 15 +LLR 25 , LLR 26 ,LLR 27}, where the addition of LLR values ​​is binary addition.

[0270] The second check matrix is ​​obtained from the mother matrix with w rows and z columns, wherein w=p+h, z=q+h, h>k, and w, z and h are all positive integers.

[0271] Furthermore, if the receiving end device successfully decodes the combined LLR sequence according to the second parity check matrix, the decoding result is output. If the receiving end device fails to decode the combined LLR sequence according to the second parity check matrix, the next retransmission is performed.

[0272] And so on, until the decoding is successful or the maximum number of retransmissions is reached, then the decoding fails.

[0273] It can be seen that after a transmission failure, the transmitting device can increase the number of redundant bits by reading a parity check matrix corresponding to a lower code rate from the mother matrix and using this parity check matrix to encode the information bit sequence, thereby reducing the code rate of the encoded codeword. Correspondingly, for the first transmission of data, the receiving device reads the same parity check matrix used by the transmitting device from the mother matrix and decodes the received LLR sequence. If the initial transmission fails, the receiving device reads the parity check matrix corresponding to the code rate used by the transmitting device for retransmission from the mother matrix and decodes the combined LLR sequence. Since retransmission adds incremental redundancy check bits to the information bit sequence, the channel coding rate is reduced. Therefore, the decoding success rate of the receiving device can be improved, the number of retransmissions can be reduced, the retransmission delay can be reduced, and the decoding performance can be improved.

[0274] The above describes in detail the LDPC encoding method provided by this application. According to the encoding method provided by this application, multiple code rates can be compatible. In the IR HARQ mechanism, LDPC encoding can be performed by reading the check matrix corresponding to the required code rate from the mother matrix. As the number of retransmissions increases, more incremental redundant bits can be obtained, thereby continuously reducing the code rate to increase the probability of successful decoding by the receiving device and improve decoding performance.

[0275] See also Figure 8 , Figure 8 The performance curve of an embodiment of the present application at various compatible bit rates is shown. Figure 8As shown, the horizontal axis represents the corresponding bit rate, and the vertical axis represents the frame error ratio (FER) equal to 10 -2 The distance between the required signal-to-noise ratio (SNR) and the channel capacity of the corresponding bit rate, that is, the distance between the decoding threshold and the channel capacity. Figure 8 In the embodiment of the present invention, the basic matrix H corresponding to the code rate 1 / 2 is MC (1 / 2) As shown in Table 1, the basic matrix H corresponding to the code rate 2 / 3 MC (2 / 3) As shown in Table 5, the basic matrix H corresponding to the code rate 3 / 4 MC (3 / 4) As shown in Table 7, the basic matrix H corresponding to the code rate 5 / 6 MC (5 / 6)As shown in Table 9.

[0276] See also Figure 9 , Figure 9 FIG shows the performance curve of another embodiment of the present application at various compatible bit rates. Figure 9 As shown, the horizontal axis represents the corresponding bit rate, and the vertical axis represents FER equal to 10 -2 The distance between the required SNR and the channel capacity of the corresponding code rate. Figure 8 In the embodiment of the present invention, the basic matrix H corresponding to the code rate 1 / 2 is MC (1 / 2) As shown in Table 4, the basic matrix H corresponding to the code rate 2 / 3 MC (2 / 3) As shown in Table 6, the basic matrix H corresponding to the code rate 3 / 4 MC (3 / 4) As shown in Table 8, the basic matrix H corresponding to the code rate 5 / 6 MC (5 / 6)As shown in Table 10.

[0277] from Figure 8 and Figure 9 It can be seen from the performance curve shown that when the mother matrix provided in the embodiment of the present application is used for LDPC encoding, the rate compatibility scheme at each code rate is close to the throughput of 5G LDPC.

[0278] in, Figure 8 and Figure 9 In the 5G LDPC throughput, Figure 5 The curves corresponding to 5G NR (BG1) or 5G NR (BG2) are shown in FIG. BG1 means that the cyclic shift matrix of the basic matrix of the LDPC code adopts the BG1 matrix, and BG2 means that the cyclic shift matrix of the basic matrix of the LDPC code adopts the BG2 matrix.

[0279] Figure 8 or Figure 9The channel in can be a binary input additive white Gaussian noise (BAWAN) channel.

[0280] It should be understood that BG represents a base graph, which can be used to represent a base matrix of a cyclic shift matrix.

[0281] In addition, “ortho” is an abbreviation of orthogonal, and “non ortho” is an abbreviation of non-orthogonal.

[0282] In addition, Wifi code refers to the performance curve of the wifi code obtained by using the coding scheme of the existing WLAN standard.

[0283] In addition, since the decoder of the present application reuses the existing WLAN LDPC code as the core, the complexity of implementation can be effectively reduced.

[0284] The above describes in detail the encoding method of the LDPC code provided by the present application. The following describes the wireless communication device provided by the present application.

[0285] See also Figure 10 , Figure 10 This is a schematic block diagram of a communication device 600 provided in this application. Figure 10 As shown, the communication device 600 includes a processing unit 610 and a transceiver unit 620 .

[0286] A processing unit 610 is configured to perform LDPC encoding on an information bit sequence according to a first check matrix to obtain a first codeword of a first code rate, wherein the first check matrix is ​​obtained by reading i rows and j columns from a mother matrix, the mother matrix includes a base matrix, an extended matrix, a first fixed matrix, and a second fixed matrix, the base matrix is ​​located at the upper left corner of the mother matrix, the extended matrix is ​​located at the lower left corner of the mother matrix, the first fixed matrix is ​​located at the upper right corner of the mother matrix, and the second fixed matrix is ​​located at the lower right corner of the mother matrix, the base matrix and the first fixed matrix have the same number of rows, the extended matrix and the second fixed matrix have the same number of columns, the extended matrix and the base matrix have the same number of columns, and the first fixed matrix and the second fixed matrix have the same number of columns, i=p+k, j=q+k, p and q are the number of rows and columns of the base matrix, respectively, k≥0, and i, j, p, q, and k are all integers;

[0287] The transceiver unit 620 is configured to send the first codeword.

[0288] Optionally, in one embodiment, the transceiver unit 620 is further configured to receive retransmission indication information;

[0289] The processing unit 610 is further configured to perform LDPC encoding on the information bit sequence to obtain a second codeword at a second code rate, wherein the second check matrix is ​​obtained by reading w rows and z columns from the mother matrix, where w = p + h, z = q + h, and h > k, and w, z, and h are all positive integers;

[0290] The transceiver unit 620 is further configured to send the second codeword.

[0291] Optionally, the transceiver unit 620 may be replaced by a sending unit or a receiving unit. For example, when the transceiver unit 620 performs a sending action, it may be replaced by a sending unit. When the transceiver unit 620 performs a receiving action, it may be replaced by a receiving unit.

[0292] Optionally, the communication apparatus 600 may be a transmitting end device, or the communication apparatus 600 may be a device, module, etc. inside the transmitting end device that has the functions of implementing the embodiments of the various methods.

[0293] In one implementation, communication device 600 is the transmitting device in each of the above-mentioned method embodiments. Communication device 600 may have any of the functions of the transmitting device in each of the method embodiments. In this case, processing unit 610 may be a processor. Transceiver unit 620 may be a transceiver. The transceiver may specifically include a receiver and a transmitter. The receiver is configured to perform a receiving function, and the transmitter is configured to perform a transmitting function.

[0294] Alternatively, in another implementation, the communication device 600 may be a circuit system in a transmitting device. In this case, the processing unit 610 may be a chip, a logic circuit, an integrated circuit, a processing circuit, or a system-on-chip (SoC) chip, and the transceiver unit 620 may be a communication interface, which may be an interface circuit, an input / output interface, or the like.

[0295] In the above embodiments, the functions of the processing unit 610 may be implemented by hardware, or by hardware executing corresponding software.

[0296] For example, the processing unit 610 may include one or more processors configured to read and execute computer programs or instructions stored in a memory, so that the communication device 600 performs the operations and / or processes performed by the transmitting end device in each method embodiment. The memory is located outside the one or more processors.

[0297] Furthermore, the processing unit 610 may also include one or more memories, and the one or more processors and the one or more memories are connected through circuits / wires. The one or more processors can read the computer programs or instructions stored in the one or more memories, so that the communication device 600 performs the operations and / or processing performed by the sending end device in the various method embodiments of the present application.

[0298] For another example, the processing unit 610 is a processor, and the transceiver unit 620 can be an interface circuit. The interface circuit is used to receive computer code or instructions and transmit them to the processor. The processor executes the computer code or instructions, so that the communication device 600 performs the operations and / or processing performed by the transmitting end device in the various method embodiments of the present application.

[0299] See also Figure 11 , Figure 11 800 is a schematic block diagram of a communication device 800 provided in this application. Figure 11 As shown, the communication device 800 includes a processing unit 810 and a transceiver unit 820 .

[0300] The transceiver unit 820 is configured to receive a first channel receive sequence from a transmitting end device;

[0301] Processing unit 810 decodes a first LLR sequence corresponding to a first channel received sequence according to a first parity check matrix, wherein the first parity check matrix is ​​obtained by reading i rows and j columns from a mother matrix, the mother matrix includes a base matrix, an extended matrix, a first fixed matrix, and a second fixed matrix, the base matrix is ​​located at the upper left corner of the mother matrix, the extended matrix is ​​located at the lower left corner of the mother matrix, the first fixed matrix is ​​located at the upper right corner of the mother matrix, and the second fixed matrix is ​​located at the lower right corner of the mother matrix, the number of rows of the base matrix is ​​equal to the number of rows of the first fixed matrix, the number of rows of the extended matrix is ​​equal to the number of rows of the second fixed matrix, the number of columns of the extended matrix is ​​equal to the number of columns of the base matrix, and the number of columns of the first fixed matrix is ​​equal to the number of columns of the second fixed matrix, i=p+k, j=q+k, p and q are the number of rows and columns of the base matrix, respectively, k≥0, and i, j, p, q, and k are all integers;

[0302] The transceiver unit 820 is further configured to output a decoding result if the processing unit 810 successfully decodes the first LLR sequence.

[0303] Optionally, in one embodiment, the transceiver unit 820 is further configured to send retransmission indication information and receive a second channel receive sequence from the transmitting end device when the processing unit 810 fails to decode the first LLR sequence;

[0304] The processing unit 810 is further configured to decode the combined LLR sequence according to a second check matrix, where the combined LLR sequence is obtained by combining a second LLR sequence corresponding to the second channel receive sequence and the first LLR sequence, and the second check matrix is ​​obtained by reading w rows and z columns from the mother matrix, where w = p + h, z = q + h, and h > k, and w, z, and h are all positive integers.

[0305] Optionally, the transceiver unit 820 may be replaced by a sending unit or a receiving unit. For example, when the transceiver unit 820 performs a sending action, it may be replaced by a sending unit. When the transceiver unit 820 performs a receiving action, it may be replaced by a receiving unit.

[0306] Optionally, the communication apparatus 800 may be a receiving-end device, or the communication apparatus 800 may be a device, module, etc. inside the receiving-end device that has the functions of implementing the embodiments of the various methods.

[0307] In one implementation, communication device 800 is the receiving device in each of the above-mentioned method embodiments. Communication device 800 may have any of the functions of the receiving device in each of the method embodiments. In this case, processing unit 810 may be a processor, and transceiver unit 820 may be a transceiver. The transceiver may specifically include a receiver and a transmitter. The receiver is configured to perform a receiving function, and the transmitter is configured to perform a transmitting function.

[0308] In another implementation, the communication device 800 may be a circuit system in a receiving device. In this case, the processing unit 810 may be a chip, a logic circuit, an integrated circuit, a processing circuit, or a system-on-chip (SoC) chip, and the transceiver unit 820 may be a communication interface, which may be an interface circuit, an input / output interface, or the like.

[0309] In the above embodiments, the functions of the processing unit 810 may be implemented by hardware, or by hardware executing corresponding software.

[0310] For example, the processing unit 810 may include one or more processors configured to read and execute computer programs or instructions stored in a memory, so that the communication apparatus 800 performs the operations and / or processes performed by the receiving device in each method embodiment. The memory is located outside the one or more processors.

[0311] Furthermore, the processing unit 810 may also include one or more memories, and the one or more processors and the one or more memories are connected through circuits / wires. The one or more processors can read the computer programs or instructions stored in the one or more memories, so that the communication device 800 performs the operations and / or processing performed by the receiving device in the various method embodiments of the present application.

[0312] For another example, the processing unit 810 is a processor, and the transceiver unit 820 is an interface circuit. The interface circuit is used to receive computer code or instructions and transmit them to the processor. The processor executes the computer code or instructions, so that the communication device 800 performs the operations and / or processing performed by the receiving device in the various method embodiments of the present application.

[0313] Optionally, the memory and the memory in the above-mentioned device embodiments may be physically independent units, or the memory may be integrated with the processor.

[0314] In addition, the present application also provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the computer executes the operations and / or processing performed by the transmitting device in the LDPC code encoding method provided in the present application.

[0315] The present application also provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the computer executes the operations and / or processing performed by the receiving device in the LDPC code decoding method provided in the present application.

[0316] The present application also provides a computer program product, which includes computer code or instructions. When the computer code or instructions are run on a computer, the LDPC code encoding method of the method embodiment of the present application is implemented.

[0317] The present application also provides a computer program product, which includes computer code or instructions. When the computer code or instructions are executed on a computer, the method for decoding the LDPC code of the method embodiment of the present application is implemented.

[0318] The present application also provides a communication device, comprising a processor and an interface circuit, wherein the interface circuit is used to receive computer code or instructions and transmit them to the processor, and the processor is used to run the computer code or instructions so that the communication device performs the operations and / or processing performed by the transmitting device in the LDPC encoding method provided in the present application.

[0319] The present application also provides a communication device, comprising a processor and an interface circuit, wherein the interface circuit is used to receive computer code or instructions and transmit them to the processor, and the processor is used to run the computer code or instructions so that the communication device performs the operations and / or processing performed by the receiving device in the LDPC encoding method provided in the present application.

[0320] The present application also provides a chip comprising one or more processors. The one or more processors are configured to execute a computer program stored in a memory to perform the operations and / or processing performed by a transmitting device in any one of the method embodiments. The memory is provided independently of the chip.

[0321] Furthermore, the chip may further include one or more communication interfaces. The one or more communication interfaces may be input / output interfaces, interface circuits, etc. Furthermore, the chip may further include one or more memories.

[0322] The present application also provides a chip comprising one or more processors. The one or more processors are configured to execute a computer program stored in a memory to perform the operations and / or processing performed by a receiving device in any one of the method embodiments. The memory is provided independently of the chip.

[0323] Furthermore, the chip may further include one or more communication interfaces. The one or more communication interfaces may be input / output interfaces, interface circuits, etc. Furthermore, the chip may further include one or more memories.

[0324] The present application also provides a wireless communication system, including a transmitting device and a receiving device in the embodiment of the present application. Optionally, one of the transmitting device and the receiving device is a network device (eg, a base station), and the other is a terminal device.

[0325] The processor in the embodiment of the present application can be an integrated circuit chip with the ability to process signals. During implementation, each step of the above method embodiment can be completed by the hardware integrated logic circuit in the processor or by instructions in the form of software. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware coding processor, or can be executed by a combination of hardware and software modules in the coding processor. The software module can be located in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0326] The memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DRRAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0327] As used in this specification, the terms "unit," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device may be a component. One or more components may reside in a process and / or an execution thread. A component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may communicate via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component across a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0328] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0329] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0330] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0331] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0332] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0333] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0334] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for encoding an LDPC code, characterized in that: include: Performing low-density parity check (LDPC) coding on an information bit sequence according to a first check matrix to obtain a first codeword of a first code rate, wherein the first check matrix is ​​obtained by reading i rows and j columns from a mother matrix, the mother matrix includes a basic matrix, an extended matrix, a first fixed matrix, and a second fixed matrix, the basic matrix is ​​located at the upper left corner of the mother matrix, the extended matrix is ​​located at the lower left corner of the mother matrix, the first fixed matrix is ​​located at the upper right corner of the mother matrix, and the second fixed matrix is ​​located at the lower right corner of the mother matrix, the number of rows of the basic matrix is ​​equal to the number of rows of the first fixed matrix, the number of rows of the extended matrix is ​​equal to the number of rows of the second fixed matrix, the number of columns of the extended matrix is ​​equal to the number of columns of the basic matrix, and the number of columns of the first fixed matrix is ​​equal to the number of columns of the second fixed matrix, i=p+k, j=q+k, p and q are the number of rows and columns of the basic matrix, respectively, k≥0, and i, j, p, q, and k are all integers; Sending the first codeword; wherein: (1) The code rate corresponding to the basic matrix is ​​1 / 2, and the mother matrix is ​​shown as follows: Among them, H(1 / 2) is the mother matrix, H MC (1 / 2) is the basic matrix, H IR (1 / 2) is the expansion matrix, the H IR The size of (1 / 2) is r rows and 24 columns, 1 / 2 represents the code rate, 0 12×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 12×r represents a zero matrix with a size of 12 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table A represents the first matrix with a size of 100 rows and 24 columns. IR (1 / 2) Read r rows and 24 columns from the first matrix, where r rows are any r rows among the 100 rows of the first matrix. Table A is as follows: Table A The mth element from top to bottom in the column where d is located represents the row weight of the mth row of the first matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the first matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the first matrix is ​​b, the remaining positions of the first matrix are all-zero matrices, the column index of the first matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers; or, (2) The code rate corresponding to the basic matrix is ​​1 / 2, and the mother matrix is ​​shown as follows: Among them, H(1 / 2) is the mother matrix, H MC (1 / 2) is the basic matrix, H IR (1 / 2) is the expansion matrix, the H IR The size of (1 / 2) is r rows and 24 columns, 1 / 2 represents the code rate, 0 12×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 12×r represents a zero matrix with a size of 12 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table B represents a second matrix with a size of 100 rows and 24 columns. IR (1 / 2) Read r rows and 24 columns from the second matrix, where r rows are any r rows among the 100 rows of the second matrix. Table B is as follows: Table B The mth element from top to bottom in the column where d is located represents the row weight of the mth row of the second matrix, and the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the second matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the second matrix is ​​b, and the remaining positions of the second matrix are all-zero matrices. The column index of the second matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers; or, (3) The code rate corresponding to the basic matrix is ​​2 / 3, and the mother matrix is ​​shown as follows: Among them, H(2 / 3) is the mother matrix, H MC (2 / 3) is the basic matrix, H IR (2 / 3) is the expansion matrix, the H IR The size of (2 / 3) is r rows and 8 columns, 2 / 3 represents the bit rate, 0 8×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 8×r Represents an all-zero matrix with a size of 8 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table C represents a third matrix with a size of 100 rows and 24 columns. IR (2 / 3) Read r rows and 24 columns from the third matrix, where r rows are any r rows among the 100 rows of the third matrix. Table C is as follows: Table C Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the third matrix, and the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the third matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the third matrix is ​​b, and the remaining positions of the third matrix are all-zero matrices, the column index of the third matrix starts from 0, n∈{1,2,3,4,5,6,7}, m is a positive integer, and a and b are both integers; or, (4) The code rate corresponding to the basic matrix is ​​2 / 3, and the mother matrix is ​​shown as follows: Among them, H(2 / 3) is the mother matrix, H MC (2 / 3) is the basic matrix, H IR (2 / 3) is the expansion matrix, H IR The size of (2 / 3) is r rows and 24 columns, 2 / 3 represents the code rate, 0 8×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 8×r Represents an all-zero matrix with a size of 8 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table D represents the fourth matrix with a size of 100 rows and 24 columns. IR (2 / 3) Read r rows and 24 columns from the fourth matrix, where r rows are any r rows among the 100 rows of the fourth matrix, and H IR The 24 columns of (2 / 3) are the 24 columns of the fourth matrix, and the table D is as follows: Table D Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the fourth matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the fourth matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the fourth matrix is ​​b, the remaining positions of the fourth matrix are all-zero matrices, the column index of the fourth matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers; or, (5) The code rate corresponding to the basic matrix is ​​3 / 4, and the mother matrix is ​​shown as follows: Among them, H(3 / 4) is the mother matrix, H MC (3 / 4) is the basic matrix, H IR (3 / 4) is the expansion matrix, the H IR The size of (3 / 4) is r rows and 24 columns, 3 / 4 represents the bit rate, 0 6×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 6×r represents a zero matrix with 6 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table E represents the fifth matrix with a size of 100 rows and 24 columns. IR (3 / 4) Read r rows and 24 columns from the fifth matrix, where r rows are any r rows among the 100 rows of the fifth matrix. Table E is shown below: Table E Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the fifth matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the fifth matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the fifth matrix is ​​b, the remaining positions of the fifth matrix are all-zero matrices, the column index of the fifth matrix starts from 0, n∈{1,2,3,4,5,6,7,8,9}, m is a positive integer, and a and b are both integers; or, (6) The code rate corresponding to the basic matrix is ​​3 / 4, and the mother matrix is ​​shown as follows: Among them, H(3 / 4) is the mother matrix, H MC (3 / 4) is the basic matrix, H IR (3 / 4) is the expansion matrix, H IR The size of (3 / 4) is r rows and 24 columns, 3 / 4 represents the bit rate, 0 6×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 6×r represents a zero matrix with 6 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table F represents the sixth matrix with a size of 100 rows and 24 columns. MC (3 / 4) is obtained by reading r rows and 24 columns from the sixth matrix, where the r rows are any r rows among the 100 rows of the sixth matrix. The table F is as follows: Table F Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the sixth matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the sixth matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the sixth matrix is ​​b, the remaining positions of the sixth matrix are all-zero matrices, the column index of the sixth matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers; or, (7) The code rate corresponding to the basic matrix is ​​5 / 6, and the mother matrix is ​​shown as follows: Among them, H(5 / 6) is the mother matrix, H MC (5 / 6) is the basic matrix, H IR (5 / 6) is the expansion matrix, the H IR The size of (5 / 6) is r rows and 24 columns, 5 / 6 represents the bit rate, 0 4×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 4×r Represents a zero matrix with a size of 4 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table G represents the seventh matrix with a size of 100 rows and 24 columns. IR (5 / 6) r rows and 24 columns are read from the seventh matrix, where r rows are any r rows among the 100 rows of the seventh matrix. The table G is as follows: Table G Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the seventh matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the seventh matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the seventh matrix is ​​b, the remaining positions of the seventh matrix are all-zero matrices, the column index of the seventh matrix starts from 0, n∈{1,2,3,4,5,6,7,8,9,10,11}, m is a positive integer, and a and b are both integers; or, (8) The code rate corresponding to the basic matrix is ​​5 / 6, and the mother matrix is ​​shown as follows: Among them, H(5 / 6) is the mother matrix, H MC (5 / 6) is the basic matrix, H IR (5 / 6) is the expansion matrix, H IR The size of (5 / 6) is r rows and 24 columns, 5 / 6 represents the bit rate, 0 4×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 4×r Represents a zero matrix with a size of 4 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table H represents the eighth matrix with a size of 100 rows and 24 columns. IR (5 / 6) r rows and 24 columns are read from the eighth matrix, where r rows are any r rows among the 100 rows of the eighth matrix. The table H is as follows: Table H Among them, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the eighth matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the eighth matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the eighth matrix is ​​b, the remaining positions of the eighth matrix are all all-zero matrices, the column index of the eighth matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers.

2. The method according to claim 1, characterized in that The method further comprises: receiving retransmission indication information; Performing LDPC encoding on the information bit sequence according to a second check matrix to obtain a second codeword at a second code rate, wherein the second check matrix is ​​obtained by reading w rows and z columns from the mother matrix, where w = p + h, z = q + h, and h > k, and w, z, and h are all positive integers; The second codeword is sent.

3. A communication device, characterized in that: include: a processing unit, configured to perform low-density parity check (LDPC) encoding on an information bit sequence according to a first check matrix to obtain a first codeword of a first code rate, wherein the first check matrix is ​​obtained by reading i rows and j columns from a mother matrix, the mother matrix includes a basic matrix, an extended matrix, a first fixed matrix, and a second fixed matrix, the basic matrix is ​​located at the upper left corner of the mother matrix, the extended matrix is ​​located at the lower left corner of the mother matrix, the first fixed matrix is ​​located at the upper right corner of the mother matrix, and the second fixed matrix is ​​located at the lower right corner of the mother matrix, the basic matrix and the first fixed matrix have the same number of rows, the extended matrix and the second fixed matrix have the same number of columns, the extended matrix and the basic matrix have the same number of columns, and the first fixed matrix and the second fixed matrix have the same number of columns, i=p+k, j=q+k, p and q are the number of rows and columns of the basic matrix, respectively, k≥0, and i, j, p, q, and k are all integers; a transceiver unit, configured to send the first codeword; wherein: (1) The code rate corresponding to the basic matrix is ​​1 / 2, and the mother matrix is ​​shown as follows: Among them, H(1 / 2) is the mother matrix, H MC (1 / 2) is the basic matrix, H IR (1 / 2) is the expansion matrix, the H IR The size of (1 / 2) is r rows and 24 columns, 1 / 2 represents the code rate, 0 12×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 12×r represents a zero matrix with a size of 12 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table A represents the first matrix with a size of 100 rows and 24 columns. IR (1 / 2) Read r rows and 24 columns from the first matrix, where r rows are any r rows among the 100 rows of the first matrix. Table A is as follows: Table A The mth element from top to bottom in the column where d is located represents the row weight of the mth row of the first matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the first matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the first matrix is ​​b, the remaining positions of the first matrix are all-zero matrices, the column index of the first matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers; or, (2) The code rate corresponding to the basic matrix is ​​1 / 2, and the mother matrix is ​​shown as follows: Among them, H(1 / 2) is the mother matrix, H MC (1 / 2) is the basic matrix, H IR (1 / 2) is the expansion matrix, the H IR The size of (1 / 2) is r rows and 24 columns, 1 / 2 represents the code rate, 0 12×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 12×r represents a zero matrix with a size of 12 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table B represents a second matrix with a size of 100 rows and 24 columns. IR (1 / 2) Read r rows and 24 columns from the second matrix, where r rows are any r rows among the 100 rows of the second matrix. Table B is as follows: Table B The mth element from top to bottom in the column where d is located represents the row weight of the mth row of the second matrix, and the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the second matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the second matrix is ​​b, and the remaining positions of the second matrix are all-zero matrices. The column index of the second matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers; or, (3) The code rate corresponding to the basic matrix is ​​2 / 3, and the mother matrix is ​​shown as follows: Among them, H(2 / 3) is the mother matrix, H MC (2 / 3) is the basic matrix, H IR (2 / 3) is the expansion matrix, the H IR The size of (2 / 3) is r rows and 8 columns, 2 / 3 represents the bit rate, 0 8×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 8×r Represents an all-zero matrix with a size of 8 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table C represents a third matrix with a size of 100 rows and 24 columns. IR (2 / 3) Read r rows and 24 columns from the third matrix, where r rows are any r rows among the 100 rows of the third matrix. Table C is as follows: Table C Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the third matrix, and the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the third matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the third matrix is ​​b, and the remaining positions of the third matrix are all-zero matrices, the column index of the third matrix starts from 0, n∈{1,2,3,4,5,6,7}, m is a positive integer, and a and b are both integers; or, (4) The code rate corresponding to the basic matrix is ​​2 / 3, and the mother matrix is ​​shown as follows: Among them, H(2 / 3) is the mother matrix, H MC (2 / 3) is the basic matrix, H IR (2 / 3) is the expansion matrix, H IR The size of (2 / 3) is r rows and 24 columns, 2 / 3 represents the code rate, 0 8×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 8×r Represents an all-zero matrix with a size of 8 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table D represents the fourth matrix with a size of 100 rows and 24 columns. IR (2 / 3) Read r rows and 24 columns from the fourth matrix, where r rows are any r rows among the 100 rows of the fourth matrix, and H IR The 24 columns of (2 / 3) are the 24 columns of the fourth matrix, and the table D is as follows: Table D Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the fourth matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the fourth matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the fourth matrix is ​​b, the remaining positions of the fourth matrix are all-zero matrices, the column index of the fourth matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers; or, (5) The code rate corresponding to the basic matrix is ​​3 / 4, and the mother matrix is ​​shown as follows: Among them, H(3 / 4) is the mother matrix, H MC (3 / 4) is the basic matrix, H IR (3 / 4) is the expansion matrix, the H IR The size of (3 / 4) is r rows and 24 columns, 3 / 4 represents the bit rate, 0 6×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 6×r represents a zero matrix with 6 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table E represents the fifth matrix with a size of 100 rows and 24 columns. IR (3 / 4) Read r rows and 24 columns from the fifth matrix, where r rows are any r rows among the 100 rows of the fifth matrix. Table E is shown below: Table E Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the fifth matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the fifth matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the fifth matrix is ​​b, the remaining positions of the fifth matrix are all-zero matrices, the column index of the fifth matrix starts from 0, n∈{1,2,3,4,5,6,7,8,9}, m is a positive integer, and a and b are both integers; or, (6) The code rate corresponding to the basic matrix is ​​3 / 4, and the mother matrix is ​​shown as follows: Among them, H(3 / 4) is the mother matrix, H MC (3 / 4) is the basic matrix, H IR (3 / 4) is the expansion matrix, H IR The size of (3 / 4) is r rows and 24 columns, 3 / 4 represents the bit rate, 0 6×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 6×r represents a zero matrix with 6 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table F represents the sixth matrix with a size of 100 rows and 24 columns. MC (3 / 4) is obtained by reading r rows and 24 columns from the sixth matrix, where the r rows are any r rows among the 100 rows of the sixth matrix. The table F is as follows: Table F Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the sixth matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the sixth matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the sixth matrix is ​​b, the remaining positions of the sixth matrix are all-zero matrices, the column index of the sixth matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers; or, (7) The code rate corresponding to the basic matrix is ​​5 / 6, and the mother matrix is ​​shown as follows: Among them, H(5 / 6) is the mother matrix, H MC (5 / 6) is the basic matrix, H IR (5 / 6) is the expansion matrix, the H IR The size of (5 / 6) is r rows and 24 columns, 5 / 6 represents the bit rate, 0 4×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 4×r Represents a zero matrix with a size of 4 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table G represents the seventh matrix with a size of 100 rows and 24 columns. IR (5 / 6) r rows and 24 columns are read from the seventh matrix, where r rows are any r rows among the 100 rows of the seventh matrix. The table G is as follows: Table G Wherein, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the seventh matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the seventh matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the seventh matrix is ​​b, the remaining positions of the seventh matrix are all-zero matrices, the column index of the seventh matrix starts from 0, n∈{1,2,3,4,5,6,7,8,9,10,11}, m is a positive integer, and a and b are both integers; or, (8) The code rate corresponding to the basic matrix is ​​5 / 6, and the mother matrix is ​​shown as follows: Among them, H(5 / 6) is the mother matrix, H MC (5 / 6) is the basic matrix, H IR (5 / 6) is the expansion matrix, H IR The size of (5 / 6) is r rows and 24 columns, 5 / 6 represents the bit rate, 0 4×r is the first fixed matrix, I r×r is the second fixed matrix, the 0 4×r Represents a zero matrix with a size of 4 rows and r columns, the I r×r represents the identity matrix of size r rows and r columns, r ≥ 1, k ≤ r, r is an integer; Among them, "-" represents an all-zero matrix; The following table H represents the eighth matrix with a size of 100 rows and 24 columns. IR (5 / 6) r rows and 24 columns are read from the eighth matrix, where r rows are any r rows among the 100 rows of the eighth matrix. The table H is as follows: Table H Among them, the mth element from top to bottom in the column where d is located represents the row weight of the mth row of the eighth matrix, the nth element (a, b) from left to right corresponding to the row weight d of the mth row of the eighth matrix represents that the cyclic shift coefficient of the cyclic shift matrix with column index a in the mth row of the eighth matrix is ​​b, the remaining positions of the eighth matrix are all all-zero matrices, the column index of the eighth matrix starts from 0, n∈{1,2,3,4,5}, m is a positive integer, and a and b are both integers.

4. The communication device according to claim 3, wherein: The transceiver unit is further configured to receive retransmission indication information; The processing unit is further configured to perform LDPC encoding on the information bit sequence according to a second check matrix to obtain a second codeword at a second code rate, wherein the second check matrix is ​​obtained by reading w rows and z columns from the mother matrix, where w = p + h, z = q + h, h > k, and w, z, and h are all positive integers; The receiving transceiver unit is further configured to send the second codeword.

5. A communication device, characterized in that: The method comprises a processor and an interface circuit, wherein the interface circuit is used to receive an information bit sequence to be encoded and transmit the information bit sequence to the processor, and the processor executes the method according to claim 1 or 2 to obtain a codeword of a corresponding code rate; the interface circuit is also used to output the codeword.

6. A communication device, characterized in that: The communication device comprises at least one processor coupled to at least one memory, and the at least one processor is configured to execute a computer program or instruction stored in the at least one memory, so that the communication device performs the method according to claim 1 or 2.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions. When the computer instructions are executed on a computer, the method according to claim 1 or 2 is implemented.

8. A computer program product, characterized in that The computer program product comprises computer program codes or instructions, and when the computer program codes or instructions are run on a computer, the method according to claim 1 or 2 is implemented.

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