Techniques for coupling high bandwidth memory devices on silicon substrates and package substrates

Abstract

Techniques are disclosed for coupling high bandwidth memory devices on a silicon substrate and a package substrate. Examples include selectively activating input / output (I / O) contacts or command and address (CA) contacts on a bottom side of a logic layer of a high bandwidth device based on an operating mode. The I / O contacts and CA contacts are used to access one or more memory devices included in the high bandwidth memory device via one or more data lanes.

Description

Technical Field

[0001] The examples described in this article typically involve high-bandwidth memory. Background Technology

[0002] In computing systems such as System-on-Chip (SoC) or System-in-Package (SiP), memory devices with multiple tightly coupled memory elements or arrays are being developed and deployed to provide additional memory density to support various computing operations. These types of memory devices can be referred to as three-dimensional (3D) stacked memory or stacked memory. A common characteristic of these types of stacked memory is higher bandwidth memory.

[0003] Common deployments of high-bandwidth memory can include stacked layers or dies of dynamic random-access memory (DRAM), which may be referred to as high-bandwidth memory stacking devices or high-bandwidth memory packaging devices. High-bandwidth memory stacking devices or high-bandwidth memory packaging devices can be used to provide a large amount of computer or system memory within a single package on a package substrate. The package may also include components such as memory controllers, central processing units (CPUs), graphics processing units (GPUs), or other components. Attached Figure Description

[0004] Figure 1 Example first system is shown.

[0005] Figure 2 The example first subsystem is shown.

[0006] Figure 3 The example first operating mode is shown.

[0007] Figure 4 Example first redistribution scheme is shown.

[0008] Figure 5 An example redistributed layout scheme is shown.

[0009] Figure 6 An example of a second subsystem is shown.

[0010] Figure 7 Example of the second operating mode is shown.

[0011] Figure 8 Example of a second redistribution scheme is shown.

[0012] Figure 9 The example first logic flow is shown.

[0013] Figure 10 An example device is shown.

[0014] Figure 11Example of a second logical flow is shown.

[0015] Figure 12 An example storage medium is shown.

[0016] Figure 13 Example of a second system is shown. Detailed Implementation

[0017] In some examples, a high-bandwidth memory stack device, comprising a stack of four DRAM devices or dies with a logic layer, may include approximately 1000 input / output (I / O) contacts (e.g., metal bumps) for physical connection to a package substrate, which, for example, couples the high-bandwidth memory stack device to a CPU and / or GPU. Several other contacts for clock (CLK) signaling or command and address (CA) signaling may also have contacts for connection to the package substrate. The large number of I / O, CLK, and CA contacts in a relatively small area beneath the high-bandwidth memory stack device can result in very compact or small spacing between these contacts. Solutions involving expensive package interconnect technologies can be used to handle this compact spacing between contacts. For example, silicon interposers or silicon bridges, such as embedded multi-die interconnect bridges (EMIBs), can be one type of solution for handling compact spacing. While EMIB solutions can handle compact or small spacing in high-bandwidth memory stack devices, they force a straight-line connection between the high-bandwidth memory stack device and the CPU or GPU and limit the flexibility for routing package interconnect signals. This linear requirement and lack of flexibility regarding EMIB can create placement and die size conflicts for CPUs, GPUs, or other types of die packages that can be included in a SoC or SiP. Furthermore, using only silicon interposers to address the compact spacing of high-bandwidth memory stacks can increase costs to unacceptable levels.

[0018] Figure 1 Example system 100 is shown. In some examples, such as... Figure 1 As shown, system 100 includes a high-bandwidth memory (HBM) stack 105 coupled to a package substrate 140 via a redistribution layer 130. In some examples, the HBM stack 105 may include multiple layers of a memory device or die having a bottom or lower logic layer. For example, as... Figure 1As shown, HBM stack 105 includes DRAMs 110-1 to 110-n stacked on top of logic layer 120, where "n" represents any positive integer greater than 1. Logic layer 120 may include circuitry, logic, and / or features for facilitating access to / from DRAMs 110-1 to 110-n, as well as command and address signals associated with access to DRAMs 110-1 to 110-n. DRAMs 110-1 to 110-n may represent individual memory devices, each having multiple addressable memory arrays accessible via corresponding memory channels. Each memory channel may include a large number of I / O signal paths (e.g., 128). As described in more detail below, logic layer 120 may include circuitry, logic, and / or features capable of merging memory channels and / or reducing I / O signal paths to reduce the number of active connections on the bottom side of logic layer 120. Merged memory channels and / or reduced I / O signal paths can be routed via a reduced number of active connections on the bottom side of logic layer 120 to connect to package substrate 140 via redistribution layer 130, thereby coupling HBM stack 105 to a CPU or GPU (not shown), for example. In some examples, redistribution layer 130 may be part of or integrated with package substrate 140. In other examples, redistribution layer 130 may be a separate layer from package substrate 140, coupled or connected between logic layer 120 and package substrate 140.

[0019] According to some examples, merging memory channels and / or I / O signal paths can enable greater flexibility for package interconnects routed through redistribution layer 130. Merging memory channels and / or I / O signal paths can also reduce the problems posed by the compact contact spacing of contacts at the lower end or bottom side of logic layer 120. For example, by merging channels and / or I / O signals, as discussed in more detail below, a reduced number of contacts may be required to couple to package substrate 140 via redistribution layer 130. If contacts are removed from redistribution layer 130, the reduced number of contacts allows for increased contact spacing. Alternatively, unwanted contacts can be logically disconnected, electrically disconnected, or not connected. These logically disconnected or electrically disconnected contacts can reduce potential signal interference or heat problems associated with all active connections.

[0020] Examples are not limited to DRAM used in memory devices included in the HBM stack 105. As described herein, a memory device can refer to a non-volatile or volatile memory type. Some non-volatile memory types can be block-addressable, such as NAND or NOR technologies. Other non-volatile memory types can be byte- or block-addressable non-volatile memories with a 3-dimensional (3-D) crosspoint memory structure, including but not limited to chalcogenide phase change materials (e.g., chalcogenide glasses) referred to below as “3-D crosspoint memory”. Non-volatile memory types may also include other types of byte- or block-addressable non-volatile memory, such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level phase-change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, resistive memory (including metal oxide-based, oxygen vacancy-based and conductive bridge random access memory (CB-RAM)), spintronic magnetic junction memory, magnetic tunnel junction (MTJ) memory, domain wall (DW) and spin orbital transfer (SOT) memory, thyristor-based memory, magnetoresistive random access memory (MRAM) incorporating memristor technology, spin torque MRAM (STT-MRAM), or any combination of the above-mentioned memories.

[0021] The use of the terms "RAM" or "RAM device" in this document applies to any memory device that allows random access, whether volatile or non-volatile. The use of DRAM or Synchronous DRAM (SDRAM), DRAM device, or SDRAM device refers to a volatile random access memory device. The term SDRAM or DRAM can refer to the die itself, a memory product in a package comprising one or more dies, or both. In some examples, a system with volatile memory that needs to be refreshed may also include at least some non-volatile memory to support at least a minimum level of memory persistence.

[0022] Figure 2 An example subsystem 200 is shown. In some examples, subsystem 200 may represent a high-bandwidth memory stack device (e.g., Figure 1 This is a portion of the HBM stack 105 shown in the image. For these examples, such as... Figure 2As shown, subsystem 200 includes a first memory array 210-1 accessible via channel A and a second memory array 210-2 accessible via channel B. Data written to or read from memory array 210-1 can be routed via signal path included in [ChA]I / O 213 in response to command and address signals routed via signal path included in [ChA]CA 215. Similarly, data written to or read from memory array 210-2 can be routed via signal path included in [ChB]I / O 217 in response to command and address signals routed via [ChB]CA 219. Control 214-1, decoder 212-1, CA buffer 216-1, and first-in-first-out (FIFO) buffer 218-1 facilitate access to memory array 210-1. The controller 214-2, decoder 212-2, CA buffer 216-2, and FIFO buffer 218-2 facilitate access to the memory array 210-2.

[0023] Based on some examples, logic layer 220 can coordinate access to memory arrays 210-1 or 210-2. For the sake of brevity, Figure 2 Some components used for coordinating access to the DRAM array that can be included in the logic layer of the HBM stack are not shown. Figure 2 The example logic layer 220 shown may include merging logic 224 and mode register 222. Mode register 222 may be programmed or configured to indicate the operating mode of merging logic 224 to determine whether it is operating in full I / O mode or merged channel mode (e.g., a bit value "1" indicates merged channel or a value "0" indicates full I / O). Figure 2 The merged channel mode is described because there are no separate active connections for both channel A and channel B on the bottom side 221 of logic layer 220. Instead, the [ChB]I / O connection and CA connection are indicated as "no connection," meaning that these connections are neither electrically connected nor logically connected / inactive. Therefore, [ChA / B]I / O 223 and [ChA / B]CA 225 are routed via a merged connection, which would be a connection only for the [ChA]I / O connection and CA connection if subsystem 200 is in full I / O mode.

[0024] According to some examples, a full I / O mode may include 128 I / O connections for both channel A and channel B on the bottom side 221 of logic layer 220. For these examples, merging logic 224 may cause signals for the full 128 I / O connections per channel to be routed through logic layer 220 at a first operating frequency (e.g., 2 gigabit per second (GT / s)). For example, a first signal for the 128 I / O connections for channel A is routed through logic layer 220 to [ChA]I / O 213 at the first operating frequency. A second signal for the 128 I / O connections for channel B is also routed through logic layer 220 to [ChB]I / O 217 at the first operating frequency. In some examples, if the merged channel mode is enabled, the 128 I / O contacts are divided such that channel A has 64 active I / O contacts and [ChB] has 64 active I / O contacts. For these examples, merging logic 224 can compensate for the reduced I / O activity per channel by doubling the first operating frequency to produce a second operating frequency (e.g., 4GT / s), via which signals for each set of 64 I / O connections per channel are routed through logic layer 220. Therefore, between full I / O mode and merged channel mode, the corresponding memory arrays 210-1 and 210-2 can see almost no reduction in data rate per unit time.

[0025] Figure 3 Example operation mode 300 is shown. In some examples, such as... Figure 3 As shown, operation mode 300 may include full I / O mode 310 and merged channel mode 320. For these examples, Figure 3The components shown may represent at least a portion of the components used to route signals for the 128 I / O connections of both DQ[0:127](ChA) and DQ[0:127](ChB) through logic layer 220 to memory arrays 210-1 and 210-2. For example, components used for routing signals for the 128 I / O connections of DQ[0:127](ChA) may include a phase-locked loop (PLL) 302, a delay phase-locked loop (DLL) 304, a transmit (Tx) circuit 306A (for even bits), a Tx circuit 308A (for odd bits), a DQ strobe (DQS) generator 310, a Tx multiplexer 312A, a MUX0 314A, a read latch 316A, a receive (Rx) circuit 318A (for even bits), an Rx circuit 320A (for odd bits), an Rx multiplexer 322A, or a write FIFO 326A. Components for routing signals for the 128 I / O connections of DQ[0:127](ChB) may include a shared PLL 302, a shared DLL 304, a Tx circuit 306B (for even bits), a Tx circuit 308B (for odd bits), a shared DQS generator 310, a Tx multiplexer 312B, a MUX0 314B, a read latch 316B, an Rx circuit 318B (for even bits), an Rx circuit 320B (for odd bits), an Rx multiplexer 322B, or a write FIFO 326B.

[0026] According to some examples, when in full I / O mode 310, the component used to route signals for the 128 I / O connections for both DQ[0:127](ChA) and DQ[0:127](ChB) through logic layer 220 is active, except that “CLK1” is not applied to either of the Tx / Rx multiplexers for channel A or channel B components. For these examples, the components for channel A and channel B can operate at a first clock frequency that may be slower than the clock frequency used for “CLK1”. For example, the first clock frequency could produce a transfer rate of 2GT / s.

[0027] In some examples, the merged channel mode 320 can be implemented by applying "CLK1" to the Tx multiplexers 312A / B and Rx multiplexers 322A / B, causing these multiplexers for channels A / B to operate at a second, faster clock frequency. For example, the second clock frequency could produce a transmission rate of 4GT / s at Tx 308A / B and Rx 320A / B. For these examples, the 128 I / O connections previously allocated for DQ[0:127](ChA) are now divided, such that 64 I / O connections are used for DQ[0:126:2](ChA) and 64 I / O connections are used for DQ[1:127:2](ChB). Moreover, for the merged channel mode 320, the Tx circuits 308A / B and Rx circuits 320A / B can be allocated for routing signals for these 64 I / O connections. For merged channel mode 320, solid lines indicate I / O signals routed for channel A and dashed lines indicate I / O signals routed for channel B.

[0028] Figure 4 An example redistribution scheme 400 is shown. In some examples, such as... Figure 4 As shown, redistribution scheme 400 depicts how bumps or connections in channels b and d for HBM channel topology 410 can be redistributed to have no connections. For these examples, HBM channel topology 410 can represent a four-channel topology for a stack of memory devices coupled to the top side of a logic layer for an HBM stacked device, such as DRAMs 110-1 to 110-n coupled to the top side of logic layer 120. Moreover, redistribution layer (RDL) channel topology 420 can represent the merging of channels b and d with the corresponding channels a and c, which can result in fewer connections or bumps at the redistribution layer (e.g., redistribution layer 130).

[0029] Based on some examples, merging channels b and c with channels a and c can be similar to the above regarding... Figure 2 and Figure 3 The mentioned merged I / O connections and CA connections are implemented in response to putting the HBM stack device into merged channel mode (e.g., merged channel mode 320). For these examples, bumps or connections for channels b and d on the bottom side of the HBM stack device's logic layer can become unconnected, and then bumps or connections for channels a and c can be redistributed with increased area, which in... Figure 4 The area shown is 425, which is the increased region. In some examples, the bumps or connections can be diffused separately to have a larger spacing at the redistribution layer that connects the HBM stacked devices to the package substrate. For example, the spacing can be increased by a factor of 4 (4X) due to this type of channel merging.

[0030] Figure 5 Example redistributed layout scheme 500 is shown. In some examples, such as... Figure 5 The redistribution layout scheme 500 shown illustrates an HBM bump layout 510 and an overlapping HBM bump pair RDL bump 520. In these examples, HBM bumps 512 of the HBM bump layout 510 may represent connections for I / O or CA signals to channels a and b on the bottom side of the logic layer of the HBM stack device, and package substrate bumps 522 represent connections for the merged channels a and b to the redistribution layer, which is connected to the package substrate. The overlapping HBM bump pair RDL bump 520 does not show a complete merging of all HBM bumps 512 for channels b and a. A larger package substrate bump 522 is shown above the smaller HBM bumps 512 to provide an example perspective view of how a larger bump pitch can be implemented when merging channels. A larger bump pitch can, for example, allow for more flexible routing of signal paths between the HBM stack and the CPU or GPU.

[0031] Figure 6 An example subsystem 600 is shown. In some examples, subsystem 600 may be similar to... Figure 2 The subsystem 200 shown can also represent an HBM stack (e.g., Figure 1 This is a portion of the HBM stack 105 shown in the image. For these examples, such as... Figure 6 As shown, subsystem 600 includes a first memory array 610-1 accessible via channel A and a second memory array 610-2 accessible via channel B. Data written to or read from memory array 610-1 can be routed via signal path included in [ChA]I / O 613 in response to command and address signals routed via signal path included in [ChA]CA 615. Similarly, data written to or read from memory array 610-2 can be routed via signal path included in [ChB]I / O 617 in response to command and address signals routed via [ChB]CA 619. Control 614-1, decoder 612-1, CA buffer 616-1, and FIFO buffer 618-1 facilitate access to memory array 610-1. The controller 614-2, decoder 612-2, CA buffer 616-2, and FIFO buffer 618-2 facilitate access to the memory array 610-2.

[0032] Based on some examples, logic layer 620 can coordinate access to memory arrays 610-1 or 610-2. For the sake of brevity, Figure 6Some components that can be included in the logic layer of the HBM stack for coordinating access to the DRAM array are not shown. Figure 6 The example logic layer 620 shown may include reduction logic 624 and mode register 622. Mode register 622 may be programmed or configured to indicate the operating mode of reduction logic 624 to determine whether to operate in full I / O mode or partial I / O mode (e.g., a bit value "1" indicates partial I / O mode or a value "0" indicates full I / O mode). Figure 6 The diagram describes a partial I / O pattern because there is a reduction in I / O connections on the bottom side 621 of logic layer 620 for both channel A and channel B. Therefore, [ChA]I / O 623 and [ChB]I / O 627 include fewer active connections compared to the corresponding [ChA]I / O 613 and [ChB]I / O 617.

[0033] According to some examples, a full I / O mode may include 128 I / O connections for both channel A and channel B on the bottom side 621 of logic layer 620. For these examples, reducing logic 624 allows signals for all 128 I / O connections per channel to be routed through logic layer 620 at a first operating frequency, resulting in a first transmission rate (e.g., 2 GT / s). For example, a first signal for the 128 I / O connections for [ChA] is routed through logic layer 620 to [ChA] I / O 613 at the first operating frequency. A second signal for the 128 I / O connections for [ChB] is also routed through logic layer 620 to [ChB] I / O 617 at the first operating frequency. In some examples, if partial I / O mode is enabled, channel A has 64 out of 128 I / O contacts for [ChA]I / O 623 as active contacts, and channel B has 64 out of 128 I / O contacts for [ChB]CA 629 as active contacts. For these examples, the reduction logic 624 can compensate for the reduced number of active I / O contacts per channel by doubling the first operating frequency to produce a second operating frequency, via which signals for each set of 64 I / O contacts per channel are routed through logic layer 620, resulting in a second transfer rate (e.g., 4 GT / s). Therefore, between full I / O mode and combined channel mode, the corresponding memory arrays 610-1 and 610-2 can see almost no reduction in data rate per unit time.

[0034] Figure 7 Example operation mode 700 is shown. In some examples, such as... Figure 7 As shown, operating mode 700 may include full I / O mode 710 and partial I / O mode 720. For these examples, Figure 7 The components shown may represent at least a portion of the components used to route signals for the 128 I / O connections of DQ[0:127] through logic layer 620 to memory array 610-1. For example, components used to route signals for the 128 I / O connections of DQ[0:127] (ChA) may include PLL 702, DLL 704, Tx circuit 706A, Tx circuit 708A, DQS generator 710, Tx multiplexer 712A, MUX0 714A, read latch 716A, Rx circuit 718A, Rx circuit 720A, Rx multiplexer 722A, or write FIFO 726A.

[0035] According to some examples, when in full I / O mode 710, the component used to route signals for the 128 I / O connections for DQ[0:127] (ChA) through logic layer 620 is active, except that “CLK1” is not applied to the Tx / Rx multiplexer for the channel A component. For these examples, the channel A component may operate at a first clock frequency that is possibly slower than the clock frequency used for “CLK1”. For example, the first clock frequency could be 2GT / s.

[0036] In some examples, partial I / O mode 720 can be implemented by applying "CLK1" to Tx multiplexer 712A and Rx multiplexer 722A, causing these components for channel A to operate at a second, faster clock frequency. For example, the second clock frequency could be 4GT / s. In these examples, the 64 I / O connections previously allocated for DQ[0:127:2] are now unconnected for partial I / O mode 720.

[0037] Figure 8 An example redistribution system 800 is shown. In some examples, such as... Figure 8 As shown, the redistribution scheme 800 depicts how half of the DQ bumps of the I / O channels for the HBM channel topology 810 are unconnected (“NC”) or inactive for a portion of the RDL channel topology 820. For these examples, similar to... Figure 4 HBM channel topology 810 can represent a four-channel topology for coupling to memory devices on the top side of a logic layer for an HBM stacked device, such as DRAM 110-1 to 110-n coupled to the top side of logic layer 120. Furthermore, redistribution layer (RDL) channel topology 820 can represent a reduction in the number of I / O connections active at the bottom side of the logic layer to the redistribution layer (e.g., redistribution layer 130).

[0038] Based on some examples, a reduction in the number of active I / O connections on the bottom side of the logic layer of an HBM stacked device can still include CA signals. Compared to redistribution scheme 400, the spacing of bumps or connections used for partial RDL channel topologies at the redistribution layer may not increase as much as mentioned above for redistribution scheme 400. However, a reduction in I / O contacts can still result in an approximately 2x (2X) increase in spacing.

[0039] Figure 9 An example logic flow 900 is shown. In some examples, logic flow 900 may illustrate a logic flow for deploying HBM stacked devices to couple with a package substrate, which may be part of a system-on-a-chip (SOC) or a system-in-package (SiP). For these examples, logic flow 900 may consist of circuitry, logic, and / or features (e.g., logic layers 120, 220, or 620) of logic layers 120, 220, or 620. Figure 2 The merging logic 224 shown in the figure or Figure 6 The reduction logic 624 shown is implemented. Furthermore, the mode register used by the circuit, logic, and / or features can be configured as described above for... Figure 2-3 and Figure 6-7 As mentioned, it is set up or programmed. Examples are not limited to these components that implement logic flow 900.

[0040] Starting at box 910, the HBM device can be started or powered on.

[0041] Moving from box 910 to box 920 allows for the initialization of the circuitry / logic and / or features of the HBM device's logic layer. Initialization may include gathering the capabilities of the logic layer and / or the HBM device (e.g., the number of memory devices, channels, I / O contacts, etc.).

[0042] Moving from box 920 to decision box 930, the collected capabilities are evaluated to determine whether the logic layer is configured to implement or execute merge logic or reduce logic. If the logic layer is configured to implement or execute merge logic, then logic flow 900 moves to decision box 940. If the logic layer is configured to implement or execute reduce logic, then logic flow 900 moves to decision box 970.

[0043] Moving from decision box 930 to decision box 940, the merging logic of the logic layer (e.g., merging logic 224) can read the mode register (e.g., MR 222) to determine which bit value to indicate. If the bit value is 0, logic flow 900 moves to box 950. If the bit value is 1, logic flow 900 moves to box 960.

[0044] Moving from decision box 940 to box 950, the merging logic can operate in full I / O mode, which can utilize all I / O connections and CA connections that are routed through at least two channels coupled to the corresponding memory array of the memory device included in the HBM device (e.g., operating in full I / O mode 310).

[0045] Moving from decision box 940 to box 960, the merging logic can operate in merge channel mode, which can merge I / O connections and CA connections for two channels coupled to a corresponding memory array of a memory device included in an HBM device (e.g., operating in merge channel mode 320).

[0046] Moving from decision box 930 to decision box 970, the logic flow's reduction logic (e.g., reduction logic 624) can read the mode register (e.g., MR 622) to determine which bit value to indicate. If the bit value is 0, the logic flow moves to box 980. If the bit value is 1, the logic flow 900 moves to box 990.

[0047] Moving from decision box 970 to box 980, the reduction logic can operate in full I / O mode, which can utilize all I / O connections and CA connections that are routed through at least two channels coupled to the corresponding memory array of the memory device included in the HBM device (e.g., operating in full I / O mode 710).

[0048] Moving from decision box 970 to box 990, the reduction logic can operate in a partial I / O mode that reduces active I / O connections for at least two channels coupled to a corresponding memory array of a memory device included in an HBM device (e.g., operating in partial I / O mode 720).

[0049] Figure 10 An example block diagram for device 1000 is shown. Although Figure 10 The device 1000 shown has a limited number of elements in some topologies, but it is understood that the device 1000 may include more or fewer elements in alternative topologies as required by a given implementation.

[0050] According to some examples, device 1000 may be supported by circuitry 1020 located at a logic layer (e.g., logic layer 120, 220, or 620) of a high-bandwidth memory stack device. Circuitry 1020 may be arranged as a module, component, or feature that performs logic or one or more firmware implementations of that logic. It is worth noting that “a”, “b”, and “c” as used herein, and similar notations, are intended to represent variables of any positive integer. Thus, for example, if the implementation sets the value a = 3, the complete set of software or firmware for the module or component used for logic 1022-a may include logic 1022-1, 1022-2, or 1022-3. The examples presented are not limited to this context, and the different variables used throughout may represent the same or different integer values. Furthermore, “module,” “component,” or “feature” may also include firmware stored on a computer-readable or machine-readable medium, and although… Figure 10 The types of features are shown as separate boxes, but this does not limit the types of these features to storage devices in different computer-readable media components (e.g., separate memory, etc.) or implemented by different hardware components (e.g., separate application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs)).

[0051] According to some examples, circuit 1020 may include one or more ASICs or FPGAs, and in some examples, at least some of the logic 1022-a may be implemented as hardware elements of these ASICs or FPGAs.

[0052] Based on some examples, such as Figure 10 As shown, device 1000 may include mode register 1005. In these examples, mode register 1005 may be set or programmed to indicate an operating mode for routing I / O or CA signals through the logic layer of a high-bandwidth memory stack device. For example, full I / O mode, merged channel mode, or partial I / O mode.

[0053] In some examples, device 1000 may also include read logic 1022-1. Read logic 1022-1 may be executed or supported by circuitry 1020 to read bit values ​​from mode register 1005. For example, mode register 1005 may have a bit value of 1 or a bit value of 0.

[0054] According to some examples, device 1000 may also include connection logic 1022-2. Connection logic 1022-2 may be executed or supported by circuitry 1020 to make a portion of the I / O contacts on the bottom side of the logic layer active and the remainder inactive based on bit values ​​in mode register 1005. In these examples, a first portion of the I / O contacts may be arranged to receive or transmit I / O signals to one or more data channels for access to multiple memory devices. Active contact 1030 may include the portion of the I / O contacts that is active based on the bit values ​​indicated by mode register 1005.

[0055] In some examples, device 1000 may also include routing logic 1022-3. Routing logic 1022-3 may be executed or supported by circuitry 1020 such that I / O signals are routed via one or more data paths through portions of the I / O contacts, such that a redirection layer below the logic layer enables high-bandwidth memory stack devices to connect to the package substrate with a reduced number of I / O contacts. For these examples, Tx signal 1040 may include I / O signals routed from multiple memory devices (e.g., data read from multiple memory devices), and Rx signal 1050 may include I / O signals routed to multiple memory devices (data written to multiple memory devices). In some examples, a transfer rate clock 1010 may be used by routing logic 1022-3 to increase the transfer rate to compensate for the inactivity of all I / O contacts.

[0056] Various components of device 1000 can be communicatively coupled to each other for coordinated operation via various types of communication media. Coordination can involve one-way or two-way exchange of information. For example, components can communicate information in the form of signals communicated via a communication medium. Information can be implemented as signals assigned to various signal lines. In such an assignment, each message is a signal. However, other embodiments can alternatively deploy data messages. Such data messages can be sent across various connections. Example connections include parallel interfaces, serial interfaces, and bus interfaces.

[0057] This document includes a collection of logical flows representing example methodologies for performing novel aspects of the disclosed architecture. Although one or more methodologies shown herein are illustrated and described as a series of actions for the purpose of simplification, those skilled in the art will understand and recognize that these methodologies are not limited to the order of the actions. Based on the above, some actions may occur in a different order than those shown and described herein and / or concurrently with other actions shown and described herein. For example, those skilled in the art will understand and recognize that methodologies may alternatively be represented as, for example, a series of associated states or events in a state diagram. Furthermore, for novel implementations, not all actions shown in the methodologies are required.

[0058] The logic flow can be implemented in software, firmware, and / or hardware. In software and firmware embodiments, the logic flow can be implemented by computer-executable instructions stored on at least one non-transitory computer-readable medium or machine-readable medium (e.g., optical, magnetic, or semiconductor storage device). Embodiments are not limited to this context.

[0059] Figure 11 An example logic flow 1100 is shown. Logic flow 1100 may represent some or all of the operations performed by one or more logics, features, or devices (e.g., apparatus 1000) described herein. More specifically, logic flow 1100 may be implemented by read logic 1022-1, connection logic 1022-2, or routing logic 1022-3.

[0060] According to some examples, at block 1102, logic flow 1100 can determine the operating mode of a high-bandwidth memory stack device, which includes multiple memory devices stacked above the logic layer, via a mode register. For these examples, read logic 1022-1 can read the mode register.

[0061] In some examples, at block 1104, logic flow 1100 can, based on a determined operating mode, make a portion of the I / O contacts on the bottom side of the logic layer active and the remainder inactive, wherein the first portion of the I / O contacts is arranged to receive or transmit I / O signals for one or more data channels to access multiple memory devices. For these examples, connection logic 1022-2 can make the I / O contacts active or inactive.

[0062] According to some examples, at block 1106, logic flow 1100 can route I / O signals via one or more data channels through a portion of the I / O contacts, such that a redirection layer below the logic layer enables high-bandwidth memory stack devices to connect to the package substrate with a reduced number of I / O contacts. For these examples, routing logic 1022-3 can route I / O signals via one or more data channels.

[0063] Figure 12 An example storage medium 1200 is shown. In some examples, storage medium 1200 may be an article of manufacture. Storage medium 1200 may include any non-transitory computer-readable or machine-readable medium, such as optical, magnetic, or semiconductor storage devices. Storage medium 1200 may store various types of computer-executable instructions, such as instructions for implementing logic flow 1100. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and so on. The example is not limited to this context.

[0064] Figure 13 An example computing platform 1300 is shown. In some examples, such as... Figure 13 As shown, computing platform 1300 may include memory system 1330, processing component 1340, other platform components 1350, or communication interface 1360. According to some examples, computing platform 1300 may be implemented as a system-on-a-chip (SOC) or system-in-package (SiP).

[0065] According to some examples, memory system 1330 may be a high-bandwidth memory stack device including logic layer 1332 and memory devices 1334. In these examples, logic and / or features residing in or located at logic layer 1332 may perform at least some processing operations or logic for device 1000 and may include a storage medium including storage medium 1200. Furthermore, memory devices(s) 1334 may include similar types of volatile or non-volatile memory (e.g., DRAM).

[0066] According to some examples, processing component 1340 may include various hardware elements, software elements, or combinations of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, management controllers, accompanying dies, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices (PLDs), digital signal processors (DSPs), FPGAs, memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application programming interfaces (APIs), instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware and / or software components can vary depending on any number of factors, such as desired computational speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints required for a given implementation.

[0067] In some examples, other platform components 1350 may include common computing elements, additional memory cells, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input / output (I / O) components (e.g., digital displays), power supplies, and so on. Examples of memory cells or memory devices may include, but are not limited to, various types of computer-readable and machine-readable storage media in the form of one or more high-speed memory cells, such as read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), double data rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, polymer memory (e.g., ferroelectric polymer memory), oscillator memory, phase-change or ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic cards or optical cards, device arrays (e.g., redundant array of independent disks (RAID) drives), solid-state storage devices (e.g., USB storage), solid-state drives (SSDs), and any other type of storage media suitable for storing information.

[0068] In some examples, communication interface 1360 may include logic and / or features for supporting the communication interface. For these examples, communication interface 1360 may include one or more communication interfaces operating according to various communication protocols or standards for communication via direct or network communication links. Direct communication may occur via communication protocols or standards described in one or more industry standards (including their successors and variations) (e.g., those associated with the PCIe specification, NVMe specification, or I3C specification). Network communication may occur via communication protocols or standards (e.g., those described in one or more Ethernet standards published by the Institute of Electrical and Electronics Engineers (IEEE). For example, such an Ethernet standard published by IEEE may include, but is not limited to, IEEE 802.3-2018, namely Carrier sense Multiple access with CollisionDetection (CSMA / CD) Access Method and Physical Layer Specifications (hereinafter referred to as the “IEEE 802.3 specification”), published in August 2018. Network communication may also occur according to one or more OpenFlow specifications (e.g., the OpenFlow Hardware Abstraction API specification). Network communication can also occur according to one or more Infiniband architecture specifications.

[0069] The components and features of the computing platform 1300 can be implemented using any combination of discrete circuits, ASICs, logic gates, and / or single-chip architectures. Furthermore, the features of the computing platform 1300 can be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any suitable combination of the foregoing components. It should be noted that hardware, firmware, and / or software elements may be collectively referred to herein or individually as “logic,” “circuit,” or “electronic circuit.”

[0070] It should be recognized that, in Figure 13 The exemplary computing platform 1300 shown in the block diagram can represent a functionally descriptive example of many potential implementations. Therefore, the partitioning, omission, or inclusion of block functions depicted in the figures does not imply that the hardware components, circuits, software, and / or elements used to implement these functions will necessarily be partitioned, omitted, or included in the embodiments.

[0071] One or more aspects of at least one example can be implemented by representative instructions representing various logic within a processor, stored on at least one machine-readable medium, which, when read by a machine, computing device, or system, cause that machine, computing device, or system to manufacture logic for performing the techniques described herein. Such a representation is considered an "IP core" and can be analogous to an IP block. IP blocks can be stored on a tangible machine-readable medium and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually manufacture the logic or processor.

[0072] Various examples can be implemented using hardware components, software components, or a combination of both. In some examples, hardware components may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software components may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware components and / or software components can vary depending on any number of factors (e.g., desired computational speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints required depending on the given implementation).

[0073] Some examples may include an article of writing or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium for storing logic. In some examples, a non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0074] As some examples, a computer-readable medium may include a non-transitory storage medium for storing or maintaining instructions that, when executed by a machine, computing device, or system, cause that machine, computing device, or system to perform methods and / or operations according to the described examples. Instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Instructions may be implemented according to predefined computer languages, methods, or syntaxes to instruct a machine, computing device, or system to perform certain functions. Instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming languages.

[0075] Some examples may be described using the phrase "in one example" or "example" and its derivatives. These terms mean that a particular feature, structure, or property described in connection with the example is included in at least one example, and the appearance of the phrase "in one example" in various places in the specification does not necessarily refer to the same example.

[0076] Some examples can be described using the terms “coupled” and “connected” and their derivatives. These terms are not necessarily intended to be synonyms of each other. For example, descriptions using the terms “connected” and / or “coupled” can indicate that two or more elements are in direct physical or electrical contact with each other. However, the terms “coupled” or “coupled with” can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0077] With respect to the various operations or functions described herein, these operations or functions can be described or defined as software code, instructions, configuration, and / or data. Content can be directly executable (in the form of an “object” or “executable”), source code, or differential code (“incremental” or “patch” code). The software content described herein can be provided via an artifact on which content is stored, or by means of operating a communication interface to transmit data via that communication interface. Machine-readable storage media can enable a machine to perform the described functions or operations and includes any mechanism for storing information in a machine-accessible form (e.g., computing devices, electronic systems, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, etc.). Communication interfaces include any mechanism that engages with any of hardwired, wireless, optical, or other media to transmit to another device, such as a memory bus interface, processor bus interface, internet connection, disk controller, etc. Communication interfaces can be configured by providing configuration parameters and / or sending signals to prepare the communication interface for providing data signals describing the software content. The communication interface can be accessed via one or more commands or signals sent to it.

[0078] The following examples are additional examples of the techniques disclosed herein.

[0079] Example 1. An example apparatus may include a mode register for indicating an operating mode of a high-bandwidth memory stack comprising a plurality of memory devices stacked above a logic layer. The apparatus may also include circuitry located at the logic layer for performing logic. This logic may read bit values ​​from the mode register and, based on these bit values, activate a portion of I / O contacts on the bottom side of the logic layer and deactivate the remainder of the I / O contacts. A portion of the I / O contacts may be configured to receive or transmit I / O signals to one or more data channels for accessing the plurality of memory devices.

[0080] Example 2. According to the apparatus of Example 1, the logic can also cause I / O signals to be routed via one or more data channels through a portion of the I / O contacts, such that a redirection layer below the logic layer enables the high-bandwidth memory stack device to connect to the package substrate by a reduced number of I / O contacts.

[0081] Example 3. According to the apparatus of Example 1, the logic can cause I / O signals to be routed via one or more data channels through a portion of the I / O contacts at a first transmission rate per second, which is twice the second transmission rate per second when both the I / O signals are routed via one or more data channels through a portion of the I / O contacts and the remainder of the I / O contacts.

[0082] Example 4. According to the apparatus of Example 2, a high-bandwidth memory stacking device can be connected to a package substrate via a first contact having a larger spacing between the first contacts compared to a second contact, the second contact corresponding to both active and inactive I / O contacts on the bottom side of the logic layer.

[0083] Example 5. According to the apparatus of Example 4, the package substrate may include an I / O signal path routed between a high-bandwidth memory device and a central processing unit or a graphics processing unit, the I / O signal path being used for coupling with a first contact.

[0084] Example 6. According to the apparatus of Example 1, a portion and the remainder of an I / O contact are included in a plurality of I / O contacts for a first data channel for accessing a memory array located at a memory device from a plurality of memory devices, the portion comprising half of the plurality of I / O contacts.

[0085] Example 7. According to the apparatus of Example 1, a portion and the remainder of the I / O contacts may be included in a plurality of I / O contacts for a first data channel and a second data channel, the first data channel being accessible to a first memory array located at a memory device from a plurality of memory devices. The second data channel being accessible to a second memory array located at a memory device, the portion comprising half of the plurality of I / O contacts for the first and second data channels.

[0086] Example 8. According to the apparatus of Example 7, the logic may further, based on the bit value of the mode register, cause a portion of the CA contacts on the bottom side of the logic layer to be active and the remainder of the CA contacts to be inactive. A portion of the CA contacts may be arranged to receive or transmit CA signals for a first data channel and a second data channel to facilitate access to multiple memory devices. The logic may also cause the CA signals for the first and second data channels to be routed through a portion of the CA contacts, such that a redirection layer below the logic layer enables high-bandwidth memory stacking devices to connect to the package substrate with a reduced number of CA contacts.

[0087] Example 9. According to the apparatus of Example 1, a plurality of memory devices may include dynamic random access memory.

[0088] Example 10. An example memory device may include a plurality of stacked memory dies. The memory device may further include a mode register for indicating an operating mode. The memory device may further include a logic layer located beneath the plurality of stacked memory dies, the logic layer including circuitry for performing logic. The logic may read bit values ​​from the mode register and, based on the bit values ​​of the mode register, make a portion of I / O contacts on the bottom side of the logic layer active and the remainder of the I / O contacts inactive, the portion of the I / O contacts being arranged to receive or transmit I / O signals to one or more data channels for accessing at least one memory array maintained on at least one of the plurality of stacked memory dies.

[0089] Example 11. According to the memory device of Example 10, the logic can also cause I / O signals to be routed via one or more data channels through a portion of the I / O contacts, such that a redirection layer below the logic layer enables the memory device to connect to the package substrate by a reduced number of I / O contacts.

[0090] Example 12. According to the memory device of Example 10, the logic can cause I / O signals to be routed via one or more data channels through a portion of the I / O contacts at a first transmission rate per second, which is twice the second transmission rate per second when both the I / O signals are routed via one or more data channels through a portion of the I / O contacts and the remainder of the I / O contacts.

[0091] Example 13. According to the memory device of Example 12, the memory device can be connected to the package substrate via a first contact having a larger spacing between the first contacts compared to a second contact, the second contact corresponding to both active I / O contacts and inactive I / O contacts on the bottom side of the logic layer.

[0092] Example 14. According to the memory device of Example 13, the package substrate includes an I / O signal path routed between the memory device and a central processing unit or a graphics processing unit, the I / O signal path being used for coupling with a first contact.

[0093] Example 15. According to the memory device of Example 10, a portion and the remainder of the I / O contacts may be included in a plurality of I / O contacts for a first data channel from one or more data channels. The first data channel can access a first memory array maintained on at least one memory die, and the portion includes half of the plurality of I / O contacts.

[0094] Example 16. According to the memory device of Example 10, a portion and the remainder of the I / O contacts may be included in a plurality of I / O contacts for a first data channel and a second data channel from one or more data channels. The first data channel can access a first memory array maintained on at least one memory die. The second data channel can access a second memory array maintained on at least one memory die. This portion includes half of the plurality of I / O contacts for the first and second data channels.

[0095] Example 17. According to the memory device of Example 16, the logic can also, based on the bit value of the mode register, make a portion of the CA contacts on the bottom side of the logic layer active and the remainder of the CA contacts inactive, wherein a portion of the CA contacts is arranged to receive or transmit CA signals for the first and second data channels to facilitate access to the first and second memory arrays. The logic can also make the CA signals for the first and second data channels routed through a portion of the CA contacts, such that a redirection layer below the logic layer enables the memory device to connect to the package substrate by a reduced number of CA contacts.

[0096] Example 18. According to the memory device of Example 10, multiple memory dies may include dynamic random access memory.

[0097] Example 19. An example method may include determining an operating mode of a high-bandwidth memory stack device, the high-bandwidth memory stack device comprising a plurality of memory devices stacked above a logic layer, via a mode register. The method may further include, based on the determined operating mode, activating a portion of I / O contacts on the bottom side of the logic layer and deactivating the remainder of the I / O contacts. A portion of the I / O contacts may be configured to receive or transmit I / O signals for one or more data channels to access the plurality of memory devices.

[0098] Example 20. The method according to Example 19 may further include routing I / O signals via one or more data channels through a portion of the I / O contacts, such that a redirection layer below the logic layer enables the high-bandwidth memory stack device to connect to the package substrate via a reduced number of I / O contacts.

[0099] Example 21. The method according to Example 19 may further include routing the I / O signal via one or more data channels through a portion of the I / O contact at a first transmission rate per second, the first transmission rate per second being twice the second transmission rate per second when the I / O signal is routed via both a portion of the I / O contact and the remainder of the I / O contact through one or more data channels.

[0100] Example 22. According to the method of Example 20, a high-bandwidth memory stacking device can be connected to a package substrate via a first contact having a larger spacing between the first contacts compared to a second contact, the second contact corresponding to both active and inactive I / O contacts on the bottom side of the logic layer.

[0101] Example 23. According to the method of Example 22, the package substrate may include an I / O signal path routed between the HBM device and the central processing unit or graphics processing unit, the I / O signal path being used for coupling with a first contact.

[0102] Example 24. According to the method of Example 19, a portion and the remainder of an I / O contact may be included in a plurality of I / O contacts for a first data channel from one or more data channels. The first data channel may access a memory array located at a memory device from a plurality of memory devices, and this portion includes half of the plurality of I / O contacts.

[0103] Example 25. According to the method of Example 19, a portion and the remainder of an I / O contact may be included in a plurality of I / O contacts for a first data channel and a second data channel from one or more data channels. The first data channel can access a first memory array located at a memory device from a plurality of memory devices. The second data channel can access a second memory array located at a memory device, and this portion includes half of the plurality of I / O contacts for the first and second data channels.

[0104] Example 26. The method of Example 25 may further include, based on a determined operating mode, activating a portion of the CA contacts on the bottom side of the logic layer and deactivating the remainder of the CA contacts. A portion of the CA contacts may be arranged to receive or transmit CA signals for a first data channel and a second data channel to facilitate access to a plurality of memory devices. The method may further include routing the CA signals for the first and second data channels through a portion of the CA contacts, such that a redirection layer below the logic layer enables high-bandwidth memory stack devices to connect to the package substrate via a reduced number of CA contacts.

[0105] Example 27. According to the method of Example 19, multiple memory devices may include dynamic random access memory.

[0106] Example 28. An example of at least one machine-readable medium that may include a plurality of instructions which, in response to execution by a system, may cause the system to perform a method according to any one of Examples 19 to 27.

[0107] Example 29. An example apparatus that may include a unit for performing the method of any one of Examples 19 to 27.

[0108] It should be emphasized that an abstract is provided to comply with Section 1.72(b) of CFR 37, requiring an abstract that allows the reader to quickly determine the nature of the technical disclosure. It should be understood that the abstract is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in a single example to simplify this disclosure. This method of disclosure is not to be construed as reflecting an intention to claim more features than are expressly cited in each claim. Rather, as reflected in the appended claims, the inventive subject matter lies in all features less than those in a single disclosed example. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is, in itself, a separately claimed subject matter. In the appended claims, the terms “including” and “in which” are used as common English equivalents to the corresponding terms “comprising” and “wherein,” respectively. Furthermore, the terms “first,” “second,” “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0109] Although the subject matter has been described in language specific to structural features and / or method actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. An apparatus for coupling a high-bandwidth memory stacking device onto a package substrate, comprising: A mode register is used to indicate the operating mode of a high-bandwidth memory stack device, which includes multiple memory devices stacked above a logic layer; as well as Circuitry located at the logic layer for performing logic, the logic being used for: Read the bit value of the mode register; and Based on the bit value of the mode register, a portion of the input / output I / O contacts on the bottom side of the logic layer are made active and the remainder of the I / O contacts are made inactive. A portion of the I / O contacts is arranged to receive or transmit I / O signals for one or more data channels to access the plurality of memory devices. This allows I / O signals to be routed via one or more data channels through a portion of the I / O contacts, such that a redirection layer below the logic layer enables the high-bandwidth memory stack device to connect to the package substrate via a reduced number of I / O contacts.

2. The apparatus according to claim 1, comprising: The logic is configured to route the I / O signal via one or more data channels through a portion of the I / O contact at a first transmission rate per second, which is twice the second transmission rate per second if the I / O signal is routed via both the one or more data channels through a portion of the I / O contact and the remainder of the I / O contact.

3. The apparatus according to claim 1, comprising: The high-bandwidth memory stack device is used to connect to the package substrate via a first contact, the first contact having a larger spacing between them compared to a second contact, the second contact corresponding to both active and inactive I / O contacts on the bottom side of the logic layer.

4. The apparatus according to claim 3, comprising: The packaging substrate includes an I / O signal path routed between the high-bandwidth memory stack and the central processing unit or graphics processing unit, the I / O signal path being used to couple with the first contact.

5. The apparatus according to claim 1, comprising: A portion and the remainder of the I / O contacts are included in a plurality of I / O contacts for a first data channel among the one or more data channels, the first data channel being used to access a memory array located at a memory device among the plurality of memory devices, the portion comprising half of the plurality of I / O contacts.

6. The apparatus according to claim 1, comprising: A portion of the I / O contact and the remainder of the I / O contact are included in a plurality of I / O contacts for a first data channel and a second data channel, the first data channel being used to access a first memory array located at a memory device located at a memory device, and the second data channel being used to access a second memory array located at the memory device, the portion comprising half of the plurality of I / O contacts for the first data channel and the second data channel.

7. The apparatus according to claim 6, further comprising: The logic is used for: Based on the bit value of the mode register, a portion of the command and address CA contacts on the bottom side of the logic layer are made active and the remainder of the CA contacts are made inactive. A portion of the CA contacts is arranged to receive or transmit CA signals for the first data channel and the second data channel to facilitate access to the first memory array and the second memory array. and This allows the CA signals for the first and second data channels to be routed through a portion of the CA contacts, such that the redirection layer below the logic layer enables the high-bandwidth memory stack device to connect to the package substrate via a reduced number of CA contacts.

8. The apparatus according to claim 1, comprising: The plurality of memory devices include dynamic random access memory.

9. A memory device, comprising: Multiple stacked memory dies; The mode register is used to indicate the operating mode; as well as A logic layer located beneath the plurality of stacked memory dies, the logic layer including circuitry for performing logic, the logic being used for: Read the bit value of the mode register; and Based on the bit value of the mode register, a portion of the input / output I / O contacts on the bottom side of the logic layer is active and the remainder of the I / O contacts is inactive. A portion of the I / O contacts is arranged to receive or transmit I / O signals for one or more data channels to access at least one memory array, which is maintained on at least one memory die among the plurality of stacked memory dies. This allows I / O signals to be routed via one or more data channels through a portion of the I / O contacts, such that a redirection layer below the logic layer enables the memory device to connect to the package substrate via a reduced number of I / O contacts.

10. The memory device of claim 9, comprising: The logic is configured to route the I / O signal via one or more data channels through a portion of the I / O contact at a first transmission rate per second, which is twice the second transmission rate per second if the I / O signal is routed via both the one or more data channels through a portion of the I / O contact and the remainder of the I / O contact.

11. The memory device of claim 10, comprising: The memory device is configured to connect to a package substrate via a first contact, the first contact having a larger spacing between them compared to a second contact, the second contact corresponding to both active and inactive I / O contacts on the bottom side of the logic layer.

12. The memory device of claim 11, comprising: The packaging substrate includes an I / O signal path routed between the memory device and the central processing unit or graphics processing unit, the I / O signal path being used to couple with the first contact.

13. The memory device of claim 9, comprising: A portion and the remainder of the I / O contacts are included in a plurality of I / O contacts for a first data channel among the one or more data channels, the first data channel being used to access a first memory array held on the at least one memory die, the portion comprising half of the plurality of I / O contacts.

14. The memory device of claim 9, comprising: A portion of the I / O contacts and the remainder of the I / O contacts are included in a plurality of I / O contacts for a first data channel and a second data channel, the first data channel being used to access a first memory array held on the at least one memory die, and the second data channel being used to access a second memory array held on the at least one memory die, the portion comprising half of the plurality of I / O contacts for the first data channel and the second data channel.

15. The memory device of claim 14, further comprising: The logic is used for: Based on the bit value of the mode register, a portion of the command and address CA contacts on the bottom side of the logic layer are made active and the remainder of the CA contacts are made inactive. A portion of the CA contacts is arranged to receive or transmit CA signals for the first data channel and the second data channel to facilitate access to the first memory array and the second memory array. and This allows the CA signals for the first and second data channels to be routed through a portion of the CA contacts, such that the redirection layer below the logic layer enables the memory device to connect to the package substrate via a reduced number of CA contacts.

16. The memory device of claim 9, comprising: The plurality of stacked memory dies include dynamic random access memory.

17. A method for coupling a high-bandwidth memory stacking device onto a package substrate, comprising: The operating mode of the high-bandwidth memory stack device, which includes multiple memory devices stacked above the logic layer, is determined via a mode register. as well as Based on the determined operating mode, a portion of the input / output I / O contacts on the bottom side of the logic layer are active while the remainder of the I / O contacts are inactive. A portion of the I / O contacts is arranged to receive or transmit I / O signals for one or more data channels to access the plurality of memory devices. This allows I / O signals to be routed via one or more data channels through a portion of the I / O contacts, such that a redirection layer below the logic layer enables the high-bandwidth memory stack device to connect to the package substrate via a reduced number of I / O contacts.

18. The method of claim 17, further comprising: The I / O signal is routed via one or more data channels through a portion of the I / O contact at a first transmission rate per second, which is twice the second transmission rate per second if the I / O signal is routed via both the one or more data channels through a portion of the I / O contact and the remainder of the I / O contact.

19. The method of claim 17, comprising: The high-bandwidth memory stack device is used to connect to the package substrate via a first contact, the first contact having a larger spacing between them compared to a second contact, the second contact corresponding to both active and inactive I / O contacts on the bottom side of the logic layer.

20. The method of claim 17, comprising: A portion and the remainder of the I / O contacts are included in a plurality of I / O contacts for a first data channel among the one or more data channels, the first data channel being used to access a memory array located at a memory device among the plurality of memory devices, the portion comprising half of the plurality of I / O contacts.

21. The method of claim 17, comprising: A portion of the I / O contact and the remainder of the I / O contact are included in a plurality of I / O contacts for a first data channel and a second data channel, the first data channel being used to access a first memory array located at a memory device among the plurality of memory devices, and the second data channel being used to access a second memory array located at the memory device; the portion includes half of the plurality of I / O contacts for the first data channel and the second data channel. Based on the determined operating mode, a portion of the command and address CA contacts on the bottom side of the logic layer are active while the remainder of the CA contacts are inactive. A portion of the CA contacts is arranged to receive or transmit CA signals for the first data channel and the second data channel to facilitate access to the first memory array and the second memory array. and This allows the CA signals for the first and second data channels to be routed through a portion of the CA contacts, such that the redirection layer below the logic layer enables the high-bandwidth memory stack device to connect to the package substrate via a reduced number of CA contacts.

22. An apparatus for coupling a high-bandwidth memory stacking device onto a package substrate, comprising a unit for performing the method of any one of claims 17 to 21.

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