Select Gate Maintenance in Memory Subsystems

Abstract

The present application relates to select gate maintenance in a memory subsystem. A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program / erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program / erase cycles performed on the data block satisfies a scan threshold condition, and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. In response to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch-up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to select gate maintenance in memory subsystems. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] One aspect of the present application is directed to a system, the system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations comprising: receiving a request to erase a data block of the memory device; determining a number of program / erase cycles performed on the data block; performing an erase operation to erase the data block; determining that the number of program / erase cycles performed on the data block satisfies a scan threshold condition; performing a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block; and in response to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, performing a touch-up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

[0004] Another aspect of the present application is directed to a method, the method comprising: detecting an occurrence of a trigger event; determining a number of program / erase cycles performed on a data block; determining whether the number of program / erase cycles performed on the data block satisfies a threshold condition; and in response to the number of program / erase cycles performed on the data block satisfying the threshold condition, performing a touch-up operation on at least one select gate device to adjust a current threshold voltage of the at least one select gate device to a target threshold voltage.

[0005] Yet another aspect of the present application is directed to a non-transitory computer-readable storage medium comprising instructions, which, when executed by a processing device, cause the processing device to perform operations comprising: receiving a request to erase a data block of the memory device; determining a number of program / erase cycles performed on the data block; performing an erase operation to erase the data block; determining that the number of program / erase cycles performed on the data block satisfies a scan threshold condition; performing a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block; and in response to the first error rate associated with the current threshold voltage of at least one select gate device satisfying an error threshold criterion, performing a touch-up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 is a block diagram illustrating a select gate device in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3 is a flow chart of an example method of performing select gate maintenance in a data block of a memory device in response to a block erase operation according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an example method of performing select gate maintenance in a data block of a memory device in response to a block fail operation according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure are directed to select gate maintenance in a memory subsystem. The memory subsystem may be a memory device, a memory module, or a mixture of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components (e.g., a memory device that stores data). The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0013] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Hereinafter, a data block refers to a cell of a memory device for storing data, and may include a group of memory cells, a word line group, a word line, or an individual memory cell. A memory page (also referred to herein as a "page") stores one or more bits of binary data corresponding to data received from a host system. The memory cells of a data block may be arranged along several separate word lines. Each data block may include several sub-blocks, wherein each sub-block is defined by associated pillars (e.g., vertical conductive traces) extending from a shared bit line. Because the sub-blocks can be accessed individually (e.g., to perform programming or reading operations), the data block can include a structure to selectively enable pillars associated with a particular sub-block while disabling pillars associated with other sub-blocks. In one embodiment, this structure includes one or more select gate devices positioned at either or both ends of each pillar. These select gate devices can enable or disable conduction of a signal through the pillars, depending on the control signal applied. In one embodiment, the select gate devices associated with each pillar in the data block are individually controlled.

[0014] Conventional memory devices may implement these select gate devices using floating gate transistors with relatively long channels, which provide good signal isolation when in the proper state. However, other memory devices may implement these select gate devices using replacement gate transistors with relatively short channels. Replacement gate transistors are programmable devices and therefore provide more general benefits, but are sensitive to a certain amount of signal leakage. In addition, the programmable threshold voltage of the replacement gate transistor may shift over time. Although initially set to a specific target value, many factors including the number of program / erase cycles performed on the device, temperature changes, etc. may cause the threshold voltage of the select gate device to increase or decrease over time. This shift relative to the target value may result in charge loss, causing the select gate device to operate improperly, and may cause reliability issues in the data stored on the word lines of the corresponding sub-block.

[0015] Aspects of the present disclosure address the above and other deficiencies by periodically performing maintenance operations on select gate devices to adjust the current threshold voltages of those select gate devices (which may have shifted over time) back to a target threshold voltage. In one embodiment, in response to a request to erase a given data block or a request to invalidate a data block, a memory subsystem controller determines the number of program / erase cycles performed on the data block and determines whether the number of program / erase cycles satisfies a scan threshold condition. In response to the number of program / erase cycles satisfying the scan threshold condition, the memory subsystem controller may perform a threshold voltage integrity scan on the data block to determine an error rate associated with the current threshold voltage of at least one select gate device of the data block. If a first error rate associated with the current threshold voltage of at least one select gate device satisfies the error threshold criteria, the memory subsystem controller may perform a touch-up programming operation on at least one select gate device to adjust the current threshold voltage back to the target threshold voltage. In another embodiment, if the number of program / erase cycles performed on the data block satisfies a separation threshold condition (e.g., a higher number of program / erase cycles), the memory subsystem controller may blindly perform a touch-up operation without first performing a threshold voltage integrity scan.

[0016] Periodically performing a touch-up operation on the select gate devices ensures that the threshold voltages of the select gate devices in a data block do not shift too far from the target threshold voltage at which the select gate devices are designed to operate. This enables the select gate devices to be correctly enabled and disabled in response to receiving the corresponding control signals. This improves the integrity of the data stored in the sub-block controlled by each corresponding select gate device because data operations (e.g., programming or reading operations) can be focused on a given sub-block without causing undesirable effects on other sub-blocks of the data block. In addition, the threshold voltages of the select gate devices can be corrected before shifting too far from the target voltage so that the select gates become irreparable and prevent the need to retire the data block entirely. Therefore, the touch-up operations described herein can maintain the expected capacity of the memory device and improve the useful life of the memory device.

[0017] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0021] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0022] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0023] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory devices 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0027] The memory subsystem controller 115 (or, for simplicity, controller 115) may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0032] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] In one embodiment, the memory subsystem 110 includes a select gate maintenance component 113 that can be used to periodically perform maintenance operations on select gate devices of a data block of the memory device 130 or the memory device 140. In one embodiment, the maintenance operations include a touch-up operation, in which the select gate maintenance component 113 iteratively applies a series of programming pulses to the select gate devices to adjust a current threshold voltage of the select gate devices back to a target threshold voltage; and after each iteration, verifies whether the current threshold voltage has reached the target threshold voltage. In one embodiment, in response to a request to erase a given data block or a request to invalidate the data block, the select gate maintenance component 113 determines a number of program / erase cycles performed on the data block, and determines whether the number of program / erase cycles satisfies a scan threshold condition. In response to the number of program / erase cycles satisfying the scan threshold condition, the select gate maintenance component 113 may perform a threshold voltage integrity scan on the data block to determine an error rate associated with the current threshold voltage of at least one select gate device of the data block. If the first error rate associated with the current threshold voltage of the at least one select gate device satisfies the error threshold criteria, the select gate maintenance component 113 may perform a touch-up operation on the at least one select gate device to adjust the current threshold voltage back to the target threshold voltage. In another embodiment, if the number of program / erase cycles is high enough, the select gate maintenance component 113 may blindly perform the touch-up operation without first performing a threshold voltage integrity scan. Additional details regarding the operation of the select gate maintenance component 113 are described below.

[0034] Figure 22 is a block diagram illustrating a select gate device in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure. In one embodiment, data block 200 represents any one of the data blocks that make up memory device 130 or memory device 140. Data block 200 may be one of several physical blocks in a memory device and may include a set of memory pages. A memory page stores one or more bits of binary data corresponding to data received from a host system. The memory cells of data block 200 may be arranged along several separate word lines 230. Data block 200 may include a shared bit line 210 having several pillars 212, 214, 216, 218 extending therefrom to separate source lines 220. Each pillar may be a vertical conductive trace, and the intersection of each of pillars 212, 214, 216, 218 with each of word lines 230 forms a memory cell. Therefore, each of pillars 212, 214, 216, 218 forms a separate sub-block within data block 200, wherein each sub-block may be accessed separately. In order to enable an access operation (e.g., a programming operation or a read operation) to be performed on a given sub-block, the data block 200 includes a number of select gate devices to selectively enable pillars (e.g., pillar 212) associated with a particular sub-block while disabling pillars (e.g., pillars 214, 216, 218) associated with other sub-blocks. For example, each pillar may include a number of select gate devices (e.g., SGD0, SGD1, SGD2) at a first end (e.g., a drain end), and a number of select gate devices (e.g., SGS0, SGS1, SGS2) at a second end (e.g., a source end).

[0035] In one embodiment, a select gate device in data block 200 is formed using a programmable replacement gate transistor. Thus, the select gate device has a programmed threshold voltage. Depending on the magnitude of the control signal applied relative to the threshold voltage, the select gate device can enable or disable the conduction of a signal through the corresponding pillar. For example, if the magnitude of the control signal applied to the select gate device is less than the threshold voltage, the select gate device can be turned off and the signal can be prevented from flowing through the corresponding pillar. On the contrary, if the magnitude of the control signal is greater than the threshold voltage, the select gate device can be turned on and the signal can be allowed to flow through the corresponding pillar. In one embodiment, the select gate device associated with each pillar in data block 200 is individually controlled so that the signal flow in a specific pillar can be prevented while allowing the signal flow in other pillars. The replacement gate transistor has a relatively short internal channel length and is therefore sensitive to a certain amount of signal leakage. Accordingly, in one embodiment, each pillar in data block 200 has multiple select gate devices at each of the drain terminal and the source terminal, thereby effectively increasing the internal channel length to provide better signal isolation when turned off.

[0036] The programmable threshold voltage of the select gate device may shift over time. Although initially set to a specific target value, many factors, such as the number of program / erase cycles performed on the device, changes in temperature, etc., may cause the threshold voltage of the select gate device to increase or decrease over time. This shift relative to the target value may result in charge loss, thereby causing the select gate device to operate improperly, and may cause reliability issues in the data stored on the word line 230 of the corresponding sub-block. Accordingly, in one embodiment, the select gate maintenance component 113 may periodically perform maintenance operations on the select gate devices SGD0, SGD1, SGD2 or SGS0, SGS1, SGS2 of the data block 200. In one embodiment, the maintenance operation includes a touch-up operation, in which the select gate maintenance component 113 iteratively applies a series of programming pulses to the select gate device to adjust the current threshold voltage of the select gate device back to the target threshold voltage; and after each iteration, verify whether the current threshold voltage has reached the target threshold voltage. After returning to the target threshold voltage, the select gate device can operate properly so that it will be correctly turned on or off in response to receiving the corresponding control signal.

[0037] Figure 3 300 is a flow chart of an example method for performing select gate maintenance in a data block of a memory device in response to a block erase operation according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The select gate maintenance component 113 is performed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0038] At operation 305, processing logic receives a request to erase a data block 200 of a memory device 130. In one embodiment, the memory subsystem controller 115 generates the request to erase the data block 200 in response to performing an internal memory management operation (e.g., garbage collection). For example, if it is determined that the data block 200 no longer contains any valid data, the memory subsystem controller 115 may determine to erase the remaining invalid data on the data block 200 so that the data block can be used to store other data instead.

[0039] At operation 310, processing logic determines the number of program / erase cycles performed on the data block 200 (i.e., the program / erase count (PEC)). A program / erase cycle may include programming data into the data block 200, and then erasing the data block 200. This process may occur many times during the useful life of the data block 200, as the data block is constantly being re-used in the memory subsystem 110. In one embodiment, the select gate maintenance component 113 or some other component in the memory subsystem controller 115 maintains a counter to track the number of program / erase operations performed on the data block 200. In one embodiment, the counter is maintained at the block level and incremented each time a program / erase cycle is performed on the data block 200. In one embodiment, the counter is initialized to an initial value (e.g., 0) and incremented in response to a read operation. Accordingly, the value of the counter represents the current program / erase count of the data block 200.

[0040] At operation 315, processing logic performs an erase operation to erase the data block 200 in response to the request. In one embodiment, the memory subsystem controller 115 issues an erase command to the memory device 130. In response, the memory device 130 may erase the remaining invalid data in the data block 200. At operation 320, processing logic determines whether the data block 200 is successfully erased. In one embodiment, in response to issuing the erase command to the memory device 130, the memory subsystem controller 115 receives a confirmation message from the memory device 130 indicating that the data block 200 is erased. If the memory subsystem controller 115 does not receive the confirmation message within a threshold time period, the memory subsystem controller 115 may determine that the erase operation is unsuccessful. If the erase operation is unsuccessful, processing may proceed to operation 350, where the processing logic retires the data block 200.

[0041] If the data block is successfully erased, then at operation 325, the processing logic determines whether the number of program / erase cycles performed on the data block 200 meets the scan threshold condition. In one embodiment, the select gate maintenance component 113 compares the number of program / erase cycles determined at operation 310 to the scan threshold. The scan threshold may depend on how the memory block is configured (e.g., configured as SLC memory, MLC memory, TLC memory, QLC memory). For example, the scan threshold may be set at a level based on testing or other diagnostics, at which time the select gate integrity scan is suitable for determining the error level or other reliability measure of the select gate device of the data block 200. If the number of program / erase cycles does meet or exceed the scan threshold, the select gate maintenance component 113 may further determine whether the number of program / erase cycles is equal to a defined interval of the data block 200. The defined interval may represent a certain number of program / erase cycles above the scan threshold, so that whenever the number of program / erase cycles occurs, a select gate integrity scan may be performed. For example, if the scan threshold is 2000 cycles and the defined interval is 100 cycles, the select gate maintenance component 113 may perform a select gate integrity scan every 100 cycles above 2000 (i.e., 2100, 2200, 2300, etc.). Thus, in one embodiment, the scan threshold condition is met when the program / erase cycles meet or exceed the scan threshold and are equal to the defined interval. If the number of program / erase cycles does not meet or exceed the scan threshold or is not equal to the defined interval, the processing logic determines that the scan threshold criteria are not met, returns to operation 305, and waits to receive another request to erase the data block 200.

[0042] If the number of program / erase cycles performed on the data block 200 satisfies the scan threshold condition, then at operation 330, the processing logic performs a first threshold voltage integrity scan on the data block 200 to determine a first error rate associated with a current threshold voltage of at least one select gate device SGD0 of the data block 200. During the scan, the select gate maintenance component 113 identifies one or more reliability statistics, such as a raw bit error rate (RBER), which represents the number of bit errors per total number of bits experienced by the select gate. In one embodiment, during the scan, the select gate maintenance component 113 applies one or more read voltages to the select gate device SGD0 and receives one or more output values ​​based on the one or more read voltages. For example, the select gate maintenance component 113 reads an original codeword (i.e., a series of a fixed number of bits) from the select gate device SGD0, applies the codeword to an error correction code (ECC) decoder to generate a decoded codeword, and compares the decoded codeword with the original codeword (i.e., an expected output value). The select gate maintenance component 113 can count the number of flipped bits between the decoded codeword and the original codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the RBER. The select gate maintenance component 113 can repeat this process for additional codewords until each of the select gate devices in the data block 200 has been scanned.

[0043] At operation 335, processing logic determines whether a first error rate associated with the current threshold voltage of the at least one select gate device SGD0 satisfies an error threshold criterion. In one embodiment, the select gate maintenance component 113 compares the first error rate to an error threshold representing the error correction capability of the memory device. If the first error rate does not meet or exceed the error threshold, processing logic determines that the error threshold criterion is not met and returns to operation 305. However, if the first error rate does meet or exceed the error threshold, processing logic determines that the error threshold criterion is met.

[0044] In one embodiment, the select gate maintenance component 113 checks the first error rate to determine whether the current threshold voltage has dropped below the target threshold voltage or increased above the target threshold voltage. In one embodiment, if the current threshold voltage has dropped below the target threshold voltage, the select gate maintenance component 113 may perform a touch-up operation to increase the current target threshold voltage to the target threshold voltage. In one embodiment, the select gate maintenance component 113 performs a single scan to determine whether the current threshold voltage has dropped below the target threshold voltage (e.g., to identify a "low tail") or increased above the target threshold voltage (e.g., to identify a "high tail"). In another embodiment, separate scans may be performed. For example, the select gate maintenance component 113 may perform a second scan to determine whether the current threshold voltage has increased above the target threshold voltage. If the current threshold voltage has increased above the target threshold voltage, the select gate maintenance component 113 may retire the data block 200.

[0045] If the first error rate associated with the current threshold voltage of the at least one select gate device SGD0 satisfies the error threshold criterion, then at operation 340, the processing logic performs a touch-up operation on the at least one select gate device SGD0 to adjust the current threshold voltage to the target threshold voltage. In one embodiment, the select gate maintenance component 113 iteratively applies a plurality of programming pulses to the at least one select gate device SGD0, to a subset of the select gate devices of the data block 200, or to all the select gate devices of the data block 200 to adjust the current threshold voltage of the select gate device back to the target threshold voltage. The select gate maintenance component 113 may verify whether the current threshold voltage has reached the target threshold voltage after each iteration to ensure that the threshold voltage is slowly stepped back to the target threshold voltage without exceeding the target threshold voltage.

[0046] At operation 345, processing logic performs a second threshold voltage integrity scan on the data block to determine a second error rate associated with the current threshold voltage of the at least one select gate device SGD0 of the data block 200 after performing the touch-up operation, and determines whether the second error rate associated with the current threshold voltage of the at least one select gate device SGD0 after performing the touch-up operation satisfies the error threshold criteria. If the second error rate associated with the current threshold voltage of the at least one select gate device SGD0 after performing the touch-up operation satisfies the error threshold criteria, then at operation 350, processing logic retires the data block 200. In one embodiment, the memory subsystem controller 115 adds the data block 200 to a list of retired data blocks in order to prevent new data from being written to the data block 200 in the future. If the second error rate associated with the current threshold voltage of the at least one select gate device SGD0 after performing the touch-up operation does not satisfy the error threshold criteria (i.e., the error rate is below the error threshold), the block is returned to the available block pool, and processing logic returns to operation 305.

[0047] In one embodiment, the select gate maintenance component 113 may blindly perform a touch-up operation at operation 340 without first performing a threshold voltage integrity scan at operation 330. For example, the select gate maintenance component 113 may compare the number of program / erase cycles determined at operation 310 to a second scan threshold, which may be higher than the scan threshold used at operation 325. This second, higher scan threshold may be set at a level based on testing or other diagnostics when a substantial shift in the threshold voltage of the select gate devices of the data block 200 is almost certain to have occurred. Accordingly, the select gate maintenance component 113 may bypass the threshold voltage integrity scan and proceed directly to performing a touch-up operation on the select gate devices. This may prevent the memory subsystem controller 115 from wasting power and bandwidth to perform the scan.

[0048] Figure 4 4 is a flow chart of an example method for performing select gate maintenance in a data block of a memory device in response to a block fail operation according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1The select gate maintenance component 113 is performed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0049] At operation 405, processing logic receives a request to invalidate a data block 200 of a memory device 130. In one embodiment, the memory subsystem controller 115 generates the request to invalidate the data block 200 in response to performing an internal memory management operation (e.g., garbage collection). For example, if it is determined that the data block 200 no longer contains any valid data, the memory subsystem controller 115 may determine to invalidate the data block 200 so that the data block can be later erased and used to store other data instead.

[0050] At operation 410, processing logic determines the number of program / erase cycles performed on the data block 200 (i.e., the program / erase count (PEC)). A program / erase cycle may include programming data into the data block 200, and then erasing the data block 200. This process may occur many times during the useful life of the data block 200, as the data block is constantly being re-used in the memory subsystem 110. In one embodiment, the select gate maintenance component 113 or some other component in the memory subsystem controller 115 maintains a counter to track the number of program / erase operations performed on the data block 200. In one embodiment, the counter is maintained at the block level and incremented each time a program / erase cycle is performed on the data block 200. In one embodiment, the counter is initialized to an initial value (e.g., 0) and incremented in response to a read operation. Accordingly, the value of the counter represents the current program / erase count of the data block 200.

[0051] At operation 415, processing logic marks the data block as invalid. In one embodiment, the memory subsystem controller 115 adds the identifier of the data block to a list of invalid data blocks. At operation 425, processing logic determines whether the number of program / erase cycles performed on the data block 200 meets the scan threshold condition. In one embodiment, the select gate maintenance component 113 compares the number of program / erase cycles determined at operation 410 to the scan threshold. The scan threshold may depend on how the memory block is configured (e.g., configured as SLC memory, MLC memory, TLC memory, QLC memory). For example, the scan threshold may be set at a level based on testing or other diagnostics, at which time the select gate integrity scan is suitable for determining the error level or other reliability measure of the select gate device of the data block 200. If the number of program / erase cycles does meet or exceed the scan threshold, the select gate maintenance component 113 may further determine whether the number of program / erase cycles is equal to the defined interval of the data block 200. The defined interval may represent a certain number of program / erase cycles above the scan threshold, such that whenever that number of program / erase cycles occurs, a select gate integrity scan may be performed. For example, if the scan threshold is 2000 cycles and the defined interval is 100 cycles, the select gate maintenance component 113 may perform a select gate integrity scan every 100 cycles above 2000 (i.e., 2100, 2200, 2300, etc.). Thus, in one embodiment, when the program / erase cycles meet or exceed the scan threshold and are equal to the defined interval, the scan threshold condition is met. If the number of program / erase cycles does not meet or exceed the scan threshold or is not equal to the defined interval, the processing logic determines that the scan threshold criteria are not met, returns to operation 405, and waits to receive another request to erase the data block 200.

[0052] If the number of program / erase cycles performed on the data block 200 satisfies the scan threshold condition, then at operation 430, the processing logic performs a first threshold voltage integrity scan on the data block 200 to determine a first error rate associated with a current threshold voltage of at least one select gate device SGD0 of the data block 200. During the scan, the select gate maintenance component 113 identifies one or more reliability statistics, such as a raw bit error rate (RBER), which represents the number of bit errors per total number of bits experienced by the select gate. In one embodiment, during the scan, the select gate maintenance component 113 applies one or more read voltages to the select gate device SGD0 and receives one or more output values ​​based on the one or more read voltages. For example, the select gate maintenance component 113 reads an original codeword (i.e., a series of a fixed number of bits) from the select gate device SGD0, applies the codeword to an error correction code (ECC) decoder to generate a decoded codeword, and compares the decoded codeword with the original codeword (i.e., an expected output value). The select gate maintenance component 113 can count the number of flipped bits between the decoded codeword and the original codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the RBER. The select gate maintenance component 113 can repeat this process for additional codewords until each of the select gate devices in the data block 200 has been scanned.

[0053] At operation 435, processing logic determines whether a first error rate associated with the current threshold voltage of the at least one select gate device SGD0 satisfies an error threshold criterion. In one embodiment, the select gate maintenance component 113 compares the first error rate to an error threshold representing the error correction capability of the memory device. If the first error rate does not meet or exceed the error threshold, processing logic determines that the error threshold criterion is not met and returns to operation 405. However, if the first error rate does meet or exceed the error threshold, processing logic determines that the error threshold criterion is met.

[0054] If the first error rate associated with the current threshold voltage of the at least one select gate device SGD0 satisfies the error threshold criterion, then at operation 440, the processing logic performs a touch-up operation on the at least one select gate device SGD0 to adjust the current threshold voltage to the target threshold voltage. In one embodiment, the select gate maintenance component 113 iteratively applies a plurality of programming pulses to the at least one select gate device SGD0, to a subset of the select gate devices of the data block 200, or to all the select gate devices of the data block 200 to adjust the current threshold voltage of the select gate device back to the target threshold voltage. The select gate maintenance component 113 may verify whether the current threshold voltage has reached the target threshold voltage after each iteration to ensure that the threshold voltage is slowly stepped back to the target threshold voltage without exceeding the target threshold voltage.

[0055] At operation 445, processing logic performs a second threshold voltage integrity scan on the data block to determine a second error rate associated with the current threshold voltage of the at least one select gate device SGD0 of the data block 200 after performing the touch-up operation, and determines whether the second error rate associated with the current threshold voltage of the at least one select gate device SGD0 after performing the touch-up operation satisfies the error threshold criteria. If the second error rate associated with the current threshold voltage of the at least one select gate device SGD0 after performing the touch-up operation satisfies the error threshold criteria, then at operation 450, processing logic retires the data block 200. In one embodiment, the memory subsystem controller 115 adds the data block 200 to a list of retired data blocks in order to prevent new data from being written to the data block 200 in the future. If the second error rate associated with the current threshold voltage of the at least one select gate device SGD0 after performing the touch-up operation does not satisfy the error threshold criteria (i.e., the error rate is below the error threshold), processing logic returns to operation 405.

[0056] Figure 5 An example machine of computer system 500 is shown, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the embodiment of the present invention may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0057] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0058] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 518, which communicate with each other via a bus 530.

[0059] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 502 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 to communicate on a network 520.

[0060] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein. The instructions 526 may also reside, in whole or in part, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0061] In one embodiment, instructions 526 include implementing Figure 1 The functional instructions of the select gate maintenance component 113 are provided. Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0062] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0063] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0064] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0065] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0066] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0067] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It should be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory device; as well as A processing device operatively coupled to the memory device to perform operations comprising: receiving a request to erase a data block of the memory device; determining a number of program / erase cycles performed on the data block; Performing an erase operation to erase the data block; determining that the number of program / erase cycles performed on the data block satisfies a scan threshold condition; performing a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block; as well as in response to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, performing a touch-up operation on the at least one select gate device to adjust the current threshold voltage to a target threshold voltage, Wherein performing the touch-up operation on the at least one select gate device comprises: iteratively applying a plurality of programming pulses to at least one select gate device, the plurality of programming pulses being used to adjust the current threshold voltage to the target threshold voltage; as well as After each iteration it is verified whether the current threshold voltage has reached the target threshold voltage.

2. The system of claim 1 , wherein performing the erase operation comprises: issuing a block erase command to the memory device; as well as A determination is made as to whether the block of data is successfully erased, wherein the processing device determines whether the number of program / erase cycles performed on the block of data satisfies the scan threshold condition in response to determining that the block of data is successfully erased.

3. The system of claim 1 , wherein determining that the number of program / erase cycles performed on the data block satisfies the scan threshold condition comprises: determining that the number of program / erase cycles performed on the data block is greater than or equal to a threshold number of program / erase cycles; as well as The number of program / erase cycles performed on the data block is determined to be equal to a defined interval of the data block.

4. The system of claim 1 , wherein performing the first threshold voltage integrity scan on the data block comprises: applying one or more read voltages to the at least one select gate device of the data block; receiving one or more output values ​​based on the one or more read voltages; as well as The one or more output values ​​are compared to expected output values ​​based on the target threshold voltage.

5. The system of claim 1, wherein the processing device is further configured to perform operations comprising: The first error rate associated with the current threshold voltage of the at least one select gate device is compared to an error rate threshold, wherein the first error rate satisfies the error threshold criteria when the first error rate meets or exceeds the error rate threshold.

6. The system of claim 1, wherein the processing device is further configured to perform operations comprising: performing a second threshold voltage integrity scan on the data block to determine a second error rate associated with the current threshold voltage of at least one select gate device of the data block after performing the touch-up operation; and In response to the second error rate associated with the current threshold voltage of at least one select gate device after performing the touch-up operation not satisfying the error threshold criteria, retiring the data block.

7. A method comprising: Detecting the occurrence of a triggering event; determining a number of program / erase cycles performed on the data block; determining whether the number of program / erase cycles performed on the data block satisfies a threshold condition; as well as in response to the number of program / erase cycles performed on the data block satisfying the threshold condition, performing a touch-up operation on at least one select gate device to adjust a current threshold voltage of the at least one select gate device to a target threshold voltage, Wherein performing the touch-up operation on the at least one select gate device comprises: iteratively applying a plurality of programming pulses to at least one select gate device, the plurality of programming pulses being used to adjust the current threshold voltage to the target threshold voltage; as well as After each iteration it is verified whether the current threshold voltage has reached the target threshold voltage.

8. The method of claim 7, wherein detecting the occurrence of the triggering event comprises at least one of: receiving a request to erase the data block, or receiving a request to invalidate the data block.

9. The method according to claim 7, further comprising: responsive to the number of program / erase cycles performed on the data block satisfying the threshold condition, performing a first threshold voltage integrity scan on the data block to determine a first error rate associated with the current threshold voltage of at least one select gate device of the data block; as well as In response to the first error rate associated with the current threshold voltage of at least one select gate device satisfying an error threshold criterion, the touch-up operation is performed on at least one select gate device.

10. The method of claim 7, wherein determining whether the number of program / erase cycles performed on the data block satisfies the threshold condition comprises: determining whether the number of program / erase cycles performed on the data block is greater than or equal to a threshold number of program / erase cycles; as well as A determination is made as to whether the number of program / erase cycles performed on the block of data is equal to a defined interval of the block of data.

11. The method of claim 9, wherein performing the first threshold voltage integrity scan on the data block comprises: applying one or more read voltages to at least one select gate device of the data block; receiving one or more output values ​​based on the one or more read voltages; as well as The one or more output values ​​are compared to expected output values ​​based on the target threshold voltage.

12. The method according to claim 9, further comprising: performing a second threshold voltage integrity scan on the data block to determine a second error rate associated with the current threshold voltage of at least one select gate device of the data block after performing the touch-up operation; as well as In response to the second error rate associated with the current threshold voltage of at least one select gate device after performing the touch-up operation not satisfying the error threshold criteria, retiring the data block.

13. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a request to erase a data block of a memory device; determining a number of program / erase cycles performed on the data block; Performing an erase operation to erase the data block; determining that the number of program / erase cycles performed on the data block satisfies a scan threshold condition; performing a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block; as well as in response to the first error rate associated with the current threshold voltage of at least one select gate device satisfying an error threshold criterion, performing a touch-up operation on the at least one select gate device to adjust the current threshold voltage to a target threshold voltage, Wherein performing the touch-up operation on the at least one select gate device comprises: iteratively applying a plurality of programming pulses to at least one select gate device, the plurality of programming pulses being used to adjust the current threshold voltage to the target threshold voltage; as well as It is verified after each iteration whether the current threshold voltage has reached the target threshold voltage.

14. The non-transitory computer-readable storage medium of claim 13, wherein performing the erase operation comprises: issuing a block erase command to the memory device; as well as A determination is made as to whether the block of data is successfully erased, wherein the processing device determines whether the number of program / erase cycles performed on the block of data satisfies the scan threshold condition in response to determining that the block of data is successfully erased.

15. The non-transitory computer-readable storage medium of claim 13, wherein determining that the number of program / erase cycles performed on the data block satisfies the scan threshold condition comprises: determining that the number of program / erase cycles performed on the data block is greater than or equal to a threshold number of program / erase cycles; as well as The number of program / erase cycles performed on the data block is determined to be equal to a defined interval of the data block.

16. The non-transitory computer-readable storage medium of claim 13, wherein performing the first threshold voltage integrity scan on the data block comprises: applying one or more read voltages to at least one select gate device of the data block; receiving one or more output values ​​based on the one or more read voltages; as well as The one or more output values ​​are compared to expected output values ​​based on the target threshold voltage.

17. The non-transitory computer-readable storage medium of claim 13, wherein the instructions are configured to cause the processing device to further perform operations comprising: performing a second threshold voltage integrity scan on the data block to determine a second error rate associated with the current threshold voltage of at least one select gate device of the data block after performing the touch-up operation; and In response to the second error rate associated with the current threshold voltage of at least one select gate device after performing the touch-up operation not satisfying the error threshold criteria, retiring the data block.

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