Semiconductor device with word line separation layer

Abstract

A semiconductor device is provided. The semiconductor device includes a peripheral circuit structure disposed on a substrate, a lower stack disposed on the peripheral circuit structure, and an upper stack disposed on the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the plurality of lower insulating layers, a plurality of channel structures extending through the lower stack and the upper stack in a cell array region, a pair of partition insulating layers extending through the lower stack and the upper stack in a vertical direction and extending in a horizontal direction, the pair of partition insulating layers being spaced apart from each other in the vertical direction, and a word line partition layer disposed at an upper portion of the lower stack and crossing the pair of partition insulating layers when viewed in a plan view, the word line partition layer extending through at least one of the plurality of lower word lines in the vertical direction.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2019-0173236, filed on December 23, 2019, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The inventive concept relates to semiconductor devices, and more particularly, to semiconductor memory devices having a multi-stack structure. BACKGROUND

[0003] Three-dimensional non-volatile memory devices having a multi-stack structure can be thinner, lighter, simpler, and more integrated than conventional memory devices. Such non-volatile memory devices include at least an upper stack, a lower stack, and word lines. However, the word lines of the lower stack can be unintentionally connected to the word lines of the upper stack (e.g., referred to as word line bridging) due to misalignment of channel holes at a boundary between the lower stack and the upper stack during fabrication. Such word line bridging can cause malfunctions such as data being written to an erroneous area of the memory device. SUMMARY

[0004] At least one embodiment of the inventive concept provides a semiconductor device including a word line separation layer vertically extending through at least one lower word line.

[0005] According to an exemplary embodiment of the inventive concept, a semiconductor device includes a substrate including a cell array region and a connection region, the connection region including a through silicon via (TSV) region; a peripheral circuit structure disposed on the substrate; a lower stack disposed on the peripheral circuit structure and an upper stack disposed on the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the plurality of lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array region; a plurality of dummy channel structures extending through the lower stack and the upper stack in the connection region; a pair of separation insulating layers vertically extending through the lower stack and the upper stack and extending in a first direction, the pair of separation insulating layers spaced apart from each other in a second direction crossing the first direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer vertically extending through at least one of the plurality of lower word lines.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a substrate including a cell array region and a first connection region and a second connection region disposed on opposite sides of the cell array region, each of the first connection region and the second connection region including a plurality of through-silicon via (TSV) regions; a peripheral circuit structure disposed on the substrate; a lower stack and an upper stack, the lower stack being disposed on the peripheral circuit structure and the upper stack being disposed on the lower stack, the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the plurality of lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array region; a plurality of dummy channel structures extending through the lower stack and the upper stack in the connection region; a plurality of separating insulating layers extending vertically through the lower stack and the upper stack and extending in a first direction, the plurality of separating insulating layers being spaced apart from each other in a second direction intersecting the first direction; and a plurality of word line separating layers disposed at the upper portion of the lower stack and intersecting two adjacent separating insulating layers among the plurality of separating insulating layers, the plurality of word line separating layers extending vertically through at least one of the plurality of lower word lines. The plurality of word line separator layers are arranged in a zigzag pattern along the second direction within the first connection area and the second connection area, and each of the plurality of word line separator layers is disposed between the cell array area and the plurality of TSV areas.

[0007] According to exemplary embodiments of the inventive concept, a semiconductor device may include: a substrate including a cell array region and a connection region, the connection region including a through-silicon via (TSV) region; a peripheral circuit structure disposed on the substrate; a lower conductive layer disposed on the peripheral circuit structure; a connection conductive layer disposed on the lower conductive layer in the cell array region; a connection molding layer disposed on the lower conductive layer in the connection region; a support member disposed on the connection conductive layer and the connection molding layer; a buried insulating layer disposed in the TSV region and extending through the lower conductive layer, the connection molding layer and the support member; a lower stack member disposed on the support member, the lower stack member including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the plurality of lower insulating layers; and an upper stack member disposed on the lower stack member, the upper stack member including a plurality of lower word lines. A plurality of upper insulating layers and a plurality of upper word lines alternately stacked with the plurality of upper insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array region; a plurality of dummy channel structures extending through the lower stack and the upper stack in the connection region; a pair of separating insulating layers extending vertically through the lower stack and the upper stack and extending in a first direction, the pair of separating insulating layers being spaced apart from each other in a second direction intersecting the first direction; a word line separator layer disposed at the upper part of the lower stack and intersecting the pair of separating insulating layers, the word line separator layer extending vertically through at least one of the plurality of lower word lines; and a TSV disposed in the TSV region, the TSV extending through the upper stack and the lower stack and connected to the peripheral circuit structure.

[0008] According to an exemplary embodiment of the inventive concept, a method for manufacturing a semiconductor device includes: forming a substrate, the substrate including a cell array region and a connection region, the connection region including a through-silicon via (TSV) region; forming a peripheral circuit structure on the substrate; forming a lower stack on the peripheral circuit structure, the lower stack including a plurality of lower insulating layers and a plurality of lower sacrificial layers stacked alternately with the plurality of lower insulating layers; forming a word line separator layer at the upper portion of the lower stack, the word line separator layer extending vertically through at least one of the plurality of lower sacrificial layers between the cell array region and the TSV region; and forming an upper stack on the lower stack, the upper stack... The stack includes multiple upper insulating layers and multiple upper sacrificial layers stacked alternately with the multiple upper insulating layers; a channel structure extending through the lower stack and the upper stack is formed in the cell array region; a dummy channel structure extending through the lower stack and the upper stack is formed in the connection region; multiple separating insulating layers are formed, which extend vertically through the lower stack and the upper stack, extend horizontally, and intersect with word line separating layers; the multiple lower sacrificial layers and the multiple upper sacrificial layers are removed; multiple lower word lines are formed between the multiple lower insulating layers; and multiple upper word lines are formed between the multiple upper insulating layers. Attached Figure Description

[0009] The inventive concept will become more apparent to those skilled in the art from the following description of exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0010] FIG. 1 This is a layout of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0011] FIG. 2 yes FIG. 1 An enlarged view of the semiconductor device shown in the image.

[0012] FIGS. 3A-3B It is intercepted along lines I-I', II-II', and III-III'. FIG. 2 The image shows a vertical cross-sectional view of a semiconductor device.

[0013] FIGS. 4-5 yes FIG. 3A An enlarged view of the semiconductor device shown in the image.

[0014] FIG. 6 This is a layout of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0015] FIGS. 7A-7B It is intercepted along lines IV-IV' and V-V'. FIG. 6 The image shows a vertical cross-sectional view of a semiconductor device.

[0016] FIG. 8This is a layout of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0017] FIGS. 9A-9B It is intercepted along lines VI-VI' and VII-VII'. FIG. 8 The image shows a vertical cross-sectional view of a semiconductor device.

[0018] FIGS. 10-11 This is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0019] FIG. 12 This is a layout of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0020] FIG. 13 It is intercepted along line VIII-VIII'. FIG. 12 The image shows a vertical cross-sectional view of a semiconductor device.

[0021] FIGS. 14A-24B This is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0022] FIG. 1 This is a layout of a semiconductor device according to an exemplary embodiment of the inventive concept. FIG. 2 yes FIG. 1 An enlarged view of the semiconductor device shown in the image. FIGS. 3A-3B It is intercepted along lines I-I', II-II', and III-III'. FIG. 2 The figure shows a vertical cross-sectional view of a semiconductor device. A semiconductor device (i.e., semiconductor device 100) according to an exemplary embodiment of the present invention may include flash memory such as 3D-NAND.

[0023] Reference FIG. 1A semiconductor device 100 according to an exemplary embodiment of the present invention includes a cell array region CA (e.g., a plurality of memory cells) and a connection region EA disposed on opposite sides of the cell array region CA. Each connection region EA may include a through-silicon-via (TSV) region TA. The TSV regions TA of the connection region EA may be arranged in a zigzag pattern within the connection region EA on opposite sides of the cell array region CA. In an exemplary embodiment, the zigzag-arranged TSV regions TA include a plurality of TSV regions TA (or TSVs) arranged in a first row and another plurality of TSV regions (or TSVs) arranged in a second row offset from the first row. In an exemplary embodiment of the present invention, the semiconductor device 100 includes a separating insulating layer WLC and a word line separating layer WLS. The separating insulating layer WLC may extend throughout the cell array region CA and the connection region EA along a first direction D1. When viewed in a plan view, the word line separating layer WLS may have strips or segments extending in a second direction D2. When viewed in a side view or cross-sectional view, the word line separating layer WLS may have a dam shape. In an exemplary embodiment of the inventive concept, the word line separator layer (WLS) is formed to intersect with two adjacent insulating separator layers (WLC). The word line separator layer (WLS) can be disposed between the cell array region CA and the TSV region TA, for example, the word line separator layer (WLS) can be disposed between the cell array region CA and the TSV region TA disposed between the two adjacent insulating separator layers (WLC) closest to the cell array region CA. In an exemplary embodiment of the inventive concept, the word line separator layer (WLS) is arranged in a single column within the connection region EA. In an alternative embodiment, the word line separator layer (WLS) is arranged in multiple columns within the connection region EA, offset from each other in a zigzag pattern along a second direction D2.

[0024] Reference FIG. 2 , FIG. 3A and FIG. 3B The cell array area CA may include multiple channel structures CS. The connection area EA may include multiple dummy channel structures DCS. The connection area EA may include a pad (or "solder pad") area PA and a TSV area TA, where the pad area PA includes multiple word line contacts WC.

[0025] The semiconductor device 100 disclosed herein may have a peripheral cell-on-a-pipe (COP) structure. For example, the semiconductor device 100 may include a peripheral circuit structure PS and a cell array structure CAS disposed on the peripheral circuit structure PS. In an exemplary embodiment of the inventive concept, the peripheral circuit structure PS includes a substrate 10, a device isolation layer 12, an impurity region 14, a transistor 20, a contact plug 30, peripheral circuit lines 32, and a peripheral insulating layer 34.

[0026] The substrate 10 may include a device isolation layer 12 and an impurity region 14. Transistors 20, contact plugs 30, and peripheral circuit lines 32 may be disposed on the substrate 10. The substrate 10 may include a semiconductor material. In an exemplary embodiment, the substrate 10 is entirely a semiconductor material. For example, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a silicon-on-insulator (SOI) substrate. In an example embodiment, the substrate 10 may include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor.

[0027] Impurity region 14 may be disposed adjacent to a corresponding transistor 20 in transistor 20. In an exemplary embodiment, impurity region 14 is in contact with one of the transistors 20. A peripheral insulating layer 34 may cover the transistor 20 and the contact plug 30. The contact plug 30 may be electrically connected to a corresponding impurity region 14 in impurity region 14. A peripheral circuit line 32 may be connected to a corresponding contact plug 30 in contact plug 30.

[0028] The cell array structure CAS can be disposed on the outer insulating layer 34. In an exemplary embodiment, the cell array structure CAS includes a lower stack 110, a lower interlayer insulating layer 116, a word line separator layer WLS, an upper stack 130, an upper interlayer insulating layer 136, a channel structure CS, a dummy channel structure DCS, a separator insulating layer WLC, dummy separator insulating layers DWLC1 and DWLC2, and a through silicon via (TSV) 170. The cell array structure CAS may also include a lower conductive layer 40, a connection molding layer 42, a connection conductive layer 43, a support member 44, and a buried insulating layer 46 disposed below the lower stack 110.

[0029] A lower conductive layer 40 may be disposed on the peripheral circuit structure PS. The lower conductive layer 40 may correspond to a common source electrode. In an exemplary embodiment, the lower conductive layer 40 comprises doped polysilicon. In an exemplary embodiment, a connection molding layer 42 is partially disposed on the lower conductive layer 40 within a connection region EA. In an exemplary embodiment, the connection molding layer 42 is disposed in a pad region PA, but not in a TSV region TA. In an exemplary embodiment, the connection molding layer 42 includes a sacrificial layer 42b and passivation layers 42a disposed on the upper and lower surfaces of the sacrificial layer 42b. For example, the sacrificial layer 42b may be disposed between a pair of passivation layers 42a. A connection conductive layer 43 may be disposed on the lower conductive layer 40 within a cell array region CA. A support member 44 may be disposed on both the connection molding layer 42 and the connection conductive layer 43. In an exemplary embodiment of the inventive concept, the support member 44 contacts the upper surface of the lower conductive layer 40 around a separating insulating layer WLC. A buried insulating layer 46 may be disposed on the lower conductive layer 40 within a TSV region TA. In an exemplary embodiment, the upper surface of the buried insulating layer 46 is disposed at the same level as the upper surface of the support member 44. In an exemplary embodiment, the buried insulating layer 46 is in contact with the first surface of the lower conductive layer 40 and with the second surface of the lower conductive layer 40 opposite to the first surface.

[0030] The lower stack 110 may include a plurality of alternately stacked lower insulating layers 112 and a plurality of lower word lines WL1. At least one of the lower word lines WL1 disposed at the lower portion of the lower stack 110 may be a ground select line. The lower stack 110 may have a stepped structure within the connection region EA. The lower stack 110 may include a plurality of lower sacrificial layers 114 alternately stacked with the plurality of lower insulating layers 112 in and around the TSV region TA. In an exemplary embodiment, each lower sacrificial layer 114 is disposed at the same level as its corresponding lower word line WL1. In an exemplary embodiment, the lower insulating layer 112 comprises silicon oxide. In an exemplary embodiment, the lower insulating layer 112 is entirely silicon oxide. The lower interlayer insulating layer 116 may cover the stepped structure of the lower stack 110.

[0031] In an exemplary embodiment, the upper stack 130 includes a plurality of alternately stacked upper insulating layers 132 and a plurality of upper word lines WL2. At least one of the upper word lines WL2 disposed at the upper portion of the upper stack 130 may be a series select line or a drain select line. The upper stack 130 may have a stepped structure within the connection region EA. The upper insulating layers 132 may include the same material as the lower insulating layer 112. The upper interlayer insulating layer 136 may cover the stepped structure of the upper stack 130.

[0032] In an exemplary embodiment of the inventive concept, the channel structure CS extends vertically through the connecting conductive layer 43, the support member 44, the lower stack member 110, and the upper stack member 130 within the cell array region CA. The channel structure CS can be electrically connected to the connecting conductive layer 43. In an exemplary embodiment of the inventive concept, the dummy channel structure DCS extends vertically through the connecting molding layer 42, the support member 44, the lower stack member 110, and the upper stack member 130 within the connection region EA. Furthermore, the dummy channel structure DCS can extend vertically through the lower interlayer insulating layer 116 and the upper interlayer insulating layer 136. The conductive pad 154 can be disposed on the channel structure CS and the dummy channel structure DCS.

[0033] A first upper insulating layer 160 may be disposed on the upper stack 130 and the upper interlayer insulating layer 136. A second upper insulating layer 162 may be disposed on the first upper insulating layer 160. A bit line plug 164 may be connected to a conductive pad 154 while extending through the first upper insulating layer 160 and the second upper insulating layer 162. A bit line 166 may be disposed on the second upper insulating layer 162 and may be connected to the bit line plug 164.

[0034] TSV 170 may be disposed within the TSV area TA. TSV 170 may extend vertically through the buried insulation layer 46, the lower stack 110, the lower interlayer insulation layer 116, and the upper interlayer insulation layer 136. Connector 172 may be disposed on TSV 170. In an exemplary embodiment, TSV 170 electrically connects connector 172 to peripheral circuit line 32 in the peripheral circuit structure PS.

[0035] In an exemplary embodiment of the inventive concept, the separating insulating layer WLC and the dummy separating insulating layers DWLC1 and DWLC2 are in contact with the lower conductive layer 40 and extend vertically through the support member 44, the lower stack member 110, the upper stack member 130, the upper interlayer insulating layer 136, and the first upper insulating layer 160. Although not shown, the separating insulating layer WLC and the dummy separating insulating layers DWLC1 and DWLC2 may extend through the lower interlayer insulating layer 116. The dummy separating insulating layers DWLC1 and DWLC2 may be disposed between the separating insulating layers WLC. In an exemplary embodiment of the inventive concept, the dummy separating insulating layers DWLC1 and DWLC2 extend in a first direction D1 and are arranged alternately in a second direction D2. The dummy separating insulating layer DWLC1 may be disposed in the connection region EA, while the dummy separating insulating layer DWLC2 may be disposed in the region extending from the cell array region CA to the connection region EA. The dummy separating insulating layer DWLC2 may be disposed in the cell array region CA.

[0036] In an exemplary embodiment, a word line separator layer (WLS) is disposed on the upper portion of the lower stack member 110 between the cell array region CA and the TSV region TA. The word line separator layer WLS can extend downward from the upper surface of the lower stack member 110 while extending vertically through the lower word lines WL1. Among the lower word lines WL1 separated by the corresponding word line separator layer WLS, the portion of the lower word line WL1 disposed in the cell array region CA can be electrically insulated from the portion disposed near the TSV region TA. Alternatively, the portion of the lower word line WL1 separated by the word line separator layer WLS can be electrically insulated from the channel structure CS. In an exemplary embodiment of the inventive concept, the word line separator layer WLS extends from the upper end of the lower stack member 110 through 13 lower word lines WL1, but is not limited thereto. In an exemplary embodiment, the word line separator layer WLS extends from the upper end of the lower stack member 110 through 13 or fewer lower word lines WL1. In an exemplary embodiment, the upper surface of the word line separator layer WLS is disposed at the same level as the upper surface of the lower interlayer insulation layer 116. In an exemplary embodiment, the lower surface of the word line separator layer WLS is positioned at a level higher than the upper surface of the support member 44.

[0037] When viewed in a plan view, the word line separator layer WLS can extend in the second direction D2, intersecting two adjacent separator insulating layers WLC. Furthermore, in an exemplary embodiment of the inventive concept, the word line separator layer WLS intersects with multiple dummy separator insulating layers DWLC1 and DWLC2. In an exemplary embodiment of the inventive concept, the word line separator layer WLS does not intersect with the dummy channel structure DCS. In an exemplary embodiment of the inventive concept, the separator insulating layer WLC completely intersects with the word line separator layer WLS. For example, when viewed in a longitudinal sectional view, the lateral ends of the word line separator layer WLS can be located outside two adjacent separator insulating layers WLC. In an exemplary embodiment of the inventive concept, the lateral ends of the word line separator layer WLS do not intersect with the dummy separator insulating layers DWLC1 and DWLC2. Furthermore, when viewed in a sectional view, the word line separator layer WLS can have a tapered shape with a gradually decreasing width as it extends downwards. In an exemplary embodiment of the inventive concept, the lower end of the cross section along the second direction D2 of the word line separator layer WLS is disposed outside the two adjacent separator insulating layers WLC.

[0038] FIGS. 4-5 yes FIG. 3A An enlarged view of the semiconductor device shown in the image.

[0039] Reference FIG. 4In an exemplary embodiment of the inventive concept, the channel structure CS includes an information storage layer 140, a channel layer 150, and a buried insulating pattern 152. The channel layer 150 may be disposed within the information storage layer 140, and the buried insulating pattern 152 may be disposed within the channel layer 150. In an exemplary embodiment of the inventive concept, the information storage layer 140 includes a barrier layer 142, a charge storage layer 144, and a tunnel insulating layer 146. The charge storage layer 144 may be disposed within the barrier layer 142, and the tunnel insulating layer 146 may be disposed within the charge storage layer 144. In an exemplary embodiment of the inventive concept, the channel layer 150 includes polysilicon. In an exemplary embodiment, the channel layer 150 is entirely made of polysilicon. The buried insulating pattern 152 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an exemplary embodiment of the inventive concept, the barrier layer 142 and the tunnel insulating layer 146 include silicon oxide. In an exemplary embodiment, the barrier layer 142 and the tunnel insulating layer 146 are entirely made of silicon oxide. The charge storage layer 144 may include silicon nitride. In an exemplary embodiment of the inventive concept, the charge storage layer 144 is entirely made of silicon nitride. The dummy channel structure DCS may have a structure substantially the same as that of the channel structure CS. For example, the dummy channel structure DCS may include an information storage layer 140, a channel layer 150, and a buried insulating pattern 152.

[0040] Reference FIG. 5 In an exemplary embodiment of the inventive concept, the conductive layer 43 extends through the information storage layer 140 while contacting the side surface of the channel layer 150. The portion of the conductive layer 43 in contact with the channel layer 150 may extend in the vertical direction.

[0041] FIG. 6 This is a layout of a semiconductor device according to an exemplary embodiment of the inventive concept. FIGS. 7A-7B It is intercepted along lines IV-IV' and V-V'. FIG. 6 The image shows a vertical cross-sectional view of a semiconductor device.

[0042] Reference FIG. 6 , FIG. 7A and FIG. 7B The semiconductor device 200 includes a word line separator layer WLS intersecting a spacer insulating layer WLC and dummy spacer insulating layers DWLC1 and DWLC2. In an exemplary embodiment, the word line separator layer WLS is stacked with a dummy channel structure DCS. For example, the word line separator layer WLS may be stacked with columns or rows of the dummy channel structures DCS. At least one of the dummy channel structures DCS may extend entirely through the word line separator layer WLS. In an exemplary embodiment of the inventive concept, at least one of the dummy channel structures DCS partially extends through the word line separator layer WLS.

[0043] FIG. 8 This is a layout of a semiconductor device according to an exemplary embodiment of the inventive concept. FIGS. 9A-9B It is intercepted along lines VI-VI' and VII-VII'. FIG. 8 The image shows a vertical cross-sectional view of a semiconductor device.

[0044] Reference FIG. 8 , FIG. 9A and FIG. 9B A semiconductor device 300 according to an exemplary embodiment of the inventive concept includes a word line separator layer WLS intersecting with a separating insulating layer WLC. In an exemplary embodiment of the inventive concept, the word line separator layer WLS does not intersect with dummy separating insulating layers DWLC1 and DWLC2. For example, the word line separator layer WLS may be disposed between the dummy separating insulating layers DWLC1 and DWLC2 and the TSV region TA. In an exemplary embodiment of the inventive concept, the word line separator layer WLS extends partially through the stepped structure of the lower stack 110.

[0045] FIGS. 10-11 This is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0046] Reference FIG. 10 Semiconductor device 400 includes a word line separator layer WLS extending vertically through a lower word line WL1. In an exemplary embodiment of the inventive concept, the word line separator layer WLS extends through a portion of the stepped structure of the lower stack 110. For example, the word line separator layer WLS may extend through a portion including the lower word line WL1 and the lower insulating layer 112. In an exemplary embodiment of the inventive concept, the upper surface of the word line separator layer WLS is disposed at a level lower than the upper surface of the lower interlayer insulating layer 116. For example, the upper surface of the word line separator layer WLS may be disposed at the same level as the upper surface of a corresponding lower word line WL1. In an exemplary embodiment of the inventive concept, the upper surface of the word line separator layer WLS is disposed at the same level as the lower surface of a corresponding lower insulating layer 112.

[0047] Reference FIG. 11 A semiconductor device 500 according to an exemplary embodiment of the inventive concept includes a word line separator layer WLS extending vertically through a lower word line WL1. In an exemplary embodiment, the word line separator layer WLS includes a gap V disposed in an inner portion of the word line separator layer WLS. In an exemplary embodiment, the gap V is a pocket or hole containing air or some other gas.

[0048] FIG. 12 This is a layout of a semiconductor device according to an exemplary embodiment of the inventive concept. FIG. 13 It is intercepted along line VIII-VIII'.FIG. 12 The image shows a vertical cross-sectional view of a semiconductor device.

[0049] Reference FIG. 12 and FIG. 13 A semiconductor device 600 according to an exemplary embodiment of the inventive concept includes a word line separator layer WLS intersecting with dummy separator insulating layers DWLC1 and DWLC2. In an exemplary embodiment of the inventive concept, the word line separator layer WLS contacts a side surface of the separator insulating layer WLC. For example, a cross-section of the word line separator layer WLS in a second direction D2 may contact a side surface of the separator insulating layer WLC.

[0050] FIGS. 14A-24B This is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. FIG. 14A , FIG. 15A , FIG. 16A , FIG. 17A , FIG. 18A , FIG. 19A , FIG. 20A , FIG. 21A , FIG. 22A , FIG. 23A and FIG. 24A Is FIG. 2 The image shows a cross-sectional view of a semiconductor device taken along lines I-I' and II-II'. FIG. 14B , FIG. 15B , FIG. 16B , FIG. 17B , FIG. 18B , FIG. 19B , FIG. 20B , FIG. 21B , FIG. 22B , FIG. 23B and FIG. 24B Is FIG. 2 The image shows a cross-sectional view of a semiconductor device taken along line III-III'.

[0051] Reference FIG. 14A and FIG. 14BA method for manufacturing a semiconductor device 100 includes forming a peripheral circuit structure PS, forming a lower conductive layer 40 on the peripheral circuit structure PS, and forming a connection molding layer 42 on the lower conductive layer 40. In an exemplary embodiment, the peripheral circuit structure PS includes a substrate 10, a device isolation layer 12, an impurity region 14, a transistor 20, a contact plug 30, peripheral circuit lines 32, and a peripheral insulating layer 34. The device isolation layer 12 and the impurity region 14 may be formed on the upper surface of the substrate 10. In an exemplary embodiment, the device isolation layer 12 includes an insulating layer made of, for example, silicon oxide or silicon nitride. The impurity region 14 may include n-type impurities or p-type impurities. The transistor 20 may be positioned adjacent to the impurity region 14. The peripheral circuit lines 32 may be disposed on the contact plug 30. The peripheral circuit lines 32 may be connected to the impurity region 14 via the contact plug 30. The peripheral insulating layer 34 may cover the transistor 20, the contact plug 30, and the peripheral circuit lines 32.

[0052] The lower conductive layer 40 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. In an exemplary embodiment of the inventive concept, the lower conductive layer 40 includes a doped polysilicon layer. In an exemplary embodiment, the connection molding layer 42 includes a sacrificial layer 42b and passivation layers 42a disposed on the upper and lower surfaces of the sacrificial layer 42b. The connection molding layer 42 may include a material having etch selectivity relative to the lower conductive layer 40. The passivation layer 42a may include a material having etch selectivity relative to the sacrificial layer 42b. In an exemplary embodiment, the passivation layer 42a may include silicon oxide, and the sacrificial layer 42b may include silicon nitride.

[0053] Reference FIG. 15A and FIG. 15B The method includes partially removing the connection molding layer 42, forming a support 44 on the lower conductive layer 40 and the connection molding layer 42, and forming a buried insulating layer 46 on the peripheral circuit structure PS. The connection molding layer 42 can be partially removed from the connection region EA by a patterning process, thereby partially exposing the upper surface of the lower conductive layer 40. For example, an etching process can be performed to remove a portion of the connection molding layer 42. The support 44 can be formed to cover the exposed lower conductive layer 40 and the connection molding layer 42. In an exemplary embodiment, the support 44 comprises polysilicon.

[0054] The lower conductive layer 40, the connecting molding layer 42, and the support member 44 can be partially removed from the TSV region TA, thereby partially exposing the upper surface of the peripheral insulating layer 34 of the peripheral circuit structure PS. A buried insulating layer 46 can be formed to cover the exposed peripheral insulating layer 34. The step of forming the buried insulating layer 46 may include performing a deposition process and a planarization process. In an exemplary embodiment of the inventive concept, the upper surface of the buried insulating layer 46 can be positioned at the same level as the upper surface of the support member 44.

[0055] Reference FIG. 16A and FIG. 16B The method includes forming a lower stack 110 and forming a lower interlayer insulating layer 116. The lower stack 110 may be formed on a support 44, and the lower interlayer insulating layer 116 may be formed on the lower stack 110. The steps of forming the lower stack 110 may include performing a deposition process and a trimming process. The lower stack 110 may include a plurality of lower insulating layers 112 and a plurality of lower sacrificial layers 114 stacked alternately with the plurality of lower insulating layers 112. In an exemplary embodiment, the lower insulating layer 112 includes silicon oxide. In an exemplary embodiment, the lower sacrificial layer 114 includes silicon nitride. The lower stack 110 may have a stepped structure formed by a trimming process within a connection region EA. The lower stack 110 may have a stepped structure formed by an etching process within the connection region EA. In an exemplary embodiment, the connection region EA includes a TSV region TA disposed between adjacent pad regions PA. The lower stack 110 may have a stepped structure in the pad region PA. In an exemplary embodiment, the lower stack 110 does not have a stepped structure in the TSV region TA and has a planar shape.

[0056] The lower interlayer insulating layer 116 may cover the lower stack 110 in the connection region EA. The lower interlayer insulating layer 116 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, high-k dielectric material, or a combination thereof. In an exemplary embodiment, the lower interlayer insulating layer 116 includes silicon oxide.

[0057] Reference FIG. 17A and FIG. 17B The method includes forming a trench T at the upper portion of the lower stack 110. The trench T can be formed by anisotropic etching of the upper portion of the lower stack 110, thereby removing a plurality of lower sacrificial layers 114 and a plurality of lower insulating layers 112. For example, portions of some of the lower sacrificial layers 114 and lower insulating layers 112 can be removed to form the trench T. In an exemplary embodiment, the trench T can be formed at a pad region PA disposed between the cell array region CA and the TSV region TA. The trench T can extend in one direction. The lower surface of the trench T can expose the lower insulating layer 112, but is not limited thereto. In an exemplary embodiment of the inventive concept, the lower surface of the trench T can be formed to expose either the lower sacrificial layer 114 or the lower insulating layer 112.

[0058] Reference FIG. 18A and FIG. 18B The method includes forming a word line separator layer (WLS) within a trench T. The steps of forming the word line separator layer WLS may include performing a deposition process and a planarization process. The word line separator layer WLS may have a tapered shape with a gradually decreasing width as it extends downwards. The word line separator layer WLS may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a high-k dielectric material, or a combination thereof. The word line separator layer WLS may include a material with etch selectivity relative to the lower sacrificial layer 114. For example, the word line separator layer WLS may include silicon oxide.

[0059] Reference FIG. 19A and FIG. 19B The method includes forming a lower channel via CH1 and a lower dummy channel via DCH1. The lower channel via CH1 can extend vertically through the lower stack 110 in the cell array region CA to expose the lower conductive layer 40. The lower dummy channel via DCH1 can extend vertically through the lower stack 110 and the lower interlayer insulating layer 116 in the connection region EA to expose the lower conductive layer 40. In an exemplary embodiment of the inventive concept, the lower dummy channel via DCH1 is not formed in the TSV region TA. The lower channel via CH1 and the lower dummy channel via DCH1 can be formed using a hard mask M disposed on the lower stack 110 and the lower interlayer insulating layer 116 via an anisotropic etching process. Because the lower dummy channel via DCH1 is not formed in the TSV region TA, the hard mask M is etched relatively lightly in and around the TSV region TA compared to the remaining areas. The hard mask M will have a greater height in and around the TSV region TA than it does around the cell array region CA.

[0060] Reference FIG. 20A and FIG. 20B The method includes forming a channel sacrificial layer 120 within a lower channel via CH1 and a lower dummy channel via DCH1. In an exemplary embodiment, the channel sacrificial layer 120 includes a first sacrificial material 121 and a second sacrificial material 122. The first sacrificial material 121 may be conformally formed within the lower channel via CH1 and the lower dummy channel via DCH1. The second sacrificial material 122 may be formed on the first sacrificial material 121, simultaneously filling the lower channel via CH1 and the lower dummy channel via DCH1. In an exemplary embodiment, the first sacrificial material 121 includes silicon nitride, and the second sacrificial material 122 includes polysilicon.

[0061] Reference FIG. 21A and FIG. 21BThe method includes forming an upper stack 130 and an upper interlayer insulating layer 136. The step of forming the upper stack 130 may include performing a deposition process and a trimming process. The upper stack 130 may be formed on a lower stack 110, and the upper interlayer insulating layer 136 may be formed on the upper stack 130. The upper stack 130 may include a plurality of upper insulating layers 132 and a plurality of upper sacrificial layers 134 alternately stacked with the upper insulating layers 132. The upper insulating layers 132 may include the same material as the lower insulating layer 112, and the upper sacrificial layers 134 may include the same material as the lower sacrificial layer 114. The upper stack 130 may have a stepped structure in a connection region EA. The upper interlayer insulating layer 136 may cover the upper stack 130 in the connection region EA. The upper interlayer insulating layer 136 may include the same material as the lower interlayer insulating layer 116.

[0062] Reference FIG. 22A and FIG. 22B The method includes forming an upper channel via CH2 and an upper dummy channel via DCH2. The upper channel via CH2 can be respectively disposed on a corresponding lower channel via CH1 in the lower channel via CH1. The upper channel via CH2 can expose the channel sacrificial layer 120 while extending vertically through the upper stack 130 in the cell array region CA. The upper dummy channel via DCH2 can be respectively disposed on a corresponding lower dummy channel via DCH1 in the lower dummy channel via DCH1. The upper dummy channel via DCH2 can expose the channel sacrificial layer 120 while extending vertically through the upper stack 130 and the upper interlayer insulating layer 136 in the connection region EA. In an exemplary embodiment, the upper dummy channel via DCH2 is not disposed in the TSV region TA.

[0063] Reference FIG. 23A and FIG. 23B The method includes removing the channel sacrificial layer 120, forming a channel structure CS, and forming a dummy channel structure DCS. The step of removing the channel sacrificial layer 120 may include forming sacrificial material within the upper channel hole CH2 and the upper dummy channel hole DCH2. The sacrificial material may include the same material as the first sacrificial material 121 and the second sacrificial material 122. Because the channel sacrificial layer 120 and the sacrificial material are removed, the lower channel hole CH1 can be connected to the corresponding upper channel hole CH2, and the lower dummy channel hole DCH1 can be connected to the corresponding upper dummy channel hole DCH2.

[0064] A channel structure CS is formed within the lower channel hole CH1 and the upper channel hole CH2. A dummy channel structure DCS is formed within the lower dummy channel hole DCH1 and the upper dummy channel hole DCH2. A conductive pad 154 may be formed on the channel structure CS and the dummy channel structure DCS. The conductive pad 154 may include a conductive layer of metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof.

[0065] A virtual channel structure DCS can have the same structure as a channel structure CS. Although a virtual channel structure DCS has... FIG. 23B The channel structure is shown not to be superimposed on the word line separator layer (WLS), but embodiments of this disclosure are not limited thereto. In an exemplary embodiment of the inventive concept, the dummy channel structure (DCS) extends vertically through the word line separator layer (WLS).

[0066] Reference FIG. 24A and FIG. 24B The method includes forming a conductive connection layer 43, forming a lower word line WL1 and an upper word line WL2, and forming a separating insulating layer WLC and dummy separating insulating layers DWLC1 and DWLC2. The step of forming the conductive connection layer 43 may include removing the conductive connection molding layer 42. In an exemplary embodiment, the lower stack 110 and the upper stack 130 are vertically and anisotropically etched to partially expose the lower conductive layer 40 and the conductive connection molding layer 42. The exposed conductive connection molding layer 42 can be selectively removed by an isotropic etching process. The conductive connection layer 43 can be formed in the space where the conductive connection molding layer 42 is removed. (Refer to...) FIG. 5 Before forming the conductive layer 43, the side surface of the information storage layer 140 is partially etched, thereby exposing the channel layer 150. The conductive layer 43 may contact the channel layer 150. The conductive layer 43 may include a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0067] The steps of forming the lower word line WL1 and the upper word line WL2 may include removing the lower sacrificial layer 114 and the upper sacrificial layer 134. The lower sacrificial layer 114 may be selectively removed, and then the lower word line WL1 may be formed between the lower insulating layers 112. Similarly, the upper sacrificial layer 134 may be selectively removed, and then the upper word line WL2 may be formed between the upper insulating layers 132. The lower word line WL1 and the lower insulating layer 112 may constitute a lower stack 110, and the upper word line WL2 and the upper insulating layer 132 may constitute an upper stack 130. In an exemplary embodiment, the lower sacrificial layer 114 is not removed from the TSV region TA and the area surrounding it. The lower word line WL1 and the upper word line WL2 may include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0068] The separating insulating layer WLC and the dummy separating insulating layers DWLC1 and DWLC2 can extend vertically through the lower stack 110, the upper stack 130, and the word line separator layer WLS. A first upper insulating layer 160 can be formed on the upper stack 130 and the upper interlayer insulating layer 136. The separating insulating layer WLC and the dummy separating insulating layers DWLC1 and DWLC2 can extend through the first upper insulating layer 160. FIG. 2As shown, the separator insulating layer WLC and the dummy separator insulating layers DWLC1 and DWLC2 can extend in a direction intersecting the word line separator layer WLS. The separator insulating layer WLC can extend from the cell array region CA to the connection region EA. The dummy separator insulating layers DWLC1 and DWLC2 can be alternately arranged with the separator insulating layer WLC and extend in the same direction as the separator insulating layer WLC. The dummy separator insulating layer DWLC1 can be disposed in the connection region EA, while the dummy separator insulating layer DWLC2 can be disposed in the region extending from the cell array region CA to the connection region EA. The separator insulating layer WLC and the dummy separator insulating layers DWLC1 and DWLC2 can include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0069] Return to reference FIG. 2 , FIG. 3A and FIG. 3B The method may include forming a second upper insulating layer 162, a bit line plug 164, a bit line 166, a TSV 170, and a connecting line 172. The second upper insulating layer 162 may be formed on the first upper insulating layer 160. The bit line plug 164 may be formed to extend through the first upper insulating layer 160 and the second upper insulating layer 162. The bit line 166 may be formed on the second upper insulating layer 162, and the bit line 166 may be connected to the bit line plug 164.

[0070] A TSV 170 can be formed within the TSV area TA. The TSV 170 can extend vertically through the buried insulation layer 46, the lower stack 110, the lower interlayer insulation layer 116, the upper stack 130, the upper interlayer insulation layer 136, the first upper insulation layer 160, and the second upper insulation layer 162, thus allowing the TSV 170 to be electrically connected to the connecting line 172. The connecting line 172 can be formed on the second upper insulation layer 162. The connecting line 172 can be electrically connected to the peripheral circuit line 32 via the TSV 170.

[0071] The first upper insulating layer 160 and the second upper insulating layer 162 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Bit plug 164, bit line 166, TSV 170, and connector 172 may include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or combinations thereof.

[0072] like FIG. 19BAs shown, the hard mask M has a greater height in and around the TSV region TA than it does around the cell array region CA. This creates a possibility of misalignment between the lower dummy channel via DCH1 and the upper dummy channel via DCH2. A word line separator layer WLS can be disposed between the cell array region CA and the TSV region TA to separate the lower word line WL1 of the lower stack 110. Therefore, the word line separator layer WLS can electrically insulate the lower word line WL1 in the cell array region CA from the lower word line WL1 in the connection region EA. This prevents or suppresses reliability degradation caused by word line bridging due to misalignment.

[0073] Although exemplary embodiments of the inventive concept have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: The substrate includes a cell array region and a connection region, the connection region including a through-silicon via region; The peripheral circuit structure is mounted on the substrate. The lower stack and the upper stack are provided. The lower stack is disposed on the peripheral circuit structure, and the upper stack is disposed on the lower stack. The lower stack includes multiple lower insulating layers and multiple lower word lines that are stacked alternately with the multiple lower insulating layers. Multiple channel structures extend through the lower and upper stacks in the cell array region; Multiple dummy channel structures extend through the lower and upper stacks in the connection area; A pair of separating insulating layers extend vertically through the lower stack and the upper stack and extend throughout the cell array area and the connection area in a first direction, the first direction being the direction extending from the cell array area toward the connection area, the pair of separating insulating layers being spaced apart from each other in a second direction perpendicular to the first direction; as well as A word line separator layer is disposed in the connection area at the top of the lower stack and is perpendicular to the pair of separator insulating layers when viewed in a plan view. The word line separator layer extends vertically through at least one of the plurality of lower word lines.

2. The semiconductor device according to claim 1, wherein, The word line separator layer is positioned between the cell array region and the through-silicon via region.

3. The semiconductor device according to claim 1, further comprising: The lower interlayer insulation layer covers the underlying stacked components. The upper surface of the word line separator layer and the upper surface of the lower insulating layer are set at the same level.

4. The semiconductor device according to claim 1, wherein, The word line separator layer is set between the virtual channel structures.

5. The semiconductor device according to claim 1, wherein, When viewed in a longitudinal sectional view, the pair of separating insulating layers extend completely through the word line separating layer.

6. The semiconductor device according to claim 1, wherein, The lateral ends of the word line separator layer are located outside the pair of separator insulating layers.

7. The semiconductor device according to claim 1, further comprising: Through-silicon vias are disposed in the through-silicon via region, extending through the upper and lower stacks and connecting to the peripheral circuit structure.

8. The semiconductor device according to claim 1, wherein, At least one of the plurality of dummy channel structures extends vertically through the word line separator layer.

9. The semiconductor device according to claim 1, further comprising: Multiple dummy insulating layers are disposed between the pair of insulating layers and spaced apart from each other in a second direction.

10. The semiconductor device according to claim 9, wherein, The word line separator layer intersects with the plurality of dummy separator insulation layers.

11. The semiconductor device according to claim 9, wherein, The word line separator layer is disposed between the through-silicon via area and the plurality of dummy separator insulating layers.

12. The semiconductor device according to claim 1, wherein: The lower stacked components have a stepped structure in the connection area; and The letter separator layer extends through part of the stepped structure.

13. The semiconductor device of claim 12, further comprising: The lower interlayer insulation layer covers the underlying stacked components. The upper surface of the word line separator layer is positioned at a lower level than the upper surface of the lower interlayer insulation layer.

14. The semiconductor device according to claim 1, wherein, The cross-section of the word line separator layer in the second direction contacts the side surface of the pair of separator insulating layers.

15. The semiconductor device according to claim 1, wherein, The word line separator layer electrically insulates portions of the multiple lower word lines from the multiple channel structures.

16. The semiconductor device according to claim 1, wherein, The letter separator extends vertically through the uppermost letter among the multiple lower letter lines, and the upper surface of the letter separator contacts the lower surface of the upper stack.

17. A semiconductor device, the semiconductor device comprising: The substrate includes a cell array region and a first connection region and a second connection region disposed on opposite sides of the cell array region, each of the first connection region and the second connection region including a plurality of through-silicon via regions. The peripheral circuit structure is mounted on the substrate. The lower stack and the upper stack are provided. The lower stack is disposed on the peripheral circuit structure, and the upper stack is disposed on the lower stack. The lower stack includes multiple lower insulating layers and multiple lower word lines that are stacked alternately with the multiple lower insulating layers. Multiple channel structures extend through the lower and upper stacks in the cell array region; Multiple dummy channel structures extend through the lower stack and the upper stack in the first and second connection areas; Multiple insulating layers extend vertically through the lower and upper stacks and across the cell array region, the first connection region, and the second connection region in a first direction, which is the direction from the cell array region toward the first or second connection region. The multiple insulating layers are spaced apart from each other in a second direction perpendicular to the first direction. as well as Multiple word line separator layers are disposed on the upper part of the lower stack in the first and second connection areas and perpendicular to two adjacent separator insulating layers among the multiple separator insulating layers. The multiple word line separator layers extend vertically through at least one of the multiple lower word lines. The plurality of character line separator layers include a first character line separator layer arranged in a first column in a first connection area and a second character line separator layer arranged in a second column in a second connection area, wherein the first character line separator layer and the second character line separator layer are arranged in a zigzag pattern in a second direction.

18. The semiconductor device according to claim 17, wherein, The plurality of through-silicon via regions are disposed between the plurality of insulating separators.

19. A semiconductor device, the semiconductor device comprising: The substrate includes a cell array region and a connection region, the connection region including a through-silicon via region; The peripheral circuit structure is mounted on the substrate. The lower conductive layer is disposed on the peripheral circuit structure; A connecting conductive layer is disposed on the lower conductive layer in the unit array region; The connecting molding layer is disposed on the lower conductive layer in the connecting area; Support components are disposed on the connecting conductive layer and the connecting molding layer; An insulating layer is buried in the through-silicon via region and extends through the underlying conductive layer, the connecting molding layer, and the support. A lower stack component is disposed on a support component. The lower stack component includes multiple lower insulating layers and multiple lower letter lines that are stacked alternately with the multiple lower insulating layers. An upper stack is disposed on a lower stack, the upper stack comprising a plurality of upper insulating layers and a plurality of upper letter lines stacked alternately with the plurality of upper insulating layers; Multiple channel structures extend through the lower and upper stacks in the cell array region; Multiple dummy channel structures extend through the lower and upper stacks in the connection area; A pair of separating insulating layers extend vertically through the lower stack and the upper stack and extend throughout the cell array area and the connection area in a first direction, the first direction being the direction extending from the cell array area toward the connection area, the pair of separating insulating layers being spaced apart from each other in a second direction perpendicular to the first direction; A word line separator layer is disposed in the connection area at the top of the lower stack and perpendicular to the pair of separator insulating layers, the word line separator layer extending vertically through at least one of the plurality of lower word lines; as well as Through-silicon vias (TSVs) are disposed within the TSV region, extending through the upper and lower stacked components and connecting to the peripheral circuit structure. Within the through-silicon via region, the lower stack also includes multiple lower sacrificial layers positioned at the same horizontal level as the multiple lower word lines, and The through-silicon vias extend vertically through the plurality of lower sacrificial layers.

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