Semiconductor devices and their manufacturing methods

Abstract

A semiconductor device is disclosed, wherein a cell array region and an extended region are arranged along a first direction, and wherein a contact region and a through region are alternately arranged in the extended region along the first direction, comprising: a molded structure including a plurality of first insulating patterns and a plurality of gate electrodes alternately stacked on a first substrate; a channel structure penetrating the molded structure in the cell array region to intersect with the plurality of gate electrodes; corresponding gate contacts on the molded structure in the contact region and connected to each of the gate electrodes; and a plurality of second insulating patterns alternately stacked with the first insulating patterns in the molded structure in the through region, the plurality of second insulating patterns comprising a material different from the plurality of first insulating patterns.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2020-0002422, entitled "Semiconductor Device and Method of Fabricating the Same", filed on January 8, 2020, with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] The integration density of semiconductor devices has increased to meet customer expectations, such as excellent performance and low price. For semiconductor devices, integration density is a key factor determining product price. Therefore, there is a growing demand for increasing integration density.

[0005] The integration density of two-dimensional (2D) or planar semiconductor devices is greatly affected by the level of fine patterning technology. However, due to the fact that expensive equipment is usually required to form fine patterns, there are limitations in increasing the integration density of 2D semiconductor devices, and therefore progress has been made in the development of three-dimensional (3D) semiconductor devices. Summary of the Invention

[0006] The embodiment relates to a semiconductor device in which a cell array region and an extended region are arranged along a first direction, and a contact region and a through region are alternately arranged in the extended region along the first direction. The semiconductor device includes: a molded structure comprising a plurality of first insulating patterns and a plurality of gate electrodes alternately stacked on a first substrate; a channel structure penetrating the molded structure in the cell array region to intersect with the plurality of gate electrodes; corresponding gate contacts on the molded structure in the contact region and connected to each of the plurality of gate electrodes; and a plurality of second insulating patterns alternately stacked with the plurality of first insulating patterns in the molded structure in the through region, the plurality of second insulating patterns comprising a material different from the plurality of first insulating patterns.

[0007] The embodiments also relate to a semiconductor device in which a cell array region and an extended region are arranged along a first direction, and in which a contact region and a through region are alternately arranged along the first direction in the extended region, the semiconductor device comprising: a molded structure including a plurality of gate electrodes stacked on a substrate and spaced apart from each other; a channel structure penetrating the molded structure in the cell array region to intersect the plurality of gate electrodes; an extended gate cleaving region extending in the first direction to cleave the plurality of gate electrodes in the molded structure in the contact region; and a plurality of insulating patterns stacked at the same level as the plurality of gate electrodes in the molded structure in the through region, each of the insulating patterns including a first side extending along the first direction and a second side forming an arc centered at an end of the extended gate cleaving region.

[0008] The embodiments also relate to a semiconductor device in which a cell array region and an extended region are arranged along a first direction, and in which a contact region and a through region are alternately arranged along the first direction in the extended region, the semiconductor device comprising: a molded structure including: a ground select line on a substrate; and a plurality of word lines stacked on the ground select line; a channel structure intersecting the ground select line and the plurality of word lines through the molded structure in the cell array region; an extended gate dicing region extending in the first direction to dice the ground select line and the plurality of word lines in the molded structure in the contact region; and a plurality of insulating patterns stacked at the same level as the plurality of word lines in the molded structure in the through region, the ground select line partially overlapping the plurality of insulating patterns in a direction perpendicular to the top surface of the substrate.

[0009] The embodiments relate to a method of manufacturing a semiconductor device, the method comprising: setting a substrate including a cell array region and an extended region arranged along a first direction, the extended region including contact regions and through regions alternately arranged along the first direction; forming a molding structure including a first insulating pattern and a second insulating pattern, the first insulating pattern and the second insulating pattern being alternately stacked on the substrate; forming a channel structure through the molding structure in the cell array region of the substrate to intersect with the first insulating pattern and the second insulating pattern; forming an extended gate dicing region extending in the first direction to cut the molding structure in the molding structure of the contact region; and selectively removing the second insulating pattern in the contact region using the extended gate dicing region, thereby retaining the second insulating pattern in the through region. Attached Figure Description

[0010] The features will become clear to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of a semiconductor device according to an example embodiment.

[0012] Figure 2 This is a circuit diagram of a semiconductor device according to an example embodiment.

[0013] Figure 3 This is a layout diagram of a semiconductor device according to an example embodiment.

[0014] Figure 4 It is shown Figure 3 The layout diagram of region R1.

[0015] Figure 5 It is along Figure 4 The cross-sectional view taken from line AA.

[0016] Figure 6 and Figure 7 It is shown Figure 5 Enlarged cross-sectional view of region R2.

[0017] Figure 8 This is a layout diagram of a semiconductor device according to an example embodiment.

[0018] Figure 9 It is shown Figure 8 A perspective view of the extended area.

[0019] Figure 10 It is shown Figure 9 A magnified perspective view of region R3.

[0020] Figure 11 This is a layout diagram of a semiconductor device according to an example embodiment.

[0021] Figure 12 and Figure 13 It is along Figure 11 The cross-sectional view of line BB.

[0022] Figure 14 This is a layout diagram of a semiconductor device according to an example embodiment.

[0023] Figure 15 This is a layout diagram of a semiconductor device according to an example embodiment.

[0024] Figure 16 This is a layout diagram of a semiconductor device according to an example embodiment.

[0025] Figure 17 This is a layout diagram of a semiconductor device according to an example embodiment.

[0026] Figures 18A to 18C It is shown Figure 17 The layout diagram of region R4.

[0027] Figure 19 This is a layout diagram of a semiconductor device according to an example embodiment.

[0028] Figure 20 This is a layout diagram of a semiconductor device according to an example embodiment.

[0029] Figures 21 to 29 This illustrates the stages in a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0030] Figure 1 This is a block diagram of a semiconductor device according to an example embodiment.

[0031] refer to Figure 1 The semiconductor device 10 may include a memory cell array 20 and peripheral circuitry 30.

[0032] The memory cell array 20 may include multiple memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include multiple memory cells. The memory cell blocks BLK1 to BLKn may be connected to the peripheral circuitry 30 via bit line BL, word line WL, at least one serial select line SSL, and at least one ground select line GSL.

[0033] Storage cell blocks BLK1 to BLKn can be connected to the row decoder 33 via word line WL, serial select line SSL, and ground select line GSL. Storage cell blocks BLK1 to BLKn can also be connected to the page buffer 35 via bit line BL.

[0034] Peripheral circuitry 30 can receive address ADDR, command CMD, and control signal CTRL from outside semiconductor device 10, and can exchange data DATA with external devices outside semiconductor device 10. Peripheral circuitry 30 may include control logic circuitry 37, row decoder 33, and page buffer 35. Peripheral circuitry 30 may further include various sub-circuits, such as input / output circuitry, voltage generation circuitry for generating various voltages required for the operation of semiconductor device 10, and error correction circuitry for correcting errors in data DATA read from memory cell array 20.

[0035] Control logic circuitry 37 can be connected to line decoder 33, input / output circuitry, and voltage generation circuitry. Control logic circuitry 37 can control the overall operation of semiconductor device 10. Control logic circuitry 37 can generate various internal control signals in response to control signal CTRL for use in semiconductor device 10. For example, control logic circuitry 37 can adjust the voltage levels to be supplied to word line WL and bit line BL during memory operations such as programming or erasing operations.

[0036] The row decoder 33 can select at least one of the memory cell blocks BLK1 to BLKn in response to the address ADDR, and can select at least one of the word line WL, the serial select signal SSL, and the ground select line GSL of the selected memory cell block. The row decoder 33 can transmit the voltage used to perform the memory operation to the selected word line WL of the selected memory cell block.

[0037] Page buffer circuit 35 can be connected to memory cell array 20 via bit line BL. Page buffer 35 can operate as a write driver and / or a sense amplifier. During program operation, page buffer 35 can operate as a write driver and can apply a voltage corresponding to the data "DATA" to be stored in memory cell array 20 to bit line BL. During read operation, page buffer 35 can operate as a sense amplifier and can sense the data "DATA" stored in memory cell array 20.

[0038] Figure 2 This is a circuit diagram of a semiconductor device according to an example embodiment.

[0039] Reference Figure 2 Array of memory cells in semiconductor devices (e.g., Figure 1 The storage cell array 20) may include a common source line CSL, a bit line BL, and a cell string CSTR.

[0040] Bit lines BL can be arranged in two dimensions. For example, bit lines BL can extend in a first direction X and can be spaced apart from each other in a second direction Y. Multiple cell strings CSTR can be connected in parallel with each bit line BL. Cell strings CSTR can be connected together to a common source line CSL. For example, multiple cell strings CSTR can be located between bit lines BL and the common source line CSL.

[0041] The common source line (CSL) can be arranged in two dimensions. For example, the common source lines (CSL) can be spaced apart from each other in a first direction X and can extend in a second direction Y. Electrically identical voltages can be applied to the common source lines (CSL). In another embodiment, different voltages can be applied to the common source lines (CSL) to control them individually.

[0042] In an example embodiment, each cell string CSTR may include a ground select transistor GST connected to a common source line CSL, a plurality of string select transistors SST connected to one of the bit lines BL, and a plurality of memory cell transistors MCTs located between the ground select transistor GST and the string select transistors SST. Each memory cell transistor MCT may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistor MCT may be connected in series.

[0043] The common source line CSL can be connected to the source of the ground select transistor GST. The ground select lines GSL1 and GSL2, the multiple word lines WL1 to WLn, and the serial select lines SSL1 to SSL3 can be located between the common source line CSL and the bit line BL.

[0044] Ground select lines GSL1 and GSL2 can be used as the gate electrodes of ground select transistor GST, word lines WL1 to WLn can be used as the gate electrodes of memory cell transistor MCT, and string select lines SSL1 to SSL3 can be used as the gate electrodes of string select transistor SST.

[0045] In an example embodiment, one ground select line (e.g., ground select line GSL1) may correspond to two string select lines (e.g., string select lines SSL1 and SSL2). For example, the unit string CSTR connected to string select lines SSL1 or SSL2 may be connected together to ground select line GSL1.

[0046] Figure 3 This is a layout diagram of a semiconductor device according to an example embodiment. Figure 4 It is shown Figure 3 The layout diagram of region R1. Figure 5 It is along Figure 4 The cross-sectional view taken from line AA. Figure 6 and Figure 7 It is shown Figure 5 Enlarged cross-sectional view of region R2.

[0047] Reference Figure 3 The semiconductor device may include a cell array region CELL and an extended region EXT, which may be arranged adjacent to each other in the second direction Y.

[0048] The cell array region (CELL) and the extended region (EXT) can be divided and segmented by multiple block isolation regions (WLCs) to form multiple storage cell blocks (BLK1 to BLKn). For example, the block isolation regions (WLCs) can extend in the second direction Y to divide the cell array region (CELL) and the extended region (EXT).

[0049] A memory cell array comprising multiple memory cells can be formed within a cell array region (CELL). For example, a channel structure (CH) and a bit line (BL) can be formed within the cell array region (CELL).

[0050] The extended region EXT can be located near the cell array region CELL. In an example embodiment, the cell array region CELL and the extended region EXT can be arranged along the direction extending from the block isolation region WLC. For example, the cell array region CELL and the extended region EXT can be arranged along a second direction Y. Figure 5As shown, multiple gate electrodes (GSL, WL1 to WLn and SSL) can be stacked in a stepped manner in the extended region EXT.

[0051] The extended region EXT may include a contact region CNR and a through region THR. The contact region CNR and the through region THR may be arranged alternately along the direction of the block isolation region WLC, for example, the contact region CNR and the through region THR may be arranged alternately along a second direction Y.

[0052] Gate contacts 152, connected to the gate electrodes (GSL, WL1 to WLn and SSL), can be formed in the contact region CNR of the extended region EXT. Through-type structures THV can be formed in the through-type region THR of the extended region EXT. (Refer to the following...) Figure 4 and Figure 5 Further description of the contact area (CNR) and the through area (THR).

[0053] Reference Figures 3 to 7 The semiconductor device may include a first substrate 100, a molded structure MS, a channel structure CH, a bit line BL, a block isolation region WLC, a cell gate dicing region CAC, an extended gate dicing region CNC, a through structure THV, a gate contact 152, and a first via 154.

[0054] The first substrate 100 may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In an embodiment, the first substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0055] In an example embodiment, the first substrate 100 may include an impurity region 105. The impurity region 105 may extend in a second direction Y and may be configured as a common source line (e.g., Figure 2 (Common source line CSL).

[0056] A molded structure MS can be formed on the first substrate 100 in the cell array region CELL and the extended region EXT. The molded structure MS can be formed in a stepped manner on the first substrate 100 in the extended region EXT.

[0057] The molded structure MS may include gate electrodes (GSL, WL1 to WLn and SSL) that are alternately stacked on the first substrate 100 with a plurality of first insulating patterns 110. For example, the gate electrodes (GSL, WL1 to WLn and SSL) and the first insulating patterns 110 may be formed in a layered structure extending in a first direction X and a second direction Y. The gate electrodes (GSL, WL1 to WLn and SSL) and the first insulating patterns 110 may be alternately stacked in a third direction Z perpendicular to the top surface of the first substrate 100. Thus, the gate electrodes (GSL, WL1 to WLn and SSL) may be stacked on the first substrate 100 while being spaced apart from each other.

[0058] In an example embodiment, the gate electrode (GSL, WL1 to WLn and SSL) may include at least one ground select line GSL, a plurality of word lines WL1 to WLn, and at least one string select line SSL. In an example embodiment, the ground select line GSL may be the lowermost of the gate electrodes (GSL, WL1 to WLn and SSL). In an example embodiment, the string select line SSL may be the uppermost of the gate electrodes (GSL, WL1 to WLn and SSL).

[0059] A modular structure MS is shown to include a ground select line GSL and a string select line SSL, but a modular structure MS may include multiple ground select lines GSL and / or multiple string select lines SSL.

[0060] The gate electrodes (GSL, WL1 to WLn and SSL) may comprise metals such as tungsten (W), cobalt (Co), or nickel (Ni) or semiconductor materials such as silicon (Si). The gate electrodes (GSL, WL1 to WLn and SSL) may be formed, for example, by a substitution process.

[0061] The first insulating pattern 110 may include an insulating material. For example, the first insulating pattern 110 may include an oxide (e.g., silicon oxide).

[0062] The channel structure CH can penetrate the molded structure MS. The channel structure CH can extend in the direction intersecting the gate electrodes (GSL, WL1 to WLn and SSL). For example, the channel structure CH can be a pillar shape extending in the third direction Z. Figure 6 As shown, each channel structure CH may include a semiconductor pattern 130 and an information storage film 132.

[0063] Semiconductor pattern 130 may extend in the third direction Z to penetrate the molded structure MS. Semiconductor pattern 130 is shown as a cup shape, but semiconductor pattern 130 may have various shapes, such as cylindrical, square, or non-hollow columnar shapes. Semiconductor pattern 130 may include semiconductor materials such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, or carbon nanostructures.

[0064] Information storage film 132 may be situated between semiconductor pattern 130 and gate electrodes (GSL, WL1 to WLn and SSL). For example, information storage film 132 may extend along the side of semiconductor pattern 130. Information storage film 132 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and high-k materials with a dielectric constant higher than silicon oxide. High-k materials may include at least one of, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0065] In an example embodiment, the information storage film 132 may be formed as a multilayer film. For example, the information storage film 132 may include a tunnel insulating film 132a, a charge storage film 132b, and a barrier insulating film 132c sequentially stacked on a semiconductor pattern 130. The tunnel insulating film 132a may include, for example, silicon oxide or a high-k material with a dielectric constant greater than silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). The charge storage film 132b may include, for example, silicon nitride. The barrier insulating film 132c may include, for example, silicon oxide or a high-k material with a dielectric constant greater than silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)).

[0066] In an example embodiment, each channel structure CH may further include a fill pattern 134. The fill pattern 134 may be formed to fill the interior of a cup-shaped semiconductor pattern 130. For example, the semiconductor pattern 130 may extend along the side and bottom surfaces of the fill pattern 134. The fill pattern 134 may include an insulating material, such as silicon oxide.

[0067] In the example embodiment, each channel structure CH may further include a channel pad 136, such as Figure 5 As shown. The channel pad 136 can be formed to connect to the top of the semiconductor pattern 130. For example, the channel pad 136 can be formed in the first insulating pattern 110 on the topmost one of the gate electrodes (GSL, WL1 to WLn and SSL) (e.g., the string select line SSL) to connect to the semiconductor pattern 130. The channel pad 136 can include, for example, polysilicon doped with impurities.

[0068] In the example embodiment, the channel structure CH can be arranged in a zigzag pattern. For example, as... Figure 4As shown in the plan view, the channel structures CH can be arranged in an alternating manner in the first direction X and the second direction Y. By arranging the channel structures CH in a sawtooth pattern, the integration density of the semiconductor device can be increased.

[0069] Bit lines BL can be formed on a molded structure MS. For example, bit lines BL can be formed on a first interlayer insulating film 142, a second interlayer insulating film 144, and a third interlayer insulating film 146 that are sequentially stacked on the molded structure MS.

[0070] The bit line BL can extend in the first direction X to connect to the channel structure CH. For example, as Figure 5 As shown, bit line BL can be connected to channel structure CH via bit line contact 170. Bit line contact 170 can be electrically connected to bit line BL and channel structure CH, for example, through first interlayer insulating film 142, second interlayer insulating film 144 and third interlayer insulating film 146.

[0071] Block isolation regions (WLCs) can be formed within the cell array region (CELL) and the extended region (EXT) to cut the gate electrodes (GSL, WL1 to WLn and SSL). The block isolation regions (WLCs) can extend in a direction intersecting the bit line (BL). For example, multiple block isolation regions (WLCs) can be arranged along a first direction (X) within the cell array region (CELL) and the extended region (EXT). The block isolation regions (WLCs) can extend in a second direction (Y) to cut the molded structure (MS).

[0072] As referenced above Figure 3 The block isolation region (WLC) can cut and divide the cell array region (CELL) and the extension region (EXT) to form memory cell blocks (BLK1 to BLKn). For example, the block isolation region (WLC) can extend in the second direction Y to completely cut the molded structure MS. The molded structure MS can be formed by cutting and dividing each pair of adjacent block isolation regions (WLC) to form each of the memory cell blocks (BLK1 to BLKn).

[0073] Cell gate dicing regions (CACs) can be formed in the cell array region (CELL) to dice the gate electrodes (GSL, WL1 to WLn and SSL). The cell gate dicing regions (CACs) can extend in a direction intersecting the bit line (BL). For example, multiple cell gate dicing regions (CACs) can be arranged in the cell array region (CELL) along a first direction (X) and can extend in a second direction (Y) to dice the molded structure (MS) in the cell array region (CELL).

[0074] The cell gate dicing region (CAC) can dic and divide the cell array region (CELL), and thus multiple first portions (I), second portions (II), and third portions (III) can be formed in each of the memory cell blocks (BLK1 to BLKn). For example, as... Figure 4As shown, two cell gate cut regions (CACs) can be formed between each pair of adjacent block isolation regions (WLCs). Therefore, three sections (e.g., section I, section II, and section III) can be formed between each pair of adjacent block isolation regions (WLCs).

[0075] An extended gate dicing region (CNC) can be formed in the extended region EXT to dice the gate electrodes (GSL, WL1 to WLn and SSL). The extended gate dicing region CNC can extend in a direction intersecting the bit line BL. For example, multiple extended gate dicing regions CNC can be arranged in the extended region EXT along a first direction X. The extended gate dicing region CNC can extend in a second direction Y to dice the molded structure MS in the extended region EXT.

[0076] In an example embodiment, at least some of the extended gate cut regions (CNC) can be arranged to overlap with their respective cell gate cut regions (CAC) in the second direction Y. For example, as Figure 4 As shown, five extended gate cut regions (CNCs) can be formed between each pair of adjacent block isolation regions (WLCs), and two of the five extended gate cut regions (CNCs) can overlap with their respective cell gate cut regions (CACs) in the second direction Y.

[0077] In an example embodiment, the extended gate cleavage region (CNC) may be formed in the contact region (CNR) of the extended region (EXT), but not in the through region (THR) of the extended region (EXT). For example, the extended gate cleavage region (CNC) may extend in the second direction Y, but without encroaching on the through region (THR).

[0078] The block isolation region WLC, the cell gate dicing region CAC, and the extended gate dicing region CNC may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-k material with a dielectric constant greater than that of silicon oxide.

[0079] In the example embodiment, the block isolation region WLC, the cell gate dicing region CAC, and the extended gate dicing region CNC may be formed at the same level. As used herein, the phrase "formed at the same level" indicates that the corresponding elements are formed using the same manufacturing process. For example, the block isolation region WLC, the cell gate dicing region CAC, and the extended gate dicing region CNC may include the same insulating material.

[0080] In an example embodiment, the block isolation region WLC may include conductive material. For example, the block isolation region WLC may include conductive patterns and isolators that isolate the molded structure MS from the conductive patterns. The conductive patterns of the block isolation region WLC may be connected to the impurity region 105 and can therefore be provided as a common source line for a semiconductor device (e.g., Figure 2(Common source line CSL).

[0081] In an example embodiment, a cut structure SC can be formed within a molded structure MS in a cell array region CELL to cut string select lines SSL. The cut structure SC can be situated between block isolation regions WLC to cut the string select lines SSL of the molded structure MS. For example, multiple cut structures SC can be arranged along a first direction X in the cell array region CELL. The cut structure SC can extend in a second direction Y to cut the string select lines SSL.

[0082] In an example embodiment, the dicing structure SC can be situated between the block isolation region WLC and the cell gate dicing region CAC. For instance, the dicing structure SC can be situated between the block isolation region WLC and the cell gate dicing region, the block isolation region WLC defining a first region I, a second region II, and a third region III in each of the memory cell blocks BLK1 to BLKn. Therefore, the first region I, the second region II, and the third region III in each of the memory cell blocks BLK1 to BLKn can be electrically isolated from each other, resulting in the provision of two string select lines SSL, which can be controlled independently.

[0083] Although not specifically shown, the additional cut structures SC can be arranged to overlap with their respective cell gate cut regions CAC in the second direction Y. For example, two additional cut structures SC can be formed in the cell array region CELL between the first region I and the second region II in each of the memory cell blocks BLK1 to BLKn, and between the second region II and the third region III in each of the memory cell blocks BLK1 to BLKn. Thus, five cut structures SC can be formed between each pair of adjacent block isolation regions WLC.

[0084] The serial select lines (SSLs) in the first region I and the second region II of each of the storage cell blocks BLK1 to BLKn are electrically isolated from each other and can therefore be controlled separately. Similarly, the serial select lines (SSLs) in the second region II and the third region III of each of the storage cell blocks BLK1 to BLKn are electrically isolated from each other and can therefore be controlled separately. Thus, for example, six serial select lines (SSLs) can be formed between each pair of adjacent block isolation regions (WLCs).

[0085] In an example embodiment, the number of extended gate cut regions (CNCs) formed between each pair of block isolation regions (WLCs) can be the same as or less than the number of cut structures (SCs) formed between each pair of adjacent block isolation regions (WLCs). For example, five cut structures (SCs) and five (or fewer) extended gate cut regions (CNCs) can be formed between each pair of adjacent block isolation regions (WLCs).

[0086] The through-structure THV can be formed in the through-region THR of the extended region EXT. Each through-structure THV may include a plurality of second insulating patterns 115 spaced apart from each other and stacked on the first substrate 100. For example, the second insulating patterns 115 may be formed in a layered structure extending in the first direction X and the second direction Y.

[0087] The second insulating pattern 115 may be stacked at the same level as at least some of the gate electrodes (GSL, WL1 to WLn and SSL). The expression "stacked at the same level" as used herein can indicate that the corresponding elements are formed at substantially the same height relative to the top surface of the first substrate 100. For example, as... Figure 5 As shown, the second insulating pattern 115 can be stacked at the same level as the gate electrode We exposed in the through region THR, and can be stacked at the same level as the gate electrodes (GSL, WL1 and Wd to Wd) disposed below the gate electrode We.

[0088] The first insulating pattern 110 and the second insulating pattern 115 may be alternately stacked in the through region THR. The second insulating pattern 115 may cut through the gate electrodes (GSL, WL1 to WLn and SSL) in the through region THR.

[0089] Reference Figure 4 In an example embodiment, each second insulating pattern 115 may include a first side S1 and a second side S2, where the first side S1 is straight in a plan view and the second side S2 is curved in a plan view. For example, as Figure 4 As shown, the second insulating pattern 115 may include a first side S1 extending straight in the second direction Y. The second insulating pattern 115 may also include a second side S2, which is curved, for example, having a recessed area.

[0090] In an example embodiment, the second side S2 of the second insulating pattern 115 may form an arc centered on the end of the extended gate dicing region CNC. For example, each second side S2 of the second insulating pattern 115 may correspond to a plurality of extended gate dicing regions CNC and may form a plurality of arcs arranged along the first direction X.

[0091] The second insulating pattern 115 may include an insulating material different from the first insulating pattern 110. For example, if the first insulating pattern 110 includes an oxide (e.g., silicon oxide), the second insulating pattern 115 may include a nitride (e.g., silicon nitride).

[0092] In an example embodiment, the length of the gate electrodes (GSL, WL1 to WLn and SSL) protruding in the through region THR can be greater than the length of the gate electrodes (GSL, WL1 to WLn and SSL) protruding in the contact region CNR. For example, as Figure 5 As shown, the length of the gate electrode We exposed in the through region THR that protrudes beyond the gate electrode Wf ​​directly above the gate electrode We can be greater than the length of the gate electrode Wg exposed in the contact region CNR that protrudes beyond the gate electrode Wh directly above the gate electrode Wg.

[0093] Reference Figure 4 In the example embodiment, the lower cut region GC can cut the selected line GSL. For example... Figure 4 As shown, the lower cut region GC can be connected to the cell gate cut region CAC, the extended gate cut region CNC, or the through structure THV to cut the ground select line GSL. For example, three ground select lines GSL cut by the cell gate cut region CAC, the extended gate cut region CNC, the through structure THV, and the lower cut region GC can be formed between a pair of adjacent block isolation regions WLC. Therefore, the first region I, the second region II, and the third region III in each of the memory cell blocks BLK1 to BLKn can be electrically isolated from each other, resulting in three individually controllable ground select lines GSL.

[0094] Gate contact 152 may be formed in extended region EXT. Gate contact 152 may be connected to gate electrode (GSL, WL1 to WLn and SSL). For example, gate contact 152 may be connected to gate electrode (GSL, WL1 to WLn and SSL) through first interlayer insulating film 142, second interlayer insulating film 144 and third interlayer insulating film 146.

[0095] In an example embodiment, the gate contact 152 may be formed in the contact region CNR of the extended region EXT. For example, as... Figure 5 As shown, the gate electrodes Wa to Wh exposed in the contact region CNR can be arranged in a stepped manner. The gate contacts 152 can be arranged in a stepped manner to connect to the ends of the gate electrodes Wa to Wh.

[0096] A first through-hole 154 may be formed in the through-region THR of the extended region EXT. The first through-hole 154 may penetrate the through-structure THV. For example, the first through-hole 154 may extend in the through-region THR along a third direction Z to penetrate the first insulating pattern 110 and the second insulating pattern 115.

[0097] In an example embodiment, the first via 154 can be connected to the gate contact 152. For example, a connection line 156 can be formed on the third interlayer insulating film 146. The gate contact 152 and the first via 154 can be connected to the connection line 156 through the first interlayer insulating film 142, the second interlayer insulating film 144, and the third interlayer insulating film 146. Therefore, the connection line 156 can connect the gate contact 152 to the first via 154.

[0098] In an example embodiment, the second substrate 200 and peripheral circuit elements PT may be formed beneath the first substrate 100.

[0099] The second substrate 200 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In an embodiment, the second substrate 200 may include an SOI substrate or a GOI substrate.

[0100] Peripheral circuit elements PT can be formed on the second substrate 200. Peripheral circuit elements PT can be configured with peripheral circuitry that controls the operation of the memory cells (e.g., Figure 1 Peripheral circuitry 30). For example, peripheral circuitry element PT may include a line decoder (e.g., Figure 1 The line decoder 33), page buffer (e.g., Figure 1 Page buffer 35) and control logic circuitry (e.g., Figure 1 (Control logic circuit 37).

[0101] Peripheral circuit elements PT may include, for example, transistors. Peripheral circuit elements PT may include various active elements (e.g., transistors) and / or various passive elements (e.g., capacitors, resistors, or inductors).

[0102] In an example embodiment, the first via 154 can be connected to a peripheral circuit element PT. For example, a fourth interlayer insulating film 240 covering the peripheral circuit element PT can be formed on the second substrate 200, and a peripheral circuit line PW can be formed in the fourth interlayer insulating film 240. The first via 154 can be connected to the peripheral circuit element PT via the peripheral circuit line PW.

[0103] Reference Figure 5 and Figure 7 The semiconductor device may also include a source structure 300.

[0104] The source structure 300 may be formed on the first substrate 100. In an example embodiment, the source structure 300 may be located between the first substrate 100 and the molded structure MS. The source structure 300 may include, for example, polysilicon doped with impurities, or a metal.

[0105] In an example embodiment, the channel structure CH can be connected to the first substrate 100 via the source structure 300. For example, as... Figure 7 As shown, the lower part of the channel structure CH can be buried in the first substrate 100 through the source structure 300.

[0106] In an example embodiment, the source structure 300 may be formed as a semiconductor pattern 130 connected to the channel structure CH. For example, the source structure 300 may be connected to the semiconductor pattern 130 via an information storage film 132.

[0107] In the example embodiment, the portion of the source structure 300 near the semiconductor pattern 130 may protrude toward the information storage film 132. For example, the length of the source structure 300 extending in the third direction Z near the semiconductor pattern 130 may be longer than the length extending anywhere else, and this structure may be formed by the characteristics of etching used to remove a portion of the information storage film 132 to form the source structure 300.

[0108] Figure 8 This is a layout diagram of a semiconductor device according to an example embodiment. Figure 9 It is shown Figure 8 A perspective view of the extended area. Figure 10 It is shown Figure 9 A magnified perspective view of region R3. Specifically, Figure 8 It is a semiconductor device according to an example embodiment. Figure 3 The layout diagram of region R1 is shown above. For convenience, the above-mentioned layout diagram can be omitted or simplified. Figures 1 to 7 A description of the components or features described. Additionally, for convenience, in Figure 9 and Figure 10 The extended gate dicing region (CNC) is not shown in the diagram.

[0109] Reference Figures 8 to 10 Multiple gate electrodes (GSL, WL1 to WLn and SSL) of the extended region EXT can be stacked in a stepped manner in the first direction X and the second direction Y.

[0110] like Figure 9 As shown, in the contact region CNR of the extended region EXT, the gate electrodes (GSL, WL1 to WLn and SSL) can be stacked in a stepped manner in the first direction X and the second direction Y. For example, as Figure 10As shown, gate electrodes from different layers in the second direction Y (e.g., Wb1 and Wc1, Wb2 and Wc2, Wb3 and Wc3, Wb4 and Wc4, Wb5 and Wc5, or Wb6 and Wc6) may have a height difference in the second direction Y. Furthermore, gate electrodes from different layers in the first direction X (e.g., Wb1 to Wb6 or Wc1 to Wc6) may have a height difference in the first direction X.

[0111] In an example embodiment, within the through region THR of the extended region EXT, the gate electrodes (GSL, WL1 to WLn, and SSL) can be stacked in a stepped manner only in the first direction X. For example, as Figure 9 As shown, the top surface of the through structure THV formed in the through region THR can have a height difference only in the first direction X.

[0112] In an example embodiment, the number of steps formed between each pair of adjacent block isolation regions (WLCs) in the first direction X can be equal to or less than the number of string selection lines (SSLs) formed between each pair of adjacent block isolation regions (WLCs). For example, as Figure 8 As shown, six steps and six string selection lines (SSLs) can be formed between each pair of adjacent block isolation regions (WLCs) along the first direction X.

[0113] Figure 11 This is a layout diagram of a semiconductor device according to an example embodiment. Figure 12 and Figure 13 It is along Figure 11 The cross-sectional view taken from line BB. Specifically, Figure 11 It is a semiconductor device according to an example embodiment. Figure 3 The layout diagram of region R1 is shown above. For convenience, the above-mentioned layout diagram can be omitted or simplified. Figures 1 to 7 A description of the components or features being described.

[0114] Reference Figures 11 to 13 At least one of the multiple gate electrodes (GSL, WL1 to WLn and SSL) may overlap with the through structure THV in the third direction Z.

[0115] For example, such as Figure 11 As shown, at least one of the gate electrodes (GSL, WL1 to WLn and SSL) may include a protruding portion GP that overlaps with the through structure THV on the third-direction Z.

[0116] In an example embodiment, the lowest one of the gate electrodes (GSL, WL1 to WLn and SSL) (e.g., the ground select line GSL) may include a protruding portion GP. For example, as Figure 12As shown, the ground select line GSL may include a protruding portion GP that protrudes beyond the other gate electrodes (i.e., WL1 to WLn and SSL) toward the via structure THV. Therefore, the protruding portion GP of the ground select line GSL may overlap with a plurality of second insulating patterns 115 in the third direction Z.

[0117] In an example embodiment, the second insulating pattern 115 corresponding to the gate electrode having the protruding portion GP may include an etch rate and a different material than the second insulating patterns 115 corresponding to other gate electrodes, thus exhibiting etch selectivity. For example, the ground select line GSL may include the protruding portion GP. In this example, the second insulating pattern 115 corresponding to the ground select line GSL may have a different nitrogen ratio than the second insulating patterns 115 corresponding to other gate electrodes (i.e., WL1 to WLn and SSL).

[0118] In an example embodiment, the amount of etching of the second insulating pattern 115 corresponding to the ground select line GSL can be increased compared to the amount of etching of the second insulating pattern 115 corresponding to the other gate electrodes (i.e., WL1 to WLn and SSL). Therefore, the ground select line GSL may include a protrusion GP that protrudes beyond the other gate electrodes (i.e., WL1 to WLn and SSL) toward the via structure THV.

[0119] In an example embodiment, the lower cut region GC can be formed as a cut selection line GSL. For example... Figure 11 and Figure 12 As shown, the lower cut region GC can be connected to the cell gate cut region CAC, the extended gate cut region CNC, or the through structure THV to cut the ground selection line GSL.

[0120] In an example embodiment, the protruding portion GP may protrude toward the through-structure THV that does not form the lower cut region GC. For example, refer to Figure 11 Some of the lower cut regions GC can surround the left, right, and bottom surfaces of the through structure THV. In this case, the protruding portion GP can protrude only from the top surface of the through structure THV toward the through structure THV.

[0121] During the process of forming the gate electrodes (GSL, WL1 to WLn and SSL) (e.g., during a replacement process), the lower cut region GC can prevent the second insulating pattern 115 corresponding to the ground select line GSL from being etched. As a result, the lower cut region can be used to adjust the area where the protrusion GP will be formed.

[0122] In an example embodiment, a second through-hole 158 connected to the protruding portion GP can be formed in the through-region THR of the extended region EXT. The second through-hole 158 can be connected to the protruding portion GP via a through-structure THV. For example, the second through-hole 158 can extend in the through-region THR in the third direction Z to penetrate a plurality of first insulating patterns 110 and a plurality of second insulating patterns 115.

[0123] In an example embodiment, the second via 158 can be electrically connected to the first via 154. For example, a connecting line 156 can be formed on the third interlayer insulating film 146. The first via 154 and the second via 158 can be connected to the connecting line 156 through the first interlayer insulating film 142 and the second interlayer insulating film 144, and through the third interlayer insulating film 146. Therefore, the connecting line 156 can connect the first via 154 to the second via 158. In an example embodiment, the ground selection line GSL can be connected to the peripheral circuit element PT via the first via 154.

[0124] Reference Figure 11 and Figure 13 The thickness of the gate electrode including the protruding portion GP can be greater than the thickness of other gate electrodes that do not include the protruding portion GP. For example, the ground select line GSL may include the protruding portion GP. The thickness D11 of the ground select line GSL can be greater than the thickness D12 of other gate electrodes (e.g., WL1) stacked on the ground select line GSL. In this example, the amount of etching of the second insulating pattern 115 corresponding to the ground select line GSL during the process of forming the gate electrodes (GSL, WL1 to WLn and SSL) (e.g., during a replacement process) can be increased. Therefore, the ground select line GSL may include the protruding portion GP that protrudes toward the via structure THV beyond the other gate electrodes (i.e., WL1 to WLn and SSL).

[0125] Figure 14 This is a layout diagram of a semiconductor device according to an example embodiment. Specifically, Figure 14 It is a semiconductor device according to an example embodiment. Figure 3 The layout diagram of region R1 is shown above. For convenience, the above-mentioned layout diagram can be omitted or simplified. Figures 1 to 13 A description of the components or features being described.

[0126] Reference Figure 14The semiconductor device also includes an additional cleaving region AC that cleaves the ground select line GSL. The additional cleaving region AC can extend from the extended gate cleaving region CNC that cleaves the ground select line GSL. For example, the additional cleaving region AC can extend in the second direction Y in the ground select line GSL to connect to the extended gate cleaving region GNC that cleaves the ground select line GSL. Therefore, the additional cleaving region AC can cleave the ground select line GSL together with the extended gate cleaving region CNC. The additional cleaving region AC can be adjacent to the protrusion GP.

[0127] The amount of etching of a second insulating pattern 115 corresponding to an additional cut region AC corresponding to the ground select line GSL can be increased during the process of forming multiple gate electrodes (GSL, WL1 to WLn and SSL) (e.g., during a replacement process). Thus, the ground select line GSL may include a protruding portion GP that protrudes beyond the other gate electrodes (i.e., WL1 to WLn and SSL) toward the through structure THV.

[0128] Figure 15 This is a layout diagram of a semiconductor device according to an example embodiment. For convenience, the diagrams already referred to above may be omitted or simplified. Figures 1 to 7 A description of the components or features being described.

[0129] Reference Figure 15 The semiconductor device includes a first extended region EXT1 and a second extended region EXT2.

[0130] The first extended region EXT1 and the second extended region EXT2 can be located on both sides of the cell array region CELL. For example, the first extended region EXT1, the cell array region CELL, and the second extended region EXT2 can be arranged sequentially along the second direction Y.

[0131] The first extended region EXT1 and the second extended region EXT2 can be connected with Figures 1 to 7 The extended regions EXT are essentially the same, therefore their detailed description will not be repeated. Each of the first extended region EXT1 and the second extended region EXT2 may include a contact region CNR and a through region THR.

[0132] In the example embodiment, the first extended region EXT1 and the second extended region EXT2 can be arranged symmetrically with respect to the cell array region CELL.

[0133] Figure 16 This is a layout diagram of a semiconductor device according to an example embodiment. For convenience, the diagrams already referred to above may be omitted or simplified. Figures 1 to 15 A description of the components or features being described.

[0134] Reference Figure 16The through-structure THV in the first extended region EXT1 and the through-structure THV in the second extended region EXT can be arranged in a sawtooth pattern.

[0135] For example, for memory cell block BLK1, the through-structure THV can be formed in the second extended region EXT2, but not in the first extended region EXT1. Similarly, for memory cell block BLK2, the through-structure THV can be formed in the first extended region EXT1, but not in the second extended region EXT2.

[0136] Figure 17 This is a layout diagram of a semiconductor device according to an example embodiment. Figures 18A to 18C It is shown Figure 17 The layout diagram for region R4. For convenience, the above-mentioned diagram can be omitted or simplified. Figures 1 to 16 A description of the components or features being described.

[0137] Reference Figure 17 The width of the storage cell blocks BLK1 to BLKn in the first extended region EXT1 and / or the second extended region EXT2 can be greater than the width of the corresponding storage cell blocks BLK1 to BLKn in the cell array region CELL.

[0138] Here, as used herein, the term "width" refers to the width of the corresponding element in the first direction X. For example, the width D22 of the portion of the first extended region EXT1 corresponding to the memory cell block BLK2 may be greater than the width D21 of the corresponding portion of the cell array region CELL.

[0139] When the width of a portion of the first extended region EXT1 and / or the second extended region EXT2 is greater than the width of the corresponding portion of the cell array region CELL, a larger contact area CNR and / or a larger through area THR can be formed compared to the first extended region EXT1 and / or the second extended region EXT2. For example, in Figure 17 The area in a semiconductor device where a through-structure (THV) can be formed can be larger than that in a semiconductor device. Figure 16 The area where the through-structure THV is formed in semiconductor devices is large.

[0140] Reference Figures 17 to 18C The cell gate cut region CAC, extended gate cut region CNC, through structure THV and lower cut region GC can be arranged in various ways between each pair of adjacent block isolation regions WLC.

[0141] For example, a cell gate cut-off region (CAC) can be formed between each pair of adjacent block isolation regions (WLCs). Therefore, two portions (e.g., a fourth portion (IV) and a fifth portion (V)) can be formed between each pair of adjacent block isolation regions (WLCs).

[0142] In an example embodiment, the cut structure SC can be situated between the block isolation region WLC and the cell gate cut region CAC. For example, the cut structure SC can be situated between the block isolation region WLC defining the fourth portion IV and the fifth portion V and the cell gate cut region CAC. Therefore, the fourth portion IV can be electrically isolated from its corresponding fifth portion V, resulting in the provision of two separately controllable string select lines SSL.

[0143] The lower cut region GC can be connected to the cell gate cut region CAC, the extended gate cut region CNC, or the through structure THV, and therefore the cut ground selection line GSL can be selected. For example, see reference. Figure 18A Two ground select lines (GSLs) can be formed between each pair of adjacent block isolation regions (WLCs), each cut by a cell gate cut region (CAC), an extended gate cut region (CNC), a through structure (THV), and a lower cut region (GC). Therefore, the fourth section (IV) can be electrically isolated from its corresponding fifth section (V), resulting in two individually controllable ground select lines (GSLs).

[0144] In an example embodiment, a portion of the lower cut region GC can connect each pair of adjacent block isolation regions WLC. For example, a portion of the lower cut region GC can extend in the first direction X in the region where each pair of adjacent block isolation regions WLC becomes closer to each other (e.g., at the boundary between the cell array region CELL and the first extended region EXT1).

[0145] Reference Figure 17 and Figure 18B ,and Figure 18A Compared to the size of a through-structure THV, the size of the through-structure THV can be increased. For example, the size of the region forming the extended gate cleavage region (CNC) can be reduced. In this example, the amount of etching of the second insulating pattern 115 in the process of forming multiple gate electrodes (GSL, WL1 to WLn and SSL) (e.g., in a replacement process) can be reduced. For example, the through-structure THV can also extend in the second direction Y.

[0146] In an example embodiment, two ground selection lines (GSLs) can be formed, which are cut by the cell gate cut region (CAC), the through structure (THV), and the lower cut region (GC).

[0147] Reference Figure 17 and Figure 18C In the first extended region EXT1, the portion of the lower cut region GC can extend in the second direction Y compared to... Figure 18AThe corresponding portion of the lower cut region GC is longer. For example, a through structure THV may not be formed between each pair of adjacent block isolation regions WLC. In this example, a portion of the lower cut region GC can extend longer in the second direction Y, resulting in two ground selection lines GSL being set between each pair of adjacent block isolation regions WLC.

[0148] Figure 19 This is a layout diagram of a semiconductor device according to an example embodiment. For convenience, details already referenced above may be omitted or at least simplified. Figures 1 to 18C A description of the components or features being described.

[0149] Reference Figure 19 Each of the multiple storage cell blocks BLK1 to BLKn may not be formed in one of the first extended region EXT1 and the second extended region EXT2.

[0150] For example, a memory cell block BLK1 can be formed in the cell array region CELL and the second extended region EXT2, but may not extend into the first extended region EXT1. Similarly, for example, a memory cell block BLK2 can be formed in both the cell array region CELL and the first extended region EXT1, but may not extend into the second extended region EXT2.

[0151] In the example embodiment, with Figure 17 In different embodiments, only one block-cutting region WLC can be formed between storage cell blocks BLK1 and BLK3.

[0152] Figure 20 This is a layout diagram of a semiconductor device according to an example embodiment. For convenience, the diagrams already referred to above may be omitted or simplified. Figures 1 to 7 A description of the components or features being described.

[0153] Reference Figure 20 The contact area CNR and the through area THR can be arranged alternately along the first direction X.

[0154] For example, in the first extended region EXT1, the contact region CNR and the through region THR can be arranged alternately along the first direction X. Furthermore, for example, in the second extended region EXT2, the contact region CNR and the through region THR can be arranged alternately along the first direction X.

[0155] Figure 20 An example is shown in which only one through region is formed in each of the multiple storage cell blocks BLK1 to BLKn. Alternatively, multiple through regions THR and multiple contact regions can be formed in each of the storage cell blocks BLK1 to BLKn, arranged alternately along the second direction Y.

[0156] In the following text, reference will be made to Figures 1 to 29 A method for manufacturing a semiconductor device according to an example embodiment is described.

[0157] Figures 21 to 29 This illustrates the various stages in a method for manufacturing a semiconductor device according to an example embodiment. For convenience, the steps already referred to above may be omitted or simplified. Figures 1 to 20 A description of the components or features being described.

[0158] refer to Figure 21 and Figure 22 A molded structure MS is formed on the first substrate 100. Figure 22 It is along Figure 21 The cross-sectional view taken from line AA.

[0159] The molded structure MS can be formed on the first substrate 100. The molded structure MS may include a first insulating film 110L and a second insulating film 115L, which are alternately stacked on the first substrate 100.

[0160] In an example embodiment, the cut structure SC can be formed in a molded structure MS within a cell array region CELL. For example, multiple cut structures SC can be arranged along a first direction X within the cell array region CELL. The cut structure SC can be arranged in a second direction Y to cut the uppermost one of the second insulating film 115L.

[0161] Reference Figure 23 and Figure 24 The molded structure MS can be patterned into a stepped shape in the extended region EXT. Figure 24 It is along Figure 23 The cross-sectional view taken from line AA.

[0162] The first insulating film 110L can be patterned into a first insulating pattern 110, which together form a stepped structure in the second direction Y. Furthermore, the second insulating film 115L can be patterned into a second insulating pattern 115, which together form a stepped structure in the second direction Y.

[0163] The extended region EXT may include a contact region CNR and a through region THR. The contact region CNR and the through region THR may be arranged alternately along the second direction Y. In an example embodiment, the length of the second insulating pattern 115 protruding in the through region THR may be greater than the length of the second insulating pattern 115 protruding in the contact region CNR.

[0164] Reference Figure 25 and Figure 26In the molded structure MS, a channel structure CH, a block isolation trench WLT, a cell gate dicing trench CAT, and an extended gate dicing trench CNT are formed. Figure 26 It is along Figure 25 The cross-sectional view taken from line AA.

[0165] The channel structure CH can penetrate the molded structure MS. The channel structure CH can extend in a direction intersecting the first insulating pattern 110 and the second insulating pattern 115. For example, the channel structure CH can be a cylindrical shape (e.g., a cylindrical shape) extending in the third direction Z.

[0166] Block isolation trenches (WLTs) can be formed in the cell array region (CELL) and the extended region (EXT) to cleave multiple gate electrodes (GSL, WL1 to WLn, and SSL). Cell gate trenches (CATs) can be formed in the cell array region (CELL) to cleave the gate electrodes (GSL, WL1 to WLn, and SSL). Extended gate cleaving trenches (CNTs) can be formed in the extended region (EXT) to cleave the gate electrodes (GSL, WL1 to WLn, and SSL).

[0167] Reference Figure 28 and Figure 29 The second insulating pattern 115 can be at least partially removed using block isolation trenches (WLT), cell gate cut trenches (CAT), and extended gate cut trenches (CNT). Figure 29 It is along Figure 28 The cross-sectional view taken from line AA.

[0168] For example, a pull-back process can be performed to at least partially remove the second insulating pattern 115 using a block isolation trench (WLT), a cell gate dicing trench (CAT), and an extended gate dicing trench (CNT). As a result, a portion of the second insulating pattern 115 can be retained, allowing a through-structure THV to be formed in the through-region THR. The through-structure THV may include a plurality of alternately stacked first insulating patterns 110 and a plurality of second insulating patterns 115.

[0169] Subsequently, a block isolation region WLC, a cell gate cut region CAC, and an extended gate cut region CNC can be formed to fill the block isolation trench WLT, the cell gate cut trench CAT, and the extended gate cut trench CNCT, respectively.

[0170] Subsequently, refer to Figure 4 and Figure 5 This allows for the formation of gate contacts 152, a first via 154, bit lines BL, and interconnect lines 156. In this way, a method for manufacturing semiconductor devices with improved integration density and reliability can be provided.

[0171] As described above, the embodiments relate to a semiconductor device including a stepped extension region and a method of manufacturing the semiconductor device.

[0172] Examples can provide semiconductor devices with improved integration density and reliability. Examples can provide a method for manufacturing semiconductor devices with improved integration density and reliability.

[0173] Example embodiments have been disclosed herein, and although specific terminology has been used, it is for descriptive purposes only and should be interpreted in a general descriptive sense, not for limiting purposes. In some instances, as will be appreciated by those skilled in the art upon which this application has been filed, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, wherein a cell array region and an extended region are arranged along a first direction, and a plurality of contact regions and a plurality of through regions are alternately arranged along the first direction in the extended region, the semiconductor device comprising: The molded structure includes multiple first insulating patterns and multiple gate electrodes alternately stacked on a first substrate; A channel structure that penetrates the molded structure in the cell array region to intersect with the plurality of gate electrodes; Corresponding gate contacts are located in the plurality of contact regions on the molded structure and are connected to each of the plurality of gate electrodes; as well as A plurality of second insulating patterns, which are alternately stacked with a plurality of first insulating patterns in the plurality of through regions, are provided in the molded structure. The plurality of second insulating patterns comprise a material different from the plurality of first insulating patterns. In each of the plurality of contact regions, the length of the gate electrode connected to the corresponding gate contact and extending from the cell array region in the first direction decreases as the distance from the first substrate increases.

2. The semiconductor device according to claim 1, further comprising: Multiple gate-cut regions are arranged in the molded structure in the extended region along a second direction intersecting the first direction. Each of the gate cutting regions extends in the first direction to cut the molded structure in the plurality of contact regions, but not in the plurality of through regions.

3. The semiconductor device according to claim 1, wherein, In the extended region, the plurality of gate electrodes are arranged in a stepped manner along the first direction.

4. The semiconductor device according to claim 3, wherein, The length of each of the plurality of gate electrodes protruding in the plurality of through regions is greater than the length of each of the plurality of gate electrodes protruding in the plurality of contact regions.

5. The semiconductor device according to claim 3, wherein, In the extended region, the plurality of gate electrodes are arranged in a stepped manner along a second direction intersecting the first direction.

6. The semiconductor device of claim 1, further comprising a via in one of the plurality of through regions, the via penetrating the plurality of first insulating patterns and the plurality of second insulating patterns.

7. The semiconductor device according to claim 6, wherein, The via is connected to one of the corresponding gate contacts.

8. The semiconductor device according to claim 6, further comprising: A second substrate on which the first substrate is stacked; as well as Peripheral circuit elements are located on the second substrate and connected to the via.

9. The semiconductor device according to claim 1, further comprising: An interlayer insulating film covers the top surface of the molded structure in the extended region. The corresponding gate contact penetrates the interlayer insulating film.

10. The semiconductor device according to claim 1, wherein, The plurality of first insulating patterns include oxides, and The plurality of second insulating patterns include nitrides.

11. The semiconductor device of claim 1, further comprising a bit line extending on the molding structure in a second direction intersecting the first direction, the bit line being connected to the channel structure.

12. A semiconductor device, wherein a cell array region and an extended region are arranged along a first direction, and a plurality of contact regions and a plurality of through regions are alternately arranged along the first direction in the extended region, the semiconductor device comprising: A molded structure comprising a plurality of gate electrodes stacked on a substrate and spaced apart from each other; A channel structure that penetrates the molded structure in the cell array region to intersect with the plurality of gate electrodes; Corresponding gate contacts are located in the plurality of contact regions on the molded structure and are connected to each of the plurality of gate electrodes; Extend the gate cutting region in the first direction to cut the plurality of gate electrodes in the molding structure in the plurality of contact regions; as well as Multiple insulating patterns are stacked at the same level as the multiple gate electrodes in the molded structure in the multiple through regions, each of the multiple insulating patterns including a first side extending along the first direction and a second side forming an arc centered at the end of the extended gate dicing region. In each of the plurality of contact regions, the length of the gate electrode connected to the corresponding gate contact and extending from the cell array region in the first direction decreases as the distance from the substrate increases.

13. The semiconductor device according to claim 12, further comprising: Multiple block isolation regions are arranged along a second direction intersecting the first direction. Each of the block isolation regions extends in the first direction to completely cut the molded structure.

14. The semiconductor device according to claim 13, further comprising: A cell gate dicing region extends in the first direction to dice the plurality of gate electrodes in the molded structure within the cell array region. The cell gate dicing region is located between pairs of adjacent block isolation regions in the plurality of block isolation regions.

15. The semiconductor device of claim 14, further comprising a dicing structure extending in the first direction to dice the uppermost of the plurality of gate electrodes, the dicing structure being between one of the plurality of block isolation regions and the cell gate dicing region.

16. The semiconductor device of claim 12, further comprising: A through-hole, in one of the plurality of through regions, is connected to an external circuit element through the plurality of insulating patterns; as well as A connecting line connects one of the corresponding gate contacts to the through hole.

17. The semiconductor device according to claim 12, wherein: In the plurality of contact regions, the plurality of gate electrodes are arranged in a stepped manner along both the first direction and the second direction intersecting the first direction, and In the plurality of through regions, the plurality of gate electrodes are arranged in a stepped manner along the second direction.

18. A semiconductor device, wherein a cell array region and an extended region are arranged along a first direction, and a plurality of contact regions and a plurality of through regions are alternately arranged along the first direction in the extended region, the semiconductor device comprising: The molded structure includes: a ground select line on a substrate; and a plurality of word lines stacked on the ground select line; The channel structure intersects the ground select line and the plurality of word lines in the cell array region via the molding structure; Extend the gate dicing region in the first direction to dice the ground select line and the plurality of word lines in the molded structure within the plurality of contact regions; and Multiple insulating patterns are stacked in the multiple through regions at the same level as the multiple word lines in the molded structure, and the ground selection line partially overlaps the multiple insulating patterns in a direction perpendicular to the top surface of the substrate.

19. The semiconductor device of claim 18, further comprising: Gate contacts, located in one of the plurality of contact areas on the molded structure and connected to the plurality of word lines; as well as A first through-hole, in one of the plurality of through regions, is connected to a peripheral circuit element through the plurality of insulating patterns.

20. The semiconductor device of claim 19, further comprising: A second through-hole in one of the plurality of through-areas, the second through-hole being connected to the ground selection line through the plurality of insulating patterns.

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