Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods for manufacturing the same. A method includes: forming an active channel region; forming a dummy channel region; forming a first gate dielectric layer above the active channel region; forming a second gate dielectric layer above the dummy channel region; removing the second gate dielectric layer from the dummy channel region; forming a gate isolation region above and in contact with the dummy channel region; and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Metal oxide semiconductor (MOS) devices are basic building blocks in integrated circuits. MOS devices can have a gate electrode formed of polysilicon doped with p-type or n-type impurities, which are doped using a doping process such as ion implantation or thermal diffusion. The work function of the gate electrode can be adjusted to the band edge of silicon. For n-type metal oxide semiconductor (NMOS) devices, the work function can be adjusted to approach the conduction band of silicon. For p-type metal oxide semiconductor (PMOS) devices, the work function can be adjusted to approach the valence band of silicon. The work function of the polysilicon gate electrode can be adjusted by selecting appropriate impurities.

[0003] MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, which is also referred to as the polysilicon gate depletion effect. The polysilicon gate depletion effect occurs when an applied electric field sweeps away carriers from the gate region near the gate dielectric to form a depletion layer. In an n-doped polysilicon layer, the depletion layer includes ionized non-mobile donor sites, wherein in a p-doped polysilicon layer, the depletion layer includes ionized non-mobile acceptor sites. The depletion effect produces an increase in the effective gate dielectric thickness, making it more difficult to form an inversion layer at the surface of the semiconductor.

[0004] The polysilicon gate depletion problem can be solved by forming a metal gate electrode, wherein the metal gate used in NMOS devices and PMOS devices can also have a band edge work function. Therefore, the resulting metal gate includes multiple layers to meet the requirements of NMOS devices and PMOS devices.

[0005] The formation of a metal gate generally includes: forming a dummy gate dielectric and a dummy gate electrode, removing the dummy gate dielectric and the dummy gate electrode to form a trench, depositing a high-k dielectric layer and a metal layer in the trench, and performing a chemical mechanical polishing (CMP) process to remove excess portions of the high-k dielectric layer and the metal layer. The remaining portion of the metal layer forms a metal gate. Summary of the invention

[0006] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming an active channel region; forming a dummy channel region; forming a first gate dielectric layer above the active channel region; forming a second gate dielectric layer above the dummy channel region; removing the second gate dielectric layer from the dummy channel region; forming a gate isolation region above and in contact with the dummy channel region; and forming a first gate stack and a second gate stack, wherein the first gate stack is on the active channel region, and wherein the gate isolation region separates the first gate stack from the second gate stack.

[0007] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a dummy fin, including a first portion and a second portion, wherein the dummy fin includes a dielectric material; a gate isolation region, above the dummy fin and in contact with the dummy fin; a first gate stack and a second gate stack, on opposite sides of the first portion of the dummy fin and in contact with the first portion of the dummy fin; a contact etch stop layer, on opposite side walls and a top surface of the second portion of the dummy fin; and an interlayer dielectric, above the contact etch stop layer.

[0008] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a first protruding semiconductor fin and a second protruding semiconductor fin, which are parallel to each other and protrude higher than the isolation region; a dummy fin between the first protruding semiconductor fin and the second protruding semiconductor fin; a first gate stack and a second gate stack, which extend on the top surface and sidewall of the first protruding semiconductor fin and the second protruding semiconductor fin, respectively; and a gate isolation region between the first gate stack and the second gate stack, wherein the gate isolation region is above the dummy fin and in contact with the dummy fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1-Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7A-1 , Figure 7A-2 , Figure 7B , Fig. 8A , Figure 8B , Figure 9A-1 , Figure 9A-2 and Fig. 9B Perspective and cross-sectional views are shown of intermediate stages in forming a fin field effect transistor (FinFET), according to some embodiments.

[0011] Figure 10-13 , Figure 14-17 , Figure 18-Figure 21 and Figure 22-Figure 25 Intermediate stages of various embodiments of forming dielectric dummy fins are shown in accordance with some embodiments.

[0012] Figure 26-Figure 30 , Figure 31-Figure 35 and Figure 36-Figure 40 Intermediate stages of various embodiments of selectively forming and removing a dummy gate dielectric and forming a gate isolation region are shown in accordance with some embodiments.

[0013] Figure 41-44 , Figure 45-Figure 48 and Figure 49-Figure 50 Intermediate stages of various embodiments of selectively forming and removing a dummy gate dielectric are shown in accordance with some embodiments.

[0014] Figure 51-Figure 53 , Figure 54-Figure 56 and Figure 57-Figure 59 Intermediate stages of various embodiments of selectively forming and removing a dummy gate dielectric are shown in accordance with some embodiments.

[0015] Fig.60 and Fig.61 Cross-sectional views of portions of structures according to some embodiments are shown.

[0016] Fig.62 A cross-sectional view of a dummy fin and gate isolation region is shown in accordance with some embodiments.

[0017] Fig.63 A process flow for forming a transistor with selective removal of a dummy gate dielectric prior to forming a gate isolation region is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0020] According to some embodiments, there is provided a method of pre-removing a dummy gate dielectric from a dielectric dummy fin, then forming a gate isolation region, and forming a corresponding fin field effect transistor (FinFET). The embodiments discussed herein will provide examples to enable the subject matter of the present disclosure to be performed or used, and those skilled in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numbers are used to indicate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0021] Figure 1-Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7A-1 , Figure 7A-2 , Figure 7B , Fig. 8A , Figure 8B , Figure 9A-1 , Figure 9A-2 and Fig. 9B 1 shows a perspective view and a cross-sectional view of an intermediate stage of forming a FinFET, a gate isolation region, and a dielectric dummy fin according to some embodiments. The corresponding process is also schematically reflected in FIG. Fig.63 In the process flow 300 shown.

[0022] Figure 1 1 shows a perspective view of an initial structure. The initial structure includes a wafer 10, which also includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type impurities. An isolation region 22 such as a shallow trench isolation (STI) region is formed to extend from the top surface of the substrate 20 into the substrate 20. The corresponding process is Fig.63 The process flow 300 is shown as process 302. The portion of the substrate 20 located between adjacent STI regions 22 is referred to as semiconductor strip 24. According to some embodiments of the present disclosure, the semiconductor strip 24 is a portion of the original substrate 20, and thus the material of the semiconductor strip 24 is the same as the material of the substrate 20. According to an alternative embodiment of the present disclosure, the semiconductor strip 24 is a replacement strip formed by etching the portion of the substrate 20 located between the STI regions 22 to form a groove, and performing an epitaxial process to re-grow another semiconductor material in the groove. Therefore, the semiconductor strip 24 is formed of a semiconductor material different from the semiconductor material of the substrate 20. According to some embodiments, the semiconductor strip 24 is formed of Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc.).

[0023] The STI region 22 may include a liner oxide (not shown separately), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. The STI region 22 may also include a dielectric material located on the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0024] Figure 2 The formation of dielectric dummy strips 25 and the recessing of STI regions 22 are shown. The tops of semiconductor strips 24 and dielectric dummy strips 25 protrude above the top surface of STI regions 22 to form protruding (semiconductor) fins 24' and (dielectric) dummy fins 25', respectively. Fig.63 The process flow 300 is shown as process 304. The protruding fin 24' and the dummy fin 25' may also be referred to as an active channel region 24' and a dummy channel region 25', respectively. Figure 10-13 , Figure 14-16 , Figure 18-Figure 21 and Figure 22-Figure 25The details of forming the dielectric dummy strips 25 and the dummy fins 25' are shown in detail in the illustrated embodiment, which will be discussed in subsequent paragraphs. According to some embodiments of the present disclosure, the material of the dummy strips 25 includes a silicon-based dielectric material, such as SiN, SiON, SiOCN, SiC, SiOC, SiO2, etc. According to alternative embodiments of the present disclosure, the material of the dummy strips 25 includes a metal-based dielectric material (oxide or nitride), such as TaN, TaO, HfO, etc. The bottom surface of the dielectric dummy strips 25 can be higher than, flush with, or lower than the top surface of the STI region 22, and can be flush with or higher than the bottom surface of the STI region 22. The dummy fins 25 can have a single-layer structure or a multi-layer structure (having multiple layers formed of different materials).

[0025] According to some embodiments, recessing the STI region 22 to form the protruding semiconductor fin 24' and the dielectric dummy fin 25' can be performed using a dry etching process, wherein, for example, HF3 and NH3 are used as etching gases. According to an alternative embodiment, recessing the STI region 22 is performed by a wet etching process. The etching chemistry may include, for example, an HF solution.

[0026] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0027] refer to Figure 3 , a dummy gate stack 30 is formed on the top surface and sidewalls of the protruding fin 24' and the dummy fin 25'. The formation of the dummy gate stack 30 may include selectively forming a gate dielectric 32 on some portions of the protruding fin 24' and the dummy fin 25', which will be discussed in detail in subsequent paragraphs. Fig.63 The process flow 300 is shown as process 306. The dummy fin 25' may therefore be alternatively referred to as a dummy channel. The dummy gate electrode 34 is formed on the dummy gate dielectric 32. The corresponding process is Fig.63 In the process flow 300 shown, this is shown as process 308. Figures 26 to 40 As discussed in detail in the illustrated embodiment, the dummy gate dielectric 32 may be selectively removed from the dummy fin 25' (see Figure 7B). However, the gate dielectric 32 (which may be a dummy gate dielectric or a real gate dielectric in different device regions) is left on the protruding fin 24'. Therefore, on the protruding fin 24', the dummy gate electrode 34 is formed on the gate dielectric 32, while on the dummy fin 25', the dummy gate electrode 34 is in physical contact with the dummy fin 25'.

[0028] Reference again Figure 3 , the gate dielectric 32 may be formed of silicon oxide, silicon nitride, etc., or include silicon oxide, silicon nitride, etc. Depending on the formation process, the gate dielectric 32 may or may not include a horizontal portion on top of the STI region 22. The dummy gate electrode 34 may be formed, for example, using polysilicon or amorphous silicon, and other materials may also be used. Each dummy gate stack 30 may also include one (or more) hard mask layers 36 above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multilayer thereof. The dummy gate stack 30 may span a single or multiple protruding fins 24', dummy fins 25', and STI regions 22. The dummy gate stack 30 also has a length direction perpendicular to the length direction of the protruding fin 24'.

[0029] Next, Figure 3 As shown in FIG. 1 , the gate spacer 38 is formed on the sidewall of the dummy gate stack 30 . Fig.63 The process flow 300 is shown as process 310. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, etc., and may have a single-layer structure or a multi-layer structure (including multiple dielectric layers).

[0030] According to some embodiments of the present disclosure, an etching step is performed to etch the portion of the protruding fin 24' that is not covered by the dummy gate stack 30 and the gate spacer 38, thereby obtaining Figure 4 The corresponding process is Fig.63 The process flow 300 shown is shown as process 312. The recess can be anisotropic, and thus the portion of the fin 24' directly below the dummy gate stack 30 and the gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 can be lower than the top surface 22A of the STI region 22. The space left by the etched portion of the protruding fin 24' is referred to as a groove 40. In the etching process, the dielectric dummy fin 25' is not etched. For example, a mixture of NF3 and NH3, a mixture of HF and NH3, etc. can be used to etch the protruding fin 24'.

[0031] Next, an epitaxial region (source / drain region) 42 is formed by selectively growing a semiconductor material from the recess 40, thereby obtaining Figure 5A The corresponding process is Fig.63 The process flow 300 shown is shown as process 314. According to some embodiments, the epitaxial region 42 includes silicon germanium, silicon, carbon silicon, etc. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, SiB, silicon germanium boron (SiGeB), GeB, etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 42 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or multiple layers thereof. After the epitaxial region 42 completely fills the recess 40, the epitaxial region 42 can begin to expand horizontally and a small plane can be formed.

[0032] Figure 5B 1 shows the formation of cladding source / drain regions 42 according to alternative embodiments of the present disclosure. According to these embodiments, Figure 4 The protruding fin 24' is shown not recessed, and the epitaxial region 41 is grown on the protruding fin 24'. The material of the epitaxial region 41 may be similar to Figure 5A The material of the epitaxial semiconductor material 42 shown depends on whether the resulting FinFET is a p-type or n-type FinFET. Thus, the source / drain region 42 includes the protruding fin 24' and the epitaxial region 41. Implantation may (or may not) be performed to implant n-type impurities or p-type impurities.

[0033] Figure 6 FIG. 4 is a perspective view of the structure after forming a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48. Fig.63The process flow 300 shown is shown as process 316. CESL 46 can be formed of silicon nitride, silicon carbonitride, etc. For example, a conformal deposition method such as ALD or CVD can be used to form CESL 46. ILD 48 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 48 can also be formed of an oxygen-containing dielectric material, or include an oxygen-containing dielectric material, which can be a silicon oxide-based material, such as silicon oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), etc. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to make the top surfaces of ILD 48, dummy gate stack 30, and gate spacer 38 flush with each other. According to some embodiments of the present disclosure, the planarization process stops on the top surface of hard mask 36. According to alternative embodiments, hard mask 36 is also removed in the planarization process, and the planarization process stops on the top surface of dummy gate electrode 34.

[0034] Figure 7A-1 and Figure 7A-2 Device regions 100 and 200 in wafer 10 (and in the same chip) and structures formed therein are shown respectively. According to some embodiments, device region 100 includes but is not limited to a core device region (sometimes referred to as a logic device region), and device region 200 includes but is not limited to an input-output (IO) device region. Therefore, according to some example embodiments, the FinFETs formed in device regions 100 and 200 may be core FinFETs and IO FinFETs, respectively.

[0035] To distinguish features in device region 100 from features in device region 200, features in device region 100 may be distinguished using Figure 6 The reference numerals of the corresponding features in the device area 200 are indicated by adding the number 100, and the features in the device area 200 can be represented by Figure 6 The reference numerals of the corresponding features in the above are indicated by adding the number 200. For example, Figure 7A-1 and Figure 7A-2 The source / drain regions 142 and 242 in Figure 6 The source / drain region 42 in the device region 100 and the ...

[0036] refer to Figure 7A-1 and Figure 7A-2, a dummy gate cutting process is performed by etching the dummy gate stacks 130 and 230 to form openings 150 and 250, respectively. The openings 150 and 250 are also collectively referred to as openings 50. The corresponding process is Fig.63 This is shown as process 318 in the illustrated process flow 300. Thus, each of the dummy gate stacks 130 and 230 is separated into discrete portions. To perform the dummy gate cut process, an etch mask (not shown) (which may include photoresist) may be formed and patterned, and then used to etch the dummy gate stacks 130 and 230.

[0037] Figure 7B Shows that from Figure 7A-1 and Figure 7A-2 7B-7B shown in any one of the cross-sectional views obtained. In the dummy gate cutting process, the dummy gate stack 30 is etched in an anisotropic process until the dielectric dummy fin 25' is exposed. As a result, a portion of the dummy gate stack 30 is removed. Therefore, the longer dummy gate stack 30 is cut into two discrete portions 30A and 30B separated from each other. Each discrete portion 30A and 30B of the dummy gate stack 30 can span one, two or more protruding fins 24' to form a single fin FinFET or a multi-fin FinFET. After etching the dummy gate stack 30, the etching mask is removed, for example, in an ashing process.

[0038] Next, the opening 50 is filled with (one or more) dielectric regions to form gate isolation regions 152 and 252 (collectively referred to as gate isolation regions 52 ), as shown in FIG. Fig. 8A and Figure 8B The gate isolation regions 152 and 252 are formed in the device regions 100 and 200, respectively, and are respectively Figure 9A-1 and Figure 9A-2 The corresponding process is shown separately in Fig.63The process flow 300 shown is shown as process 320. The formation process includes depositing (one or more) dielectric materials and performing a planarization process such as a CMP process. The deposition process can be performed using a method selected from the following: atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), low pressure chemical vapor deposition (LPCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) or other applicable deposition methods. The gate isolation regions 152 and 252 may have a single-layer structure formed by a homogeneous dielectric material, or may have a multilayer structure including multiple layers formed by different materials. The dielectric material includes, but is not limited to, an oxide-based dielectric material, a nitride-based dielectric material, an oxynitride-based dielectric material, a carbide-based dielectric material, and the like.

[0039] As described above, the gate dielectric 32 is removed from the dummy fin 25'. Therefore, the gate isolation region 52 physically contacts the dummy fin 25'. On the other hand, the protruding semiconductor fin 24' still has the gate dielectric 32 formed thereon.

[0040] Then, the dummy gate stacks 30A and 30B are etched, and the hard mask 36 and gate electrode 34 are removed. In the device region 100, the gate dielectric 32 is removed (and is therefore a dummy gate dielectric) and replaced with a core gate oxide, while in the device region 200, the gate dielectric 32 is not removed in the process and is exposed after the gate dielectric is removed, as shown in FIG. Fig.29 , Fig.34 and Fig.39 This will be discussed in detail in the following paragraphs.

[0041] Then, replacement gate stacks 158 and 258 (collectively referred to as 58 ) are formed in device regions 100 and 200 , respectively. Fig.63 This is shown as process 322 in the illustrated process flow 300 . Figure 9A-1 , Figure 9A-2 and Fig. 9B The resulting structure is shown in . Gate stacks 158 and 258 include high-k dielectrics 154 and 254 (collectively referred to as 54) and replacement gate electrodes 156 and 256 (collectively referred to as 56). High-k dielectric 54 can be formed of hafnium oxide, zirconium oxide, lanthanum oxide, etc. Gate electrode 64 can have a composite structure including multiple layers formed of TiN, TaN, TiAl, TaAlC, Co, Al, etc. The corresponding metals and structures are selected so that the resulting replacement gate electrodes 156 and 256 have an appropriate work function. Therefore, FinFETs 160A and 160B are formed in device region 100, as shown in FIG. Figure 9A-1 and Fig. 9B FinFETs 260A and 260B are also formed in the device region 200, as shown. Figure 9A-2 and Fig. 9B shown.

[0042] The previous figures show a brief process flow for forming the dummy fin 25' and the corresponding FinFET.In the subsequent figures and paragraphs, the details of some of the processes briefly discussed in the previous figures are shown and discussed.

[0043] Figure 10-13 , Figure 14-17 , Figure 18-Figure 21 and Figure 22-Figure 25 Details of the formation of dummy strips 25 and dummy fins 25' are shown in accordance with some embodiments. Figure 10-13 , Figure 14-17 , Figure 18-Figure 21 and Figure 22-Figure 25 The process shown can correspond to Figure 1 and Figure 2 As can be understood, Figure 10-Figure 25 Shows Figure 2 The features in region 11 in FIG. 1 are shown, and underlying features such as STI region 22 and substrate 20 are not shown. These features can be referenced Figure 1 and Figure 2 to identify.

[0044] Figures 10 to 13 The formation of dummy strips 25 by deposition and patterning is shown. Fig.10 , semiconductor strips 24 are formed by etching the substrate 20 , and trenches 13 are formed between the semiconductor strips 24 . Fig.10 The structure shown is formed as Figure 1 The STI region 22 is previously formed. Next, referring to Fig.11 , the dielectric layer 25 is formed by deposition and then performing a planarization process to planarize its top surface. Figure 2 The material of the dielectric region 25 is discussed. The dielectric layer 25 is patterned to form a dummy dielectric strip 25, such as Fig.12 As shown. Before the patterning process, an etch-back process may be performed to lower the top surface of the dielectric region 25. In a subsequent process, the STI region 22 is formed to fill the trench 13 and then recessed to form the protruding fin 24' and the dummy fin 25'. It should be understood that whether the STI region 22 is formed first or the dummy dielectric strip 25 is formed first, Figure 14-17 The process sequence shown is similar to Figure 1 and Figure 2 The order of processing shown is slightly different.

[0045] Figures 14 to 17 The formation of dummy strips 25 and dummy fins 25 ′ is shown according to an alternative embodiment, wherein semiconductor strips 24 are etched and then refilled. Fig.14 and Fig.15 Shown is the method for forming Figure 1 The process of the structure shown. Fig.14 In the process, substrate 20 is etched to form semiconductor strips 24, wherein trenches 13 are formed between semiconductor strips 24. Next, trenches 13 are filled to form STI regions 22. Fig.16 Semiconductor strips 24 are shown recessed to form trenches 15 between adjacent STI regions 22. In subsequent processing, dielectric material is filled into trenches 15 to form dummy strips 25, and then STI regions 22 are recessed to form protruding fins 24' and dummy fins 25'.

[0046] Figures 18 to 21 The formation of dummy stripes 25 according to an alternative embodiment is shown, wherein the formation process includes conformal deposition of STI regions 22 and a dielectric fill process. Fig.18 The formation of semiconductor strips 24 and trenches 13 is shown, which includes etching semiconductor substrate 20 to form semiconductor strips 24, wherein trenches 13 are formed between semiconductor strips 24. Fig.19 In the embodiment, a dielectric material is deposited. The dielectric material is the same as the material used to form the STI region 22 and is therefore referred to as dielectric material 22. According to some embodiments, the dielectric material 22 is formed using a conformal deposition method such as ALD, CVD, etc., so that the surface of the dielectric material 22 follows the topology of the protruding fin 24'. Thus, trenches 15 are formed in the dielectric material 22. Fig. 20 In the process, dummy strips 25 are formed in STI regions 22, which includes a deposition process, a planarization process, and an etch-back process. Dummy strips 25 and STI regions 22 are formed of different dielectric materials. Fig.21 The etching back of dummy strip 25 and the recessing of STI region 22 are shown to form protruding fin 24 ′ and dummy fin 25 ′. In the resulting structure, dummy strip 25 is formed directly on top of a portion of STI region 22 .

[0047] Figure 22 to Figure 25 The formation of dummy strips 25 and dummy fins 25 ′ is shown according to an alternative embodiment, wherein the dielectric layer used to form STI regions 22 is etched and filled. Fig. 22 The formation of semiconductor strips 24 and trenches 13 is shown, and the formation process includes etching the semiconductor substrate 20 to form semiconductor strips 24, wherein trenches 13 are formed between the semiconductor strips 24. Fig.10 The process shown is essentially the same. Fig.23In the embodiment, a dielectric material is deposited. The dielectric material is the same as the material used to form the STI region 22 and is therefore referred to as the dielectric material 22. Next, the trench 15 is formed by etching the dielectric material 22, as shown in FIG. Fig.24 Next, a dummy strip 25 ( Fig.25 ). The formation of the dummy strip 25 may include a deposition process, a planarization process, and an etch-back process. The dummy strip 25 and the STI region 22 are formed of different dielectric materials. As shown in the figure, the dielectric material 22 is then etched back to form the STI region 22. According to these embodiments, the dummy strip 25 is formed directly above a portion of the STI region 22.

[0048] Figure 26-Figure 30 , Figure 31-Figure 35 and Figure 36-Figure 40 Several different embodiments are shown, including forming a dummy gate and replacing the dummy gate with a replacement gate, and forming a gate isolation region 52 on the dummy fin 25'. Figure 26-Figure 40 The process shown in corresponds to Figure 3-Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7A-1 , Figure 7A-2 , Figure 7B , Fig. 8A , Figure 8B , Figure 9A-1 , Figure 9A-2 and Fig. 9B The process shown in Figure 26-Figure 30 , Figure 31-Figure 35 and Figure 36-Figure 40 In each of the 100 and subsequent figures, four regions and corresponding cross-sectional views are obtained and shown in each figure. The cross-sectional views are obtained from regions 100-channel, 200-channel, 100-non-iso, and 100-iso. The cross-sectional 100-channel is obtained from a channel in device region 100, as shown in FIG. Figure 9A-1 The cross-sectional view 200 of the channel is obtained from the channel in the device region 200, as shown in FIG. Figure 9A-2 The non-isolated cross section 100 is obtained from the portion of the device region 100 that passes through the dummy fin 25' but does not pass through the gate isolation region 52, as shown in FIG. Figure 9A-1 The cross section 100 is isolated through the gate isolation region 52, as shown in FIG. Figure 9A-1 shown.

[0049] Figure 26-Figure 30 FIG. 1 shows a cross section of a formation process according to some embodiments. Fig.26, forming a protruding fin 24' and a dummy fin 25'. This structure also corresponds to Figure 2 Next, refer to Fig. 27 , the dummy gate dielectric 32 is selectively formed on the protruding fin 24', but not on the dummy fin 25'. This process corresponds to Figure 3 The process shown. Figure 41-44 The embodiment shown in the figure shows in detail the method for forming Fig. 27 The material of the dummy gate dielectric 32 may include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0050] Fig.28 The formation of the dummy gate electrode 34 is shown, and the dummy gate electrode 34 can be formed of or include polysilicon, amorphous silicon or other types of materials. The process also corresponds to Figure 3 It can be understood that in the cross-sections 100 and 200, the dummy gate electrode 34 is separated from the corresponding protruding fin 24' by the gate dielectric 32, while in the cross-sections 100 and 100, the dummy gate electrode 34 is in physical contact with the dummy fin 25'. Fig.28 As shown, a gate isolation region 52 is formed to contact the underlying dummy fin 25'. This process corresponds to Figure 7A-1 , Figure 7A-2 , Figure 7B , Fig. 8A and Figure 8B Process shown.

[0051] Fig.29 3 shows the removal of the dummy gate electrode 34. Fig.29 As shown, the dummy gate dielectric 32 (132) is removed from the device region 100 (see Fig.28 ), and a gate dielectric 132' is formed, as shown in the cross-section 100 channel. The gate dielectric 232 in the cross-section 200 channel remains unremoved. Therefore, the gate dielectric 232 serves as the actual gate dielectric of the corresponding FinFET. Figure 51-Figure 53 The embodiment shown in the figure shows Fig.29 Details of the process shown.

[0052] Fig.30 The formation of high-k dielectrics 154 and 254 and replacement gate electrodes 156 and 256 are shown, which form replacement gate stacks 158 and 258. This process corresponds to Figure 9A-1 , Figure 9A-2 and Fig. 9B As shown in the process Fig.30As shown in the cross-section 100 in FIG. 1 , the dummy fin 25′ contacts the overlying gate isolation region 52 to completely separate the replacement gate stack 158A from the replacement gate stack 158B. However, if the dummy gate dielectric 32 is not removed from the dummy fin 25′ before forming the gate isolation region 52, then the dummy gate dielectric 32 will be removed from the dummy fin 25′. Fig.29 The dummy gate dielectric 32 is removed in the process shown, and a space will be formed between the dummy fin 25' and the overlying gate isolation region 52. The material of the replacement gate electrode 56 may be filled into the space, resulting in leakage between the gate stacks 158A and 158B. According to some embodiments of the present disclosure, the dummy gate dielectric is selectively removed from the dummy fin 25' before forming the gate isolation region, thereby eliminating the leakage path.

[0053] Figure 31 to Figure 35 A cross section of a formation process according to an alternative embodiment is shown. Figures 26 to 30 The embodiment shown is similar except that there is a gate dielectric layer ( Fig.34 ). refer to Fig.31 , forming a protruding fin 24' and a dummy fin 25'. Next, as Fig.32 As shown, a dummy gate dielectric 32 is formed. Fig. 27 Unlike the illustrated embodiment, the dummy gate dielectric 32 remains on the portion of the dummy fin 25' that is not isolated in the cross section 100. Figure 45-Figure 48 The process shown in the figure shows Fig.32 Details of the formation of the structure. Fig.33 2 shows the formation of the dummy gate electrode 34. Next, the dummy gate electrode 34 is removed. Fig.34 As shown. In addition, the dummy gate dielectric 132 is removed from the device region 100 (cross-section 100 channel) and replaced with a replacement dielectric layer 132', for example by deposition, natural oxidation, etc. At the same time, a gate dielectric 132" is formed on the dummy fin 25' and is non-isolated in the cross-section 100. Figure 54-Figure 56 The process shown in the figure shows Fig.34 Details of the formation of the structure. Fig.35 The formation of a replacement gate 58 is shown.

[0054] Figures 36 to 40 A cross section of a formation process according to an alternative embodiment is shown. Figures 26 to 30 The embodiment shown is similar except that the dummy gate dielectric 32 is formed by oxidizing the surface portion of the protruding fin 24'. Fig.36 , forming a protruding fin 24' and a dummy fin 25'. Next, as Fig.37 As shown, a dummy gate dielectric 32 is formed. Figure 49-Figure 50The process shown in the figure shows Fig.37 Details of the formation of the structure. Fig.38 2 shows the formation of the dummy gate electrode 34. Next, the dummy gate electrode 34 is removed. Fig.39 In addition, the dummy gate dielectric 132 is removed from the device region 100 (cross-section 100 channel) and replaced by a replacement dielectric layer 132'. Figure 57-Figure 59 The process shown in the figure shows Fig.39 Details of the formation of the structure. Fig.40 The formation of a replacement gate 58 is shown.

[0055] Figure 41 to Figure 44 A process for forming a gate dielectric and then selectively removing the gate dielectric is shown. This process can be used to form Fig. 27 The structure shown. Fig.41 It shows that Fig.26 Next, Fig.42 As shown, dummy gate dielectric 32 is formed in both device regions 100 and 200 and thus covers all portions of protruding fins 24' and dummy fins 25' in cross-section 100 channel, 200 channel, 100 non-isolated, and 100 isolated. Fig.43 In the embodiment, an etching mask 66 (which may be formed of a photoresist) is formed to cover the channel portions of the dummy gate dielectric 32 that cover the protruding fins 24' in the device regions 100 and 200, while allowing the portions of the dummy gate dielectric 32 that cover the dummy fins 25' to be exposed through the etching mask 66. Next, the exposed portions of the dummy gate dielectric 32 on the dummy fins 25' are removed. The etching mask 66 is then removed, and the resulting structure is Fig.44 Shown in.

[0056] Figures 45 to 48 A process for forming a gate dielectric and then selectively removing the gate dielectric is shown. This process can be used to form Fig.32 The structure shown. Fig.45 It shows that Fig.31 Next, Fig.46 As shown, dummy gate dielectric 32 is formed in both device regions 100 and 200 and thus covers all portions of protruding fins 24' and dummy fins 25' in cross-section (area) 100 channel, 200 channel, 100 non-isolated, and 100 isolated. Fig.47In the embodiment, an etch mask 66 (which may be formed of a photoresist) is formed to cover the channel portions of the dummy gate dielectric 32 covering the protruding fins 24' in the device regions 100 and 200. The portions of the dummy gate dielectric 32 in the non-isolated cross section 100 are also covered, while the portions of the dummy gate dielectric 32 covering the dummy fins 25' in the isolated cross section 100 are exposed through the etch mask 66. Next, the exposed portions of the dummy gate dielectric 32 are removed. The etch mask 66 is then removed, and the resulting structure is Fig.48 Shown in.

[0057] like Figures 41 to 48 The process shown has the cost of an additional photolithography process. However, the thickness of the resulting dummy gate dielectric 32 can be adjusted to a desired value.

[0058] Fig.49 and Fig.50 A process for selectively forming a gate dielectric according to some embodiments is shown. The process may be used to form Fig.37 The structure shown. Fig.49 It shows that Fig.36 Next, Fig.50 As shown, a dummy gate dielectric 32 is formed on the protruding fin 24', wherein the exposed surface layer (e.g., formed of Si, SiGe, etc.) of each protruding fin 24' is converted into a dielectric layer 32, which includes silicon oxide (SiO2), SiN, SiCN, etc. The surface layer of the dummy fin 25' remains a dielectric, and therefore the surface layer is not shown separately, but some elements, such as oxygen, nitrogen, carbon, etc., may also be added to the surface layer. The conversion may be achieved by thermal oxidation, thermal nitridation, chemical oxidation, etc. For example, thermal oxidation may be performed using O2, SO2, CO2, CO, similar process gases, or a combination thereof. Thermal nitridation may be performed using N2, NH3, similar process gases, or a combination thereof. The thickness of the resulting dummy gate dielectric 32 may be about 1000 nm. Peace In the range between Fig.49 and Fig.50 The process shown has the advantageous feature of skipping a photolithography operation. However, the thickness of the resulting dummy gate dielectric 32 is limited.

[0059] Figure 51-Figure 53 , Figure 54-Figure 56 and Figure 57-Figure 59 Some processes are shown for selectively replacing the gate dielectric in the device region 100 (eg, core region) while retaining the gate dielectric 232 in the device region 200 (eg, IO region) as a true gate dielectric.

[0060] Figure 51-Figure 532 shows an embodiment in which no gate dielectric is formed on the dummy fin 25'. Fig.29 The structure shown. Fig.51 Can correspond to Fig.28 The structure shown is different in that Fig.28 The gate electrode 34 shown has been removed. Fig.52 As shown, an etch mask 68 (which may be a photoresist) is formed and patterned to cover the device region 200 (cross-section 200 channel) so that the device region 100 (including the portions appearing in the cross-section 100 channel, 100 non-isolated and 100 isolated) is exposed. Next, the dummy gate dielectric 132 is removed and replaced by the gate dielectric 132', as shown. Fig.52 The gate dielectric 132' may be a native oxide, or may be formed by a deposition or oxidation process. The thickness may be about to about The etching mask 68 is then removed and the resulting structure is Fig.53 Shown in.

[0061] Figure 54-Figure 56 An embodiment is shown in which a thin gate dielectric is formed on portions of the dummy fin 25' that are not isolated in the cross section 100 and is not formed on portions of the dummy fin 25' that are isolated in the cross section 100. This process may be used to form Fig.34 The structure shown. Fig.54 Can correspond to Fig.33 The structure shown is different in that Fig.33 The gate electrode 34 shown has been removed. Fig.55 As shown, an etching mask 68 is formed and patterned to cover the device region 200 (cross-section 200 channel), so that the device region 100 (including the cross-section 100 channel, 100 non-isolated and 100 isolated portions) is exposed. Next, as shown in FIG. Fig.54 The dummy gate dielectric 132 is shown removed and replaced by a gate dielectric 132', as shown in FIG. Fig.55 As shown. Gate dielectric 132" is also formed in the cross section 100 without isolation. The formation process may include a deposition process. Gate dielectrics 132' and 132" may be formed of silicon oxide, silicon nitride, etc., or include silicon oxide, silicon nitride, etc. The etching mask 68 is removed, and the resulting structure is Fig.56 Shown in.

[0062] Figure 57-Figure 59 Shown with Figure 51-Figure 53 The embodiment shown in FIG. 1 is similar to the embodiment shown in FIG. 1 , except that the dummy gate dielectric 32 is formed by oxidation, nitridation, etc. The process may be used to form Fig.39The structure shown. Fig.57 can correspond to Fig.38 the structure shown, except that, as Fig.38 shown, the gate electrode 34 has been removed. As Fig.58 shown, an etch mask 68 is formed. Next, as Fig.57 shown, the dummy gate dielectric 132 is removed and replaced by a gate dielectric 132’, as Fig.58 shown. Then the etch mask 68 is removed, and the resulting structure is shown in Fig.59 .

[0063] Fig.60 Cross-sections of the gate structure are shown that are obtained from the structures shown in Figure 9A-1 , Figure 9A-2 and Fig. 9B , and are also shown in Fig.30 and Fig.40 . The sidewall thicknesses of the dielectric layers 132’, 232, 132” (if present) and 132”’ (if present) are shown as CDS1, CDS2, CDS3 and CDS4, respectively. The top thicknesses of the dielectric layers 132’, 232, 132” (if present) and 132”’ (if present) are shown as CDT1, CDT2, CDT3 and CDT4, respectively.

[0064] According to some embodiments, there is a relationship CDS1 > CDS3 and CDS1 > CDS4. There can also be relationships CDS1 < CDS2 and CDT1 < CDT2. The ratios CDS2 / CDS1 and CDT2 / CDT1 can be greater than about 2 and can be between about 5 and about 10. The thicknesses CDT3, CDT4, CDS3 and CDS4 can be equal to zero (when the corresponding dielectric layers 132” and / or 132”’ are not present), or equal to the thickness of the native oxide (about and can be between and ).

[0065] Fig.61 Cross-sections of the gate structure are shown that are obtained from the structures shown in Figure 9A-1 , Figure 9A-2 and Fig. 9B , and are also shown in Fig.35is shown. According to some embodiments, thickness CDS1 is close to or equal to thickness CDS3, and the relationship CDS3 > CDS4 may exist. Thickness CDT1 is close to or equal to thickness CDT3, and the relationships CDT1 < CDT2 and CDT3 > CDT4 may exist. The relationship CDS1 < CDS2 and CDT1 < CDT2 exist. The ratios CDS2 / CDS1 and CDT2 / CDT1 may be greater than about 2 and may be between about 5 and about 10. In Fig.61 and Fig.62 each of CDS1, CDT1, CDS3, CDT3, CDS4, and CDT4 may be in the range of about (when it is a native oxide) and about In the range between. CDS2 and CDT2 may be in the range of about and about In the range between.

[0066] Fig.62 FIG. shows a cross-sectional view of the gate isolation region 152 and the dummy fin 125' according to some embodiments. Through the formation process of the present disclosure, due to the selective removal of the gate dielectric 32 (this selective removal process is performed before the formation of the gate isolation region 152), the intermediate top surface portion of the dummy fin 125' can be recessed below the opposite portion. The gate isolation region 152 accordingly extends into the groove in the dummy fin 125'. In addition, the bottom corner 53 of the gate isolation region 152 has a right angle (90 degrees).

[0067] Embodiments of the present disclosure have some advantageous features. By removing the dummy gate dielectric from the dummy fin before forming the gate isolation region, no space is generated between the dummy fin and the overlying gate isolation region. If a space is formed (which is caused by removing the dummy gate dielectric between the gate isolation region and the underlying dummy fin), the space may be filled with the material of the replacement gate electrode. This will result in leakage between the corresponding gate isolation region and the replacement gate electrode on the opposite side of the dummy fin. Therefore, through the embodiments of the present disclosure, the risk of leakage is eliminated.

[0068] According to some embodiments of the present disclosure, a method includes: forming an active channel region; forming a dummy channel region; forming a first gate dielectric layer above the active channel region; forming a second gate dielectric layer above the dummy channel region; removing the second gate dielectric layer from the dummy channel region; forming a gate isolation region above the dummy channel region and in contact with the dummy channel region; and forming a first gate stack and a second gate stack, wherein the first gate stack is on the active channel region, and wherein the gate isolation region separates the first gate stack from the second gate stack. In an embodiment, the method further includes: after removing the second gate dielectric layer, forming a dummy gate electrode above the dummy channel region; and patterning the dummy gate electrode to form an opening, wherein the gate isolation region is formed in the opening. In an embodiment, the method further includes: after forming the gate isolation region, removing the dummy gate electrode. In an embodiment, the first gate stack and the second gate stack are in contact with both the dummy channel region and the gate isolation region, and are separated from each other by both the dummy channel region and the gate isolation region. In an embodiment, the first gate stack and the second gate stack include a first gate dielectric and a second gate dielectric, respectively, wherein each of the first gate dielectric and the second gate dielectric has a sidewall portion that is in physical contact with both the dummy channel region and the gate isolation region. In an embodiment, the first gate dielectric layer and the second gate dielectric layer are deposited in a common deposition process. In an embodiment, the method further includes: removing the first gate dielectric layer from the active channel region; and forming a replacement gate dielectric layer on the active channel region. In an embodiment, the dummy channel region includes: a first portion, wherein the second gate dielectric layer is removed from the first portion; and a second portion, wherein the second gate dielectric layer remains on the second portion after the second gate dielectric layer is removed from the first portion. In an embodiment, the first portion is between the first gate stack and the second gate stack, and the method further includes: forming a first source / drain region and a second source / drain region on opposite sides of the second portion.

[0069] According to some embodiments of the present disclosure, a device includes: a dummy fin including a first portion and a second portion, wherein the dummy fin includes a dielectric material; and a gate isolation region, which is above the dummy fin and in contact with the dummy fin; a first gate stack and a second gate stack, which are on opposite sides of the first portion of the dummy fin and in contact with the first portion of the dummy fin; a contact etch stop layer, which is on opposite sidewalls and a top surface of the second portion of the dummy fin; and an interlayer dielectric, which is above the contact etch stop layer. In an embodiment, the first gate stack and the second gate stack are parts of a first FinFET and a second FinFET, respectively. In an embodiment, the first FinFET includes a first gate dielectric having a first silicon oxide layer, and the device also includes a third FinFET, which includes: a protruding semiconductor fin; and a second gate dielectric, which is above the protruding semiconductor fin and in contact with the protruding semiconductor fin, wherein the second gate dielectric includes a second silicon oxide layer that is thicker than the first silicon oxide layer. In an embodiment, the dummy fin and the gate isolation region are formed of different materials. In an embodiment, the dummy fin includes a first top surface and a second top surface on an opposite side of the first top surface, wherein the first top surface is recessed below the second top surface. In an embodiment, the gate isolation region extends laterally beyond an edge of the dummy fin, and the gate isolation region includes a bottom corner having a right angle. In an embodiment, the device further includes: a dummy gate dielectric between and in contact with the contact etch stop layer and the second portion of the dummy fin.

[0070] According to some embodiments of the present disclosure, a device includes: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a first protruding semiconductor fin and a second protruding semiconductor fin, parallel to each other and protruding higher than the isolation region; a dummy fin, between the first protruding semiconductor fin and the second protruding semiconductor fin; a first gate stack and a second gate stack, extending on the top surface and sidewalls of the first protruding semiconductor fin and the second protruding semiconductor fin, respectively; and a gate isolation region, between the first gate stack and the second gate stack, wherein the gate isolation region is above the dummy fin and in contact with the dummy fin. In an embodiment, the device further includes: a first gate spacer and a second gate spacer, wherein each of the gate isolation region, the first gate stack and the second gate stack is between and in contact with both the first gate spacer and the second gate spacer. In an embodiment, the device further includes: a contact etch stop layer, in contact with the opposite sidewalls of the dummy fin; and an interlayer dielectric, above the contact etch stop layer. In an embodiment, the gate isolation region is in contact with the first gate stack and the second gate stack.

[0071] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments or examples introduced herein and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0072] Example 1. A method for manufacturing a semiconductor device, comprising: forming an active channel region; forming a dummy channel region; forming a first gate dielectric layer above the active channel region; forming a second gate dielectric layer above the dummy channel region; removing the second gate dielectric layer from the dummy channel region; forming a gate isolation region above and in contact with the dummy channel region; and forming a first gate stack and a second gate stack, wherein the first gate stack is on the active channel region, and wherein the gate isolation region separates the first gate stack from the second gate stack.

[0073] Example 2. The method according to Example 1 further includes: after removing the second gate dielectric layer, forming a dummy gate electrode above the dummy channel region; and patterning the dummy gate electrode to form an opening, wherein the gate isolation region is formed in the opening.

[0074] Example 3. The method according to Example 2 further includes: removing the dummy gate electrode after forming the gate isolation region.

[0075] Example 4. The method of Example 1, wherein the first gate stack and the second gate stack are in contact with both the dummy channel region and the gate isolation region, and are separated from each other by both the dummy channel region and the gate isolation region.

[0076] Example 5. A method according to Example 1, wherein the first gate stack and the second gate stack include a first gate dielectric and a second gate dielectric, respectively, wherein each of the first gate dielectric and the second gate dielectric has a sidewall portion that is in physical contact with both the virtual channel region and the gate isolation region.

[0077] Example 6. The method of Example 1, wherein the first gate dielectric layer and the second gate dielectric layer are deposited in a common deposition process.

[0078] Example 7. The method of Example 1, further comprising: removing the first gate dielectric layer from the active channel region; and forming a replacement gate dielectric layer on the active channel region.

[0079] Example 8. A method according to Example 1, wherein the dummy channel region includes: a first portion, wherein the second gate dielectric layer is removed from the first portion; and a second portion, wherein the second gate dielectric layer remains on the second portion after the second gate dielectric layer is removed from the first portion.

[0080] Example 9. The method of Example 8, wherein the first portion is between the first gate stack and the second gate stack, and the method further comprises: forming a first source / drain region and a second source / drain region on opposite sides of the second portion.

[0081] Example 10. A semiconductor device comprising: a dummy fin comprising a first portion and a second portion, wherein the dummy fin comprises a dielectric material; a gate isolation region above the dummy fin and in contact with the dummy fin; a first gate stack and a second gate stack on opposite sides of the first portion of the dummy fin and in contact with the first portion of the dummy fin; a contact etch stop layer on opposite side walls and a top surface of the second portion of the dummy fin; and an interlayer dielectric above the contact etch stop layer.

[0082] Example 11. The semiconductor device of Example 10, wherein the first gate stack and the second gate stack are parts of a first fin field effect transistor FinFET and a second FinFET, respectively.

[0083] Example 12. A semiconductor device according to Example 11, wherein the first FinFET includes a first gate dielectric having a first silicon oxide layer, and the device also includes a third FinFET, the third FinFET including: a protruding semiconductor fin; and a second gate dielectric above and in contact with the protruding semiconductor fin, wherein the second gate dielectric includes a second silicon oxide layer thicker than the first silicon oxide layer.

[0084] Example 13. The semiconductor device of Example 10, wherein the dummy fin and the gate isolation region are formed of different materials.

[0085] Example 14. The semiconductor device of Example 10, wherein the dummy fin includes a first top surface and a second top surface on an opposite side of the first top surface, wherein the first top surface is recessed lower than the second top surface.

[0086] Example 15. The semiconductor device of Example 10, wherein the gate isolation region extends laterally beyond an edge of the dummy fin, and the gate isolation region includes a bottom corner having a right angle.

[0087] Example 16. The semiconductor device of Example 10, further comprising: a dummy gate dielectric between and in contact with the contact etch stop layer and the second portion of the dummy fin.

[0088] Example 17. A semiconductor device, comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a first protruding semiconductor fin and a second protruding semiconductor fin, parallel to each other and protruding above the isolation region; a dummy fin between the first protruding semiconductor fin and the second protruding semiconductor fin; a first gate stack and a second gate stack, extending on the top surface and sidewall of the first protruding semiconductor fin and the second protruding semiconductor fin, respectively; and a gate isolation region between the first gate stack and the second gate stack, wherein the gate isolation region is above the dummy fin and in contact with the dummy fin.

[0089] Example 18. The semiconductor device according to Example 17 further includes: a first gate spacer and a second gate spacer, wherein each of the gate isolation region, the first gate stack and the second gate stack is between and in contact with both the first gate spacer and the first gate spacer.

[0090] Example 19. The semiconductor device of Example 17, further comprising: a contact etch stop layer in contact with opposite sidewalls of the dummy fin; and an interlayer dielectric on the contact etch stop layer.

[0091] Example 20. The semiconductor device of Example 17, wherein the gate isolation region contacts the first gate stack and the second gate stack.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming an active channel region; forming a dummy channel region; forming a first gate dielectric layer over the active channel region; forming a second gate dielectric layer over the dummy channel region; removing the second gate dielectric layer from the dummy channel region; After removing the second gate dielectric layer, forming a dummy gate electrode on the dummy channel region; patterning the dummy gate electrode to form an opening, wherein the dummy channel region is exposed through the opening; forming a gate isolation region in the opening and in contact with the dummy channel region; and A first gate stack and a second gate stack are formed, wherein the first gate stack is on the active channel region, and wherein the gate isolation region separates the first gate stack from the second gate stack.

2. The method according to claim 1, further comprising: After forming the gate isolation region, the dummy gate electrode is removed.

3. The method according to claim 1, wherein: The first gate stack and the second gate stack are in contact with both the dummy channel region and the gate isolation region, and are separated from each other by both the dummy channel region and the gate isolation region.

4. The method according to claim 1, wherein: The first gate stack and the second gate stack include a first gate dielectric and a second gate dielectric, respectively, wherein each of the first gate dielectric and the second gate dielectric has a sidewall portion in physical contact with both the dummy channel region and the gate isolation region.

5. The method according to claim 1, wherein: The first gate dielectric layer and the second gate dielectric layer are deposited in a common deposition process.

6. The method according to claim 1, further comprising: removing the first gate dielectric layer from the active channel region; as well as A replacement gate dielectric layer is formed over the active channel region.

7. The method according to claim 1, wherein: The dummy channel region includes: a first portion, wherein the second gate dielectric layer is removed from the first portion; and A second portion, wherein the second gate dielectric layer remains on the second portion after the second gate dielectric layer is removed from the first portion.

8. The method according to claim 7, wherein: The first portion is between the first gate stack and the second gate stack, and the method further includes forming a first source / drain region and a second source / drain region on opposite sides of the second portion.

9. A semiconductor device comprising: a dummy fin comprising a first portion and a second portion, wherein the dummy fin comprises a dielectric material; a gate isolation region, above and in contact with the dummy fin; a first gate stack and a second gate stack on opposite sides of and in contact with the first portion of the dummy fin; a contact etch stop layer on opposite sidewalls and a top surface of the second portion of the dummy fin; a dummy gate dielectric between and in contact with the contact etch stop layer and the second portion of the dummy fin; as well as An interlayer dielectric is above the contact etch stop layer.

10. The semiconductor device according to claim 9, wherein The first gate stack and the second gate stack are parts of a first fin field effect transistor FinFET and a second FinFET, respectively.

11. The semiconductor device according to claim 10, wherein: The first FinFET includes a first gate dielectric including a first silicon oxide layer, and the device further includes a third FinFET, the third FinFET including: protruding semiconductor fins; and A second gate dielectric is over and in contact with the protruding semiconductor fin, wherein the second gate dielectric comprises a second silicon oxide layer thicker than the first silicon oxide layer.

12. The semiconductor device according to claim 9, wherein The dummy fin and the gate isolation region are formed of different materials.

13. The semiconductor device according to claim 9, wherein: The dummy fin includes a first top surface and a second top surface on an opposite side of the first top surface, wherein the first top surface is recessed lower than the second top surface.

14. The semiconductor device according to claim 9, wherein: The gate isolation region laterally extends beyond an edge of the dummy fin, and the gate isolation region includes a bottom corner having a right angle.

15. A semiconductor device comprising: Semiconductor substrate; an isolation region extending into the semiconductor substrate; A first protruding semiconductor fin and a second protruding semiconductor fin are parallel to each other and protrude higher than the isolation region; a dummy fin between the first protruding semiconductor fin and the second protruding semiconductor fin, wherein the dummy fin includes a first portion and a second portion; a dummy gate dielectric in contact with sidewalls and a top surface of a second portion of the dummy fin, wherein the dummy gate dielectric is absent on a first portion of the dummy fin; a contact etch stop layer on the dummy gate dielectric; A first gate stack and a second gate stack extending on top surfaces and sidewalls of the first protruding semiconductor fin and the second protruding semiconductor fin, respectively; and A gate isolation region is between the first gate stack and the second gate stack, wherein the gate isolation region is above and in contact with a first portion of the dummy fin.

16. The semiconductor device according to claim 15, further comprising: A first gate spacer and a second gate spacer, wherein each of the gate isolation region, the first gate stack, and the second gate stack is between and in contact with both the first gate spacer and the first gate spacer.

17. The semiconductor device according to claim 15, further comprising: An interlayer dielectric is above the contact etch stop layer.

18. The semiconductor device according to claim 15, wherein: The gate isolation region contacts the first gate stack and the second gate stack.

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