Scrambled clock generation circuit

Abstract

The present invention provides a scrambled clock generating circuit, comprising: a pseudo-random number generator, configured to generate a pseudo-random number according to an original clock signal generated by an original clock; a scrambled enable generator, configured to generate an enable signal according to the original clock signal and the pseudo-random number; and a final output clock, configured to output the original clock signal as a final clock signal according to the enable signal.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a scrambled clock generating circuit. Background Art

[0002] In recent years, with the development of technologies such as cloud computing, the Internet of Things, and mobile computing, and the continuous expansion of their application fields, modern information technology has played an increasingly prominent role in social life. At the same time, the demand for information security is growing. In more and more fields such as financial bank cards, social security cards, computer security boot chips, and vehicle-mounted MCUs, complex security tests need to be performed on chips. High-security chips not only require faster response speeds, but also need to resist various attacks, especially energy attacks.

[0003] Energy attack, also known as power consumption attack, is a type of side-channel attack. It exploits the correlation between the power consumption of cryptographic devices and cryptographic algorithms, and obtains key information by measuring the power consumption of cryptographic devices multiple times and then performing statistical analysis.

[0004] The mask method is a commonly used method to resist energy attacks. It makes attacks more difficult by masking the intermediate values ​​of encryption operations. However, the mask method requires major modifications to existing encryption algorithms, which results in high hardware overhead.

[0005] Clock scrambling is another anti-attack method. After random scrambling, the clock signal changes randomly, so that the current curve inside the security chip no longer changes regularly, but changes randomly, thereby increasing the difficulty of attack and improving the anti-attack performance of the security chip.

[0006] Chinese invention patent CN105894079B proposes a clock scrambling circuit based on a phase delay unit. This method requires the design of a delay unit including multiple delay positions. This type of custom circuit design has a large hardware overhead and cannot accurately control the performance overhead caused by the scrambled clock. Summary of the invention

[0007] The object of the present invention is to provide a novel scrambled clock generating circuit, which can realize a scrambled clock with accurately controlled performance loss overhead through a digital circuit design method.

[0008] In order to solve the above technical problems, the present invention provides a scrambled clock generating circuit, comprising:

[0009] a pseudo-random number generator configured to generate a pseudo-random number based on an original clock signal generated by an original clock;

[0010] a scrambling enable generator configured to generate an enable signal according to an original clock signal and a pseudo-random number; and

[0011] The final output clock is configured to output the original clock signal as the final clock signal according to the enable signal.

[0012] Optionally, in the scrambled clock generating circuit, the pseudo-random number generator generates a pseudo-random number according to the original clock signal, including:

[0013] The pseudo-random number generator generates a serial pseudo-random binary sequence, and within a period length of the pseudo-random binary sequence 2^31-1, 0 and 1 appear randomly.

[0014] Optionally, in the scrambled clock generating circuit, the pseudo-random number generator is based on the PRBS31=X31+X28+1 code type, and the pseudo-random number generator includes 32 delay units, and the delay unit includes a D flip-flop;

[0015] The output signal of the first delay unit, the output signal of the 29th delay unit and the output signal of the 32nd delay unit generate a pseudo-random binary sequence through two XOR gates;

[0016] The pseudo-random binary sequence is fed back to the input of the first delay unit for cyclic shifting.

[0017] Optionally, in the scrambled clock generating circuit, the original clock signal is generated by a phase-locked loop or a crystal oscillator, and one clock cycle of the original clock signal includes a high-level valid time and a low-level valid time, and the high-level valid time accounts for 50% of the entire clock cycle.

[0018] Optionally, in the scrambled clock generating circuit, the scramble enable generator includes:

[0019] The counter is configured to generate a count value and determine whether the count value is equal to a set value, and if so, output a count signal equal to 1, otherwise, output a count signal equal to 0;

[0020] The AND gate circuit is configured to perform an AND operation on the counting signal and the pseudo-random number to generate an enable signal. If the counting signal and the pseudo-random number are both 1, the enable signal is 1, otherwise the enable signal is 0.

[0021] Optionally, in the scrambled clock generating circuit, the scramble enable generator includes a first scrambling circuit, and the first scrambling circuit includes:

[0022] The modulo-2 counter is configured to perform a jump upon encountering a rising edge of the original clock signal to output a first sequence signal of 0 and 1 that alternately appears in a cycle, and when the first sequence signal is equal to 1, the counting signal is 1, otherwise the counting signal is 0;

[0023] The first AND gate is configured to perform an AND operation on the counting signal generated by the modulo-2 counter and the pseudo-random number.

[0024] Optionally, in the scrambled clock generating circuit, the scramble enable generator further includes a second scrambling circuit, and the second scrambling circuit includes:

[0025] The modulo-4 counter is configured to perform a jump upon encountering a rising edge of the original clock signal, so as to output a second sequence signal of 0, 1, 2, and 3 that appears in an alternating cycle;

[0026] The judgment circuit is configured to make the counting signal 1 when it is detected that the second sequence signal is equal to 3, and make the counting signal 0 otherwise;

[0027] The second AND gate is configured to perform an AND operation on the counting signal generated by the judgment circuit and the pseudo-random number.

[0028] Optionally, the scrambled clock generating circuit further includes:

[0029] an inverter configured to invert the enable signal;

[0030] The effective high level time of the first AND gate output occupies 25% of the entire clock cycle, and the effective high level time of the second AND gate output occupies 12.5% ​​of the entire clock cycle.

[0031] Optionally, the scrambled clock generating circuit further includes:

[0032] The mode selector is configured to select the enable signal output by the first AND gate to be provided to the inverter, or to select the enable signal output by the second AND gate to be provided to the inverter.

[0033] Optionally, in the scrambled clock generating circuit, the original clock is connected to the asynchronous bus bridge, the system bus, the CPU, the DMA and the on-chip memory to provide the original clock signal to the asynchronous bus bridge, the system bus, the CPU, the DMA and the on-chip memory;

[0034] The final output clock is connected to the asynchronous bus bridge and the safety subsystem to provide the final clock signal to the asynchronous bus bridge and the safety subsystem;

[0035] The security subsystem includes an encryption and decryption module, which communicates with the system bus through an asynchronous bus bridge;

[0036] The security subsystem operates in the scrambled clock domain according to the final clock signal to enhance the ability to resist energy attacks;

[0037] The system bus, CPU, DMA and on-chip memory operate in a non-scrambled clock domain according to the original clock signal;

[0038] The asynchronous bus bridge communicates data with the scrambled clock domain based on a non-scrambled clock domain.

[0039] In the scrambled clock generating circuit provided by the present invention, a pseudo-random number generator generates a pseudo-random number according to an original clock signal, a scramble enable generator generates an enable signal according to the original clock signal and the pseudo-random number, and the final output clock outputs the original clock signal as the final clock signal according to the enable signal. The pseudo-random number generator and the scramble enable generator are both implemented by digital circuits, and the entire circuit is implemented by digital circuits, with low circuit overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic diagram of a scrambled clock generating circuit system according to an embodiment of the present invention;

[0041] Figure 2 It is a schematic diagram of the principle of a scrambled clock generating circuit according to an embodiment of the present invention;

[0042] Figure 3 2 is a schematic diagram of a scrambled clock generation circuit applied to a system on chip according to an embodiment of the present invention;

[0043] Figure 4 1 is a schematic diagram of an original clock waveform of a scrambled clock generating circuit according to an embodiment of the present invention;

[0044] Figure 5 1 is a schematic diagram of a scrambled clock waveform of a scrambled clock generating circuit according to an embodiment of the present invention;

[0045] Figure 6 1 is a waveform diagram of a first scrambling circuit of a scrambled clock generating circuit according to an embodiment of the present invention;

[0046] Figure 7 1 is a waveform diagram of a second scrambling circuit of a scrambled clock generating circuit according to an embodiment of the present invention;

[0047] As shown in the figure: 10-original clock; 20-pseudo-random number generator; 30-scrambling enable generator. DETAILED DESCRIPTION

[0048] In the present invention, each embodiment is only intended to illustrate the scheme of the present invention and should not be understood as restrictive. In the present invention, unless otherwise specified, the quantifiers "one" and "one" do not exclude the scene of multiple elements. It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a part of the parts or components may be shown, but a person of ordinary skill in the art can understand that under the teachings of the present invention, the required parts or components can be added according to the needs of the specific scene. In addition, unless otherwise specified, the features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can be used to replace the corresponding or functionally identical or similar features in the first embodiment, and the resulting embodiment also falls within the scope of disclosure or the scope of record of the present application.

[0049] The following is a further detailed description of the scrambled clock generation circuit proposed in the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0050] In addition, unless otherwise specified, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding feature in the first embodiment or a feature with the same or similar function, and the resulting embodiment also falls within the disclosure or description scope of the present application.

[0051] The core idea of ​​the present invention is to provide a novel scrambled clock generating circuit, which realizes a scrambled clock with accurately controlled performance loss overhead through a digital circuit design method.

[0052] To realize the above idea, the present invention provides a scrambled clock generating circuit, comprising: a pseudo-random number generator, configured to generate a pseudo-random number according to an original clock signal generated by an original clock; a scrambled enable generator, configured to generate an enable signal according to the original clock signal and the pseudo-random number; and a final output clock, configured to output the original clock signal as a final clock signal according to the enable signal.

[0053] The present invention provides a scrambled clock generating circuit, such as Figure 1As shown, it includes: an original clock 10, which is configured to generate an original clock signal; a pseudo-random number generator 20, which is configured to generate a pseudo-random number according to the original clock signal; a scrambling enable generator 30, which is configured to generate an enable signal according to the original clock signal and the pseudo-random number; and a final output clock (scrambled clock 60), which is configured to output the original clock signal as the final clock signal after receiving the enable signal. It should be noted that in some embodiments, the oscillation circuit that implements the original clock 10 can be separated from the scrambled clock generation circuit of the present invention. In this case, the scrambled clock generation circuit of the present invention receives the original clock signal from the outside and generates the scrambled clock 60 accordingly.

[0054] Figure 1 The scrambled clock generating circuit proposed by the present invention. The original clock 10 is used as the control clock of the pseudo-random number generator 20 to generate a random tap. The pseudo-random number generator 20 can be a commonly used PRBS7, PRBS9, PRBS15, PRSB23 or PRBS31, etc., and can be a random number generator with a fixed code type or a random number generator with a specific code type. The longer the code word, the better the random performance. In the scrambled clock generating circuit, the original clock signal is generated by a phase-locked loop or a crystal oscillator, and a clock cycle of the original clock signal includes a high level valid time and a low level valid time, and the high level valid time occupies about 50% of the entire clock cycle.

[0055] In one embodiment of the present invention, in the scrambled clock generating circuit, the pseudo-random number generator 20 generates a pseudo-random number according to the original clock signal, including: the pseudo-random number generator 20 generates a serial pseudo-random binary sequence, and 0 and 1 appear randomly within the period length of the pseudo-random binary sequence 2^31-1.

[0056] In one embodiment of the present invention, in the scrambled clock generating circuit, as Figure 2 As shown, the pseudo-random number generator 20 is based on the PRBS31=X31+X28+1 code type, and the pseudo-random number generator 20 includes 32 delay units, and the delay unit includes a D flip-flop; the output signal of the first delay unit, the output signal of the 29th delay unit and the output signal of the 32nd delay unit are used to generate a pseudo-random binary sequence through two XOR gates; the pseudo-random binary sequence is fed back to the input end of the first delay unit for cyclic shifting.

[0057] A pseudo-random binary sequence (PRBS) is a pseudo-random sequence that contains only 0 and 1. If a sequence can be predetermined, produced and reproduced repeatedly, and has the random characteristics (i.e., statistical characteristics) of a certain random sequence, then this sequence is called a pseudo-random sequence. The difference between a pseudo-random signal and a random signal is that a random signal is unpredictable, but the value of a random signal in the future can only be described in a statistical sense; a pseudo-random sequence is not random in essence, but a deterministic periodic signal known to both the sender and the receiver. It is called a pseudo-random sequence because it exhibits the statistical characteristics of a white noise sampling sequence, and looks like a real random sequence to a listener who does not know how it is generated. The theoretical development of pseudo-random binary sequences is relatively mature. The implementation is relatively simple, and an n-stage shift register can be used to generate a 2-bit random signal. n-1 M sequence. In different applications, there are different requirements for the period length of the random sequence generated by the linear feedback shift register. As m increases, the consumption of the internal logic resources of the FPGA by the linear feedback shift register increases linearly, while the longest sequence period output by the linear feedback shift register increases exponentially, which is very beneficial for practical applications. When m = 63. The period of the maximum length sequence can reach 9.22337×10^18. If the CLK frequency is 50MHz, the repetition period exceeds 5800 years. In most practical applications, such a sequence length is very sufficient.

[0058] In one embodiment of the present invention, in the scrambled clock generating circuit, the scrambled enable generator 30 includes: a counter, configured to generate a count value, and determine whether the count value is equal to a set value, if so, output a count signal equal to 1, otherwise output a count signal equal to 0; and an AND gate circuit, configured to perform an AND operation on the count signal and a pseudo-random number to generate an enable signal, if the count signal and the pseudo-random number are both 1, the enable signal is 1, otherwise the enable signal is 0.

[0059] In one embodiment of the present invention, in the scrambled clock generating circuit, the scramble enable generator 30 includes a first scramble circuit 302, and the first scramble circuit 302 includes: a modulo 2 counter 320, which is configured to perform a jump when encountering a rising edge of the original clock signal to output a first sequence signal in which 0 and 1 appear alternately and cyclically, and when the first sequence signal is equal to 1, the counting signal is 1, otherwise the counting signal is 0; a first AND gate 322, which is configured to perform an AND operation on the counting signal generated by the modulo 2 counter and the pseudo-random number.

[0060] In one embodiment of the present invention, in the scrambled clock generating circuit, the scramble enable generator 30 further includes a second scrambling circuit 303, wherein the second scrambling circuit includes: a modulo-4 counter 330, configured to perform a jump upon encountering a rising edge of the original clock signal to output a second sequence signal of 0, 1, 2, and 3 that appears alternately and cyclically; a judgment circuit 331, configured to make the counting signal 1 when detecting that the second sequence signal is equal to 3, otherwise the counting signal is 0; and a second AND gate 332, configured to perform an AND operation on the counting signal generated by the judgment circuit and a pseudo-random number.

[0061] The scrambling enable generator 30 is a low hardware overhead circuit based on a counter. For example, the scrambling enable generator can be a 2-bit counter, which counts in a cycle of 0->1->2->3->0->1->2->3->1... When the counter jumps to 3, the output tap of the pseudo-random generator can be used as the enable of the gated clock unit 50. In theory, the output tap of the pseudo-random number generator 20 is a random 0 or 1, but the probability of 0 or 1 occurring is 50%. When the 2-bit counter jumps to 3 to select the output tap, the probability of high-level pulse enable is 1 / 4*50%=12.5%. The high-level pulse enable is negated, which is equivalent to controlling the gating of the original clock 10 with an enable probability of 87.5% to generate a scrambled clock 60; the performance of the scrambled clock 60 is about 87.5% of the original clock 10, that is, a performance overhead of 12.5%. If a 1-bit counter is used, the performance of the generated scrambled clock is about 75% of the original clock, that is, a performance overhead of 25%. The performance overhead of the scrambled clock can be controlled by using different counters. The software can generate a variety of different scrambled clocks through the mode control terminal.

[0062] In one embodiment of the present invention, the scrambled clock generating circuit further includes: an inverter 305 configured to invert the enable signal; the high level valid time of the first AND gate output occupies 25% of the entire clock cycle, and the high level valid time of the second AND gate output occupies 12.5% ​​of the entire clock cycle.

[0063] In one embodiment of the present invention, the scrambled clock generating circuit further includes: a mode selector 304, configured to select the enable signal output by the first AND gate to be provided to the inverter 305, or to select the enable signal output by the second AND gate to be provided to the inverter 305. The scramble enable generator 30 may include only the first scramble circuit 302, or only the second scramble circuit 303, or both the first scramble circuit 302 and the second scramble circuit 303 and select one of the two to function according to the mode selector 304.

[0064] In one embodiment of the present invention, Figure 3 As shown, in the scrambled clock generating circuit, the original clock 10 is connected to the asynchronous bus bridge 200, the system bus 300, the CPU, the DMA and the on-chip memory to provide the original clock signal to the asynchronous bus bridge 200, the system bus 300, the CPU, the DMA and the on-chip memory; the final output clock (scrambled clock 60) is connected to the asynchronous bus bridge 200 and the security subsystem 100 to provide the final clock signal to the asynchronous bus bridge 200 and the security subsystem 100; the security subsystem 100 includes an encryption and decryption module, which communicates with the system bus 300 through the asynchronous bus bridge 200; the security subsystem 100 operates in the scrambled clock domain according to the final clock signal to enhance the ability to resist energy attacks; the system bus 300, the CPU, the DMA and the on-chip memory operate in the non-scrambled clock domain according to the original clock signal; the asynchronous bus bridge 200 performs data communication according to the non-scrambled clock domain and the scrambled clock domain.

[0065] In the scrambled clock generating circuit provided by the present invention, a pseudo-random number generator 20 generates a pseudo-random number according to an original clock signal, a scramble enable generator 30 generates an enable signal according to the original clock signal and the pseudo-random number, and the final output clock outputs the original clock signal as the final clock signal according to the enable signal (for example, at the moment of the high level of the enable signal, or vice versa, this operation can be achieved by, for example, performing an AND operation (AND) on the enable signal and the original clock signal). The pseudo-random number generator 20 and the scramble enable generator 30 are both implemented by digital circuits. The entire circuit is implemented by digital circuits, the circuit overhead is small, and the performance overhead caused by clock scrambling can be accurately controlled (such as 12.5%, 25% or other values).

[0066] RAW_CLK is the original clock generated by a phase-locked loop or a crystal oscillator, and is generally an ideal clock signal. Each original clock cycle includes a high-level effective time and a low-level effective time. The proportion of the high-level effective time in the entire clock cycle is called the duty cycle. Figure 4 The duty cycle is close to 50%.

[0067] like Figure 5 As shown in Figure 1, Swallow_CLK is the final output clock after being processed by the clock scrambling circuit. It can be found that high-level pulses will be randomly discarded: the discarding time is random, the format of the continuously discarded pulses is random, but the total discarded ratio is controllable.

[0068] Figure 2It is an example of a pseudo-random number generator, and is a pseudo-random number generator based on the PRBS31=X31+X28+1 code. PRBS, or Pseudo-Random Binary Sequence, is a pseudo-random binary sequence. In this code stream, 0 and 1 appear randomly within a period length of 2^31-1.

[0069] The pseudo-random number generator 20 includes 32 delay units X0, X1, ... X30, X31; for example, 211X15 is the 16th delay unit. In the present invention, the delay unit is a simple D flip-flop to achieve a delay of a RAW_CLK cycle. 212 is the output tap of the first delay unit X0; 213 is the output tap of the delay unit X28; 214 is the output tap of the delay unit X31; the three taps 212, 213, and 214 generate 217 through two XOR gates 215 and 216, so 217 is the output of the code generator PRBS31 = X31 + X28 + 1. 217 will be fed back to the input end of X0 to achieve cyclic shift. The probability of 0 and 1 appearing on 217 is 50%.

[0070] like Figure 2 , 6 As shown, the first scrambling circuit 302 is implemented based on a modulo-2 counter 320. 320 is a modulo-2 counter working on RAW_CLK. 324 is actually a 0->1->0->1->0->1->... sequence based on the rising edge of the RAW_CLK clock. Through the AND gates 322, 324 and 217, a logic "AND" operation is performed to generate an enable control model 325. In terms of probability, the time when the high level appears on the 325 signal occupies 25% of the total time.

[0071] like Figure 2 , 7 As shown, the second scrambling circuit 303 is implemented based on a modulo-4 counter 330. 330 is a modulo-4 counter working on RAW_CLK. 333 is actually a 0->1->2->3->0->1->2->3->0->1->2->3... cycle sequence based on the rising edge of the RAW_CLK clock. 331 is a judgment circuit. Only when 333 is "3", 334 outputs "1", otherwise it outputs "0". Therefore, the proportion of time when a high level appears on 334 is 25%. Through the AND gate 332, 334 and 217 perform a logical "AND" operation to generate an enable control model 335. Since the probability of 0 and 1 appearing on 217 at any time is 50% each, 335 randomly removes the high level pulse on 334 with a probability of 50%, such as Figure 7 As shown, the second pulse of 334 is swallowed up. Therefore, the proportion of time when 335 is high is 12.5%.

[0072] 304 is a two-choice selection circuit. When the mode control terminal is 1, 325 is selected, otherwise 335 is selected. Through 305, we invert the output of 304. Therefore, when the mode control terminal is 1, the high level time ratio on 306 is 75%; otherwise, the high level time ratio is 87.5%. 50 is a gated clock unit. By controlling the original RAW_CLK through 306, the final scrambled clock can be generated.

[0073] In summary, the above embodiments describe in detail different configurations of the scrambled clock generating circuit. Of course, the present invention includes but is not limited to the configurations listed in the above embodiments. Any content that is transformed based on the configurations provided in the above embodiments belongs to the scope of protection of the present invention. Those skilled in the art can draw inferences based on the contents of the above embodiments.

[0074] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0075] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A scrambled clock generating circuit, characterized in that: include: a pseudo-random number generator configured to generate a pseudo-random number based on an original clock signal generated by an original clock; A scrambling enable generator, configured to generate an enable signal according to an original clock signal and a pseudo-random number; as well as The final output clock is configured to output the original clock signal as the final clock signal according to the enable signal. The pseudo-random number generator is based on a PRBS31=X31+X28+1 pattern, and includes 32 delay units, each of which includes a D flip-flop; The output signal of the first delay unit, the output signal of the 29th delay unit and the output signal of the 32nd delay unit generate a pseudo-random binary sequence through two XOR gates; The pseudo-random binary sequence is fed back to the input of the first delay unit for cyclic shifting. The scrambling enable generator comprises: The counter is configured to generate a count value and determine whether the count value is equal to a set value, and if so, output a count signal equal to 1, otherwise, output a count signal equal to 0; The AND gate circuit is configured to perform an AND operation on the counting signal and the pseudo-random number to generate an enable signal. If the counting signal and the pseudo-random number are both 1, the enable signal is 1, otherwise the enable signal is 0.

2. The scrambled clock generating circuit according to claim 1, wherein: The pseudo-random number generator generates pseudo-random numbers according to the original clock signal including: The pseudo-random number generator generates a serial pseudo-random binary sequence, and within a period length of the pseudo-random binary sequence 2^31-1, 0 and 1 appear randomly.

3. The scrambled clock generating circuit according to claim 1, wherein: The original clock signal is generated by a phase-locked loop or a crystal oscillator. One clock cycle of the original clock signal includes a high-level effective time and a low-level effective time, and the high-level effective time accounts for 50% of the entire clock cycle.

4. The scrambled clock generating circuit according to claim 1, wherein: The scrambling enable generator includes a first scrambling circuit, wherein the first scrambling circuit includes: The modulo-2 counter is configured to perform a jump upon encountering a rising edge of the original clock signal to output a first sequence signal of 0 and 1 that alternately appears in a cycle, and when the first sequence signal is equal to 1, the counting signal is 1, otherwise the counting signal is 0; The first AND gate is configured to perform an AND operation on the counting signal generated by the modulo-2 counter and the pseudo-random number.

5. The scrambled clock generating circuit as claimed in claim 4, characterized in that: The scrambling enable generator further includes a second scrambling circuit, wherein the second scrambling circuit includes: The modulo-4 counter is configured to perform a jump upon encountering a rising edge of the original clock signal, so as to output a second sequence signal of 0, 1, 2, and 3 that appears in an alternating cycle; The judgment circuit is configured to make the counting signal 1 when it is detected that the second sequence signal is equal to 3, and make the counting signal 0 otherwise; The second AND gate is configured to perform an AND operation on the counting signal generated by the judgment circuit and the pseudo-random number.

6. The scrambled clock generating circuit according to claim 5, characterized in that: Also includes: an inverter configured to invert the enable signal; The effective high level time of the first AND gate output occupies 25% of the entire clock cycle, and the effective high level time of the second AND gate output occupies 12.5% ​​of the entire clock cycle.

7. The scrambled clock generating circuit according to claim 6, characterized in that: Also includes: The mode selector is configured to select the enable signal output by the first AND gate to be provided to the inverter, or to select the enable signal output by the second AND gate to be provided to the inverter.

8. The scrambled clock generating circuit according to claim 1, characterized in that: The original clock is connected to the asynchronous bus bridge, the system bus, the CPU, the DMA and the on-chip memory to provide the original clock signal to the asynchronous bus bridge, the system bus, the CPU, the DMA and the on-chip memory; The final output clock is connected to the asynchronous bus bridge and the safety subsystem to provide the final clock signal to the asynchronous bus bridge and the safety subsystem; The security subsystem includes an encryption and decryption module, which communicates with the system bus through an asynchronous bus bridge; The security subsystem operates in the scrambled clock domain according to the final clock signal to enhance the ability to resist energy attacks; The system bus, CPU, DMA and on-chip memory operate in a non-scrambled clock domain according to the original clock signal; The asynchronous bus bridge communicates data with the scrambled clock domain based on a non-scrambled clock domain.

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