comparator circuit, constant current control circuit, and constant current drive circuit

Abstract

The application discloses a comparator circuit, a constant current control circuit and a constant current drive circuit. The comparator circuit comprises a comparator, a selection circuit, a storage circuit and an output holding circuit. The comparator circuit controls the selection circuit, the storage circuit and the output holding circuit to periodically switch a storage stage and a comparison stage of the circuit according to a clock signal, stores a sum of one input signal and an offset voltage of the comparator as a first voltage at a second input end of the comparator in the storage stage, and compares another signal and the sum of the offset voltage of the comparator as a second voltage with the first voltage in the comparison stage, so that the influence of the offset voltage of the comparator on the output result of the comparator can be offset, and therefore the problem caused by mismatch can be well solved, and the consistency of the output is obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of LED driving circuit, more particularly, to a comparator circuit, constant current control circuit and constant current driving circuit. BACKGROUND

[0002] When LED is used for lighting, constant current driving circuit is used to adjust the brightness to meet the individual needs of users or to dim according to the environmental needs to reduce energy consumption. The constant current driving circuit is, for example, a conventional Pulse Width Modulation (PWM) dimmer or 0-10V dimmer. The dimmable LED driving circuit usually changes the output current according to the dimming signal to achieve the dimming function. When the dimming signal is less than a certain value, the output current is turned off by the off signal generated by the comparator circuit.

[0003] Figure 1 A schematic circuit diagram of a conventional comparator is shown. Referring to Figure 1 In the conventional comparator, MOS transistor N1 and N2 are used as input pair transistors, MOS transistor N3 receives bias voltage Vibias and is used to provide bias current to MOS transistors N1 and N2 according to bias voltage Vibias, MOS transistors P1, P2, P3, P4, N4 and N5 are used as intermediate stage current mirror to make the output current Icomp of the comparator = Gm*(VP-VN), Icomp is the output current of the comparator, Gm is the transconductance, VP is the input signal of the positive input terminal of the comparator, and VN is the input signal of the negative input terminal of the comparator circuit. The size of the transconductance Gm is related to the size of the MOS transistors N1 and N2 as input pair transistors and the ratio of the mirror current transfer of the intermediate stage current mirror.

[0004] The mismatch of the comparator will cause the actual value of the control to deviate from the target value. In the LED driving circuit, especially the dimmable LED driving circuit, in order to ensure the consistency of the circuit, it is required to accurately make the transconductance of the circuit and to reduce the mismatch of the circuit as much as possible. However, due to the deviation in the process manufacturing process and the packaging stress, the designed symmetrical input pair transistors and the mirror current ratio will be mismatched, resulting in that the actual transconductance of the circuit is no longer accurate and the mismatch of the circuit is significantly increased. In order to reduce this mismatch, it is generally required to make all the elements that will cause the mismatch as symmetrical as possible, including the central symmetry of the layout, and to increase the size of the symmetrical elements, but this will result in the need for larger chip area and increased matching cost. In addition, even if these measures are taken, the problems caused by the mismatch cannot be well solved, especially the mismatch is affected by the packaging stress, and the effect of increasing the size of the symmetrical elements is not obvious. SUMMARY

[0005] The technical problem solved by the present application is to provide a comparator circuit, a constant current control circuit and a constant current drive circuit, which can solve the existing comparator imbalance caused by packaging stress and device matching, and can significantly improve the consistency of the output.

[0006] According to a first aspect of the embodiments of the present application, a comparator circuit is provided, comprising: a comparator comprising a first input end, a second input end and an output end; a selection circuit configured to provide a first input signal or a second input signal to the first input end of the comparator according to a clock signal, wherein the second input signal is provided to the first input end of the comparator in a storage phase of each clock cycle of the clock signal, and the first input signal is provided to the first input end of the comparator in a comparison phase of each clock cycle of the clock signal; a storage circuit connected to the second input end and the output end of the comparator, wherein the storage circuit is configured to provide, as a first voltage, a sum of the second input signal of a current cycle and an offset voltage of the comparator to the second input end of the comparator in the storage phase, and the comparator is configured to provide, as a second voltage, the first input signal and the sum of the offset voltage, and compare the first voltage with the second voltage to obtain a comparison result in the comparison phase; and an output holding circuit connected to the output end of the comparator, wherein the output holding circuit is configured to store the comparison result in the comparison phase, and output the comparison result stored in the comparison phase by the output holding circuit as an output signal in a storage phase of a next clock cycle.

[0007] Optionally, the comparator circuit further comprises a clock signal generator configured to generate the clock signal, wherein the clock signal comprises a periodic first clock signal and a second clock signal, the first clock signal and the second clock signal are inverse to each other, and the comparator circuit is in the storage phase when the second clock signal is active, and the comparator circuit is in the comparison phase when the first clock signal is active.

[0008] Optionally, the selection circuit comprises: a first switch having a first end configured to receive the first input signal, a second end connected to the first input end of the comparator, and a control end configured to receive the first clock signal; and a second switch having a first end configured to receive the second input signal, a second end connected to the first input end of the comparator, and a control end configured to receive the second clock signal, wherein the second switch is turned on to provide the second input signal to the first input end of the comparator when the second clock signal is active, and the first switch is turned on to provide the first input signal to the first input end of the comparator when the first clock signal is active.

[0009] Optionally, the storage circuit comprises: a fourth switch, a first end of which is connected to an output end of the comparator, a control end of which receives the second clock signal; a transistor, a first end of which is connected to a power supply voltage, a control end of which is connected to a second end of the fourth switch; a resistor, a first end of which is connected to a second end of the transistor, a second end of which is grounded; a capacitor, a first end of which is connected to a second input end of the comparator, a second end of which is grounded; and a fifth switch, a first end of which is connected to the first end of the capacitor, a second end of which is connected to the first end of the resistor, a control end of which receives the second clock signal.

[0010] Optionally, when the second clock signal is valid, the fourth switch and the fifth switch are turned on, and the first voltage is stored on the capacitor; when the first clock signal is valid, the fourth switch and the fifth switch are turned off, and the comparator compares the second voltage of the first input end with the first voltage stored on the capacitor to obtain a comparison result.

[0011] Optionally, the output holding circuit comprises: a third switch, a first end of which is connected to an output end of the comparator, a control end of which receives the first clock signal; a first inverter, an input end of which is connected to a second end of the third switch, an output end of which is connected to a first node; a sixth switch, a first end of which is connected to the second end of the third switch, a control end of which receives the second clock signal; a second inverter, an input end of which is connected to the first node, an output end of which is connected to a second end of the sixth switch; a seventh switch, a first end of which is connected to the first node, a control end of which receives the second clock signal; a third inverter, an input end of which is connected to a second end of the seventh switch, an output end of which is used for outputting the output signal; and an eighth switch, a first end of which is connected to an input end of the third inverter, a second end of which is connected to an output end of the third inverter, a control end of which receives the first clock signal.

[0012] Optionally, when the first clock signal is valid, the third switch and the eighth switch are turned on, the sixth switch and the seventh switch are turned off, and the comparison result is stored on the first node; when the second clock signal is valid, the third switch and the eighth switch are turned off, the sixth switch and the seventh switch are turned on, and the third inverter obtains the output signal according to the comparison result stored on the first node.

[0013] Optionally, duty cycles of the first clock signal and the second clock signal are 0.5.

[0014] According to a second aspect of the embodiments of the present application, a constant current control circuit is provided, comprising: a transconductance amplifier configured to perform error amplification on a dimming signal and an output equivalent current to obtain a compensation signal; a PWM signal generation circuit connected to the transconductance amplifier to receive the compensation signal and configured to generate a PWM signal according to the compensation signal; a logic control circuit connected to the PWM signal generation circuit to receive the PWM signal and configured to generate a pre-drive signal according to the PWM signal; a drive circuit connected to the logic control circuit to receive the pre-drive signal and configured to generate a drive signal according to the pre-drive signal, the drive signal being configured to control the turn-on and turn-off of a power switch tube to control the stability of an output current; and the above-mentioned comparator circuit, the comparator circuit being connected to the logic control circuit, and the comparator circuit being configured to provide an off signal to turn off the output current when the dimming signal is less than a preset voltage.

[0015] Optionally, the constant current control circuit further comprises: a peak current sampling circuit configured to receive a voltage sampling signal representing a current flowing through the power switch tube; and an output equivalent current calculation circuit configured to obtain the output equivalent current signal according to the voltage sampling signal.

[0016] According to a third aspect of the embodiments of the present application, a constant current drive circuit is provided, comprising: a main power circuit configured to convert an input voltage into an output current; and the above-mentioned constant current control circuit, the constant current control circuit being configured to control the main power circuit to convert the input voltage into the output current.

[0017] Optionally, the main power circuit is any one of a Buck type power circuit, a flyback type power circuit, a Buck-boost type power circuit, and a Boost type power circuit.

[0018] The comparator circuit, the constant current control circuit, and the constant current drive circuit of the present application comprise a selection circuit, a comparator, a storage circuit, and an output holding circuit. The comparator circuit controls the selection circuit, the storage circuit, and the output holding circuit to periodically switch between a storage phase and a comparison phase according to a clock signal, stores a sum of one input signal and an offset voltage as a first voltage at a second input terminal of the comparator in the storage phase, and compares another signal and the offset voltage as a second voltage with the first voltage in the comparison phase, so that the influence of the offset voltage of the comparator on the output result can be offset, and thus the problem caused by mismatch can be well solved, and the consistency of the output can be significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings.

[0020] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings.Figure 1 A schematic circuit block diagram of a conventional comparator is shown;

[0021] Figure 2 A schematic circuit block diagram of a comparator circuit according to the present invention is shown.

[0022] Figure 3 A waveform diagram of the clock signal according to the present invention is shown;

[0023] Figure 4 A schematic circuit block diagram of a constant current drive circuit according to the present invention is shown. Detailed Implementation

[0024] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0025] Figure 2 A schematic circuit block diagram of a comparator circuit according to the present invention is shown. Figure 3 As shown, the comparator circuit 200 includes a selection circuit 201, a comparator 202, a storage circuit 203, and an output hold circuit 204. The selection circuit 201 is connected to the first input terminal of the comparator 202. The selection circuit 201 is used to periodically switch between a first input signal VP and a second input signal VN according to a clock signal, so as to provide either the first input signal VP or the second input signal VN to the first input terminal of the comparator 202. During the storage phase of each clock cycle of the clock signal, the second input signal VN is provided to the first input terminal of the comparator 202. The storage circuit 203 is connected to the second input terminal and the output terminal of the comparator 202. During the storage phase of each clock cycle, the storage circuit 203 stores the sum of the second input signal VN of the current cycle and the offset voltage of the comparator 202 as a first voltage. The output holding circuit 204 is connected to the output of the comparator 202. The output holding circuit 204 is used to store the comparison result output by the comparator 202 during the comparison phase of each clock cycle, and to output the comparison result as the output signal VA during the storage phase of the next clock cycle. The first input terminal of the comparator 202 receives the first input signal VP during the comparison phase, and uses the sum of the first input signal VP and the offset voltage of the comparator 202 as the second voltage. The comparison result is obtained by the comparator 202 comparing the first voltage with the second voltage during the comparison phase.

[0026] Further, the clock signals include a first clock signal CL0 and a second clock signal CH0. The working states of the selection circuit 201, the storage circuit 203 and the output holding circuit 204 are controlled by the first clock signal CL0 and the second clock signal CH0, and the first clock signal CL0 and the second clock signal CH0 are periodic and non-overlapping signals.

[0027] Further, the comparator circuit 200 further includes a clock signal generator 205, and the first clock signal CL0 and the second clock signal CH0 can be generated by the clock signal generator 205. The first clock signal CL0 and the second clock signal CH0 are periodic, opposite to each other and non-overlapping. The clock signal generator 205 can be implemented by any appropriate structure in the prior art. Preferably, the first clock signal CL0 and the second clock signal CH0 can be square wave signals with a duty cycle of 0.5.

[0028] Further, the selection circuit includes a first switch S1 and a second switch S2. The first end of the first switch S1 receives the first input signal VP, the second end of the first switch S1 is connected to the first input end of the comparator 202, and the control end of the first switch S1 receives the first clock signal CL0. The first end of the second switch S2 receives the second input signal VN, the second end of the second switch S2 is connected to the first input end of the comparator 202, and the control end of the second switch S2 receives the second clock signal CH0.

[0029] The storage circuit 203 includes a fourth switch S4, a fifth switch S5, a transistor M2, a resistor R1 and a capacitor C3. The first end of the fourth switch S4 is connected to the output end of the comparator 202, the second end of the fourth switch S4 is connected to the control end of the transistor M2, and the control end of the fourth switch S4 receives the second clock signal CH0. The first end of the transistor M2 is connected to the power supply voltage VDD, the second end of the transistor M2 is connected to the first end of the resistor R1, and the second end of the resistor R1 is grounded. The first end of the capacitor C3 is connected to the second input end of the comparator 202, and the second end of the capacitor C3 is grounded. The first end of the fifth switch S5 is connected to the first end of the capacitor C3, the second end of the fifth switch S5 is connected to the first end of the resistor R1, and the control end of the fifth switch S5 receives the second clock signal CH0.

[0030] The output holding circuit 204 comprises a third switch S3, a sixth switch S6, a seventh switch S7, an eighth switch S8, and a first to third inverters INV1-INV3. The first end of the third switch S3 is connected to the output end of the comparator 202, the second end of the third switch S3 is connected to the input end of the first inverter INV1, and the control end of the third switch S3 receives the first clock signal CL0. The output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and the first end of the seventh switch S7 at the first node A. The first end of the sixth switch S6 is connected to the second end of the third switch S3, the second end of the sixth switch S6 is connected to the output end of the second inverter INV2, and the control end of the sixth switch S6 receives the second clock signal CH0. The second end of the seventh switch S7 is connected to the input end of the third inverter INV3, and the control end of the seventh switch S7 receives the second clock signal CH0. The first end of the eighth switch S8 is connected to the input end of the third inverter INV3, the second end of the eighth switch S8 is connected to the output end of the third inverter INV3, and the control end of the eighth switch S8 receives the first clock signal CL0. The output end of the third inverter INV3 is used to provide the output signal VA.

[0031] Figure 3 The waveform diagram of the clock signal according to the present application is shown. As a non-limiting example, when the first clock signal CL0 is at logic low level and the second clock signal CH0 is at logic high level (i.e. the second clock signal CH0 is active), it is the storage phase of the clock cycle (the storage phase of the comparator circuit 200), the first switch S1, the third switch S3 and the eighth switch S8 are off, and the second switch S2, the fourth switch S4, the fifth switch S5, the sixth switch S6 and the seventh switch S7 are on. At this time, the circuit works in the storage phase, the first input end of the comparator 202 receives the second input signal VN, and the whole system is equivalent to a LDO (low dropout regulator), and the sum of the second input signal VN and the offset voltage of the comparator 202 is stored as the first voltage on the capacitor C3. At the same time, the third inverter INV3 obtains the output signal VA according to the comparison result of the comparison phase of the previous clock cycle stored on the first node A.

[0032] When the first clock signal CL0 is at a logic high level and the second clock signal CH0 is at a logic low level (i.e. when the first clock signal CL0 is active), the first clock period is a comparison phase (the comparison phase of the comparator circuit 200), the first switch S1, the third switch S3 and the eighth switch S8 are turned on, and the second switch S2, the fourth switch S4, the fifth switch S5, the sixth switch S6 and the seventh switch S7 are turned off. At this time, the circuit operates in the comparison phase, the first input of the comparator 202 receives the first input signal VP, the comparator 202 compares the sum of the first input signal VP on the first input and the offset voltage of the comparator 202 as the second voltage with the first voltage stored on the capacitor C3, and stores the comparison result to the first node A through the third switch S3 and the first inverter INV1. The output signal VA is obtained according to the comparison result stored on the first node A in the next clock period, which can effectively prevent the abnormal output of the comparator circuit 200 caused by the glitch voltage of the switch.

[0033] Figure 4 A schematic circuit block diagram of a constant current driving circuit according to the present application is shown. The constant current driving circuit adopts a flyback topology, and comprises a main power circuit and a constant current control circuit 300. The main power circuit comprises a transformer T1, a resistor R2, a capacitor C1, a power switch M1, a rectifier diode D1, a sampling resistor Rcs, a freewheeling diode D2 and an output capacitor C2. The same name end of a primary winding L1 of the transformer T1 receives an input voltage Vin, a first end of the capacitor C1 is connected to the same name end of the primary winding L1, a second end of the capacitor C1 is connected to the cathode of the rectifier diode D1, and the anode of the rectifier diode D1 is connected to the different name end of the primary winding L1. The resistor R2 is connected in parallel between the two ends of the capacitor C1. The different name end of a secondary winding L2 of the transformer T1 is connected to the anode of the freewheeling diode D2, and the same name end of the secondary winding L2 is connected to the secondary ground. The drain of the power switch M1 is connected to the different name end of the primary winding L1, the gate of the power switch M1 is connected to the output of the constant current control circuit 300 to receive a driving signal GT, the first end of the sampling resistor Rcs is connected to the source of the power switch M1 and the sampling input of the constant current control circuit 300 to provide a voltage sampling signal Vcs representing the current flowing through the power switch M1, and the second end of the sampling resistor Rcs is connected to the primary ground. The first end of the output capacitor C2 is connected to the cathode of the freewheeling diode D2, the second end of the output capacitor C2 is connected to the secondary ground, and a load is connected in parallel between the two ends of the output capacitor C2. The two ends of the output capacitor C2 provide an output voltage Vout to supply power to the load. The load is, for example, an LED load. It should be noted that "ground" herein refers to connection to a conventional ground, not floating ground.

[0034] The constant current control circuit 300 generates a driving signal GT according to the dimming signal Vtrac and the voltage sampling signal Vcs, and controls the on and off of the power switch tube M1 according to the driving signal GT, so as to control the output current, thereby dimming the LED load.

[0035] Further, the constant current control circuit 300 comprises a transconductance amplifier 301, a PWM signal generation circuit 302, a logic control circuit 303, a driving circuit 304, an output equivalent current calculation circuit 305, a peak current sampling circuit 306 and a comparator circuit 307. The peak current sampling circuit 306 is used to obtain the peak value of the voltage sampling signal Vcs representing the current flowing through the power switch tube M1 at both ends of the sampling resistor Rcs when the power switch tube M1 is turned on. The output equivalent current calculation circuit 305 calculates the output equivalent current signal according to the peak value of the voltage sampling signal Vcs on the sampling resistor Rcs. The transconductance amplifier 301 performs error amplification on the equivalent current signal and the dimming signal Vtrac to generate a compensation signal Vcomp for controlling the stability of the loop. The PWM signal generation circuit 302 receives the compensation signal Vcomp and generates a PWM signal according to the compensation signal Vcomp, and the duty cycle of the PWM signal is adjusted by the compensation signal Vcomp. The logic control circuit 303 generates a pre-driving signal GT1 according to the PWM signal, and the driving circuit 304 generates a driving signal GT to the power switch tube M1 according to the pre-driving signal GT1. The comparator circuit 307 is used to output an off signal to the logic control circuit 303 to turn off the output current when the dimming signal Vtrac is less than a certain value.

[0036] The dimming signal Vtrac is an analog dimming signal or a PWM dimming signal, for example, generated by a pulse width modulation (PWM) dimming device or a 0-10V dimmer.

[0037] Figure 4 The structure of the comparator circuit 307 in the constant current driving circuit 300 is the structure of the comparator circuit 200 shown in Figure 2 The application scenarios of the present application are illustrated by taking the constant current driving circuit shown in Figure 4 , but are not limited thereto. The comparator circuit of the present application can be applied to any scene requiring a comparator circuit.

[0038] The comparator circuit of the present application controls the selection circuit, the storage circuit and the output holding circuit to periodically switch the storage phase and the comparison phase of the circuit according to the clock signal, stores the sum of one input signal and the offset voltage of the comparator as the first voltage at the second input terminal of the comparator in the storage phase, and compares the sum of another signal and the offset voltage of the comparator as the second voltage with the first voltage in the comparison phase, so that the influence of the offset voltage of the comparator on the output result can be offset, and thus the problem caused by the mismatch can be well solved, and the consistency of the output is significantly improved.

[0039] Those skilled in the art should understand that, although the present application is described by taking the constant current driving circuit with the flyback topology as a specific embodiment, the constant current control circuit of the embodiment of the present application can also be used in the constant current driving circuit with other topologies, and the main power circuit can be any one of the Buck power circuit, the flyback power circuit, the Buck-boost power circuit and the Boost power circuit.

[0040] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0041] According to the embodiments of the present application as described above, these embodiments do not describe all the details, and do not limit the present application to only the specific embodiments described. Obviously, according to the above description, many modifications and changes can be made. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A comparator circuit, comprising: The application relates to a comparator circuit, comprising: a comparator, comprising a first input end, a second input end and an output end, a selection circuit, configured to provide a first input signal or a second input signal to the first input end of the comparator according to a clock signal, wherein the second input signal is provided to the first input end of the comparator during a storage phase of each clock cycle of the clock signal, and the first input signal is provided to the first input end of the comparator during a comparison phase of each clock cycle of the clock signal; a storage circuit, connected to the second input end and the output end of the comparator, wherein the storage circuit is configured to provide, as a first voltage, a sum of the second input signal of a current cycle and an offset voltage of the comparator to the second input end of the comparator during the storage phase, and the comparator is configured to provide, as a second voltage, the first input signal and the sum of the offset voltage, and compare the first voltage with the second voltage to obtain a comparison result during the comparison phase; and an output holding circuit, connected to the output end of the comparator, wherein the output holding circuit is configured to store the comparison result during the comparison phase, and output the comparison result stored by the output holding circuit during the comparison phase as an output signal during a storage phase of a next clock cycle, wherein the storage circuit comprises: a fourth switch, having a first end connected to the output end of the comparator; a transistor, having a first end connected to a power supply voltage and a control end connected to a second end of the fourth switch; a resistor, having a first end connected to a second end of the transistor and a second end grounded; a capacitor, having a first end connected to the second input end of the comparator and a second end grounded; and a fifth switch, having a first end connected to the first end of the capacitor and a second end connected to the first end of the resistor, wherein the clock signal comprises a periodic first clock signal and a second clock signal, the comparator circuit is in the storage phase when the second clock signal is active, and the comparator circuit is in the comparison phase when the first clock signal is active, and a duty cycle of the first clock signal and the second clock signal is 0.

5.

2. The comparator circuit of claim 1, wherein, The application further comprises: a clock signal generator, configured to generate the first clock signal and the second clock signal, and the first clock signal and the second clock signal are opposite to each other.

3. The comparator circuit of claim 2, wherein, The selection circuit comprises: a first switch, having a first end receiving the first input signal, a second end connected to the first input end of the comparator and a control end receiving the first clock signal; a second switch, having a first end receiving the second input signal, a second end connected to the first input end of the comparator and a control end receiving the second clock signal, wherein the second switch is turned on to provide the second input signal to the first input end of the comparator when the second clock signal is active, and the first switch is turned on to provide the first input signal to the first input end of the comparator when the first clock signal is active.

4. The comparator circuit of claim 2, wherein, The fourth switch and the fifth switch are turned on to store the first voltage on the capacitor when the second clock signal is active. When the first clock signal is valid, the fourth switch and the fifth switch are turned off, and the comparator compares the second voltage of the first input end with the first voltage stored on the capacitor to obtain a comparison result.

5. The comparator circuit of claim 2, wherein, The output holding circuit comprises: a third switch, a first end of which is connected to an output end of the comparator, and a control end of which receives the first clock signal; a first inverter, an input end of which is connected to a second end of the third switch, and an output end of which is connected to a first node; a sixth switch, a first end of which is connected to the second end of the third switch, and a control end of which receives the second clock signal; a second inverter, an input end of which is connected to the first node, and an output end of which is connected to a second end of the sixth switch; a seventh switch, a first end of which is connected to the first node, and a control end of which receives the second clock signal; a third inverter, an input end of which is connected to a second end of the seventh switch, and an output end of which is used for outputting the output signal; and an eighth switch, a first end of which is connected to the input end of the third inverter, a second end of which is connected to the output end of the third inverter, and a control end of which receives the first clock signal.

6. The comparator circuit of claim 5, wherein, When the first clock signal is valid, the third switch and the eighth switch are turned on, the sixth switch and the seventh switch are turned off, and the comparison result is stored in the first node; When the second clock signal is valid, the third switch and the eighth switch are turned off, the sixth switch and the seventh switch are turned on, and the third inverter obtains the output signal according to the comparison result stored in the first node.

7. A constant current control circuit, comprising: a transconductance amplifier for error amplifying a dimming signal and an output equivalent current to obtain a compensation signal; a PWM signal generation circuit connected to the transconductance amplifier to receive the compensation signal and generate a PWM signal according to the compensation signal; a logic control circuit connected to the PWM signal generation circuit to receive the PWM signal and generate a pre-drive signal according to the PWM signal; a drive circuit connected to the logic control circuit to receive the pre-drive signal and generate a drive signal according to the pre-drive signal, the drive signal controlling the turn-on and turn-off of a power switch tube to control the stability of an output current; and a comparator circuit according to any one of claims 1 to 6, the comparator circuit being connected to the logic control circuit, and the comparator circuit being used to provide an off signal to turn off the output current when the dimming signal is less than a preset voltage. Further comprising:

8. The constant current control circuit of claim 7, wherein, a peak current sampling circuit receiving a voltage sampling signal representing a current flowing through the power switch tube; and an output equivalent current calculation circuit obtaining the output equivalent current signal according to the voltage sampling signal.

9. A constant current drive circuit, comprising: a main power circuit for converting an input voltage into an output current; and the constant current control circuit according to claim 7 or 8, the constant current control circuit controlling the main power circuit to convert the input voltage into the output current. ​ ​ ​ 10. The constant current driving circuit according to claim 9, wherein, The main power circuit is any one of a Buck type power circuit, a flyback type power circuit, a Buck-boost type power circuit and a Boost type power circuit.

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