Improved bit flipping method for decoding LDPC codes and system therefor

Abstract

This disclosure provides an improved bit-flipping method and system for decoding received LDPC codewords. The decoding process may include estimating the bit values ​​relative to the received LDPC codeword using multiple bit nodes and check nodes. The flipping energy of a bit node can be obtained as a function of the values ​​of the check nodes connected to it. The flipping reliability of the bit node can then be determined by comparing the flipping energy with at least one flipping energy threshold. Furthermore, the flipping probability of the bit node can be determined based on the flipping reliability and a flipping rule. A flipping test can be performed based on this flipping probability, and as a result, at least one target bit node that needs to be flipped can be identified and flipped.

Description

Technical Field

[0001] This disclosure generally relates to low-density parity-check (LDPC) codes, and more specifically, to an improved bit-flipping decoding method for LDPC codes and a system for decoding received LDPC codewords using the improved bit-flipping method. Background Technology

[0002] LDPC codes are widely used due to their superior error correction capabilities. Traditionally, bit-flipping decoders and / or min-sum decoders are used to decode received LDPC codewords. For SSD applications, bit-flipping decoders are typically used first to decode received LDPC codewords due to their high speed, high throughput, and low power consumption. If the received LDPC codewords cannot be decoded by the bit-flipping decoder, a min-sum decoder, which has better error correction capabilities, can be used. However, min-sum decoders are slower (and have lower throughput) than bit-flipping decoders. Frequent use of min-sum decoders can significantly reduce overall decoding throughput.

[0003] Therefore, it is desirable to provide an improved bit-flipping method with higher error correction capability, thereby reducing the use of minimum and decoder and improving the overall decoding throughput. Summary of the Invention

[0004] According to one aspect of this disclosure, a system for decoding received LDPC codewords can be provided. The system may include at least one storage device storing executable instructions, and at least one processor communicating with the at least one storage device. When the executable instructions are executed, the at least one processor may cause the system to perform the following operations: receive an LDPC codeword via a channel, the received LDPC codeword comprising a plurality of bits; obtain a parity check matrix defining a relationship between a plurality of bit nodes and a plurality of check nodes, each bit node corresponding to one of the plurality of bits; and decode the received LDPC codeword by estimating the value of the LDPC codeword relative to the plurality of bit nodes and the plurality of check nodes during an iterative process including one or more iterations. At least one of the one or more iterations includes: determining a parity weight based on the current values ​​of the plurality of bit nodes and the parity check matrix; determining whether the parity weight is equal to zero; in response to determining that the parity weight is not equal to zero, determining one or more flipping reliability of the plurality of bit nodes, each flipping reliability representing the reliability of a flipping operation on one of the plurality of bit nodes; determining at least one target bit node that needs to be flipped among the plurality of bit nodes based on the one or more flipping reliability of the plurality of bit nodes; and flipping the at least one target bit node to update the current values ​​of the plurality of bit nodes.

[0005] In some embodiments, determining at least one target bit node to be flipped among the plurality of bit nodes may include: determining one or more flip probabilities of the plurality of bit nodes, each flip probability corresponding to one of the plurality of bit nodes; for each of the plurality of bit nodes, performing a test based on its corresponding flip probability to determine whether the bit node needs to be flipped, wherein, in the test, the bit node has a first probability equal to the flip probability of being flipped; and determining the at least one target bit node to be flipped based on the test result.

[0006] In some embodiments, determining one or more flip probabilities of the plurality of bit nodes may include: obtaining a flip rule, the flip rule including the relationship between the flip reliability and the flip probability of the same bit node; and for each of the plurality of bit nodes, determining the flip probability of the bit node based on the flip rule and the corresponding flip reliability of the bit node.

[0007] In some embodiments, determining one or more flip reliability of the plurality of bit nodes may include: determining whether the check weight is greater than a check weight threshold; and in response to determining that the check weight is greater than the check weight threshold, specifying a preset flip reliability as one or more flip reliability of the plurality of bit nodes.

[0008] In some embodiments, the channel may provide soft information including an initial probability of each of the plurality of bit nodes, and determining one or more flip reliability of the plurality of bit nodes may include: determining whether the checksum weight is greater than a checksum weight threshold; and in response to determining that the checksum weight is greater than the checksum weight threshold, determining the flip reliability of the bit node based on its initial probability for each of the plurality of bit nodes.

[0009] In some embodiments, determining one or more flip reliability of the plurality of bit nodes may include: for each of the plurality of bit nodes, determining a flip energy; obtaining at least one flip energy threshold; comparing the flip energy with the at least one flip energy threshold; and determining the flip reliability of the bit node based on the result of the comparison.

[0010] In some embodiments, for each of the plurality of bit nodes, the flip energy is a function of the value of the check node connected to the bit node.

[0011] In some embodiments, the flip energy threshold corresponding to a particular bit node may have different values ​​in different iterations.

[0012] In some embodiments, at least one flip energy threshold corresponding to a specific bit node may be determined based on at least one of the following: the index of the specific bit node, channel mismatch information between the current hard decision and the channel input hard decision, the number of check nodes connected to the specific bit node, the number of iterations, the number of target bit nodes flipped in the previous iteration, the check weight in the current iteration, or the check weight in the previous iteration.

[0013] In some embodiments, different bit nodes may correspond to different values ​​of the at least one flip energy threshold.

[0014] In some embodiments, the system can be used in a solid-state drive (SSD) controller for decoding low-density parity-check (LDPC) codewords.

[0015] According to one aspect of this disclosure, a method for decoding received LDPC codewords can be provided. The method may include one or more operations, including: receiving an LDPC codeword via a channel, the received LDPC codeword comprising a plurality of bits; obtaining a parity check matrix defining a relationship between a plurality of bit nodes and a plurality of check nodes, each bit node corresponding to one of the plurality of bits; and decoding the received LDPC codeword by estimating the values ​​of the LDPC codeword relative to the plurality of bit nodes and the plurality of check nodes during an iteration process including one or more iterations. At least one of the one or more iterations includes: determining a checksum weight based on the current values ​​of the plurality of bit nodes and the parity check matrix; determining whether the checksum weight is equal to zero; in response to determining that the checksum weight is not equal to zero, determining one or more flipping reliability of the plurality of bit nodes, each flipping reliability representing the reliability of a flipping operation on one of the plurality of bit nodes; among the plurality of bit nodes, determining at least one target bit node that needs to be flipped based on the one or more flipping reliability of the plurality of bit nodes; and flipping the at least one target bit node to update the current values ​​of the plurality of bit nodes.

[0016] According to one aspect of this disclosure, a non-transitory computer-readable medium having executable instructions for decoding received LDPC codewords can be provided. When executed by at least one processor, the executable instructions can instruct the at least one processor to perform a method comprising one or more operations, the method comprising: receiving an LDPC codeword via a channel, the received LDPC codeword comprising a plurality of bits; obtaining a parity check matrix defining a relationship between a plurality of bit nodes and a plurality of check nodes, each bit node corresponding to one of the plurality of bits; and decoding the received LDPC codeword by estimating the value of the LDPC codeword relative to the plurality of bit nodes and the plurality of check nodes during an iterative process including one or more iterations. At least one of the one or more iterations includes: determining a checksum weight based on the current values ​​of the plurality of bit nodes and the parity check matrix; determining whether the checksum weight is equal to zero; in response to determining that the checksum weight is not equal to zero, determining one or more flipping reliability of the plurality of bit nodes, each flipping reliability representing the reliability of a flipping operation on one of the plurality of bit nodes, each flipping reliability corresponding to a flipping probability; among the plurality of bit nodes, determining at least one target bit node that needs to be flipped based on the one or more flipping reliability of the plurality of bit nodes; and flipping the at least one target bit node to update the current values ​​of the plurality of bit nodes.

[0017] Other features of the invention will be set forth in part in the description which follows, and will become apparent to those skilled in the art upon reading the following description and the accompanying drawings, or may be learned by practicing or operating the invention. The features of this disclosure can be realized and obtained by practicing or using various aspects of the methods, means, and combinations set forth in the detailed examples discussed below.

[0018] Brief description of the attached figures

[0019] This disclosure is further described with reference to exemplary embodiments. These exemplary embodiments are described in detail with reference to the accompanying drawings. These embodiments are non-limiting exemplary embodiments, wherein similar reference numerals denote similar structures throughout the drawings, and wherein:

[0020] Figure 1 This is a schematic diagram illustrating an exemplary data transmission system according to some embodiments of the present disclosure;

[0021] Figure 2 This is a schematic diagram illustrating received codewords and parity check matrices according to some embodiments of the present disclosure.

[0022] Figure 3 This is a block diagram illustrating an exemplary decoder according to some embodiments of the present disclosure;

[0023] Figure 4 This is a flowchart illustrating an exemplary process for decoding codewords according to some embodiments of the present disclosure;

[0024] Figure 5 This is a flowchart illustrating an exemplary process for decoding codewords according to some embodiments of the present disclosure;

[0025] Figure 6 This is a schematic diagram illustrating an exemplary process for decoding codewords according to some embodiments of the present disclosure;

[0026] Figure 7 This is a schematic diagram illustrating an exemplary process for decoding codewords according to some embodiments of the present disclosure;

[0027] Figure 8 This is a schematic diagram illustrating an exemplary process for decoding codewords according to some embodiments of the present disclosure;

[0028] Figure 9 This is a schematic diagram illustrating an exemplary process for decoding codewords according to some embodiments of the present disclosure;

[0029] Figure 10 This is a schematic diagram illustrating an exemplary relationship between initial reliability and flip-flop reliability according to some embodiments of the present disclosure;

[0030] Figure 11 This is a schematic diagram illustrating an exemplary relationship between the iterations of the decoding process and the checker weights according to some embodiments of the present disclosure; and

[0031] Figure 12 This is a schematic diagram illustrating an exemplary relationship between the initial checker weight and the chance of decoding failure according to some embodiments of the present disclosure. Detailed Implementation

[0032] In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without such details. In other instances, well-known methods, processes, systems, components, and / or circuits have been described at a relatively high level (without detail) to avoid unnecessarily obscuring aspects of this disclosure. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not limited to the embodiments shown but is to be given the widest scope consistent with the claims.

[0033] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” may also be intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that, when used in this specification, the terms “comprising,” “including,” and / or “having” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups of such features.

[0034] It should be understood that the terms “system,” “module,” and / or “block” used herein are a way of distinguishing different components, elements, parts, components, or assemblies at different levels in ascending order. However, these terms may be replaced if other expressions serve the same purpose.

[0035] Generally, the terms "module" or "block" as used herein refer to logic embodied in hardware or firmware, or a collection of software instructions. The modules or blocks described herein may be implemented as software and / or hardware and may be stored in any type of non-transitory computer-readable medium or other storage device. In some embodiments, the software module / unit / block may be compiled and linked into an executable program. It should be appreciated that a software module may be callable from other modules / units / blocks or from itself, and / or may be invoked in response to a detected event or interrupt. It is configured to operate on a computer device (e.g., such as...) Figure 1 The software modules / units / blocks executing on the decoder 130 shown may be provided in a computer-readable medium, such as an optical disc, digital video disc, flash drive, magnetic disk, or any other tangible medium, or as a digital download (and may be initially stored in a compressed or installable format that requires installation, decompression, or decryption prior to execution). Such software code may be stored, in part or in whole, on the storage device of the executing computer device for execution by the computer device. Software instructions may be embedded in firmware, such as electrically programmable read-only memory (EPROM). It should also be appreciated that hardware modules / units / blocks may be included in connected logical components (e.g., gates and flip-flops) and / or may be included in programmable units (e.g., programmable gate arrays or processors). The modules / units / blocks or computer device functions described herein may be implemented as software modules / units / blocks, but may be represented in hardware or firmware. Generally, the modules / units / blocks described herein refer to logical modules / units / blocks that can be combined with other modules / units / blocks or divided into multiple modules / units / blocks. This description may apply to a system, an engine, or a part thereof.

[0036] It should be understood that when a module or block is referred to as being "connected to" or "coupled to" another module or block, it may be directly connected to or coupled to another module or block, or communicate with another module or block, or there may be intermediate units, engines, modules, or blocks present, unless the context explicitly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] These and other features and characteristics of this disclosure, as well as the function of the related elements of the method of operation and structure, and the economy of combination and manufacture of these parts, will become clearer when referring to the following description and the accompanying drawings. All of these constitute a part of this disclosure. However, it should be explicitly understood that the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of this disclosure. It should be understood that the drawings are not drawn to scale.

[0038] It should be noted that the decoding method described in this disclosure is provided in conjunction with a bit-flipping method for LDPC codes used in SSD controllers. However, this is not limiting. Those skilled in the art can make modifications or variations based on the teachings of this disclosure, and can use the decoding method in other decoders or controllers, or to decode other types of code. Such modifications or variations are within the scope of this disclosure.

[0039] This paper provides an improved bit-flipping method for low-density parity-check (LDPC) codes and a system for decoding received LDPC codewords using this improved bit-flipping method. The received LDPC codewords can be decoded using a two-dimensional matrix called a parity check matrix. The parity check matrix can define multiple bit nodes and check nodes. The decoding process may include estimating the bit values ​​(also called "hard decisions") relative to the received LDPC codeword (or, for simplicity, "codeword") by the multiple bit nodes and check nodes. In some embodiments, the flipping energy of a bit node can be obtained as a function of the values ​​of the check nodes connected to it. The flipping reliability of a bit node, representing the reliability of a flipping operation on that bit node, can be determined by comparing the flipping energy with at least one flipping energy threshold. The flipping probability of a bit node can then be determined based on the flipping reliability and a flipping rule. A flipping test can be performed based on this flipping probability, and as a result, at least one target bit node that needs to be flipped can be identified and flipped. After the flipping, the hard decisions of these bit nodes can be updated accordingly, and the check weights associated with the updated hard decisions can be verified. The process of updating hard decisions can be performed iteratively until the checksum weight associated with a particular updated hard decision vector is zero or a preset number of iterations is reached. For the sake of brevity, the terms "bit," "bit node," and "variable node" are used interchangeably in this disclosure to refer to binary digits in a codeword or variable nodes corresponding to binary digits defined by the parity check matrix.

[0040] Traditional bit-flipping methods typically decide whether to flip a bit node based solely on the flip energy. For example, if the flip energy is greater than a threshold, the hard decision to flip the bit node is flipped; otherwise, the hard decision is not flipped. Therefore, traditional bit-flipping methods suffer from low randomness and require a large number of iterations to update the hard decision before convergence. In other words, the convergence speed is slow. In contrast, the improved bit-flipping method disclosed in this disclosure introduces the use of a flip test based on the flip probability of a bit node. In a generalized sense, the flip probability is positively correlated with the flip energy across all bit nodes, consistent with conventional bit-flipping methods. Within a specific view of each individual bit node, the flip probability provides a degree of randomness; for example, a bit node with a 10% flip probability may still have a chance to be flipped. This design provides randomness while maintaining overall accuracy, resulting in higher error correction capability and faster convergence. Higher error correction capability and faster convergence reduce the computational load in subsequent decoding (e.g., using a minimum-sum decoder) and improve the overall speed of the LDPC decoder.

[0041] Figure 1 This is a schematic diagram illustrating an exemplary data transmission system according to some embodiments of the present disclosure. For example... Figure 1 As shown, the data transmission system 100 may include an encoder 110, a channel 120, and a decoder 130 (also referred to as a decoding system). The encoder 110 may be mounted on a transmitter, and the decoder 130 may be mounted on a receiver. The encoder 110 may encode the input data using an encoding method to generate codewords. The encoding method may include symmetric encryption methods and / or asymmetric encryption methods. Symmetric encryption methods may include, but are not limited to, LDPC encoding. The encoded codewords may be transmitted to the decoder 130 via the channel 120. The channel 120 may include, but is not limited to, satellite communication channels using satellite antennas, wireless communication channels using base stations and / or local antennas, wired communication channels, fiber optic communication channels using electro-optical (E / O) interfaces, etc. The encoded codewords may be decoded by the decoder 130, allowing the input data to be recovered. In some embodiments, the encoder 110 and decoder 130 may correspond to similar types of codes. For example, both the encoder 110 and decoder 130 may correspond to LDPC codes. In some embodiments, the encoder 110, channel 120, and / or decoder 130 may be part of a solid-state drive (SSD) controller, but this should not be limiting.

[0042] Figure 2 This is a schematic diagram illustrating received codewords and parity check matrices according to some embodiments of the present disclosure. For example... Figure 2As shown, the received codeword 240 may include multiple bits, such as seven bits. In some embodiments, each of the multiple bits may include a binary value, such as "0" or "1". Alternatively, the multiple bits may include decimal values, octal values, hexadecimal values, etc. In some embodiments, the values ​​of the multiple bits may be referred to as hard information (or "hard decision"). Soft information 250 may be received together with hard information 240. The received soft information 250 may be provided by a channel (e.g., channel 120). In some embodiments, the received soft information 250 may be related to the reliability of the hard information. For example, the received soft information 250 may include an initial reliability percentage for each of the multiple bits. A higher percentage may indicate that the bit is more reliable, and vice versa. For example, 100% initial reliability may indicate that the bit is completely reliable, while 0% initial reliability may indicate that the bit is completely unreliable. The received soft information 250 may be represented by binary numbers, decimal numbers, octal numbers, or hexadecimal numbers, etc. In some embodiments, the parity check matrix 210 may be pre-stored in the decoder, or it may be received simultaneously with, before, or after the received codeword 240 and the received soft information 250. The parity check matrix 210 may be received through the same or different channel as the codeword 240. The parity check matrix 210 may include multiple rows and multiple columns. Each column of the parity check matrix 210 may correspond to a bit node 220, and each row of the parity check matrix 210 may correspond to a parity node 230. The number of columns may be equal to the number of bits in the received codeword 240 (e.g., 7). In some embodiments, the parity check matrix 210 may be a regular LDPC parity check matrix, for example, where the sum of the values ​​in each row is a fixed value, and the sum of the values ​​in each column is also a fixed value. Alternatively, the parity check matrix 210 may be an irregular LDPC parity check matrix, for example, where the sum of the values ​​in each row is not a fixed value, and the sum of the values ​​in each column is also not a fixed value. In some embodiments, the relationship between bit nodes 220 and parity nodes 230 defined by parity check matrix 210 can be shown in a bipartite figure 260 (also called a Tanner diagram). As shown in bipartite figure 260, three squares can represent three parity nodes 230 corresponding to three rows of parity check matrix 210. Seven circles can each represent seven bit nodes 220 corresponding to seven columns of parity check matrix 210. The connection between parity node 230 and bit node 220 can correspond to a "1" in a corresponding position in parity check matrix 210. For example, a "1" in the third row and fifth column of parity check matrix 210 can be shown in bipartite figure 260 as a connection between the fifth bit node 220 and the third parity node 230.

[0043] In some embodiments, a checksum weight can be calculated to evaluate whether the received codeword 240 is the same as the target codeword generated in the encoder 110 by encoding the input data. If the checksum weight is zero, the received codeword 240 is considered to be the same as the target codeword; otherwise, the received codeword 240 is considered to be different from the target codeword. In the case where the received codeword 240 is different from the target codeword, an iterative decoding process can be performed by iteratively updating the value of bit node 220 (i.e., hard decision) until the checksum weight becomes zero or the maximum number of iterations is reached.

[0044] Typically, a Tanner diagram can be used to illustrate the process of decoding a received codeword. For example, a codeword may include seven bits corresponding to seven bit nodes 220. Initially, an initial value (e.g., a value from the received codeword) can be assigned to each bit node 220 relative to the corresponding bit of the codeword 240. Each bit node 220 can send its corresponding initial value to a check node 230 connected to it. Each bit node 220 can then be evaluated based on the value of the check node connected to it. Based on the evaluation result, one or more bit nodes 220 can be flipped to update their values. In the next iteration, each bit node 220 can be further evaluated based on these updated values. The decoder can continuously perform iterations until the check weights indicate that the latest updated bit node matches the target codeword or satisfies a preset number of iterations. Further descriptions of the iterative decoding process can be found elsewhere in this disclosure, for example, Figure 4 And its description.

[0045] Figure 3 This is a block diagram illustrating an exemplary decoder according to some embodiments of the present disclosure. Decoder 130 may include an acquisition module 310, a checksum weight calculation module 320, a processing module 330, a determination module 340, a flip test module 350, and a storage module 360.

[0046] The acquisition module 310 can be configured to acquire data or information from other modules or units inside or outside the decoder 130. For example, the acquisition module 310 can receive noisy codewords through a channel. Additionally, the acquisition module 310 can acquire one or more parameters that can be used during the decoding process, such as a flip energy threshold for a specific bit node, or a parity check matrix for decoding the received codewords. Optionally, the acquisition module 310 can update one or more parameters during the decoding process.

[0047] The parity check weight calculation module 320 can be configured to check, for example, the parity check weight of a noise codeword received from the channel, the update value of the codeword (hard decision), etc., based on the parity check matrix.

[0048] Processing module 330 can be configured to determine one or more parameters during the decoding process. For example, processing module 330 can determine the flip energy of a set of bit nodes. Furthermore, processing module 330 can determine the flip reliability of the bit node group based on the flip energy. Additionally, processing module 330 can determine the flip probability of the bit node group based on the flip reliability. In some embodiments, processing module 330 can flip one or more bit nodes to update the corresponding value or hard decision. In some embodiments, processing module 330 can compare the checksum weight determined by checksum weight calculation module 320 with a specific value (e.g., zero) to determine whether the received codeword has been correctly decoded.

[0049] The determining module 340 can be configured to determine whether preset conditions are met during the decoding process. For example, the determining module 340 can determine whether the decoding process should be terminated based on preset conditions. Exemplary preset conditions may include the checksum weight being equal to zero, the number of iterations reaching a threshold, and the checksum weight not decreasing within a preset number of consecutive iterations.

[0050] The flip test module 350 can be configured to perform flip tests on bit nodes to determine at least one target bit node that needs to be flipped. In the flip test, whether to flip a bit node can be determined based on the flip probability corresponding to each bit node. For example, a bit node with a 70% flip probability in the flip test may have a 70% probability of being flipped, while having a 30% (i.e., 1-70%) probability of not being flipped.

[0051] The storage module 360 ​​can be configured to store instructions that can be executed by at least one processor to perform one or more operations as described elsewhere in this disclosure.

[0052] The modules in decoder 130 can connect to or communicate with each other via wired or wireless connections. Wired connections can include metal cables, optical fibers, hybrid cables, or any combination thereof. Wireless connections can include local area networks (LANs), wide area networks (WANs), Bluetooth, ZigBee, near field communication (NFC), or any combination thereof. Two or more modules can be combined into a single module, and any single module can be divided into two or more units.

[0053] It should be noted that the above description is provided for illustrative purposes only and is not intended to limit the scope of this disclosure. Various variations and modifications can be made by those skilled in the art based on the teachings of this disclosure. However, such variations and modifications do not depart from the scope of this disclosure.

[0054] Figure 4This is a flowchart illustrating an exemplary process for decoding received codewords according to some embodiments of the present disclosure. In some embodiments, at least a portion of process 400 may be executed by decoder 130. For example, process 400 may be stored in a storage device (e.g., external storage device, storage module 360) in the form of instructions (e.g., an application program) and executed by decoder 130 (e.g., ...). Figure 3 The processing module 330 shown is invoked and / or executed. The operation of the process presented below is intended to be illustrative. In some embodiments, method 400 may be accomplished using one or more additional steps not described and / or without one or more steps discussed. Additionally, as Figure 4 The order of operations in process 400 shown and described below is not intended to be limiting. It can be... Figure 7 Find an exemplary diagram illustrating process 400.

[0055] In 405, decoder 130 (e.g., acquisition module 310) can receive noisy codewords via a channel. For example, encoded LDPC codewords are transmitted via channel 120, which may introduce noise into the encoded LDPC codewords. Decoder 130 can then receive the noisy LDPC codewords. The channel may provide hard and / or soft information of the received noisy codewords to decoder 130. Hard information may refer to the bit values ​​of the codewords, while soft information may refer to the initial reliability of the bit values. In some embodiments, soft information may be provided by channel 120. Examples of received codewords can be found elsewhere in this disclosure, such as codeword 240, codeword 710, codeword 810, codeword 910, etc.

[0056] In 410, decoder 130 (e.g., parity weight calculation module 320) can verify the parity weight of the received codeword according to the parity check matrix. The parity check matrix can define the relationship between multiple bit nodes and multiple parity nodes. Examples of parity check matrices can be found elsewhere in this disclosure, such as parity check matrix 210. In some embodiments, the parity weight can be determined based on the product of the parity check matrix and the received codeword. For example, the parity vector can be calculated as:

[0057] S = H * r; (1)

[0058] Where S represents the parity vector, H represents the parity check matrix, and r represents the received codeword. In some embodiments, the decoder 130 may further determine the parity weight of the codeword based on the parity vector. For example, the parity weight of the codeword may be represented as the sum of the non-zero values ​​in the parity vector, or as the count of the non-zero values ​​in the parity vector.

[0059] In step 415, decoder 130 (e.g., determination module 340) can determine whether a preset condition is met. The preset condition may include conditions that should terminate the decoding process. For example, the preset condition may include a checksum weight equal to zero, the number of iterations reaching a threshold, or the checksum weight decreasing within a preset number of consecutive iterations. In response to determining that the preset condition is met, process 400 may proceed to operation 465; otherwise, process 400 may proceed to operation 420.

[0060] In 420, decoder 130 (e.g., processing module 330) can determine the flip energy of a set of bit nodes. In some embodiments, each bit node in the set has a corresponding flip energy. The flip energy of each bit node can be determined based on a function of the value of the check node connected to that bit node. In the general expression, bit node v at the i-th iteration... k The flipping energy E(v) k i) can be connected to v during the i-th iteration. k The function that verifies the value of a node (e.g., summation). As used herein, the function that verifies the value of a node can be any suitable arithmetic operation on those values. For example only, assume there exists a function with respect to v. k There are g connected check nodes, and their values ​​in the i-th iteration are CN. k1 i), CN k2 (i), ..., and CN kg (i) are respectively represented as:

[0061] E(v k ,i)=CN k1 (i)+CN k2 (i)+…+CN kg (i); (2)

[0062] Since the value of the check node is binary for the LDPC code (e.g., CN(i) is 0 or 1), the value of the flip energy E(v) is... k i) satisfies the condition: 0 <= E(v) k (i) <= g. For example, if a bit node is connected to three parity nodes, the flip energy of the bit node can be calculated as the sum of the values ​​of the three parity nodes. If two of the three parity nodes are 1 and the other is 0, the flip energy of the bit node can be 2.

[0063] In some embodiments, a group of bit nodes may include one or more bit nodes from all bit nodes defined by the parity check matrix. For example, a group of bit nodes may consist of only a single bit node, meaning that the decoder 130 may process only one bit node at a time. As another example, a group of bit nodes may include two or more bit nodes, meaning that the decoder 130 may process multiple bit nodes at once (e.g., in parallel processing). In some embodiments, all bit nodes defined by the parity check matrix may be grouped into one or more groups based on the index of the bit nodes. For example, a predetermined number of bit nodes with consecutive indices may be grouped into the same group. By way of example only, the predetermined number may be three, for example, grouping the 1st, 2nd, and 3rd bit nodes into the 1st group, the 4th, 5th, and 6th bit nodes into the 2nd group, and so on. The predetermined number may be any suitable integer, such as 1, 2, 3, 5, 10, 20, 30, etc. In some embodiments, the predetermined number may be an integer between 1 and the count of all bit nodes.

[0064] In some embodiments, bit nodes can be classified based on the initial reliability (also known as soft information) of the bits corresponding to them. For example, bit nodes whose corresponding bits have high (e.g., greater than 80%) initial reliability can be classified into a first group. Bit nodes whose corresponding bits have low (e.g., less than 40%) initial reliability can be classified into a second group. Bit nodes whose corresponding bits have medium (e.g., between 40% and 80%) initial reliability can be classified into a third group. In some embodiments, bit node classification can be performed in each iteration, for example, reclassifying all bit nodes in each iteration. Alternatively, bit node classification can vary across different iterations of the decoding process. As used herein, in one iteration of the decoding process, the decoder can process all bit nodes according to the procedure from operation 420 to operation 415. Alternatively, bit node classification can be performed only once during the entire decoding process, for example, classifying bit nodes into groups only at the beginning of the first iteration.

[0065] In step 425, decoder 130 (e.g., acquisition module 310, processing module 330) can acquire or update at least one flip energy threshold. In the first iteration, acquisition module 310 can acquire at least one flip energy threshold. In subsequent iterations, processing module 330 can update at least one flip energy threshold.

[0066] In some embodiments, each bit node in a group of bit nodes may correspond to multiple flip energy thresholds. For illustrative purposes, in a general expression, a particular bit node may have L different flip energy thresholds, denoted as T_F0, T_F1, T_F2, ..., T_F...L-1 T_F0 can be the smallest, T_F1 can be greater than T_F0, T_F2 can be greater than both T_F0 and T_F1, and so on, while T_F... L-1 It can be the largest. In some embodiments, T_F0 can be greater than or equal to 0, and T_F L-1 It can be less than the maximum flip energy, which is equal to the total number of parity nodes connected to a specific bit node. For example, the total number of parity nodes connected to a specific bit node can be three, and at least one flip energy threshold can be a first flip energy threshold T_F0 consisting of 0 and a second flip energy threshold T_F1 consisting of 2.

[0067] In some embodiments, at least one flip energy threshold (e.g., the flip energy threshold for each bit node) can be updated based on the bit node's index, channel mismatch information between the current hard decision and the channel input hard decision, the number of check nodes connected to the bit node, the number of iterations, the number of flip operations in the previous iteration, the check weight in the current iteration, the check weight at the previous time point, etc. In some embodiments, the flip energy thresholds corresponding to different bit nodes can be the same or different. For example, if two bit nodes are connected to different numbers of check nodes, the flip energy thresholds for the two bit nodes can be different. Specifically, a larger flip energy threshold can be assigned to a bit node connected to more check nodes. In some embodiments, the flip energy thresholds corresponding to the same bit node can be the same or different. For example, for the same bit node, a smaller flip energy threshold can be assigned in subsequent iterations than in previous iterations. In some embodiments, if a channel mismatch occurs (e.g., the current hard decision of the bit node differs from its channel input hard decision), a first flip energy threshold can be assigned to the bit node, and if no channel mismatch occurs, a second flip energy threshold (different from the first flip energy threshold) can be assigned to the bit node.

[0068] In 430, decoder 130 (e.g., processing module 330) can determine the flip reliability of a group of bit nodes based on the flip energy and at least one flip energy threshold. In some embodiments, decoder 130 can determine the flip reliability of each bit node in the group by comparing the flip energy of a bit node with the flip energy threshold corresponding to that bit node. For example, in the i-th iteration, if bit node v k The flipping energy E(v) k , i ) greater than or equal to T_F L-1 Then bit node v k Flip reliability FR(v k i) can be determined as level "L-1". As another example, if bit node vk The flipping energy E(v) k i) is less than T_F L -1 but greater than or equal to T_F L-2 Then bit node v k Flip reliability FR(v k i) can be determined as level "L-2". As another example, if bit node v k The flipping energy E(v) k If i) is greater than or equal to T_F0 but less than T_F1, then bit node v can be... k Flip reliability FR(v k i) Determined as level "0". It should be noted that the flip reliability levels "0", "L-2", "L-1", etc., can correspond to different degrees of reliability of the bit node. For example, level "L-1" can indicate that the value of the bit node is "extremely unreliable", while level "0" can indicate that the value of the bit node is "extremely reliable".

[0069] In 435, decoder 130 (e.g., processing module 330) can determine the flip probability of a group of bit nodes based on flip reliability. In some embodiments, decoder 130 can determine the flip probability of each bit node based on the flip reliability of the bit node and a flip rule (e.g., the relationship between flip reliability and flip probability). For example, the flip rule may include the flip reliability of levels "0", "1", ..., "L-2", "L-1" being related to "p0", "p1", ..., "p L-2 “p” L-1 The mapping between the flip probabilities of "" and ", where 1>=p L-1 >=p L-2 >=…>=p1>=p0>=0. As an example only, the flipping rules may include mappings between the flipping reliability of level “3”, level “2”, level “1” and level “0” and the flipping probabilities of 90%, 70%, 50% and 10%, respectively.

[0070] In 440, decoder 130 (e.g., flip test module 350) can perform tests based on the flip probabilities to determine at least one target bit node that needs to be flipped. In the flip test, it can be determined whether a bit node in the group is to be flipped based on its corresponding flip probability. For example, a bit node with a 70% flip probability in the flip test may have a 70% probability of being flipped, and a 30% probability (i.e., 1-70%) of not being flipped. For illustrative purposes, for a bit node with a 70% flip probability, a random value between 0 and 1 can be generated. If the generated random value is in the range of 0 to 0.7 (corresponding to a 70% flip probability), the bit node may need to be flipped. If the generated random value is in the range of 0.7 to 1 (corresponding to a 30% non-flip probability), the bit node may not be flipped. After the flip test, the bit node that needs to be flipped can be identified as the target bit node.

[0071] In 445, decoder 130 (e.g., processing module 330) can flip at least one target bit node to update the value of at least one target bit node. As used herein, "flipping" a bit node can refer to changing the value of a bit node from "0" to "1" or from "1" to "0". Further descriptions of flipping bit nodes can be found elsewhere in this disclosure, for example, Figures 6 to 8 And its description.

[0072] In step 450, decoder 130 (e.g., parity weight calculation module 320) can calculate new parity weights based on the updated value of at least one target bit node and the parity check matrix. For example, the parity weights can be determined based on the product of the parity check matrix and the updated values ​​of multiple bit nodes (including the updated value of at least one target bit node and the values ​​of other unupdated bit nodes). Operation 450 can be similar to operation 410, and will not be described again here.

[0073] In step 455, decoder 130 (e.g., processing module 330) can determine whether the new checksum weight is equal to zero. If the new checksum weight is equal to zero, decoder 130 can determine that the updated values ​​of multiple bit nodes match, for example, the target codeword encoded by encoder 110, meaning that the received codeword has been successfully decoded. If the new checksum weight is not equal to zero, process 400 can proceed to step 460.

[0074] In step 460, decoder 130 (e.g., processing module 330) can determine whether the currently processed bit node belongs to the last group of bit nodes. In response to determining that the currently processed bit node belongs to the last group of bit nodes, i.e., all bit nodes have been processed in the current iteration, process 400 can return to operation 415, where the decoder can further determine whether a new iteration needs to be executed. In response to determining that one or more other groups of bit nodes in the current iteration have not yet been processed, process 400 can proceed to operation 420, where the decoder can further acquire another group of bit nodes to determine their flip energies.

[0075] In step 465, decoder 130 (e.g., processing module 330) can specify the latest updated value of all bit nodes as the decoding result. In some embodiments, if the preset condition in operation 415 is that the checksum weight is equal to zero, the decoding result in operation 465 can be considered as successful decoding. If the preset condition in operation 415 is that the number of iterations reaches a threshold, the decoding result in 465 can be considered as successful decoding (if the checksum weight is also equal to zero), or as a decoding failure (if the checksum weight is not yet equal to zero).

[0076] Various variations and modifications can be made to the teachings of this disclosure by those skilled in the art. However, such variations and modifications do not depart from the scope of this disclosure. For example, operation 425 can be performed before operation 420. In this case, in each iteration, decoder 130 can use the same set of flip energy thresholds to determine the flip operations of different groups of bit nodes.

[0077] Figure 5 This is a flowchart illustrating an exemplary process for decoding codewords according to some embodiments of the present disclosure. In some embodiments, at least a portion of process 500 may be executed by decoder 130. For example, process 500 may be stored in a storage device (e.g., external storage device, storage module 360) in the form of instructions (e.g., an application program) and executed by decoder 130 (e.g., ...). Figure 3 The processing module 330 shown is invoked and / or executed. The operation of the process presented below is for illustrative purposes. In some embodiments, method 500 may be accomplished using one or more additional steps not described and / or one or more steps not discussed. Additionally, Figure 5 The order of operations shown in the diagram and described below for process 500 is not intended to be limiting. (Separately in...) Figure 7 and Figure 8 Exemplary diagrams illustrating operations 560 and 570 can be found in the document.

[0078] In 510, decoder 130 (e.g., acquisition module 310) can receive codewords via the channel. Operation 510 can be similar to operation 405, and will not be described again here.

[0079] In step 520, decoder 130 (e.g., parity weight calculation module 320) can verify the parity weight of the received codeword according to the parity check matrix. Operation 520 can be similar to operation 410, and will not be described again here.

[0080] In step 530, decoder 130 (e.g., determination module 340) can determine whether the parity weight is greater than a parity weight threshold. In some embodiments, the parity weight threshold can be set according to the size of the parity check matrix. For example, a larger parity check matrix may correspond to a larger parity weight threshold. If the parity weight exceeds the parity weight threshold, the value of the bit node (also referred to as hard information) can be considered "extremely unreliable". In some embodiments, the parity weight threshold can be any suitable value, including but not limited to 50, 100, 200, 400, 500, 600, 1000, etc. In response to determining that the parity weight is greater than the parity weight threshold, process 500 can proceed to operation 550; otherwise, process 500 can proceed to operation 540.

[0081] In 540, decoder 130 can decode the received codeword in a conventional manner. For example, the conventional manner of decoding the received codeword may include some or all of operations 415 to 465.

[0082] At 550, decoder 130 can receive soft information from channel 120. The soft information can be referred to as the initial reliability of the hard information (e.g., the value of the bit node). In response to the presence of soft information by the channel, process 500 can proceed to operation 570; otherwise, process 500 can proceed to operation 560.

[0083] In 560, decoder 130 (e.g., processing module 330) may specify a preset flip reliability as the flip reliability of a bit node. In some embodiments, each bit node (e.g., in a set of bit nodes) may be specified with the same flip reliability. Alternatively, each bit node may be specified with a separate flip reliability that is the same as or different from each other. In some embodiments, since hard information is extremely unreliable (e.g., the checksum weight in 530 is greater than the checksum weight threshold), the preset flip reliability of each bit node may be a maximum value or a relatively high value, indicating that each bit node is more likely to flip in subsequent operations. By way of example only, decoder 130 may specify a level "L-1" as the flip reliability of each bit node.

[0084] In 570, decoder 130 (e.g., processing module 330) can determine the flip reliability of a bit node based on soft information. In some embodiments, a relationship between initial reliability and flip reliability can be obtained. This relationship can be represented by a linear function, a nonlinear function, a continuous function, or a discrete function, etc. The flip reliability of a bit node can be determined based on soft information and the relationship between initial reliability and flip reliability. For illustrative purposes, Figure 10 An exemplary relationship between initial reliability and flip-flop reliability is provided. Figure 10 As shown, if the initial reliability is between 0% and 40%, the flip-over reliability can be determined as level "3". If the initial reliability is between 40% and 65%, the flip-over reliability can be determined as level "2". If the initial reliability is between 65% and 90%, the flip-over reliability can be determined as level "1". If the initial reliability is between 90% and 100%, the flip-over reliability can be determined as level "0".

[0085] In some embodiments, after determining the flipping reliability of one or more bit nodes in operation 560 or 570, process 500 may proceed to operation 435.

[0086] Various modifications and variations can be made to the teachings of this disclosure by those skilled in the art. However, such modifications and variations do not depart from the scope of this disclosure. In some embodiments, operation 530 can be omitted, regardless of whether the checksum weight is greater than the checksum weight threshold, and the received codeword can be decoded based solely on hard information or both hard and soft information.

[0087] Figure 6 This is a schematic diagram illustrating an exemplary process for decoding received codewords according to some embodiments of the present disclosure. Figure 6 As shown, the initially received codeword 610 can be "1011010", that is, the initially received codeword 610 includes seven bits with values ​​(i.e., initial hard decisions) of "1", "0", "1", "1", "0", "1", and "0", respectively. In some embodiments, the initially received codeword 610 can be the received codeword 240. In some embodiments, the flip energy 620 of each bit node can be determined based on a parity check matrix (e.g., a parity check matrix 210 defining seven bit nodes and three parity nodes). Figure 2As shown in parity matrix 210, the first bit node can be connected only to the first parity node (not connected to the second and third parity nodes), and the flip energy of the first bit node can be equal to the value of the first parity node. The third bit node can be connected to the first and second parity nodes, and the flip energy of the third bit node can be the sum of the values ​​of the first and second parity nodes. For illustrative purposes only, assume that the three parity nodes have values ​​"1", "1", and "0" respectively, then the flip energy of the first bit node is "1", and the flip energy of the third bit node is "2". Similarly, the flip energies of the second, fourth, fifth, sixth, and seventh bit nodes can be calculated as "1", "0", "1", "2", and "2" respectively.

[0088] In some embodiments, the flip reliability 630 of the seven bit nodes can be determined based on the flip energy 620 and at least one flip energy threshold. For example, the at least one flip energy threshold may include a first flip energy threshold 0, a second flip energy threshold 1, and a third flip energy threshold 2. As an example only, if the flip energy of a bit node is greater than the third flip energy threshold (i.e., 2), the flip reliability of that bit node can be determined as "2". If the flip energy of a bit node (e.g., the first bit node) is greater than or equal to the second flip energy threshold (i.e., 1) but less than the third flip energy threshold (i.e., 2), the flip reliability of that bit node can be determined as "1". If the flip energy of a bit node (e.g., the fourth bit node) is greater than or equal to the first flip energy threshold (i.e., 0) but less than the second flip energy threshold (i.e., 1), the flip reliability of that bit node can be determined as "0". Therefore, the flip reliability 630 of the seven bit nodes can be "1", "1", "2", "0", "1", "2", and "2". It should be noted that the flip reliability "0", "1", or "2" is only used to indicate a specific level of flip reliability. As an example only, a level "0" can indicate that the corresponding bit node is very reliable, while a level "2" can indicate that the corresponding bit node is very unreliable.

[0089] In some embodiments, the flip probability 640 of the seven bit nodes can be determined based on flip reliability 630 and flip rules (e.g., the relationship between flip reliability and flip probability). For example, the flip rule may include a mapping between flip reliability of level "0" and a 10% flip probability, a mapping between flip reliability of level "1" and a 50% flip probability, and a mapping between flip reliability of level "2" and a 70% flip probability. In this case, the flip probability 640 of the bit nodes can be determined as 50%, 50%, 70%, 10%, 50%, 70%, and 50%, respectively.

[0090] Then, a flip test can be performed on the bit nodes based on their flip probabilities. In the flip test, whether to flip is determined based on the flip probability corresponding to each bit node. For example, a bit node with a 70% flip probability might have a 70% chance of flipping and a 30% (i.e., 1-70%) chance of not flipping. As an example only, a flip test is performed on seven bit nodes, and the result is shown as flip test result 650. The values ​​of the bit nodes can be updated based on flip test result 650 (i.e., hard decision). For example, the first, third, fifth, sixth, and seventh bit nodes can be identified as target nodes that need to be flipped (e.g., from "1" to "0", or "0" to "1"). The result is based on the initial codeword 610.

[0091] "1011010" generates the updated codeword 660 "0001101".

[0092] Figure 7 This is a schematic diagram illustrating an exemplary process for decoding received codewords according to some embodiments of the present disclosure. Figure 7 The process shown can correspond to Figure 5 Operation 560. For example... Figure 7 As shown, the initial codeword 710 can be "1011010" (e.g., the same as the initial codeword 610 and the received codeword 240). In some embodiments, the initial checksum weight of the initial codeword 710 can be greater than a checksum weight threshold, and the channel may not include soft information (e.g., the initial reliability of the bit nodes). In this case, a preset level "3" indicating that the bit nodes are very unreliable can be specified as the flip reliability 720 of each of the seven bit nodes.

[0093] In some embodiments, the flip probability 730 of a bit node can be determined based on the bit node's flip reliability 720 and a flip rule (e.g., the relationship between flip reliability and flip probability). For example, the flip rule could include a mapping between a flip reliability of level "3" and a 90% flip probability. Therefore, the flip probability 730 of the bit node can be set to 90% in all cases. Figure 6The process described is similar, and a flip test can be performed on the bit nodes based on a flip probability of 730 (i.e., 90%). Specifically, it is determined whether each bit is flipped individually. In the flip test, each bit node has a 90% chance of being flipped and a 10% (i.e., 1-90%) chance of not being flipped. As an example only, a flip test is performed on seven bit nodes, and the result is shown as flip test result 740. The value of the bit nodes can be updated based on the flip test result 740. For example, the first, second, third, fifth, sixth, and seventh bit nodes can be identified as target nodes that need to be flipped (e.g., from "1" to "0", or "0" to "1"). The fourth bit node can remain unchanged. The result is based on the initial codeword 710.

[0094] "1011010" generates the updated codeword 750 "0101101".

[0095] Figure 8 This is a schematic diagram illustrating an exemplary process for decoding codewords according to some embodiments of the present disclosure. Figure 8 The process shown can correspond to Figure 5 Operation 570 in the example. Figure 8 As shown, the initial codeword 810 can be "1011010" (e.g., the same as initial codeword 610, initial codeword 710, and received codeword 240). In some embodiments, the initial checksum weight of the initial codeword 810 can be greater than the checksum weight threshold, and the channel can provide soft information 820 (e.g., the initial reliability of the bit node). Since the initial checksum weight is greater than the checksum weight threshold, the initial codeword 810 is very unreliable. When the soft information is available, the flip-over reliability 830 of the seven bit nodes can be determined based on this soft information. For example, the relationship between the initial reliability and the flip-over reliability can be obtained. This relationship can be represented by a linear function, a nonlinear function, a continuous function, or a discrete function, etc. Based on the soft information 820 and Figure 10 Based on the relationship in the example, the flip reliability of the seven bit nodes 830 can be determined as "0033021".

[0096] The flip probability 840 of a bit node can be determined based on flip reliability 830 and flip rules (e.g., the relationship between flip reliability and flip probability). For example, flip rules could include a mapping between flip reliability for levels "3", "2", "1", and "0" and their corresponding flip probabilities of 90%, 70%, 50%, and 10%, respectively. Figure 6 and Figure 7The process described is similar, and a flip can be tested based on the flip probability 840 of the bit node. As an example only, a flip test is performed on seven bit nodes, and the result is shown as flip test result 850. The value of the bit node can be updated based on flip test result 850. As a result, the updated codeword 860 "1000011" can be generated based on the initial codeword 810 "1011010".

[0097] Figure 9 This is a schematic diagram illustrating an exemplary process for decoding codewords according to some embodiments of the present disclosure. Figure 9 The process shown can correspond to Figure 5 Operation 570 in the example. Figure 9 As shown, the initial codeword 910 can be "1011010" (e.g., the same as initial codewords 610, 710, 810, and the received codeword 240). In some embodiments, the initial parity weight of the initial codeword 910 can be greater than a parity weight threshold, and the channel can provide soft information 920. Because the initial parity weight is greater than the parity weight threshold, the initial codeword 910 is highly unreliable. When the soft information is available, the flip reliability 930 of the seven-bit node can be determined based on this soft information.

[0098] and Figure 8 Unlike the soft information 820 shown, soft information 920 is represented by binary values ​​"0" and "1". A value "1" can indicate that the corresponding bit node is reliable (e.g., has high initial reliability), while a value "0" can indicate that the corresponding bit node is unreliable (e.g., has low initial reliability). For example, a value "1" can correspond to a flip reliability of level "0", while a value "0" can correspond to a flip reliability of level "3". As a result, the flip reliability 930 of the seven bit nodes can be determined as "0033330".

[0099] The flip probability 940 of a bit node can be determined based on the flip reliability 930 and flip rules (e.g., the relationship between flip reliability and flip probability). For example, the flip rule could include a mapping between flip retrieval tiers "3" and "0" and their corresponding flip probabilities of 90% and 10%. Figure 6 , Figure 7 and Figure 8 The process described is similar, and a flip can be tested based on the flip probability 940 of the bit node. As an example only, a flip test is performed on seven bit nodes, and the result is shown as flip test result 950. The value of the bit node can be updated based on the flip test result 950. As a result, the updated codeword 960 "1000100" can be generated based on the initial codeword 910 "1011010".

[0100] It should be noted that, Figure 6-9 The determination of the described flip energy, flip reliability, and / or flip probability is based on treating the seven bit nodes as being in the same group (e.g., as described in Operation 420). However, other bit node classification methods may also be used in the decoding process of this disclosure, such as each group including only one bit node. It should be noted that the above description is provided for illustrative purposes only and is not intended to limit the scope of this disclosure. Various variations and modifications can be made to the teachings of this disclosure by those skilled in the art. However, such variations and modifications do not depart from the scope of this disclosure. For example, the relationship between flip reliability and flip probability can be adjusted according to the specific circumstances. By way of example only, in the specific case of an SSD application, the flip probability of any bit node may be "0%" or "100%" depending on the flip reliability of that bit node. For example, in combination with, for example Figures 6 to 9 In the described flipping rules, the flipping reliability of level "3" and level "2" can both correspond to a 100% flipping probability, while the flipping reliability of level "1" and level "0" can both correspond to a 0% flipping probability. In this case, if combined with... Figures 6 to 9 As described, the flip test can be omitted, and the bit node with a 100% flip probability can be directly identified as the target bit node to be flipped.

[0101] Figure 11 This is a schematic diagram illustrating an exemplary relationship between the iteration of the decoding process and the check sub-weights according to some embodiments of the present disclosure. Figure 10 As shown, curve 1010 corresponds to a conventional bit-flipping method, and curve 1020 corresponds to the improved bit-flipping method disclosed in this disclosure. Conventional bit-flipping methods determine whether to flip a bit node solely based on its flip energy. If the flip energy is greater than a threshold, the bit is flipped; otherwise, it is not. Therefore, conventional bit-flipping methods have low randomness, and the number of iterations required to update the codeword before the checksum weights reach zero can be large. In other words, the convergence speed can be slow. Conversely, the improved bit-flipping method disclosed in this disclosure introduces the use of a flip test related to the flip probability of a bit node. In a generalized sense, the flip probability is positively correlated with the flip energy across all bit nodes, consistent with conventional bit-flipping methods. In a specific view of each individual bit node, a bit node with a 10% flip probability may still have a chance to flip. This design provides low randomness while maintaining overall accuracy. Therefore, when using this method, the number of iterations required for convergence is much smaller.

[0102] Figure 12 This is a schematic diagram illustrating an exemplary relationship between the initial check subweight and the chance of decoding failure according to some embodiments of this disclosure. Figure 11 As shown, curve 1110 corresponds to a conventional bit-flipping method, and curve 1120 corresponds to the improved bit-flipping method disclosed in this disclosure. As mentioned above, conventional bit-flipping methods have low randomness. If the initial checksum weight is large, the chance of decoding failure may be high. Conversely, the improved bit-flipping method disclosed in this disclosure provides a method for determining the flipping reliability of bit nodes when the initial checksum weight is very large (e.g., specifying a preset flipping reliability or using soft information to determine the flipping, such as...). Figure 5 (As shown in Figures 560 and 570). Furthermore, this method provides a degree of randomness. Therefore, the chance of decoding failure does not increase significantly when the initial checksum weights are increased. The high error correction capability and fast convergence speed of this method result in less computational load in subsequent decoding processes (e.g., using a minimum-sum decoder) and a faster overall speed for the LDPC decoder.

[0103] Having described the basic concepts, it will be apparent to those skilled in the art, upon reading this detailed disclosure, that the foregoing detailed disclosure is intended to be illustrative only and not restrictive. Although not explicitly stated herein, various changes, modifications, and alterations may be made, and such changes, modifications, and alterations are desirable to those skilled in the art. These changes, modifications, and alterations are intended to be set forth in this disclosure and are within the spirit and scope of the exemplary embodiments of this disclosure.

[0104] Furthermore, certain terms have been used to describe embodiments of this disclosure. For example, the terms "one embodiment" and / or "some embodiments" indicate that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, it should be emphasized and understood that two or more references to "one embodiment" or "optional embodiment" in various parts of this specification do not necessarily refer to the same embodiment. Additionally, specific features, structures, or characteristics may be appropriately combined in one or more embodiments of this disclosure.

[0105] Furthermore, those skilled in the art will recognize that various aspects of this disclosure can be described and illustrated in any of many patentable classes or environments, including any new and useful methods, apparatus, manufacture, or composition of matter, or any new and useful improvement thereof. Therefore, the various aspects of this disclosure generally referred to as “units,” “modules,” or “systems” can be implemented entirely in hardware, entirely in software (including firmware, resident software, microcode, etc.), or by a combination of software and hardware. Furthermore, various aspects of this disclosure can be embodied in the form of a computer program product having computer-readable program code on one or more computer-readable media.

[0106] Computer-readable signal media may include, for example, a propagated data signal in baseband or as part of a carrier wave, the propagated data signal having computer-readable program code contained therein. Such a propagated signal may take any of a variety of forms, including electromagnetic, optical, etc., or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium and may be any computer-readable medium for transmitting, propagating, or transmitting a computer-readable program for use by or in connection with an instruction execution system, apparatus, or device. The computational program code embodied on the computer-readable signal medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, radio frequency (RF), etc., or any suitable combination thereof.

[0107] Computer program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​(e.g., Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB, .NET, Python, etc.), conventional procedural programming languages ​​(e.g., the "C" programming language, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP), dynamic programming languages ​​(e.g., Python, Ruby, and Groovy), or other programming languages. The program code can be entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer (e.g., via the Internet through an Internet service provider) or provided in a cloud computing environment or as a service (e.g., Software as a Service (SaaS)).

[0108] Furthermore, the order of the elements or sequences described herein, or therefore the use of numbers, letters, or other names, is not intended to limit the claimed processes and methods to any order unless specified in the claims. While the foregoing disclosure has discussed various useful embodiments currently considered to be part of this disclosure by way of various examples, it should be understood that such detail is for that purpose only, and the appended claims are not limited to the disclosed embodiments, but rather are intended to cover modifications and equivalents within the spirit and scope of the disclosed embodiments. For example, although the implementation of the various components described above can be embodied in a hardware device, it can also be implemented as a purely software solution, such as an installation on an existing server or mobile device.

[0109] Similarly, it should be understood that in the foregoing description of embodiments of this disclosure, various features are sometimes combined in a single embodiment, drawing, or description thereof to simplify the disclosure and aid in understanding one or more of the various embodiments. However, the approach of this disclosure should not be construed as reflecting an intention that the claimed subject matter requires more features than expressly recited in each claim. Rather, the claimed subject matter may have fewer than all the features of a single foregoing embodiment.

Claims

1. A system for decoding received codewords, characterized in that, include: At least one storage device storing executable instructions, and At least one processor communicating with the at least one storage device, wherein, when the executable instructions are executed, the at least one processor causes the system to perform the following operations: The received codewords are received through the channel, and the received codewords include multiple bits; Obtain a parity check matrix, which defines the relationship between multiple bit nodes and multiple check nodes, where each bit node corresponds to one of the multiple bits; and The received codeword is decoded by estimating the value of the codeword relative to the plurality of bit nodes and the plurality of check nodes during an iterative process including one or more iterations, wherein at least one of the one or more iterations includes: The parity subweights are determined based on the current values ​​of the multiple bit nodes and the parity check matrix. Determine whether the weight of the check sub is equal to zero; In response to determining that the checker weight is not equal to zero, one or more flip reliability of the plurality of bit nodes are determined, each flip reliability representing the reliability of a flip operation on one of the plurality of bit nodes; Among the plurality of bit nodes, based on one or more flipping reliability of the plurality of bit nodes, at least one target bit node that needs to be flipped is determined; and Flip the at least one target bit node to update the current value of the plurality of bit nodes; Determining the flip reliability of one or more of the plurality of bit nodes includes: for each of the plurality of bit nodes Determine the flip energy; Obtain at least one flip energy threshold; Compare the flip energy with the at least one flip energy threshold; and The flipping reliability of the bit node is determined based on the result of the comparison.

2. The system according to claim 1, characterized in that, Among the plurality of bit nodes, determining at least one target bit node that needs to be flipped includes: Determine one or more flip probabilities of the plurality of bit nodes, each flip probability corresponding to one of the plurality of bit nodes; For each of the plurality of bit nodes, a test is performed based on its corresponding flip probability to determine whether the bit node needs to be flipped, wherein, in this test, the bit node has a first probability equal to the flip probability of being flipped; and Based on the test results, determine at least one target bit node that needs to be flipped.

3. The system according to claim 2, characterized in that, Determining one or more flip probabilities of the plurality of bit nodes includes: Obtain the flipping rules, which include the relationship between the flipping reliability and the flipping probability of the same bit node; and For each of the plurality of bit nodes, the flip probability of the bit node is determined based on the flip rule and the corresponding flip reliability of the bit node.

4. The system according to claim 1, characterized in that, Determining the reliability of one or more flips of the plurality of bit nodes includes: Determine whether the checksum weight is greater than the checksum weight threshold; and In response to determining that the checker weight is greater than the checker weight threshold, a preset flip reliability is assigned as one or more flip reliability of the plurality of bit nodes.

5. The system according to claim 1, characterized in that, The channel provides soft information including the initial probability of each of the plurality of bit nodes, and determining the reliability of one or more flips of the plurality of bit nodes includes: determining whether the checksum weight is greater than a checksum weight threshold; and In response to determining that the checksum weight is greater than the checksum weight threshold, for each of the plurality of bit nodes, the flip reliability of the bit node is determined based on its initial probability.

6. The system according to claim 1, characterized in that, For each of the plurality of bit nodes, the flip energy is a function of the value of the check node connected to the bit node.

7. The system according to claim 1, characterized in that, The flip energy threshold corresponding to a specific bit node has different values ​​in different iterations.

8. The system according to claim 1, characterized in that, At least one flip energy threshold corresponding to a specific bit node is determined based on at least one of the following: The index of the specific bit node, channel mismatch information, number of check nodes connected to the specific bit node, number of iterations, number of target bit nodes that were flipped in the previous iteration, check weight in the current iteration, or check weight in the previous iteration.

9. The system according to claim 1, characterized in that, Different bit nodes correspond to different values ​​of the at least one flip energy threshold.

10. The system according to claim 1, characterized in that, The system is used in solid-state drive (SSD) controllers to decode low-density parity-check (LDPC) codes.

11. A method for decoding received codewords, characterized in that, include: The received codewords are received through the channel, and the received codewords include multiple bits; Obtain a parity check matrix, which defines the relationship between multiple bit nodes and multiple check nodes, where each bit node corresponds to one of multiple bits; and The received codeword is decoded by estimating the value of the codeword relative to the plurality of bit nodes and the plurality of check nodes during an iterative process including one or more iterations, wherein at least one of the one or more iterations includes: The parity subweights are determined based on the current values ​​of the multiple bit nodes and the parity check matrix. Determine whether the weight of the check sub is equal to zero; In response to determining that the checker weight is not equal to zero, one or more flip reliability of the plurality of bit nodes are determined, each flip reliability representing the reliability of a flip operation on one of the plurality of bit nodes; Among the plurality of bit nodes, based on one or more flipping reliability of the plurality of bit nodes, at least one target bit node that needs to be flipped is determined; and Flip the at least one target bit node to update the current value of the plurality of bit nodes; Determining the flip reliability of one or more of the plurality of bit nodes includes: for each of the plurality of bit nodes Determine the flip energy; Obtain at least one flip energy threshold; Compare the flip energy with the at least one flip energy threshold; and The flipping reliability of the bit node is determined based on the result of the comparison.

12. The method according to claim 11, characterized in that, Among the plurality of bit nodes, determining at least one target bit node that needs to be flipped includes: Determine one or more flip probabilities of the plurality of bit nodes, each flip probability corresponding to one of the plurality of bit nodes; For each of the plurality of bit nodes, a test is performed based on its corresponding flip probability to determine whether the bit node needs to be flipped, wherein, in this test, the bit node has a first probability equal to the flip probability of being flipped; and Based on the test results, determine at least one target bit node that needs to be flipped.

13. The method according to claim 12, characterized in that, Determining one or more flip probabilities of the plurality of bit nodes includes: Obtain the flipping rules, which include the relationship between the flipping reliability and the flipping probability of the same bit node; and For each of the plurality of bit nodes, the flip probability of the bit node is determined based on the flip rule and the corresponding flip reliability of the bit node.

14. The method according to claim 11, characterized in that, Determining the reliability of one or more flips of the plurality of bit nodes includes: Determine whether the checksum weight is greater than the checksum weight threshold; and In response to determining that the checker weight is greater than the checker weight threshold, a preset flip reliability is assigned as one or more flip reliability of the plurality of bit nodes.

15. The method according to claim 11, characterized in that, The channel provides soft information including an initial probability for each of the plurality of bit nodes, and determining the reliability of one or more flips of the plurality of bit nodes includes: Determine whether the checksum weight is greater than the checksum weight threshold; and In response to determining that the checksum weight is greater than the checksum weight threshold, for each of the plurality of bit nodes, the flip reliability of the bit node is determined based on its initial probability.

16. The method according to claim 11, characterized in that, For each of the plurality of bit nodes, the flip energy is a function of the value of the check node connected to the bit node.

17. The method according to claim 11, characterized in that, The flip energy threshold corresponding to a specific bit node has different values ​​in different iterations.

18. A non-transitory computer-readable medium having executable instructions, characterized in that, The executable instructions, when executed by at least one processor, cause the at least one processor to perform a method comprising: The received codewords are received through the channel, and the received codewords include multiple bits; Obtain a parity check matrix, which defines the relationship between multiple bit nodes and multiple check nodes, where each bit node corresponds to one of multiple bits; and The received codeword is decoded by estimating the value of the codeword relative to the plurality of bit nodes and the plurality of check nodes during an iterative process including one or more iterations, wherein at least one of the one or more iterations includes: The parity subweights are determined based on the current values ​​of the multiple bit nodes and the parity check matrix. Determine whether the weight of the check sub is equal to zero; In response to determining that the checker weight is not equal to zero, one or more flip reliability of the plurality of bit nodes are determined, each flip reliability representing the reliability of a flip operation on one of the plurality of bit nodes; each flip reliability corresponds to a flip probability; Based on one or more flipping reliability and corresponding flipping probability of the plurality of bit nodes, determine at least one target bit node among the plurality of bit nodes that needs to be flipped and the flipping probability of the plurality of bit nodes; and Flip the at least one target bit node to update the current value of the plurality of bit nodes; Determining the flip reliability of one or more of the plurality of bit nodes includes: for each of the plurality of bit nodes Determine the flip energy; Obtain at least one flip energy threshold; Compare the flip energy with the at least one flip energy threshold; and The flipping reliability of the bit node is determined based on the result of the comparison.

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