Display device and multi-screen display device including the same

Abstract

A display device and a multi-screen display device including the display device are disclosed. The display device includes: a first substrate, the first substrate includes a plurality of pixels arranged in a display portion; a second substrate bonded to the first substrate; and a wiring portion arranged on an outer surface of the first substrate and an outer surface of the second substrate, wherein the first substrate includes: a first pad portion connected to the wiring portion and the plurality of pixels; and a gate drive circuit arranged in the display portion, the gate drive circuit including a shift register for providing a scan signal to the plurality of pixels, wherein the first pad portion includes a plurality of first gate pads, the plurality of first gate pads are arranged in the outermost pixels located at an edge portion of the first substrate among the plurality of pixels and connected to the gate drive circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0180115, filed on December 31, 2019, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a display device and a multi-screen display device comprising the display device. Background Art

[0004] Recently, with the development of multimedia, the importance of display devices has been increasing, and thus, display devices such as liquid crystal display (LCD) devices, organic light emitting display devices, and light emitting diode display devices are being commercialized.

[0005] Display devices have excellent characteristics such as thinness, lightness and low power consumption, and are therefore widely used as display screens for televisions (TVs), laptop computers and monitors, as well as portable electronic devices such as electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, super mobile personal computers (PCs), mobile phones, smart phones, smart watches, tablet personal computers (PCs), watch phones and mobile communication terminals.

[0006] A display device may include a display panel including a plurality of pixels having thin film transistors (TFTs) connected to data lines and gate lines; a data driving circuit for supplying data voltages to the data lines; and a gate driving circuit for supplying scan signals to the gate lines. The display panel may include a display area and a frame area surrounding the display area, the display area including a plurality of pixels displaying an image.

[0007] The related art display device may require a bezel (or mechanism) for covering a bezel area provided at a boundary (or edge portion) of a display panel, and for this reason, the width of the bezel may increase.

[0008] Recently, a multi-display device that realizes a large screen by arranging a plurality of display devices in a lattice type has been commercialized.

[0009] However, in a related art multi-screen display device, due to the frame area or frame of each of the multiple display devices, a boundary portion such as a seam is formed between adjacent display devices. When an image is displayed on the entire screen of the multi-screen display device, the boundary portion causes a sense of discontinuity (or discontinuity) in the image, and for this reason, the immersion of the viewer viewing the image is reduced.

[0010] [Prior art literature]

[0011] [Patent Document]

[0012] Korean Patent Registration No. 10-1441956 (Invention Title: Multi-panel Display Device, International Classification Numbers: G02F 1 / 1335, G02F 1 / 13357) Summary of the Invention

[0013] Accordingly, the present invention is directed to a display device and a multi-screen display device including the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0014] One aspect of the present invention is to provide a display device without a bezel.

[0015] Another aspect of the present invention is directed to providing a multi-screen display device that displays images without a sense of discontinuity.

[0016] The following description will partially list additional advantages and features of the present invention, some of which will become apparent to those skilled in the art after studying the following or may be learned through practice of the present invention. These and other advantages of the present invention may be realized and obtained through the structures specifically pointed out in the specification, claims, and drawings.

[0017] To achieve these and other advantages and in accordance with the intent of the present invention, as embodied and generally described herein, a display device is provided, comprising: a first substrate, the first substrate including a plurality of pixels arranged in a display portion; a second substrate bonded to the first substrate; and a wiring portion arranged on an outer surface of the first substrate and an outer surface of the second substrate, wherein the first substrate includes: a first pad portion connected to the wiring portion and the plurality of pixels; and a gate drive circuit arranged in the display portion, the gate drive circuit including a shift register for providing scan signals to the plurality of pixels, wherein the first pad portion includes a plurality of first gate pads, the plurality of first gate pads being arranged in the outermost pixels among the plurality of pixels, located at an edge portion of the first substrate, and connected to the gate drive circuit.

[0018] According to some embodiments of the present invention, a display device includes: a first substrate including a display area; a plurality of pixel areas arranged at a first interval in the display area; a gate driving circuit including a shift register, the shift register being configured to include a plurality of stage circuit units arranged in each horizontal row of the display area, each of the plurality of stage circuit units including a plurality of branch circuits arranged separated from each other within a horizontal row; a gate control line group, the gate control line group being arranged between one or more pixel areas and connected to the plurality of stage circuit units; and a plurality of first gate pads, the plurality of first gate pads being arranged in the display area and electrically connected to the gate control line group, wherein an outermost pixel area among the plurality of pixel areas includes the plurality of first gate pads.

[0019] According to some embodiments of the present invention, a display device includes: a first substrate including a display portion, the display portion being defined on an outer surface located between a first surface and a second surface of the first substrate and on the first surface; a second substrate including an outer surface located between a front surface and a rear surface of the second substrate; and a joining member disposed between the second surface of the first substrate and the front surface of the second substrate, wherein a size of the display portion is the same as a total size of the first surface of the first substrate, and an end of the display portion is an outer surface of the first substrate.

[0020] A display device according to some embodiments of the present invention includes a first substrate and a display area including a plurality of pixels on the first substrate, wherein a size of the display area is substantially the same as a size of the first substrate.

[0021] According to some embodiments of the present invention, a display device includes: a first substrate including an outer surface and a pixel array including a plurality of pixels arranged on the first substrate, wherein each of the plurality of pixels of the pixel array is immediately adjacent to or directly adjacent to a neighboring pixel in a first direction and a second direction intersecting the first direction, and the outermost pixels of the pixel array are aligned on the outer surface of the first substrate.

[0022] A display device according to some embodiments of the present invention includes a first substrate including an outer surface and a display portion disposed on the first substrate, the display portion including a side surface, wherein the side surface of the display portion is substantially aligned with the outer surface of the first substrate.

[0023] According to some embodiments of the present invention, a display device includes: a first substrate, the first substrate including an outer surface located between a first surface and a second surface of the first substrate and a display portion defined on the first surface; a second substrate, the second substrate including an outer surface located between a front surface and a rear surface of the second substrate; and a joining member, the joining member being arranged between the second surface of the first substrate and the front surface of the second substrate, wherein a size of the display portion is the same as a total size of the first surface of the first substrate, and an end of the display portion is the outer surface of the first substrate.

[0024] A display device according to some embodiments of the present invention includes a first substrate and a display area including a plurality of pixels on the first substrate, wherein a size of the display area is substantially the same as a size of the first substrate.

[0025] According to some embodiments of the present invention, a multi-screen display device includes: a plurality of display modules arranged along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display modules includes: a first substrate including a plurality of pixels arranged in a display portion; a second substrate bonded to the first substrate; and a wiring portion arranged on an outer surface of the first substrate and an outer surface of the second substrate, wherein the first substrate includes: a first pad portion connected to the wiring portion and the plurality of pixels; and a gate driving circuit arranged in the display portion, the gate driving circuit including a shift register for providing a scan signal to the plurality of pixels, wherein the first pad portion includes a plurality of first gate pads, and the plurality of first gate pads are arranged in the outermost pixels among the plurality of pixels, located at an edge portion of the first substrate, and are connected to the gate driving circuit.

[0026] According to some embodiments of the present invention, a multi-screen display device includes: a plurality of display modules arranged along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display modules includes: a first substrate including a display area; a plurality of pixel areas arranged at a first interval in the display area; a gate driving circuit including a shift register, the shift register including a plurality of branch circuits, the plurality of branch circuits being arranged in each horizontal row of the display area separated from each other; a gate control line group, the gate control line group being arranged between one or more pixel areas and connected to the plurality of stage circuit units; and a plurality of first gate pads, the plurality of first gate pads being arranged in the display area and electrically connected to the gate control line group, wherein an outermost pixel area among the plurality of pixel areas includes the plurality of first gate pads.

[0027] According to some embodiments of the present invention, a multi-screen display device includes: a plurality of display modules arranged along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display modules includes: a first substrate including an outer surface and a pixel array including a plurality of pixels arranged on the first substrate, wherein each of the plurality of pixels of the pixel array is adjacent to or directly adjacent to adjacent pixels in the first direction and a second direction intersecting the first direction, and the outermost pixels of the pixel array are aligned on the outer surface of the first substrate.

[0028] According to some embodiments of the present invention, a multi-screen display device includes: a plurality of display modules arranged along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display modules includes: a first substrate including an outer surface and a display portion arranged on the first substrate, the display portion including a side surface, wherein the side surface of the display portion is basically aligned with the outer surface of the first substrate.

[0029] According to some embodiments of the present invention, a multi-screen display device includes: a plurality of display modules arranged along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display modules includes: a first substrate, the first substrate including an outer surface located between a first surface and a second surface of the first substrate and a display portion defined on the first surface; a second substrate, the second substrate including an outer surface located between a front surface and a rear surface of the second substrate; and a joining member, the joining member being arranged between the second surface of the first substrate and the front surface of the second substrate, wherein a size of the display portion is the same as a total size of the first surface of the first substrate, and an end of the display portion is the outer surface of the first substrate.

[0030] According to some embodiments of the present invention, a multi-screen display device includes: a plurality of display modules arranged along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display modules includes: a first substrate and a display area including a plurality of pixels on the first substrate, wherein a size of the display area is substantially the same as a size of the first substrate.

[0031] According to some embodiments of the present invention, a display device including no bezel and a multi-screen display device including the display device may be provided.

[0032] According to some embodiments of the present invention, a display device may include a blocking pattern portion arranged at an edge portion of a display portion to isolate the light-emitting device, thereby providing a display device and a multi-screen display device including the display device, which can prevent the light-emitting device from being degraded due to moisture penetration in a lateral direction and improve the reliability of the light-emitting device.

[0033] According to some embodiments of the present invention, a multi-screen display device that displays images without a sense of discontinuity may be provided.

[0034] It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which provide a further understanding of the present invention and are incorporated in and constitute a part of this application, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. In the drawings:

[0036] Figure 1A and Figure 1B is a diagram illustrating a display device according to the present invention;

[0037] Figures 2A to 2D yes Figure 1A An enlarged view of the area "B1" shown in FIG;

[0038] Figure 3A and Figure 3B is a diagram illustrating a bezel area of ​​a display device according to a comparative example and an air-bezel of a display device according to the present invention;

[0039] Figure 4 is a perspective view illustrating a display device according to an embodiment of the present invention;

[0040] Figure 5 is a diagram illustrating a rear surface of a display device according to an embodiment of the present invention;

[0041] Figure 6 yes Figure 4 An enlarged view of area "B2" shown in FIG;

[0042] Figure 7 It is a diagram Figure 4 Schematic diagram of a gate drive circuit provided in a display area shown in ;

[0043] Figure 8 It is a diagram Figure 4 and Figure 6 A circuit diagram of a pixel shown in ;

[0044] Figure 9 It is a diagram Figure 5 ;

[0045] Figure 10 yes Figure 9 An enlarged view of area "B3" shown in FIG;

[0046] Figure 11 It is a diagram Figure 7 The circuit diagram of the i-th stage circuit unit shown in ;

[0047] Figure 12 It is a diagram Figure 11 A circuit diagram of each of the node control circuit, the first inverter circuit, the second inverter circuit, and the first sensing control circuit shown in ;

[0048] Figure 13 It is a diagram Figure 11 A circuit diagram of each of the node reset circuit, the output buffer circuit, and the second sensing control circuit shown in ;

[0049] Figure 14 is a description Figure 4 FIG. 1 is a diagram of a gate driving circuit according to another embodiment of the present invention;

[0050] Figure 15 It is along Figure 4 A cross-sectional view taken along line II' shown in FIG.

[0051] Figure 16 yes Figure 15 An enlarged view of area "B4" shown in FIG;

[0052] Figure 17 It is along Figure 4 A cross-sectional view taken along line II-II' shown in FIG.

[0053] Figure 18 It is a diagram Figure 5 ;

[0054] Figure 19 It is along Figure 18 A cross-sectional view taken along line III-III' shown in FIG.

[0055] Figure 20 It is along Figure 6 A cross-sectional view taken along line IV-IV' shown in FIG.

[0056] Figure 21 It is along Figure 6 Another cross-sectional view taken along line IV-IV' shown in FIG.

[0057] Figure 22 It is along Figure 4Another cross-sectional view taken along line II-II' shown in FIG;

[0058] Figure 23 yes Figure 22 An enlarged view of area "B5" shown in;

[0059] Figure 24 It is along Figure 4 Another cross-sectional view taken along line II-II' shown in FIG;

[0060] Figure 25 yes Figure 24 An enlarged view of area "B6" shown in;

[0061] Figure 26 It is along Figure 4 Another cross-sectional view taken along line II-II' shown in FIG;

[0062] Figure 27 yes Figure 26 An enlarged view of area "B7" shown in;

[0063] Figure 28 It is along Figure 4 Another cross-sectional view taken along line II-II' shown in FIG;

[0064] Figure 29 yes Figure 28 An enlarged view of area "B8" shown in;

[0065] Figure 30 It shows Figure 29 A microscopic photograph of a cross section of the lower trench structure shown in FIG.

[0066] Figure 31 It is along Figure 4 Another cross-sectional view taken along line II-II' shown in FIG;

[0067] Figure 32 yes Figure 31 An enlarged view of area "B9" is shown in;

[0068] Figures 33A to 33E It is graphic manufacturing Figure 31 Schematic diagram of a method of each of the light emitting device, common electrode and encapsulation layer shown in ;

[0069] Figure 34 yes Figure 33B Microscope photos of

[0070] Figure 35 It is a diagram Figure 4 a diagram of the rear surface of the second substrate shown in ;

[0071] Figure 36is a diagram illustrating a multi-screen display device according to an embodiment of the present invention;

[0072] Figure 37 It is a diagram Figure 36 ;

[0073] Figure 38 It is along Figure 36 A cross-sectional view taken along line V-V' shown in FIG.

[0074] Figure 39A and Figure 39B are diagrams illustrating images displayed by a multi-screen display device according to a comparative example and a multi-screen display device according to the present invention, respectively. DETAILED DESCRIPTION

[0075] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0076] The advantages and features of the present invention and their implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present invention can be implemented in various forms and should not be construed as limited to the embodiments listed here. Rather, these embodiments are provided so that the disclosure of the present invention will be comprehensive and complete and will fully convey the scope of the present invention to those skilled in the art. Furthermore, the present invention is limited only by the scope of the claims.

[0077] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings for the purpose of describing the embodiments of the present invention are merely examples, and the present invention is therefore not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when it is determined that a detailed description of related known functions or structures would unnecessarily obscure the key points of the present invention, such detailed description will be omitted. Where the words "including," "having," and "comprising" are used in this application for description, other parts may be added unless "only" is used.

[0078] When interpreting an element, even if not explicitly stated, the element should be interpreted as including a range of error.

[0079] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "above", "below", and "after", one or more other parts may be set between the two parts unless "just" or "directly" is used.

[0080] When describing a temporal relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "directly" or "directly" is used.

[0081] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention.

[0082] When describing the elements of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only used to distinguish the corresponding elements from other elements, and these terms do not limit the nature, order or priority of the corresponding elements. It will be understood that when an element or layer is said to be "on" or "connected to" another element or layer, the element may be directly located on or directly connected to the other element or layer, or there may be an intermediate element or layer. In addition, it should be understood that when an element is arranged above or below another element, it can represent a situation where these elements are arranged to be in direct contact with each other, but it can also represent that these elements are not arranged in direct contact with each other.

[0083] The term "at least one" should be understood to include any and all combinations of one or more of the relevant listed elements. For example, "at least one of a first element, a second element, and a third element" means all combinations of two or more elements selected from the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0084] The term "surrounding" used herein includes situations where one or more of the relevant elements are at least partially surrounded as well as situations where one or more of the relevant elements are completely surrounded. Similarly, the term "covering" used herein includes situations where one or more of the relevant elements are at least partially covered as well as situations where one or more of the relevant elements are completely covered. For example, if the encapsulation layer surrounds the weir pattern, this can be interpreted as the encapsulation layer at least partially surrounding the weir pattern. However, in some embodiments, the encapsulation layer may completely surround the weir pattern. The meaning of the term "surrounding" used herein may be further specified based on the relevant drawings. In the present invention, the terms "surrounding", "at least partially surrounding", "completely surrounding" and the like are used. According to the above definition of "surrounding", when only the term "surrounding" is used in an embodiment, it may refer to situations where one or more of the relevant elements are at least partially surrounded or completely surrounded. A similar explanation applies to the term "covering".

[0085] As will be fully understood by those skilled in the art, the features of the various embodiments of the present invention may be combined or integrated with each other in part or in whole, and may interoperate and drive each other in various technical aspects. The embodiments of the present invention may be implemented independently of each other, or implemented together in a mutually dependent relationship.

[0086] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When reference numerals are added to the elements of each drawing, similar reference numerals may refer to similar elements even if the same elements are shown in other drawings. In addition, for ease of description, the scale of each element shown in the drawings is different from the actual scale, and thus is not limited to the scale shown in the drawings.

[0087] Figure 1A is a plan view illustrating a display device according to the present invention, Figure 1B is a side view illustrating a display device according to the present invention. Figures 2A to 2D yes Figure 1A An enlarged view of area "B1" is shown in FIG.

[0088] Reference Figure 1A and Figure 1B , a display device according to the present invention may include a first substrate 100 including a display area AA and a plurality of pixels P arranged at a first interval D1 in the display area AA of the first substrate 100 .

[0089] The first substrate 100 may include a first surface 100a, a second surface 100b and an outer surface OS. The first surface 100a of the first substrate 100 may be defined as a front surface, a top surface or an upper surface facing the front surface (or forward direction) of the display device. The second surface 100b of the first substrate 100 may be defined as a back surface, a rear surface, a bottom surface or a lower surface facing the back surface (or backward direction) of the display device. The outer surface OS of the first substrate 100 may be defined as a side surface, a side surface or a sidewall extending along the periphery between the first surface 100a and the second surface 100b, facing the side (or lateral direction) of the display device and exposed to the surrounding air. In the case where some multiple display devices are connected together, the outer surface (OS) (or outermost surface OS) of the display device located at the periphery of the connected multiple display devices may be surrounded by surrounding air. For example, when the first substrate 100 has a hexahedral structure, the outer surface OS of the first substrate 100 may include the side surface of the hexahedral structure.

[0090] The outer surface OS of the first substrate 100 may be formed parallel to the thickness direction Z of the display device. For example, the outer surface OS of the first substrate 100 may include: a first outer surface parallel to a first direction X, a second outer surface parallel to the first outer surface, a third outer surface parallel to a second direction Y (the second direction Y is transverse (or intersecting) the first direction X) and connected between one end of the first outer surface and one end of the second outer surface, and a fourth outer surface parallel to the third outer surface and connected between the other end of the first outer surface and the other end of the second outer surface. The first direction X may be a first longitudinal direction (e.g., a transverse direction) of the first substrate 100 or the display device, and the second direction Y may be a second longitudinal direction (e.g., a longitudinal direction) of the first substrate 100 or the display device.

[0091] The display area AA of the first substrate 100 may be an area for displaying an image and may be referred to as a display portion or an active portion. The size of the display area AA may be the same or substantially the same as that of the first substrate 100 (or display device). For example, the size of the display area AA may be the same as the overall size of the first surface 100a of the first substrate 100. Therefore, the display area AA may be implemented (or provided) on the entire front surface of the first substrate 100, and thus the first substrate 100 may not include an opaque non-display area provided along an edge portion of the first surface 100a to surround the entire display area AA. Therefore, the entire front surface of the display device may implement the display area AA.

[0092] The end portion (or outermost portion) AAa of the display area AA may overlap with the outer surface OS of the first substrate 100 or may be substantially aligned with the outer surface OS of the first substrate 100. For example, the side surface AAa of the display portion AA may be substantially coplanar with the outer surface OS of the first substrate 100. In other words, the side surface of the display portion AA and the outer surface OS of the first substrate 100 may be aligned substantially at the same position. The side surface AAa of the display portion AA may not be surrounded by a separate mechanism and may be surrounded only by air. As another example, the side surface of the display portion AA may overlap with the outer surface OS of the first substrate 100 or may be substantially aligned with the outer surface OS of the first substrate 100. That is, all side surfaces of the display portion AA may be provided as a structure that is in direct contact with the air and is not surrounded by a separate mechanism.

[0093] With respect to the thickness direction Z of the first substrate 100, the end AAa of the display area AA and the vertical extension line VL extending perpendicularly from the outer surface OS of the first substrate 100 may overlap with each other or may be substantially aligned in the same plane. For example, the first end (or upper end) of the display area AA may be the first outer surface (or upper sidewall) of the first substrate 100, the second end (or lower end) of the display area AA may be the second outer surface (or lower sidewall) of the first substrate 100, the third end (or left end) of the display area AA may be the third outer surface (or left sidewall) of the first substrate 100, and the fourth end (or right end) of the display area AA may be the fourth outer surface (or right sidewall) of the first substrate 100. Therefore, the outer surface OS of the first substrate 100 corresponding to the end AAa of the display area AA may be surrounded by air, and thus the display device according to the present invention may have an air-bezel structure or a bezel-less structure, in which the end AAa of the display area AA (or the side surface of the display area AA) is surrounded by air rather than by an opaque non-display area.

[0094] The display area (or display portion) AA according to an embodiment may include a plurality of pixel areas PA.

[0095] According to one embodiment, a plurality of pixel areas PA may be arranged (or set) at a first interval D1 in the display area AA of the first substrate 100. Two pixel areas PA adjacent to each other along the first direction X and the second direction Y of the first substrate 100 may have the same first interval D1 without the error range of the manufacturing process. The first interval D1 may be the pitch (or pixel spacing) between two adjacent pixel areas PA. For example, the first interval D1 may be the shortest distance (or shortest length) between the center portions of two adjacent pixel areas PA. Alternatively, the pixel spacing may be the dimension between one end and the other end of the pixel area PA parallel to the first direction X. In addition, as another example, the pixel spacing may refer to the dimension between one end and the other end of the pixel area PA parallel to the second direction Y.

[0096] Each of the plurality of pixel areas PA may have a first length L1 parallel to the first direction X and a second length L2 parallel to the second direction Y. Each of the first length L1 and the second length L2 may be the same as the first interval D1. For example, the first length L1 may be referred to as a first width, a horizontal length, or a horizontal width. The second length L2 may be referred to as a second width, a vertical length, or a vertical width. The first length L1 or the second length L2 of the pixel area PA may be referred to as a pixel pitch.

[0097] The second interval D2 between each outermost pixel area PAo among the plurality of pixel areas PA and the outer surface OS of the first substrate 100 may be half or less than the first interval D1, so that the entire front surface of the first substrate 100 (or the entire front surface of the display device) is referred to as the display area AA. For example, the second interval D2 may be the shortest distance (or shortest length) between the center portion of the outermost pixel area PAo and the outer surface OS of the first substrate 100.

[0098] When the second interval D2 is greater than half of the first interval D1, the first substrate 100 may have a size larger than the display area AA due to the area between the end of the outermost pixel area PAo (or the end AAa of the display area AA) and the outer surface OS of the first substrate 100, and thus the area between the end of the outermost pixel area PAo and the outer surface OS of the first substrate 100 will be set as a non-display area surrounding the entire display area AA. Therefore, the first substrate 100 will inevitably include a frame area based on the non-display area surrounding the entire display area AA. On the other hand, when the second interval D2 is half of the first interval D1 or less, the end of the outermost pixel area PAo (or the end AAa of the display area AA) may overlap with the outer surface OS of the first substrate 100, or may be set in the space outside the outer surface OS of the first substrate 100, and thus the display area AA can be realized (or set) on the entire front surface of the first substrate 100.

[0099] The display area (or display portion) AA according to an embodiment may include an outermost pixel area PAo and an inner pixel area (or inner pixel area) PAi.

[0100] Among the plurality of pixel areas PA, the outermost pixel area PAo may be disposed along an edge portion (or peripheral portion) of the first substrate 100. For example, the outermost pixel area PAo may be referred to as a first pixel area PA1.

[0101] The inner pixel area PAi may be a pixel area other than the outermost pixel area PAo among the plurality of pixel areas PA, or may be surrounded by the outermost pixel area PAo. The inner pixel area PAi may be referred to as a second pixel area PA2.

[0102] Each of the plurality of pixels P may be arranged in a corresponding pixel area PA among the plurality of pixel areas PA defined on the first surface 100a of the first substrate 100. For example, the display area AA may be a pixel array including a plurality of pixels P arranged on the first substrate 100. The pixels P of the pixel array may be adjacent to each other along the first direction X and the second direction Y. For example, the pixels P of the pixel array may be adjacent to each other along the first direction X and the second direction Y without a separation space (or a separation space). As another example, the plurality of outermost pixels Po of the pixel array may match each other to overlap on the outer surface of the first substrate 100, or may be aligned on the same plane. For example, each pixel P of the pixel array may be arranged on the first substrate 100 to have a pixel pitch D1 along the first direction X and the second direction Y, and the interval D2 between the center portion of each outermost pixel Po and the outer surface OS of the first substrate 100 may be half of the pixel pitch D1 or less.

[0103] The display area (or display portion) AA according to an embodiment may include outermost pixels Po and inner pixels (or inside pixels) Pi.

[0104] The outermost pixel Po may be disposed at an edge portion (or peripheral portion) of the first substrate 100 among the plurality of pixel areas PA. For example, the outermost pixel Po may be referred to as a first pixel P1 disposed in the outermost pixel area PAo.

[0105] The inner pixel Pi may be a pixel other than the outermost pixel Po among the plurality of pixels P, or may be disposed to be surrounded by the outermost pixel Po. For example, the inner pixel Pi may be referred to as a second pixel P2. The inner pixel Pi (or the second pixel P2) may be implemented to have a different configuration or structure from the outermost pixel Po (or the first pixel P1).

[0106] The second interval D2 between each outermost pixel Po among the plurality of pixels P and the outer surface OS of the first substrate 100 may be half or less than the first interval D1, so that the entire front surface of the first substrate 100 (or the entire front surface of the display device) is referred to as the display area AA. The first interval D1 may be the shortest distance (or shortest length) between the center portions of two adjacent pixels P. The second interval D2 may be the shortest distance (or shortest length) between the center portion of the outermost pixel Po and the outer surface OS of the first substrate 100.

[0107] like Figure 2A As shown in FIG, each of the plurality of pixels P according to an embodiment may include a central portion Pc and an edge portion (or peripheral portion) Pe surrounding the entire central portion Pc, the central portion Pc including a plurality of light emitting areas PA.

[0108] The center of the central portion Pc may overlap with the central portion of the pixel P. The central portion Pc may be referred to as an opening portion of the pixel P or a light emitting portion.

[0109] The central portion Pc according to an embodiment may include first to fourth light emitting areas EA1 to EA4 disposed relative to the central portion of the pixel P. For example, the first to fourth light emitting areas EA1 to EA4 may be adjacent to each other along the first direction X and the second direction Y. For example, the first to fourth light emitting areas EA1 to EA4 may directly contact each other along the first direction X and the second direction Y without a separation space (or partition space).

[0110] The first to fourth light emitting areas EA1 to EA4 may each have a square shape and may be arranged in a 2×2 form or a quad form. According to another embodiment, the first to fourth light emitting areas EA1 to EA4 may each have a rectangular shape including a short side parallel to the first direction X and a long side parallel to the second direction Y, and may be arranged in a 1×4 form or a 1×4 stripe form, for example.

[0111] The first light-emitting area EA1 may be configured to emit light of a first color, the second light-emitting area EA2 may be configured to emit light of a second color, the third light-emitting area EA3 may be configured to emit light of a third color, and the fourth light-emitting area EA4 may be configured to emit light of a fourth color. For example, each of the first to fourth colors may be different. For example, the first color may be red, the second color may be blue, the third color may be white, and the fourth color may be green. As another example, some of the first to fourth colors may be the same. For example, the first color may be red, the second color may be a first green, the third color may be a second green, and the fourth color may be blue.

[0112] According to another embodiment, Figure 2B As shown in , the center portion Pc may include first to third light-emitting areas EA1 to EA3 arranged relative to the center portion of the pixel P. In this case, the first to third light-emitting areas EA1 to EA3 may each have a rectangular shape including a short side parallel to the first direction X and a long side parallel to the second direction Y, and may be arranged in a 1×3 form or a 1×3 stripe form, for example. For example, the first color may be red, the second color may be blue, and the third color may be green.

[0113] The edge portion Pe may be provided in the pixel area PA to surround the entire central portion Pc, thereby defining the pixel area PA or the central portion Pc of the pixel P. The edge portion Pe may have a size wider than the central portion Pc. The edge portion Pe may be referred to as a non-opening portion, a non-light emitting portion, or a pixel separation portion of the pixel P.

[0114] Refer again Figure 2A , each of the plurality of pixels P according to another embodiment may include first to fourth sub-pixels SP1 to SP4 .

[0115] The first subpixel SP1 may be disposed in the first subpixel region of the pixel area PA, the second subpixel SP2 may be disposed in the second subpixel region of the pixel area PA, the third subpixel SP3 may be disposed in the third subpixel region of the pixel area PA, and the fourth subpixel SP4 may be disposed in the fourth subpixel region of the pixel area PA. For example, with respect to the center portion of the pixel area PA, the first subpixel SP1 may be in the upper left region of the pixel area PA, the second subpixel SP2 may be in the upper right region of the pixel area PA, the third subpixel SP3 may be in the lower left region of the pixel area PA, and the fourth subpixel SP4 may be in the lower right region of the pixel area PA.

[0116] The first to fourth sub-pixels SP1 to SP4 may include a plurality of emission areas EA1 to EA4 and a plurality of circuit areas CA1 to CA4, respectively.

[0117] The light emitting areas EA1 to EA4 may be disposed at the central portion Pc of the pixel P, or may be disposed close to the central portion of the pixel P.

[0118] Each of the circuit areas CA1 to CA4 may be disposed adjacent to a corresponding one of the emission areas EA1 to EA4 , and each of the circuit areas CA1 to CA4 may include a signal line, a power line, and a circuit for causing a corresponding sub-pixel to emit light.

[0119] According to an embodiment, the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have the same size in the corresponding pixel P or pixel area PA. For example, the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may have a uniform quadrilateral structure or a non-uniform stripe structure. For example, the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may be implemented to have the same size around (or near) the center portion of the pixel P.

[0120] According to another embodiment, Figure 2C As shown in FIG, each of the emission areas EA1 to EA4 of each of the first to fourth subpixels SP1 to SP4 may have different sizes in the corresponding pixel P or pixel area PA. For example, the emission areas EA1 to EA4 of the first to fourth subpixels SP1 to SP4 may have a non-uniform quadrilateral structure or a non-uniform stripe structure. For example, the emission areas EA1 to EA4 of the first to fourth subpixels SP1 to SP4 may be implemented to have different sizes around (or near) the center portion of the pixel P.

[0121] The size of each of the emission areas EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quadrilateral structure (or a non-uniform stripe structure) may be set based on resolution, luminous efficiency, or image quality. For example, when the emission areas EA1 to EA4 have a non-uniform quadrilateral structure (or a non-uniform stripe structure), among the emission areas EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the emission area EA4 of the green sub-pixel SP4 may have the smallest size, and the emission area EA3 of the white sub-pixel SP3 may have the largest size.

[0122] In the first to fourth sub-pixels SP1 to SP4 according to another embodiment, each of the emission areas EA1 to EA4 may be spaced apart from each other along the first direction X and the second direction Y, but is not limited thereto and may be adjacent to each other.

[0123] Alternatively, if Figure 2D As shown in , in order to increase the aperture ratio of the subpixels SP1 to SP4 corresponding to the size of the emission areas EA1 to EA4 or to reduce the pixel pitch D1 as the resolution of the pixel P is higher, the emission areas EA1 to EA4 of the first to fourth subpixels SP1 to SP4 may extend to the circuit areas CA1 to CA4 to overlap with some or all of the circuit areas CA1 to CA4. For example, each of the emission areas EA1 to EA4 of the first to fourth subpixels SP1 to SP4 may be implemented on the first substrate 100 to overlap with a corresponding circuit area of ​​the circuit areas CA1 to CA4. In this case, the emission areas EA1 to EA4 may have a size equal to or larger than that of the circuit areas CA1 to CA4.

[0124] Refer again Figures 1A to 2D The display device according to the present invention may further include a pad portion 110 including a plurality of pads disposed in the display area AA and selectively connected to the plurality of pixels P. For example, the pad portion 110 may be a first pad portion or a front pad portion.

[0125] The pad portion 110 may be included in the outermost pixel Po located at the first edge portion parallel to the first direction X in the first surface 100a of the first substrate 100. That is, the outermost pixel Po located at the first edge portion of the first substrate 100 may include at least one of the plurality of pads. Therefore, the plurality of pads may be disposed or included within the display area AA, and thus a non-display area (or border area) based on the pad portion 110 may not be formed or exist on the first substrate 100. Therefore, the outermost pixel Po (or first pixel P1) may include the pad portion 110, and thus may be implemented to have a different configuration or structure than the inner pixel Pi (or second pixel P2) that does not include the pad portion 110.

[0126] For example, when the pad portion 110 is not disposed within the outermost pixel Po but is disposed between the outermost pixel Po and the outer surface OS of the first substrate 100, the first substrate 100 will include a non-display area (or non-display portion) corresponding to the area where the pad portion 110 is disposed; due to the non-display area, the second interval D2 between the outermost pixel Po and the outer surface OS of the first substrate 100 will be greater than half of the first interval D1, the entire first substrate 100 will not be implemented as the display area AA, and a separate frame (or separate structure) will be required to cover the non-display area. On the other hand, the pad portion 110 according to the present invention can be disposed between the emission areas EA1 to EA4 of the outermost pixel Po and the outer surface OS of the first substrate 100 and can be included within the outermost pixel Po, so that a non-display area (or frame area) based on the pad portion 110 will not be formed or exist between the outermost pixel Po and the outer surface OS of the first substrate 100.

[0127] Therefore, the display device according to the present invention may have an air-bezel structure, in which the entire first substrate 100 including the pad portion 110 is implemented as the display area AA, and thus all outer surfaces of the first substrate 100 (or outer surfaces of the display panel) OS aligned with the end of the display area AA are surrounded by air.

[0128] Figure 3A and Figure 3B are diagrams illustrating a bezel area of ​​a display device according to a comparative example and an air bezel of a display device according to the present invention.

[0129] Reference Figure 3A In the display device according to the comparative example, it can be seen that the display device includes a frame area (or non-display area) BA surrounding the entire display area AA where an image is displayed. Consequently, a black frame area BA exists surrounding the image displayed in the display area AA. In a multi-display device in which a plurality of display devices according to the comparative example are arranged in a grid pattern, a sense of discontinuity (or discontinuity) in the image appears at the boundary between adjacent display devices due to the frame area BA of each display device.

[0130] like Figure 3BAs shown in , in the display device according to the present invention, it can be seen that the display device does not include a frame area (or non-display area) surrounding the entire display area AA displaying the image, but has an air frame structure in which the display area AA is surrounded by air, so that there is no frame around the image displayed by the display area AA. For example, the outer surface OS of the first substrate 100 may be exposed to the outside of the display device or may be surrounded by air, and the display portion AA implemented as being overlaid on the first substrate 100 may be arranged so that the side surface (or end) AAa of the display portion AA substantially matches the outer surface OS of the first substrate 100. As another example, the side surface (or end) AAa of the display portion AA and the outer surface OS of the first substrate 100 may be arranged and arranged on the same plane substantially aligned with each other, directly exposed to the outside of the display device and directly surrounded by air. In a multi-screen display device in which a plurality of display devices according to the present invention are arranged as a lattice type, since a frame area is not provided in each display device, no sense of discontinuity (or discontinuity) of the image occurs in the boundary portion between adjacent display devices.

[0131] Figure 4 is a perspective view illustrating a display device 10 according to an embodiment of the present invention, Figure 5 is a diagram illustrating a rear surface of a display apparatus 10 according to an embodiment of the present invention.

[0132] Reference Figure 4 and Figure 5 , a display device 10 according to an embodiment of the present invention may include a first substrate 100 , a second substrate 200 , a bonding member 300 , and a wiring portion 400 .

[0133] The first substrate 100 may be referred to as a display substrate, a pixel array substrate, an upper substrate, a front substrate, or a base substrate. The first substrate 100 may include a glass material or a plastic material. The first substrate 100 may be a glass substrate, or may be a bendable or flexible thin glass substrate or a plastic substrate. According to one embodiment, the first substrate 100 may be a glass substrate or tempered glass. For example, the tempered glass may include sapphire glass, Gorilla Glass, or a stack of these.

[0134] The display device 10 according to an embodiment may include a plurality of pixel driving lines and a plurality of pixels P disposed on a first substrate 100 .

[0135] The pixel drive lines may be provided on the first surface 100a of the first substrate 100 and may transmit signals required for driving (lighting) each of the plurality of pixels P. For example, the pixel drive lines may include a data line DL, a gate line GL, a pixel drive power line (or first power line) PL, and a pixel common power line (or second power line) CPL. Furthermore, the pixel drive lines may further include a reference power line (or sensing line) RL based on the driving (or operation) of the pixel circuit provided in the circuit region of the pixel P.

[0136] Each pixel driving line according to an embodiment may be electrically connected to a first pad portion 110 provided at a first edge portion of the first surface 100a of the first substrate 100. The first pad portion 110 may be included in a plurality of outermost pixels Po located at a first edge portion of the first substrate 100 parallel to the first direction X. Here, the first edge portion of the first surface 100a of the first substrate 100 may include a first outer surface (or one side surface) OS1a among the outer surfaces OS of the first substrate 100.

[0137] The first pad portion 110 may include a plurality of first pads disposed parallel to each other along a first direction X on the passivation layer 101d exposed at a first edge portion of the first surface 100a of the first substrate 100 (see FIG. Figure 16 )superior.

[0138] According to one embodiment, the plurality of first pads may be divided (or classified) into a plurality of first data pads, a plurality of first pixel driving power pads, and a plurality of first pixel common power pads. Therefore, the first pad portion 110 may include: a first data pad portion including a plurality of first data pads connected to a plurality of data lines DL; a first pixel driving power pad portion including a plurality of first pixel driving power pads connected to a plurality of pixel driving power lines PL; and a first pixel common power pad portion including a plurality of first pixel common power pads connected to a plurality of pixel common power lines CPL. Alternatively, the first pad portion 110 may further include a first reference power pad portion including a plurality of first reference power pads connected to a plurality of reference power lines RL.

[0139] A plurality of pixels P may be respectively arranged in a plurality of pixel areas PA arranged at a first interval (or first interval) D1 along a first direction X and a second direction Y. Each of the plurality of pixels P may include a self-luminous device (or self-luminous element) and a pixel circuit. The self-luminous device emits light based on a top emission type and irradiates the light onto a portion located above the first surface 100a of the first substrate 100 according to a signal provided through a corresponding pixel driving line adjacent thereto, and the pixel circuit is connected to the pixel driving line adjacent thereto so that the self-luminous device emits light. For example, the pixel circuit may include a driving thin film transistor (TFT) that provides a data current corresponding to a data signal provided through a data line DL to the self-luminous device.

[0140] The distance between the outermost pixel among the plurality of pixels P and the outer surface OS of the first substrate 100 can be half of the first distance D1 or less. The second distance D2 between the center portion of the outermost pixel and the outer surface OS of the first substrate 100 can be half of the first distance D1 or less, so that the entire front surface of the first substrate 100 (or the entire front surface of the display device) can be implemented as the display area AA. Therefore, the display device 10 according to the present invention can have an air frame structure in which the display area AA is surrounded by air.

[0141] The first substrate 100 may further include a first chamfer provided at a corner portion between the first surface 100a and the outer surface OS. The first chamfer may minimize damage to the corner portion of the first substrate 100 caused by a physical impact applied from the outside and may prevent disconnection of the wiring portion 400 caused by the corner portion of the first substrate 100. For example, the first chamfer may have an angle of 45 degrees, but is not limited thereto. The first chamfer may be achieved by a chamfering process using a cutting wheel or a polishing wheel. Therefore, each outer surface of the first pad of the first pad portion 110 provided to be in contact with the first chamfer may include an inclined surface inclined at an angle corresponding to the angle of the first chamfer by removing or polishing the corresponding portion together with the corner portion of the first substrate 100 through a chamfering process. For example, when the first chamfer is formed at an angle of 45 degrees between the outer surface OS of the first substrate 100 and the first surface 100a, the outer surface of the first pad may be formed at an angle of 45 degrees.

[0142] The first substrate 100 may further include a gate driving circuit 150 disposed in the display area AA.

[0143] The gate driving circuit 150 may be disposed in the display area AA to provide scanning signals (or gate signals) to the pixels P disposed on the first substrate 100. The gate driving circuit 150 may simultaneously provide scanning signals to the pixels P disposed in a horizontal row parallel to the first direction X. For example, the gate driving circuit 150 may provide at least one scanning signal to the pixels P disposed in one horizontal row through at least one gate line GL.

[0144] The gate driving circuit 150 according to one embodiment may be implemented using a shift register including a plurality of stage circuit units 1501 to 150m (m is an integer of 2 or greater). That is, the display device according to the present invention may include a shift register disposed in the display area AA of the first substrate to provide a scan signal to the pixel P.

[0145] Each of the plurality of stage circuit units 1501 to 150m may include a plurality of branch circuits 1511 to 151n (n is an integer of 2 or greater) spaced apart from one another in each horizontal row along the first direction X (i.e., along the length direction of the gate line) of the first substrate 100. The plurality of branch circuits 1511 to 151n may include at least one TFT (or branch TFT) and may be disposed between two adjacent pixels P (or pixel areas PA) within a horizontal row along the first direction X. For example, the branch circuits 1511 to 151n may be disposed one by one between two adjacent pixels P (or pixel areas PA) within a horizontal row along the first direction X. Each of the plurality of stage circuit units 1501 to 150m may generate scan signals in a predetermined sequence in response to gate control signals provided via the first pad portion 110, and may provide the scan signals to the gate line GL. For example, the gate control signals may include a start signal, a plurality of shift clocks, at least one gate drive power supply, and at least one gate common power supply.

[0146] The first substrate 100 may further include a plurality of gate control line groups GCL that are spaced apart from each other or individually disposed between the plurality of pixels P and connected to the gate driving circuit 150. Each gate control line group GCL may be selectively connected to a plurality of branch circuits 1511 to 151n disposed in the plurality of stage circuit units 1501 to 150m, respectively. For example, the plurality of gate control line groups GCL may be dispersedly disposed between the plurality of pixels P.

[0147] According to one embodiment, the gate control line group GCL may include a start signal line, a plurality of shift clock lines, at least one gate drive power line, and at least one gate common power line. According to one embodiment, the plurality of shift clock lines may be divided (or classified) into a plurality of scan clock lines and a plurality of carry clock lines. Here, the plurality of carry clock lines may be omitted.

[0148] The first pad portion 110 may further include a first gate pad portion including a plurality of first gate pads connected to the gate control line group GCL.

[0149] According to one embodiment, the plurality of first gate pads can be divided (classified) into: a first start signal pad connected to a start signal line, a plurality of first shift clock pads respectively connected to a plurality of shift clock lines, at least one first gate drive power pad connected to at least one gate drive power line, and at least one first gate common power pad connected to at least one gate common power line. Therefore, the first gate pad portion may include a first start signal pad, a plurality of first shift clock pads, at least one first gate drive power pad, and at least one first gate common power pad. According to one embodiment, the plurality of first shift clock pads may include: a plurality of first scan clock pads respectively connected to a plurality of scan clock lines; and a plurality of first carry clock pads respectively connected to a plurality of carry clock lines. Here, the plurality of first carry clock pads may be omitted.

[0150] The second substrate 200 may be referred to as a wiring substrate, a wiring substrate, a lower substrate, a rear substrate, or wiring glass. The second substrate 200 may be made of glass or plastic. The second substrate 200 may be a glass substrate, or may be a thin, bendable or flexible glass or plastic substrate. According to one embodiment, the second substrate 200 may be made of the same material as the first substrate 100. For example, the size of the second substrate 200 may be the same or substantially the same as the size of the first substrate 100.

[0151] The second substrate 200 may be bonded (or connected) to the second surface 100b of the first substrate 100 using a bonding member 300. The second substrate 200 may include a front surface facing the second surface 100b of the first substrate 100 or bonded to the bonding member 300; a rear surface (or back surface) 200b opposite the front surface; and an outer surface OS between the front and rear surfaces. The second substrate 200 may transmit signals to the pixel driving lines and increase the rigidity of the first substrate 100.

[0152] The display apparatus 10 according to an embodiment may further include a second pad portion 210 disposed on the second substrate 200 .

[0153] The second pad portion 210 may be provided at a first edge portion of the rear surface 200b of the second substrate 200 overlapping the first pad portion 110 provided on the first substrate 100. The first edge portion of the rear surface 200b of the second substrate 200 may include a first outer surface (or one surface) OS1b of the outer surfaces OS of the second substrate 200.

[0154] The second pad portion 210 may include a plurality of second pads arranged at intervals along the first direction X so as to overlap the pads of the first pad portion 110 , respectively.

[0155] According to one embodiment, the plurality of second pads may be divided (or classified) into a plurality of second data pads, a plurality of second pixel driving power pads, and a plurality of second pixel common power pads. Therefore, the second pad portion 210 may include: a second data pad portion including a plurality of second data pads, a second gate pad portion including a plurality of second gate pads, a second pixel driving power pad portion including a plurality of second pixel driving power pads, and a second pixel common power pad portion including a plurality of second pixel common power pads. Optionally, the second pad portion 210 may further include a second reference power pad portion, the second reference power pad portion including a plurality of second reference power pads.

[0156] According to one embodiment, the plurality of second gate pads can be divided (or classified) into a second start signal pad, a plurality of second shift clock pads, at least one second gate drive power pad, and at least one second gate common power pad. Therefore, the second gate pad portion can include a second start signal pad, a plurality of second shift clock pads, at least one second gate drive power pad, and at least one second gate common power pad. According to one embodiment, the plurality of second shift clock pads can be divided (or classified) into a plurality of second scan clock pads and a plurality of second carry clock pads. Here, the plurality of second carry clock pads can be omitted.

[0157] The display device 10 according to an embodiment may further include a third pad portion (or input pad portion) 230 and a connection portion 250 provided on the second substrate 200 .

[0158] The third pad portion 230 may be provided on the rear surface 200b of the second substrate 200. For example, the third pad portion 230 may be provided in a middle portion adjacent to the first edge portion of the rear surface 200b of the second substrate 200. The third pad portion 230 according to one embodiment may include a plurality of third pads (or input pads) spaced apart from each other by a certain interval.

[0159] The connection portion 250 may be provided between the second pad portion 210 and the third pad portion 230 on the rear surface 200b of the second substrate 200. For example, the connection portion 250 may include a plurality of connection lines that individually (or separately) connect the second pad of the second pad portion 210 to the third pad of the third pad portion 230.

[0160] The second substrate 200 may further include a second chamfer provided at a corner portion between the rear surface 200b and the outer surface OS. The second chamfer may minimize damage to the corner portion of the second substrate 200 caused by a physical impact applied from the outside and may prevent disconnection of the wiring portion 400 caused by the corner portion of the second substrate 200. For example, the second chamfer may have an angle of 45 degrees, but is not limited thereto.

[0161] The bonding member 300 may be disposed between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 may be bonded relative to each other via the bonding member 300. For example, the second surface 100b of the first substrate 100 may be bonded to one surface of the bonding member 300, and the front surface of the second substrate 200 may be bonded to the other surface of the bonding member 300. Therefore, the first substrate 100 and the second substrate 200 bonded (or coupled) relative to each other via the bonding member 300 may be referred to as a display panel.

[0162] The wiring portion 400 may be provided to surround the outer surface OS of the first substrate 100 and the outer surface OS of the second substrate 200. According to one embodiment, the wiring portion 400 may include a plurality of wirings, and the plurality of wirings are provided on each of the first outer surface (or one surface) OS1a of the outer surface OS of the first substrate 100 and the first outer surface (or one surface) OS1b of the outer surface OS of the second substrate 200. Each of the plurality of wirings may be formed to surround each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200. For example, the plurality of wirings may be respectively (or individually) connected to the pixel driving lines located on the first substrate 100 and may be directly connected to the pixel driving lines. As another example, the plurality of wirings may be respectively (or individually) connected to the pixel driving lines through the pads of the first pad portion 110 provided on the first substrate 100; in this case, since the size increases based on the pads, the resistance of each pixel driving line and / or the voltage drop (or IR drop) of the signal applied to the pixel driving line may be reduced.

[0163] The plurality of wirings according to an embodiment may be divided (or classified) into a plurality of data wirings, a plurality of gate wirings, a plurality of pixel driving power wirings, and a plurality of pixel common power wirings.

[0164] According to another embodiment, the wiring portion 400 may include a data wiring portion, a gate wiring portion, a pixel driving power wiring portion, and a pixel common power wiring portion.

[0165] The data wiring portion (or first wiring portion) may electrically connect the first data pad portion of the first pad portion 110 to the second data pad portion of the second pad portion 210. The data wiring portion according to one embodiment may include a plurality of data wirings 410. The plurality of data wirings (or first wirings) 410 may individually (or separately) connect the plurality of first data pads provided in the first pad portion 110 to the plurality of second data pads located in the second pad portion 210.

[0166] The gate wiring portion (or second wiring portion) may electrically connect the first gate pad portion of the first pad portion 110 to the second gate pad portion of the second pad portion 210. The gate wiring portion according to one embodiment may include a plurality of gate wirings 430. The plurality of gate wirings (or second wirings) 430 may individually (or separately) connect the plurality of first gate pads provided in the first pad portion 110 to the plurality of second gate pads located in the second pad portion 210.

[0167] According to one embodiment, the plurality of gate wirings 430 can be divided (or classified) into a start signal wiring, a plurality of shift clock wirings, at least one gate drive power wiring, and at least one gate common power wiring. Therefore, the gate wiring portion may include a start signal wiring, a plurality of shift clock wirings, at least one gate drive power wiring, and at least one gate common power wiring. According to one embodiment, the plurality of shift clock wirings can be divided (or classified) into a plurality of scan clock wirings and a plurality of carry clock wirings. Here, the plurality of carry clock wirings may be omitted.

[0168] The start signal wiring may electrically connect a first start signal pad provided in the first pad portion 110 to a second start signal pad provided in the second pad portion 210 .

[0169] The plurality of shift clock wirings may individually (or separately) connect the plurality of first shift clock pads provided in the first pad portion 110 to the plurality of second shift clock pads provided in the second pad portion 210 .

[0170] The plurality of scan clock wirings among the plurality of shift clock wirings according to an embodiment may individually (or separately) connect the plurality of first scan clock pads provided in the first pad portion 110 to the plurality of second scan clock pads provided in the second pad portion 210 .

[0171] The plurality of carry clock wirings among the plurality of shift clock wirings according to an embodiment may individually (or separately) connect the plurality of first carry clock pads provided in the first pad portion 110 to the plurality of second carry clock pads provided in the second pad portion 210 .

[0172] At least one gate driving power supply wiring line may electrically connect at least one first gate driving power supply pad provided in the first pad portion 110 to at least one second gate driving power supply pad provided in the second pad portion 210 .

[0173] At least one gate common power wiring may electrically connect at least one first gate common power pad provided in the first pad portion 110 to at least one second gate common power pad provided in the second pad portion 210 .

[0174] The pixel driving power supply wiring portion (or the third wiring portion) may electrically connect the first pixel driving power supply pad portion of the first pad portion 110 to the second pixel driving power supply pad portion of the second pad portion 210. The pixel driving power supply wiring portion according to one embodiment may include a plurality of pixel driving power supply wirings 450. The plurality of pixel driving power supply wirings (or the third wirings) 450 may individually (or separately) connect the plurality of first pixel driving power supply pads provided in the first pad portion 110 to the plurality of second pixel driving power supply pads provided in the second pad portion 210.

[0175] The pixel common power wiring portion (or fourth wiring portion) may electrically connect the first pixel common power pad portion of the first pad portion 110 to the second pixel common power pad portion of the second pad portion 210. The pixel common power wiring portion according to one embodiment may include a plurality of pixel common power wirings 470. The plurality of pixel common power wirings (or fourth wirings) 470 may individually (or separately) connect the plurality of first pixel common power pads provided in the first pad portion 110 to the plurality of second pixel common power pads provided in the second pad portion 210.

[0176] The wiring portion 400 according to an embodiment may further include a reference power wiring portion.

[0177] The reference power wiring portion (or fifth wiring portion) may electrically connect the first reference power pad portion of the first pad portion 110 to the second reference power pad portion of the second pad portion 210. The reference power wiring portion according to one embodiment may include a plurality of reference power wirings 490. The plurality of reference power wirings (or fifth wirings) 490 may individually (or separately) connect the plurality of first reference power pads provided in the first pad portion 110 to the plurality of second reference power pads provided in the second pad portion 210.

[0178] The display device 10 according to an embodiment of the present invention may further include a driving circuit unit 500 .

[0179] The driving circuit unit 500 can drive the pixels P disposed on the first substrate 100 or cause them to emit light based on the digital video data and timing synchronization signals provided by the display driving system, so that the display area AA displays an image corresponding to the image data. The driving circuit unit 500 can be connected to the third pad portion 230 disposed on the rear surface 200b of the second substrate 200 and can output data signals, gate control signals, and driving power for driving the pixels P disposed on the first substrate 100 (or causing them to emit light) to the third pad portion 230. For example, the driving circuit unit 500 can have a size smaller than that of the second substrate 200, and thus can be covered by the second substrate 200 and can be not exposed on the outer surface of the second substrate 200 or the outer surface of the first substrate 100.

[0180] The driving circuit unit 500 according to an embodiment may include a flexible circuit film 510 , a driving integrated circuit (IC) 530 , a printed circuit board (PCB) 550 , and a timing controller 570 .

[0181] The flexible circuit film 510 can be connected to the third pad portion 230 provided on the rear surface 200b of the second substrate 200. The flexible circuit film 510 according to one embodiment can be a tape carrier package (TCP) or a chip on film (COF). For example, one edge portion (or output bonding portion) of the flexible circuit film 510 can be attached to the third pad portion 230 located on the second substrate 200 using a film attachment process using an anisotropic conductive film. The other edge portion (or input bonding portion) of the flexible circuit film 510 can be attached to the PCB 550 using a film attachment process using an anisotropic conductive film.

[0182] The driver IC 530 may be mounted on the flexible circuit film 510. The driver IC 530 may receive sub-pixel data and a data control signal provided from the timing controller 570, and convert the sub-pixel data into an analog data signal based on the data control signal to provide the analog data signal to the corresponding data line DL. For example, the driver IC 530 may be a data driver IC or a source driver IC.

[0183] The driver IC 530 according to an embodiment can generate a plurality of grayscale voltages using a plurality of reference gamma voltages provided from the PCB 550, and can select a grayscale voltage corresponding to sub-pixel data from the plurality of grayscale voltages to output a data signal. The data signal can be provided to the corresponding data line DL via the output bonding portion of the flexible circuit film 510, the third pad portion 230, the connection portion 250, the second pad portion 210, the wiring portion 400, and the first pad portion 110.

[0184] In addition, the driver IC 530 can generate and output pixel driving power and pixel common power required for driving (or emitting light) of the pixel P by using a plurality of reference gamma voltages. For example, the driver IC 530 can select and output a predetermined reference gamma voltage or a predetermined grayscale voltage from among a plurality of reference gamma voltages or a plurality of grayscale voltages as the pixel driving power and the pixel common power.

[0185] In addition, the driver IC 530 may additionally generate and output a reference power source based on driving (or operation) of a pixel circuit provided in a circuit region of the pixel P. For example, the driver IC 530 may select and output a predetermined reference gamma voltage or a predetermined grayscale voltage from among a plurality of reference gamma voltages or a plurality of grayscale voltages as a reference voltage.

[0186] The pixel driving power, the pixel common power, and the reference power may have different voltage levels. The pixel driving power, the pixel common power, and the reference power may be provided to the corresponding pixel driving power line PL, the corresponding pixel common power line CPL, and the corresponding reference power line RL, respectively, via the output bonding portion of the flexible circuit film 510, the third pad portion 230, the connection portion 250, the second pad portion 210, the wiring portion 400, and the first pad portion 110.

[0187] The driving IC 530 may sense characteristic values ​​of driving TFTs provided in the pixels P through a plurality of reference power lines RL provided on the first substrate 100 , generate sensing raw data corresponding to the sensing values, and provide the sensing raw data to the timing controller 570 .

[0188] The PCB 550 may be connected to the other edge portion of the flexible circuit film 510. The PCB 550 may transmit signals and power between elements of the driving circuit unit 500.

[0189] The timing controller 570 may be mounted on the PCB 550 and may receive digital video data and timing synchronization signals provided from the display driving system through a user connector provided on the PCB 550. Alternatively, the timing controller 570 may not be mounted on the PCB 550 but may be implemented in the display driving system or may be mounted on a separate control board connected between the PCB 550 and the display driving system.

[0190] The timing controller 570 may arrange the digital video data based on the timing synchronization signal to generate pixel data matching the pixel arrangement structure provided in the display area AA and may provide the generated pixel data to the driving IC 530 .

[0191] According to one embodiment, when the pixel P includes a white sub-pixel SP, the timing controller 570 may extract white pixel data based on the digital video data (i.e., red input data, green input data, and blue input data to be respectively provided to the corresponding pixel P), reflect offset data based on the extracted white pixel data in each of the red input data, green input data, and blue input data to calculate red pixel data, green pixel data, and blue pixel data, and arrange the calculated red pixel data, green pixel data, blue pixel data, and white pixel data according to the pixel arrangement structure to provide the arranged pixel data to the driver IC 530. For example, the timing controller 570 may convert the red input data, green input data, and blue input data into four-color (e.g., red, green, blue, and white) data based on the data conversion method disclosed in Korean Patent Application Publication No. 10-2013-0060476 or 10-2013-0030598.

[0192] The timing controller 570 may generate each of a data control signal and a gate control signal based on the timing synchronization signal, control the driving timing of the driver IC 530 based on the data control signal, and control the driving timing of the gate driving circuit 150 based on the gate control signal. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a main clock (or dot clock).

[0193] The data control signal according to an embodiment may include a source start pulse, a source shift clock, and a source output signal. The data control signal may be provided to the driving IC 530 through the input bonding portion of the flexible circuit film 510 and the flexible circuit film 510.

[0194] The gate control signal according to one embodiment may include a start signal (or gate start pulse), a plurality of shift clocks, a forward drive signal, and a reverse drive signal. In this case, the plurality of shift clocks may include a plurality of scan clocks whose phases are sequentially shifted and a plurality of carry clocks whose phases are sequentially shifted. In addition, the gate control signal according to one embodiment may further include an external sensing line selection signal for sensing the characteristic value of the driving TFT provided in the pixel P, an external sensing reset signal, and an external sensing control signal. The gate control signal may be provided to the gate drive circuit 150 via the input bonding portion of the flexible circuit film 510, the flexible circuit film 510, the output bonding portion of the flexible circuit film 510, the third pad portion 230, the connection portion 250, the second pad portion 210, the wiring portion 400, and the first pad portion 110.

[0195] The timing controller 570 may drive each of the gate driver circuit 150 and the driver IC 530 based on an external sensing pattern during a predetermined external sensing period, generate compensation data for compensating for characteristic variations of the driving TFT of each pixel P based on the sensing raw data provided from the driver IC 530, and modulate the pixel data based on the generated compensation data. For example, the timing controller 570 may drive each of the gate driver circuit 150 and the driver IC 530 based on the external sensing pattern during each external sensing period corresponding to the blanking period of the vertical synchronization signal (or the vertical blanking period). For example, the external sensing pattern may be executed during a power-on process of the display device, a power-off process of the display device, a process of powering off the display device after long-term driving, or a blanking period of a frame set in real time or periodically.

[0196] According to one embodiment, the timing controller 570 may store the sensing raw data of each pixel P provided from the driver IC 530 in a storage circuit based on the external sensing mode. Furthermore, in the display mode, the timing controller 570 may correct the pixel data to be provided to each pixel based on the sensing raw data stored in the storage circuit and may provide the corrected pixel data to the driver IC 530. Here, the sensing raw data of each pixel may include sequential variation information related to each of the driving TFT and self-luminous device provided in the corresponding sub-pixel. Therefore, in the external sensing mode, the timing controller 570 may sense the characteristic value (e.g., threshold voltage or mobility) of the driving TFT provided in each sub-pixel and, based on this, may correct the pixel data to be provided to each sub-pixel SP, thereby minimizing or preventing degradation of image quality caused by variations in the characteristic values ​​of the driving TFTs of the plurality of sub-pixels SP. The external sensing mode of the display device may be a technique known to those skilled in the art, and thus a detailed description thereof is omitted. For example, the display device according to the present invention may sense a characteristic value of the driving TFT provided in each subpixel SP based on a sensing pattern disclosed in Korean Patent Application Publication No. 10-2016-0093179, 10-2017-0054654, or 10-2018-0002099.

[0197] The driving circuit unit 500 according to an embodiment may further include a power circuit unit 590 .

[0198] The power supply circuit unit 590 may be mounted on the PCB 550 and may generate various source voltages required for displaying an image on the pixels P using an input power source supplied from the outside, and supply the generated source voltages to corresponding circuits. For example, the power supply circuit unit 590 may generate and output logic source voltages required for driving each of the timing controller 570 and the driver IC 530, a plurality of reference gamma voltages supplied to the driver IC 530, and at least one gate driving power supply and at least one gate common power supply required for driving the gate driver circuit 150. The gate driving power supply and the gate common power supply may have different voltage levels.

[0199] Each of the plurality of reference gamma voltages may be provided to the driver IC 530 via the input bonding portion of the flexible circuit film 510 and the flexible circuit film 510. Each of at least one gate driving power source and at least one gate common power source may be provided to the gate driving circuit 150 via the input bonding portion of the flexible circuit film 510, the flexible circuit film 510, the output bonding portion of the flexible circuit film 510, the third pad portion 230, the connection portion 250, the second pad portion 210, the wiring portion 400, and the first pad portion 110.

[0200] Figure 6 yes Figure 4 , which is an enlarged view of a region “ B2 ” shown in , and is a diagram for describing pixels provided on a first substrate.

[0201] Reference Figures 4 to 6 According to the present invention, the first substrate 100 may include a plurality of data lines DLo and DLe, a plurality of gate lines GLo and GLe, a plurality of pixel driving power lines PL, a plurality of pixel common power lines CPL, a plurality of pixels P, a common electrode CE, a plurality of common power contact portions CPCP, a gate control line group GCL, a gate driving circuit 150 and a first pad portion 110.

[0202] A plurality of data lines DLo and DLe may extend long along the second direction Y and may be disposed in the display area AA of the first substrate 100 at predetermined intervals apart from each other along the first direction X. For example, among the plurality of data lines DLo and DLe, the odd-numbered data lines DLo may be disposed at a first edge portion of each of the plurality of pixel areas PA disposed on the first substrate 100 along the second direction Y, and the even-numbered data lines DLe may be disposed at a second edge portion of each of the plurality of pixel areas PA disposed on the first substrate 100 along the second direction Y. Here, with respect to the first direction X, the first edge portion of each of the plurality of pixel areas PA may be a left edge portion of the corresponding pixel area PA, and the second edge portion of each of the plurality of pixel areas PA may be a right edge portion of the corresponding pixel area PA.

[0203] A plurality of gate lines GLo and GLe may extend long along a first direction X and may be arranged in the display area AA of the first substrate 100 at predetermined intervals apart from each other along a second direction Y. For example, among the plurality of gate lines GLo and GLe, odd-numbered gate lines GLo may be arranged at a third edge portion of each of the plurality of pixel areas PA arranged on the first substrate 100 along the first direction X, and even-numbered gate lines GLe may be arranged at a fourth edge portion of each of the plurality of pixel areas PA arranged on the first substrate 100 along the first direction X. Here, with respect to the second direction Y, the third edge portion of each of the plurality of pixel areas PA may be an upper edge portion of the corresponding pixel area PA, and the fourth edge portion of each of the plurality of pixel areas PA may be a lower edge portion of the corresponding pixel area PA.

[0204] The plurality of pixel driving power lines PL may extend long along the second direction Y and may be disposed in the display area AA of the first substrate 100 at predetermined intervals apart from each other along the first direction X. For example, among the plurality of pixel driving power lines PL, the odd-numbered pixel driving power lines PL may be disposed at a first edge portion of the odd-numbered pixel area PA with respect to the first direction X, and the even-numbered pixel driving power lines PL may be disposed at a second edge portion of the even-numbered pixel area PA with respect to the first direction X.

[0205] Two adjacent pixel drive power lines PL among the plurality of pixel drive power lines PL can be connected to a plurality of power common lines PSL provided in each pixel area PA arranged along the second direction Y. For example, the plurality of pixel drive power lines PL can be electrically connected to each other through the plurality of power common lines PSL, and thus can have a ladder structure (ladder structure) or a mesh structure. The plurality of pixel drive power lines PL can have a ladder structure or a mesh structure, and thus can prevent or minimize the voltage drop (or IR drop) of the pixel drive power caused by the line resistance of each of the plurality of pixel drive power lines PL. Therefore, the display device 10 according to the present invention can prevent or minimize the degradation of image quality caused by the deviation of the pixel drive power provided to each pixel P.

[0206] Each of the plurality of power sharing lines PSL may be branched from an adjacent pixel driving power line PL in parallel with the first direction X and may be disposed in a middle region of each pixel area PA.

[0207] The plurality of pixel common power lines CPL may extend long along the second direction Y and may be disposed in the display area AA of the first substrate 100 at predetermined intervals apart from each other along the first direction X. For example, each of the plurality of pixel common power lines CPL may be disposed at a first edge portion of the even-numbered pixel area PA with respect to the first direction.

[0208] The plurality of pixels P may be respectively disposed in a plurality of pixel areas PA defined to have equal sizes in the display area AA of the first substrate 100 .

[0209] Each of the plurality of pixels P may include at least three sub-pixels. For example, as shown in FIG. 2 , each of the plurality of pixels P may include first to fourth sub-pixels SP1 to SP4.

[0210] Refer to Figure 2 and Figure 6 , each of the first to fourth sub-pixels SP1 to SP4 may include a pixel circuit PC and a light emitting device ED.

[0211] The pixel circuit PC according to an embodiment may be disposed in the circuit area CA of the pixel area PA and may be connected to the adjacent gate lines GLo and GLe, the adjacent data lines DLo and DLe, and the pixel driving power line PL. For example, the pixel circuit PC disposed in the first subpixel SP1 may be connected to the odd data line DLo and the odd gate line GLo, the pixel circuit PC disposed in the second subpixel SP2 may be connected to the even data line DLe and the odd gate line GLo, the pixel circuit PC disposed in the third subpixel SP3 may be connected to the odd data line DLo and the even gate line GLe, and the pixel circuit PC disposed in the fourth subpixel SP4 may be connected to the even data line DLe and the even gate line GLe.

[0212] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 may sample a data signal supplied from the corresponding data lines DLo and DLe in response to a scan signal supplied from the corresponding gate lines GLo and GLe, and may control a current flowing from the pixel driving power line PL to the light-emitting device ED based on the sampled data signal. For example, the pixel circuit PC may sample the data signal by using at least two TFTs and at least one capacitor, and may control a current flowing into the light-emitting device ED based on the sampled data signal.

[0213] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can be implemented as a pixel driver chip through a semiconductor manufacturing process. The pixel driver chip is disposed in the circuit area CA of the corresponding pixel area PA and is connected to the adjacent gate lines GLo and GLe, the adjacent data lines DLo and DLe, and the pixel driver power line PL. For example, the pixel driver chip can be a minimum-unit microchip or a chipset and can be a semiconductor package device having fine dimensions including two or more transistors and one or more capacitors. Such a pixel driver chip can sample the data signals provided from the corresponding data lines DLo and DLe in response to the scan signals provided from the corresponding gate lines GLo and GLe, and can control the current flowing from the pixel driver power line PL to the light-emitting device ED based on the sampled data signals.

[0214] The light-emitting device ED may be disposed in the light-emitting area EA of the pixel area PA, electrically connected to the pixel circuit PC and to the common electrode CE. The light-emitting device ED may emit light using current flowing from the pixel circuit PC to the common electrode CE. For example, the light-emitting device ED may emit light based on a top emission type and may irradiate the light to a portion above the first surface of the first substrate 100, but is not limited thereto.

[0215] The light-emitting device ED according to one embodiment may include a self-luminous device. For example, the light-emitting device ED may include an organic light-emitting device or an inorganic light-emitting device. The inorganic light-emitting device may include a semiconductor light-emitting diode, a micro light-emitting diode, or a quantum dot light-emitting diode. For example, when the light-emitting device ED is an inorganic light-emitting device, the light-emitting device ED may have a size of 1 μm to 100 μm, but is not limited thereto.

[0216] The light emitting device ED according to an embodiment may emit one of red, green, blue, and white light. For example, the light emitting device ED of each of the first to fourth sub-pixels SP1 to SP4 may be implemented to emit white light, but is not limited thereto.

[0217] Refer again Figures 4 to 6 The common electrode CE may be disposed in the display area AA of the first substrate 100 and may be electrically connected to the light emitting device ED of each of the plurality of pixels P. For example, the common electrode CE may be disposed in an area other than the first pad portion 110 located in the display area AA of the first substrate 100 .

[0218] The common electrode CE according to an embodiment may include a transparent conductive material that transmits light emitted from the light emitting device ED of each of the plurality of pixels P. For example, the transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0219] Each of the plurality of common power contact portions CPCP may be disposed between two adjacent pixels P among the plurality of pixels P respectively overlapping the plurality of pixel common power lines CPL, and may electrically connect the common electrode CE to a corresponding pixel common power line CPL among the plurality of pixel common power lines CPL. With respect to the second direction Y, each of the plurality of common power contact portions CPCP according to an embodiment may be electrically connected to a corresponding pixel common power line CPL among the plurality of pixel common power lines CPL at a portion between the plurality of pixels P or at a boundary portion between the plurality of pixels P, and may be electrically connected to a portion of the common electrode CE, thereby electrically connecting the common electrode CE to the corresponding pixel common power line CPL among the plurality of pixel common power lines CPL.

[0220] Each of the plurality of common power contact portions CPCP may be disposed between two adjacent pixels P among the plurality of pixels P to electrically connect the common electrode CE to a corresponding pixel common power line CPL among the plurality of pixel common power lines CPL, thereby preventing or minimizing a voltage drop (or IR drop) of the pixel common power caused by the surface resistance of the common electrode CE. Therefore, the display device 10 according to the present invention can prevent or minimize degradation of image quality caused by deviation of the pixel common power supplied to each pixel P arranged in the display area AA.

[0221] The gate control line group GCL may include a gate driving circuit 150 and a plurality of gate control lines in the display area AA of the first substrate 100 .

[0222] The gate control line group GCL according to one embodiment may include a start signal line, a plurality of shift clock lines, at least one gate driving power line, and at least one gate common power line. These lines of the gate control line group GCL may extend long along the second direction Y and may be arranged in the display area AA of the first substrate 100 at predetermined intervals along the first direction X. For example, each line of the gate control line group GCL may be arranged between one or more pixels P along the first direction X.

[0223] The gate driver circuit 150 may be disposed in the display area AA of the first substrate 100. Therefore, because the gate driver circuit 150 is disposed in the display area AA of the first substrate 100, the second interval D2 between the center portion of the outermost pixel area PAo and each outer surface OS of the first substrate 100 may be half or less of the first interval (or pixel pitch) D1 between adjacent pixel areas PA. For example, when the gate driver circuit 150 is not disposed in the display area AA of the first substrate 100 but is disposed between the outermost pixel area PAo and the outer surface OS of the first substrate 100, the second interval D2 will not be half or less of the first interval D1 due to the size (or width) occupied by the gate driver circuit 150. Therefore, in one embodiment of the present invention, because the gate driver circuit 150 is disposed within the display area AA of the first substrate 100, the second interval D2 may be implemented to be half or less of the first interval D1.

[0224] Reference Figure 6 and Figure 7 The gate driving circuit 150 according to one embodiment may be implemented using a shift register, and the shift register includes a plurality of stage circuit units 1501 to 150m.

[0225] Each of the plurality of stage circuit units 1501 to 150m may be disposed in each horizontal row of the first surface 100a of the first substrate 100, spaced apart from each other along the first direction X, and may be attached to each other along the second direction Y. Each of the plurality of stage circuit units 1501 to 150m may generate a scan signal in a predetermined order in response to a gate control signal provided through the first pad portion 110 and the gate control line group GCL, and may provide the scan signal to a corresponding gate line GL.

[0226] Each of the plurality of stage circuit units 1501 to 150 m according to an embodiment may include a plurality of branch circuits 1511 to 151 n and a branch network 153 .

[0227] The plurality of branch circuits 1511 to 151n may be selectively connected to lines of the gate control line group GCL through the branch net 153 and may be electrically connected to each other through the branch net 153. Each of the plurality of branch circuits 1511 to 151n may generate a scan signal based on a gate control signal provided through a corresponding line of the gate control line group GCL and the branch net 153 and a signal transmitted between the branch nets 153, and may provide the scan signal to a corresponding gate line GL.

[0228] Each of the plurality of branch circuits 1511 to 151n may include at least one TFT among the plurality of TFTs constituting one of the stage circuit units 1501 to 150m. Each of the plurality of branch circuits 1511 to 151n may be disposed in a circuit region between two adjacent pixels P or between two pixels P in each horizontal row of the first substrate 100, but is not limited thereto. Based on the number of TFTs constituting each stage circuit unit 1501 to 150m and the number of pixels P disposed in one horizontal row, each of the plurality of branch circuits 1511 to 151n may be disposed in a circuit region between one or more pixels P.

[0229] The branch network 153 may be provided in each horizontal row of the first substrate 100 and may electrically connect the plurality of branch circuits 1511 to 151n. The branch network 153 according to an embodiment may include a network line and a plurality of control nodes.

[0230] A plurality of control nodes may be provided in each horizontal row of the first substrate 100 and may be selectively connected to the plurality of branch circuits 1511 to 151n in one horizontal row. For example, the plurality of control nodes may be provided in the upper edge region (or lower edge region) of the pixel region arranged in each horizontal row of the first substrate 100.

[0231] A network line may be selectively connected to the lines of the gate control line group GCL located in the first substrate 100 and may be selectively connected to the plurality of branch circuits 1511 to 151n. For example, the network line may transmit gate control signals provided through the lines of the gate control line group GCL to corresponding branch circuits 1511 to 151n and may transmit signals between the plurality of branch circuits 1511 to 151n.

[0232] Refer again Figures 4 to 6 , the first pad portion 110 may be disposed at a first edge portion parallel to the first direction X in the first surface of the first substrate 100. The first pad portion 110 may be disposed at a third edge portion of each outermost pixel area PAo located at the first edge portion of the first substrate 100. Relative to the second direction Y, an end portion of the first pad portion 110 may overlap or be aligned with an end portion of each outermost pixel area PAo. Therefore, the first pad portion 110 may be included (or disposed) in each outermost pixel area PAo located at the first edge portion of the first substrate 100, and thus a non-display area (or frame area) based on the first pad portion 110 will not be formed or exist on the first substrate 100.

[0233] The first pad portion 110 may include a plurality of first pads disposed parallel to one another on a first edge portion of the first substrate 100 along a first direction X. The plurality of first pads may be divided (or classified) into a plurality of first data pads DP1, a plurality of first gate pads GP1, a plurality of first pixel driving power pads PPP1, and a plurality of first pixel common power pads CPP1.

[0234] The first pad portion 110 according to an embodiment may include a first data pad portion, a first gate pad portion, a first pixel driving power pad portion, and a first pixel common power pad portion.

[0235] The first data pad portion may include a plurality of first data pads DP1. Each of the plurality of first data pads DP1 may be individually (or separately) connected to one end of each of the plurality of data lines DLo and DLe disposed on the first substrate 100.

[0236] The first data pad portion may be connected to a data wiring portion located in the wiring portion 400. Each of the plurality of first data pads DP1 provided in the first data pad portion may be individually (or separately) connected to one end of each of the plurality of data wirings 410 provided in the wiring portion 400. Thus, each of the plurality of data lines DLo and DLe provided on the first substrate 100 may be electrically connected to a corresponding data wiring 410 among the plurality of data wirings 410 through a corresponding first data pad DP1 among the plurality of first data pads DP1.

[0237] The first gate pad portion may include a plurality of first gate pads GP1 , each of which may be individually (or separately) connected to one end of a corresponding gate control line among gate control lines included in the gate control line group GCL on the first substrate 100 .

[0238] The first gate pad portion may be connected to a gate wiring portion located in the wiring portion 400. Each of the plurality of first gate pads GP1 provided in the first gate pad portion may be individually (or separately) connected to one end of each of the plurality of gate wirings 430 among the plurality of wirings located in the wiring portion 400. Therefore, each line included in the gate control line group GCL provided on the first substrate 100 may be electrically connected to a corresponding gate wiring 430 among the plurality of gate wirings 430 through a corresponding first gate pad GP1 among the plurality of first gate pads GP1.

[0239] The plurality of first gate pads GP1 according to an embodiment may be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, at least one first gate driving power pad, and at least one first gate common power pad.

[0240] The first start signal pad may be electrically connected to a start signal wiring located in a gate wiring portion of the wiring portion 400. Therefore, a start signal line disposed on the first substrate 100 may be electrically connected to the start signal wiring through the first start signal pad.

[0241] Each of the plurality of first shift clock pads may be electrically connected to a corresponding shift clock wiring among the plurality of shift clock wirings provided in the gate wiring portion of the wiring portion 400. Therefore, each of the plurality of shift clock lines provided on the first substrate 100 may be electrically connected to a corresponding shift clock wiring among the plurality of shift clock wirings through a corresponding first shift clock pad among the plurality of first shift clock pads.

[0242] The at least one first gate driving power supply pad may be electrically connected to at least one gate driving power supply wiring provided in the gate wiring portion of the wiring portion 400. Therefore, the at least one first gate driving power supply line provided on the first substrate 100 may be electrically connected to the at least one gate driving power supply wiring through the at least one first gate driving power supply pad.

[0243] At least one first gate common power supply pad may be electrically connected to at least one gate common power supply wiring provided in the gate wiring portion of the wiring portion 400. Therefore, at least one first gate common power supply line provided on the first substrate 100 may be electrically connected to at least one gate common power supply wiring through the at least one first gate common power supply pad.

[0244] The first pixel driving power supply pad portion may include a plurality of first pixel driving power supply pads PPP1. Each of the plurality of first pixel driving power supply pads PPP1 may be individually (or separately) connected to one end of a corresponding pixel driving power supply line PL among a plurality of pixel driving power supply lines PL disposed on the first substrate 100.

[0245] The first pixel driving power supply pad portion may be electrically connected to a pixel driving power supply wiring portion provided in the wiring portion 400. Each of the plurality of first pixel driving power supply pads PPP1 provided in the first pixel driving power supply pad portion may be individually (or separately) connected to one end of a corresponding pixel driving power supply wiring 450 among the plurality of pixel driving power supply wirings 450 provided in the wiring portion 400. Therefore, each of the plurality of pixel driving power supply lines PL provided on the first substrate 100 may be individually (or separately) connected to one end of a corresponding pixel driving power supply wiring 450 among the plurality of pixel driving power supply wirings 450 through a corresponding first pixel driving power supply pad PPP1 among the plurality of first pixel driving power supply pads PPP1.

[0246] The first pixel common power pad portion may include a plurality of first pixel common power pads CPP1. Each of the plurality of first pixel common power pads CPP1 may be individually (or separately) connected to one end of a corresponding pixel common power line CPL among a plurality of pixel common power lines CPL disposed on the first substrate 100.

[0247] The first pixel common power pad portion may be electrically connected to a pixel common power wiring portion provided in the wiring portion 400. Each of the plurality of first pixel common power pads CPP1 provided in the first pixel common power pad portion may be individually (or separately) connected to one end of a corresponding pixel common power wiring 470 among the plurality of pixel common power wirings 470 provided in the wiring portion 400. Therefore, each of the plurality of pixel common power lines CPL provided on the first substrate 100 may be individually (or separately) connected to one end of a corresponding pixel common power wiring 470 among the plurality of pixel common power wirings 470 through the corresponding first pixel common power pad CPP1 among the plurality of first pixel common power pads CPP1.

[0248] According to one embodiment, the first pad portion 110 may include a plurality of pad groups PG arranged in the order of a first pixel driving power pad PPP1, two first data pads DP1, a first gate pad GP1, a first pixel common power pad CPP1, two first data pads DP1, and a first pixel driving power pad PPP1 along the first direction X. Each of the plurality of pad groups PG may be connected to two adjacent pixels P arranged along the first direction X. For example, the plurality of pad groups PG may include a first pad group PG1 including a first pixel driving power pad PPP1, two first data pads DP1, and a first gate pad GP1 continuously arranged in the odd-numbered pixel area PA along the first direction X, and a second pad group PG2 including a first pixel common power pad CPP1, two first data pads DP1, and a first pixel driving power pad PPP1 continuously arranged in the even-numbered pixel area PA along the first direction X.

[0249] The first substrate 100 according to the present invention may further include a plurality of auxiliary power lines SPL and a plurality of auxiliary power contact portions SPCP.

[0250] Each of the plurality of auxiliary power lines SPL may extend long along the second direction Y and may be disposed adjacent to a corresponding pixel common power line CPL among the plurality of pixel common power lines CPL. Each of the plurality of auxiliary power lines SPL may be electrically connected to an adjacent pixel common power line CPL without being electrically connected to the first pixel common power pad CPP1, and may be supplied with a pixel common power supply via the adjacent pixel common power line CPL. To this end, the first substrate 100 according to the present invention may further include a plurality of line connection patterns LCP that electrically connect adjacent pixel common power lines CPL and the auxiliary power lines SPL.

[0251] Each of the plurality of line connection patterns LCP may be disposed on the first substrate 100 such that the line connection pattern LCP intersects adjacent pixel common power lines CPL and auxiliary power lines SPL and electrically connects the adjacent pixel common power lines CPL and auxiliary power lines SPL using a line jumping structure. For example, one side of each of the plurality of line connection patterns LCP may be electrically connected to a portion of the auxiliary power line SPL via a first line contact hole formed in an insulating layer on the auxiliary power line SPL, and the other side of each of the plurality of line connection patterns LCP may be electrically connected to a portion of the pixel common power line CPL via a second line contact hole formed in an insulating layer on the pixel common power line CPL.

[0252] Each of the plurality of auxiliary power contact portions SPCP can be disposed between a plurality of pixels P that overlap with the plurality of auxiliary power lines SPL, and can electrically connect the common electrode CE to each of the plurality of auxiliary power lines SPL. With respect to the second direction Y, each of the plurality of auxiliary power contact portions SPCP according to one embodiment can be electrically connected to a corresponding auxiliary power line SPL among the plurality of auxiliary power lines SPL at a portion between the plurality of pixels P or at a boundary portion between the plurality of pixels P, and can also be electrically connected to a portion of the common electrode CE, thereby electrically connecting the common electrode CE to each of the plurality of auxiliary power lines SPL. Therefore, the common electrode CE can be additionally connected to each of the plurality of auxiliary power lines SPL via each of the plurality of auxiliary power contact portions SPCP. Therefore, the display device 10 according to the present invention can prevent or minimize degradation in image quality caused by a deviation in the pixel common power supplied to each pixel P arranged in the display area AA. Furthermore, in the display device 10 according to the present invention, although a first pixel common power pad CPP1 connected to each of the plurality of auxiliary power lines SPL is not additionally disposed (or formed), the pixel common power can be supplied to the common electrode CE in each of the plurality of pixel areas PA.

[0253] The display device 10 according to the present invention may further include a plurality of reference power lines RL.

[0254] The plurality of reference power lines RL may extend long along the second direction Y and may be disposed in the display area AA of the first substrate 100 at predetermined intervals apart from each other along the first direction X. Each of the plurality of reference power lines RL may be disposed in a central region of each pixel area PA arranged along the second direction Y. For example, each of the plurality of reference power lines RL may be disposed between the odd-numbered data lines DLo and the even-numbered data lines DLe in each pixel area PA.

[0255] Each of the plurality of reference power lines RL may be shared by two adjacent sub-pixels (SP1, SP2, SP3, SP4) in each pixel area PA along the first direction X. To this end, each of the plurality of reference power lines RL may include a reference branch line RDL.

[0256] The reference branch line RDL may branch (or protrude) to two adjacent sub-pixels ((SP1, SP2), (SP3, SP4)) in each pixel area PA along the first direction X and may be electrically connected to the two adjacent sub-pixels ((SP1, SP2), (SP3, SP4)).

[0257] The first pad portion 110 according to the present invention may further include a first reference power source pad portion.

[0258] The first reference power pad portion may include a plurality of first reference power pads RPP1. Each of the plurality of first reference power pads RPP1 may be individually (or separately) connected to one end of a corresponding reference power line RL among the plurality of reference power lines RL. For example, each of the plurality of first reference power pads RPP1 may be disposed between two first data pads DP1 located in each of the plurality of outermost pixel areas PAo, but is not limited thereto.

[0259] The first reference power supply pad section may be connected to a reference power supply wiring section provided in the wiring section 400. Each of the plurality of first reference power supply pads RPP1 provided in the first reference power supply pad section may be individually (or separately) connected to one end of a corresponding reference power supply wiring 490 among the plurality of reference power supply wirings 490 provided in the wiring section 400. Therefore, each of the plurality of reference power supply lines RL provided on the first substrate 100 may be electrically connected to a corresponding reference power supply wiring 490 among the plurality of reference power supply wirings 490 through a corresponding first reference power supply pad RPP1 among the plurality of first reference power supply pads RPP1.

[0260] Alternatively, the plurality of reference power supply lines RL, the reference branch lines RDL, the plurality of first reference power supply pads RPP1 , and the plurality of reference power supply wirings 490 may be omitted based on the circuit configuration of the pixel circuit PC.

[0261] Figure 8 It is a diagram Figure 4 and Figure 6 The circuit diagram of one pixel shown in FIG is a diagram describing a pixel circuit of a sub-pixel. Figure 8 When, with Figures 4 to 7 The same or corresponding elements are denoted by the same reference numerals, and repeated descriptions thereof will be omitted or briefly described below.

[0262] Reference Figure 8 , the pixel P according to the present invention may include first to fourth sub-pixels SP1 to SP4 , and each of the first to fourth sub-pixels SP1 to SP4 includes a pixel circuit PC, a pixel electrode PE, and a light emitting device ED.

[0263] The pixel circuit PC included in each of the first to fourth subpixels SP1 to SP4 of the pixel P may be disposed in a circuit region and may be connected to adjacent gate lines GLo and GLe, adjacent data lines DLo and DLe, a reference power line RL, and a pixel driving power line PL. The pixel circuit PC may supply a data current corresponding to a differential voltage between a data signal supplied through the adjacent data lines DLo and DLe and a reference voltage supplied through the reference power line RL to the light-emitting device ED in response to a scan signal supplied through the adjacent gate lines GLo and GLe, thereby causing the light-emitting device ED to emit light.

[0264] The pixel circuit PC according to an embodiment may include a first switching TFT Tsw1, a second switching TFT Tsw2, a storage capacitor Cst, and a driving TFT Tdr. In the following description, a thin film transistor may be referred to as a TFT.

[0265] At least one of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be an N-type or P-type TFT. At least one of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be an amorphous silicon (a-Si) TFT, a polycrystalline silicon TFT, an oxide TFT, or an organic TFT. For example, in the pixel circuit PC, some of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be TFTs having a semiconductor layer (or active layer) including low-temperature polycrystalline silicon (LTPS), which has excellent response characteristics, and the other of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be TFTs having a semiconductor layer (or active layer) including an oxide, which has excellent off-current characteristics. The first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may have different sizes (or channel sizes). For example, the driving TFT Tdr may have a size larger than each of the first and second switching TFTs Tsw1 and Tsw2 , and the second switching TFT Tsw2 may have a size larger than the first switching TFT Tsw1 .

[0266] The first switching TFT Tsw1 may include a gate electrode connected to adjacent gate lines GLo and GLe, first source / drain electrodes connected to adjacent data lines DLo and DLe, and second source / drain electrodes connected to a first node n1 (or the gate electrode of the driving TFT Tdr). The first switching TFT Tsw1 may be turned on by a scan signal supplied through the corresponding gate lines GLo and GLe and may transmit a data signal supplied through the corresponding data lines DLo and DLe to the first node n1 (i.e., the gate electrode n1 of the driving TFT Tdr).

[0267] According to one embodiment, a gate electrode of the first switching TFT Tsw1 provided in the pixel circuit PC of each of the first subpixel SP1 and the second subpixel SP2 may be connected to the odd-numbered gate line GLo, and a gate electrode of the first switching TFT Tsw1 provided in the pixel circuit PC of each of the third subpixel SP3 and the fourth subpixel SP4 may be connected to the even-numbered gate line GLe. A first source / drain electrode of the first switching TFT Tsw1 provided in the pixel circuit PC of each of the first subpixel SP1 and the third subpixel SP3 may be connected to the odd-numbered data line DLo, and a first source / drain electrode of the first switching TFT Tsw1 provided in the pixel circuit PC of each of the second subpixel SP2 and the fourth subpixel SP4 may be connected to the even-numbered data line DLe.

[0268] The second switching TFT Tsw2 may include a gate electrode connected to adjacent gate lines GLo and GLe, a first source / drain electrode connected to an adjacent reference power line RL, and a second source / drain electrode connected to a second node (or the source electrode of the driving TFT Tdr) n2. The second switching TFT Tsw2 may be turned on by a scan signal supplied through the corresponding gate lines GLo and GLe and may transmit a reference voltage supplied through the corresponding reference branch line RDL and the reference power line RL to the source electrode n2 of the driving TFT Tdr.

[0269] According to one embodiment, a gate electrode of the second switch TFT Tsw2 provided in the pixel circuit PC of each of the first and second subpixels SP1 and SP2 may be connected to the odd-numbered gate line GLo, and a gate electrode of the second switch TFT Tsw2 provided in the pixel circuit PC of each of the third and fourth subpixels SP3 and SP4 may be connected to the even-numbered gate line GLe. A first source / drain electrode of the second switch TFT Tsw2 provided in the pixel circuit PC of each of the first to fourth subpixels SP1 to SP4 may be connected to an adjacent reference power line RL through a corresponding reference branch line RDL.

[0270] The scan signal supplied to the gate electrode of the first switching TFT Tsw1 and the scan signal supplied to the gate electrode of the second switching TFT Tsw2 may be the same signal. For example, the gate electrode of the first switching TFT Tsw1 and the gate electrode of the second switching TFT Tsw2 may be connected to the same gate lines GLo and GLe. Therefore, the first switching TFT Tsw1 and the second switching TFT Tsw2 provided in the pixel circuit PC of each of the first subpixel SP1 and the second subpixel SP2 can be turned on or off simultaneously using the scan signal provided via the odd-numbered gate line GLo. Similarly, the first switching TFT Tsw1 and the second switching TFT Tsw2 provided in the pixel circuit PC of each of the third subpixel SP2 and the fourth subpixel SP4 can be turned on or off simultaneously using the scan signal provided via the even-numbered gate line GLe.

[0271] Alternatively, the scan signal supplied to the gate electrode of the first switching TFT Tsw1 and the scan signal supplied to the gate electrode of the second switching TFT Tsw2 may be different signals. For example, the gate electrode of the first switching TFT Tsw1 and the gate electrode of the second switching TFT Tsw2 may be connected to different gate lines GLo and GLe.

[0272] Each of the odd-numbered gate lines GLo and the even-numbered gate lines GLe according to an embodiment may include a first gate line and a second gate line.

[0273] A first gate line of the odd-numbered gate line GLo may be connected to a gate electrode of a first switching TFT Tsw1 provided in a pixel circuit PC of each of the first subpixel SP1 and the second subpixel SP2, and a second gate line of the odd-numbered gate line GLo may be connected to a gate electrode of a second switching TFT Tsw2 provided in a pixel circuit PC of each of the first subpixel SP1 and the second subpixel SP2.

[0274] A first gate line of the even-numbered gate line GLe may be connected to a gate electrode of a first switching TFT Tsw1 provided in a pixel circuit PC of each of the third subpixel SP3 and the fourth subpixel SP4, and a second gate line of the even-numbered gate line GLe may be connected to a gate electrode of a second switching TFT Tsw2 provided in a pixel circuit PC of each of the third subpixel SP3 and the fourth subpixel SP4.

[0275] Therefore, the first switching TFT Tsw1 and the second switching TFT Tsw2 provided in the pixel circuit PC of each of the first subpixel SP1 and the second subpixel SP2 can be simultaneously turned on or off using the same scan signal supplied via the first gate line and the second gate line of the odd-numbered gate line GLo, or can be individually turned on or off using different scan signals supplied via the first gate line and the second gate line of the odd-numbered gate line GLo. Similarly, the first switching TFT Tsw1 and the second switching TFT Tsw2 provided in the pixel circuit PC of each of the third subpixel SP3 and the fourth pixel SP4 can be simultaneously turned on or off using the same scan signal supplied via the first gate line and the second gate line of the even-numbered gate line GLe, or can be individually turned on or off using different scan signals supplied via the first gate line and the second gate line of the even-numbered gate line GLe. For example, in each of the first to fourth subpixels SP1 to SP4, the first switching TFT Tsw1 can be turned on based on the first scan signal supplied via the first gate line, and the second switching TFT Tsw2 can be turned on based on the second scan signal supplied via the second gate line.

[0276] The second switch TFT Tsw2 provided in the pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can transmit a reference voltage to the source node n2 of the driving TFT Tdr through the reference power line RL during a data charging period (or segment) based on an external sensing mode, and can transmit the current flowing in the source node n2 of the driving TFT Tdr to the reference power line RL during a sensing period (or segment) of the pixel P. In this case, the driving circuit unit can sense the current supplied to the reference power line RL to generate compensation data for compensating for characteristic variations of the driving TFT Tdr, and the driving circuit unit can modulate the pixel data based on the generated compensation data. For example, the characteristic variations of the driving TFT Tdr may include a shift in threshold voltage and / or mobility.

[0277] The storage capacitor Cst may be disposed in an overlapping region between the gate node n1 and the source node n2 of the driving TFT Tdr. The storage capacitor Cst may include a first capacitor electrode connected to the gate electrode of the driving TFT Tdr, a second capacitor electrode connected to the source electrode of the driving TFT Tdr, and a dielectric layer formed in the overlapping region between the first capacitor electrode and the second capacitor electrode. The storage capacitor Cst may be charged with a differential voltage between the gate node n1 and the source node n2 of the driving TFT Tdr and may then turn the driving TFT Tdr on or off based on the charged voltage.

[0278] The driving TFT Tdr may include a gate electrode (or gate node) n1 connected to the second source / drain electrodes of the first switch TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst; a source electrode (or source node) commonly connected to the second source / drain electrodes of the second switch TFT Tsw2, the second capacitor electrode of the storage capacitor Cst, and the pixel electrode PE; and a drain electrode (or drain node) connected to the adjacent pixel driving power line PL.

[0279] The drain electrode of the driving TFT Tdr provided in the pixel circuit PC of each of the first to fourth subpixels SP1 to SP4 may be connected to an adjacent pixel driving power line PL through a power sharing line PSL. The power sharing line PSL may branch from an adjacent pixel driving power line PL adjacent thereto in parallel with the first direction X and may be provided in a central region of the pixel P. The driving TFT Tdr may be turned on based on the voltage of the storage capacitor Cst and may control the amount of current flowing from the pixel driving power line PL to the light emitting device ED.

[0280] The driving TFTs Tdr provided in the pixel circuits PC of the first to fourth sub-pixels SP1 to SP4, respectively, may have different sizes (or channel sizes) based on the luminous efficiency of the corresponding light-emitting devices ED. For example, the driving TFT Tdr of the first sub-pixel (or red sub-pixel) SP1 may have a larger size than the driving TFT Tdr of each of the second to fourth sub-pixels SP2 to SP4, the driving TFT Tdr of the fourth sub-pixel (or green sub-pixel) SP4 may have a larger size than the driving TFT Tdr of each of the second sub-pixel SP2 and the third sub-pixels SP2 and SP3, and the driving TFT Tdr of the second sub-pixel (or blue sub-pixel) SP2 may have a larger size than the driving TFT Tdr of the third sub-pixel (or white sub-pixel) SP3.

[0281] Alternatively, in each of the first to fourth sub-pixels SP1 to SP4, the pixel circuit PC including the first switching TFT Tsw1, the second switching TFT Tsw2, the storage capacitor Cst, and the driving TFT Tdr may be implemented as a pixel driver chip, disposed in the circuit area CA of the corresponding pixel area PA, and connected to the adjacent gate lines GLo and GLe, the adjacent data lines DLo and DLe, and the pixel driving power line PL. Such a pixel driver chip may sample data signals supplied from the corresponding data lines DLo and DLe in response to scan signals supplied from the corresponding gate lines GLo and GLe, and may supply a data current corresponding to the sampled data signals to the pixel electrode PE.

[0282] The pixel electrode PE may be disposed in a light emitting region of each of the first to fourth sub-pixels SP1 to SP4 and may be connected to a drain electrode of a driving TFT Tdr disposed in a corresponding pixel circuit PC.

[0283] Based on the resolution of the display device 10, the pixel electrode PE may be disposed in the corresponding sub-pixel region without overlapping the pixel circuit PC or overlapping a portion or all of the pixel circuit PC. Figures 2A to 2C As shown in FIG, the pixel electrode PE may be disposed in the sub-pixel region and overlap a portion or the entirety of the circuit area CA.

[0284] The pixel electrode PE according to an embodiment may be disposed in the sub-pixel region and may not overlap with the pixel circuit PC. For example, the pixel electrode PE may be disposed in the sub-pixel region near the center portion of the pixel P.

[0285] According to another embodiment, the pixel electrode PE may be disposed in the sub-pixel region and overlap with a portion of the pixel circuit PC. For example, the pixel electrode PE may be disposed in the sub-pixel region near the center of the pixel P and overlap with a portion of the pixel circuit PC.

[0286] According to another embodiment, the pixel electrode PE may be disposed in the sub-pixel region and overlap the entire pixel circuit PC. For example, the pixel electrode PE may be disposed in the entire sub-pixel region and overlap the entire pixel circuit PC.

[0287] The light-emitting device ED may be disposed on the pixel electrode PE and may be electrically connected to the pixel electrode PE. Furthermore, the light-emitting device ED may be electrically connected to a common electrode. That is, the light-emitting device ED may be disposed between the pixel electrode PE and the common electrode. The light-emitting device ED may emit light using a data current supplied from the corresponding pixel circuit PC. The light-emitting device ED may emit light using the data current supplied from the corresponding pixel circuit PC and may irradiate the light onto a portion above the first surface of the first substrate 100. The light-emitting device ED according to one embodiment may include a self-luminous device as described above.

[0288] Alternatively, in the pixel circuit PC according to an embodiment, the second switch TFT Tsw2 may be omitted based on a driving (or operating) method of the pixel P, and in this case, the reference power line RL provided on the first substrate 100 may also be omitted.

[0289] Figure 9 It is a diagram Figure 5 , Figure 10 yes Figure 9 An enlarged view of the area "B3" is shown in FIG. Figure 9 and Figure 10 When the Figures 4 to 8 The same or corresponding elements are described repeatedly.

[0290] Reference Figure 5 、 Figure 6 、 Figure 9 and Figure 10 , the second substrate 200 according to the present invention may include a second pad portion 210 .

[0291] The second pad portion 210 may be disposed at a first edge portion of the second surface 200b of the second substrate 200 parallel to the first direction X, thereby overlapping the first pad portion 110 disposed on the first substrate 100. The second pad portion 210 may include a plurality of second pads disposed parallel to one another along the first direction X at the first edge portion of the second substrate 200. The plurality of second pads may be divided (or classified) into a plurality of second data pads DP2, a plurality of second gate pads GP2, a plurality of second pixel driving power pads PPP2, and a plurality of second pixel common power pads CPP2.

[0292] The second pad portion 210 according to an embodiment may include a second data pad portion, a second gate pad portion, a second pixel driving power pad portion, and a second pixel common power pad portion.

[0293] The second data pad portion may be electrically connected to the first data pad portion of the first pad portion 110 through the wiring portion 400 .

[0294] The second data pad portion according to an embodiment may include a plurality of second data pads DP2. Each of the plurality of second data pads DP2 may be disposed so as to overlap individually (or separately) with a corresponding first data pad DP1 among the plurality of first data pads DP1 disposed in the first pad portion 110 of the first substrate 100. Each of the plurality of second data pads DP2 according to an embodiment may be individually (or separately) connected to a corresponding first data pad DP1 among the plurality of first data pads DP1 through a corresponding data wiring 410 among the plurality of wirings disposed in the wiring portion 400. Therefore, each of the plurality of second data pads DP2 may be electrically connected to a corresponding data line DLo and DLe through the corresponding data wiring 410 and the corresponding first data pad DP1.

[0295] The second gate pad portion may be electrically connected to the first gate pad portion of the first pad portion 110 through the wiring portion 400 .

[0296] The second gate pad portion according to an embodiment may include a plurality of second gate pads GP2. Each of the plurality of second gate pads GP2 may be disposed so as to overlap individually (or separately) with a corresponding first gate pad GP1 among the plurality of first gate pads GP1 disposed in the first pad portion 110 of the first substrate 100. Each of the plurality of second gate pads GP2 according to an embodiment may be individually (or separately) connected to the other end of a corresponding gate wiring 430 among the plurality of gate wirings 430 disposed in the wiring portion 400. Therefore, each of the plurality of second gate pads GP2 may be electrically connected to a corresponding gate control line included in the gate control line group GCL through the corresponding gate wiring 430 and the corresponding first gate pad GP1.

[0297] The plurality of second gate pads GP2 according to an embodiment may be divided (or classified) into a second start signal pad, a plurality of second shift clock pads, at least one second gate driving power pad, and at least one second gate common power pad.

[0298] The second start signal pad may be electrically connected to a start signal wiring provided in a gate wiring portion of the wiring portion 400. Therefore, the second start signal pad may be electrically connected to a corresponding start signal line included in the gate control line group GCL through a corresponding first start signal pad and a corresponding start signal wiring among the plurality of gate wirings 430.

[0299] Each of the plurality of second shift clock pads may be electrically connected to a corresponding shift clock wiring among the plurality of shift clock wirings provided in the gate wiring portion of the wiring portion 400. Therefore, each of the plurality of second shift clock pads may be electrically connected to a corresponding shift clock line among the plurality of shift clock lines included in the gate control line group GCL through a corresponding first shift clock pad and a corresponding shift clock wiring among the plurality of gate wirings 430.

[0300] The at least one second gate driving power supply pad may be electrically connected to at least one gate driving power supply wiring provided in the gate wiring portion of the wiring portion 400. Therefore, the at least one second gate driving power supply pad may be electrically connected to the gate driving power supply line included in the gate control line group GCL through the corresponding first gate driving power supply pad and the corresponding gate driving power supply wiring among the plurality of gate wirings 430.

[0301] The at least one second gate common power supply pad may be electrically connected to at least one gate common power supply wiring provided in the gate wiring portion of the wiring portion 400. Therefore, the at least one second gate common power supply pad may be electrically connected to a gate common power supply line included in the gate control line group GCL through the corresponding first gate common power supply pad and the corresponding gate common power supply wiring among the plurality of gate wirings 430.

[0302] The second pixel driving power supply pad portion may be electrically connected to the first pixel driving power supply pad portion of the first pad portion 110 through the wiring portion 400 .

[0303] The second pixel driving power supply pad portion according to one embodiment may include a plurality of second pixel driving power supply pads PPP2. Each of the plurality of second pixel driving power supply pads PPP2 may be arranged to overlap individually (or separately) with a corresponding first pixel driving power supply pad PPP1 among the plurality of first pixel driving power supply pads PPP1 provided in the first pad portion 110 of the first substrate 100. Each of the plurality of second pixel driving power supply pads PPP2 according to one embodiment may be connected individually (or separately) to a corresponding first pixel driving power supply pad PPP1 among the plurality of first pixel driving power supply pads PPP1 through a corresponding pixel driving power supply wiring 450 among the plurality of wirings provided in the wiring portion 400. Therefore, each of the plurality of second pixel driving power supply pads PPP2 may be electrically connected to a corresponding pixel driving power line PL through a corresponding pixel driving power supply wiring 450 and a corresponding first pixel driving power supply pad PPP1.

[0304] The second pixel common power pad portion may be electrically connected to the first pixel common power pad portion of the first pad portion 110 through the wiring portion 400 .

[0305] The second pixel common power pad portion according to one embodiment may include a plurality of second pixel common power pads CPP2. Each of the plurality of second pixel common power pads CPP2 may be disposed so as to individually (or separately) overlap with a corresponding first pixel common power pad CPP1 among the plurality of first pixel common power pads CPP1 disposed in the first pad portion 110 of the first substrate 100. Each of the plurality of second common driving power pads CPP2 according to one embodiment may be individually (or separately) connected to a corresponding first pixel common power pad CPP1 among the plurality of first pixel common power pads CPP1 via a corresponding pixel common power wiring 470 among the plurality of wirings disposed in the wiring portion 400. Therefore, each of the plurality of second pixel common power pads CPP2 may be electrically connected to a corresponding pixel common power line CPL via the corresponding pixel common power wiring 470 and the corresponding first pixel common power pad CPP1.

[0306] According to one embodiment, the second pad portion 210 may include a plurality of pad groups PG arranged in the same order (or matching) as the arrangement order of the pads provided in the first pad portion 110, namely, a second pixel driving power pad PPP2, two second data pads DP2, a second gate pad GP2, a second pixel common power pad CPP2, two second data pads DP2, and a second pixel driving power pad PPP2 along the first direction X. For example, the plurality of pad groups PG may include a first pad group PG1 and a second pad group PG2, the first pad group PG1 including a second pixel driving power pad PPP2, two second data pads DP2, and a second gate pad GP2 arranged consecutively along the first direction X, and the second pad group PG2 including a second pixel common power pad CPP2, two second data pads DP2, and a second pixel driving power pad PPP2 arranged consecutively along the first direction X.

[0307] The second pad portion 210 according to the present invention may further include a second reference power source pad portion.

[0308] The second reference power source pad portion may be electrically connected to the first reference power source pad portion of the first pad portion 110 through the wiring portion 400 .

[0309] According to one embodiment, the second reference power pad portion may include a plurality of second reference power pads RPP2. Each of the plurality of second reference power pads RPP2 may be disposed so as to individually (or separately) overlap with a corresponding first reference power pad RPP1 among a plurality of first reference power pads RPP1 disposed in the first pad portion 110 of the first substrate 100. Therefore, each of the plurality of second reference power pads RPP2 may be electrically connected to a corresponding reference power line RL through a corresponding reference power wiring 490 and a corresponding first reference power pad RPP1.

[0310] The second substrate 200 according to the present invention may further include a third pad portion 230 and a connection portion 250 .

[0311] The third pad portion 230 may be disposed on the rear surface 200b of the second substrate 200. For example, the third pad portion 230 may be disposed at a central portion of the rear surface 200b of the second substrate 200 adjacent to the first edge portion.

[0312] The third pad portion 230 according to an embodiment may include a plurality of third pads (or input pads) spaced apart from each other by a certain interval along the first direction X. The plurality of third pads may be divided (or classified) into a plurality of third data pads DP, a third pixel driving power pad PPP3, a plurality of third gate pads GP3, and a plurality of third pixel common power pads CPP3.

[0313] The third pad portion 230 according to an embodiment may include a third data pad portion, a third pixel driving power pad portion, a third gate pad portion, and a third pixel common power pad portion.

[0314] The third pad portion 230 may include: a first region (or central region) including a third data pad portion and a third pixel driving power pad portion, a second region (or one region) including a third gate pad portion, and a third region (or another region) including a third pixel common power pad portion.

[0315] The third data pad portion may be electrically connected to the second data pad portion of the second pad portion 210 through the connection portion 250 .

[0316] The third data pad portion according to an embodiment may include a plurality of third data pads DP3. The plurality of third data pads DP3 may be arranged in parallel along the first direction X and spaced apart from each other in the first region of the third pad portion 230.

[0317] Each of the plurality of third data pads DP3 according to an embodiment may be individually (or separately) connected to a corresponding second data pad DP2 among the plurality of second data pads DP2 provided in the second pad portion 210 through the connection portion 250. Each of the plurality of third data pads DP3 may be supplied with a data signal from the driving IC 530 of the driving circuit unit 500. The data signal according to an embodiment may be supplied to each of the plurality of second data pads DP2 provided in the second pad portion 210 through the corresponding third data pad DP3 among the plurality of third data pads DP3 and the connection portion 250.

[0318] The third pixel driving power supply pad portion may be electrically connected to the second pixel driving power supply pad portion of the second pad portion 210 through the connection portion 250 .

[0319] The third pixel driving power supply pad portion according to an embodiment may include a plurality of third pixel driving power supply pads PPP3. The plurality of third pixel driving power supply pads PPP3 may be arranged in parallel along the first direction X and spaced apart from each other in the first region of the third pad portion 230.

[0320] Each of the plurality of third pixel driving power supply pads PPP3 according to an embodiment may be individually (or separately) connected to a corresponding second pixel driving power supply pad PPP2 among the plurality of second pixel driving power supply pads PPP2 provided in the second pad portion 210 through the connection portion 250. For example, each of the plurality of third pixel driving power supply pads PPP3 may be supplied with pixel driving power from the driving IC 530 of the driving circuit unit 500. The pixel driving power according to an embodiment may be supplied to each of the plurality of second pixel driving power supply pads PPP2 provided in the second pad portion 210 through the corresponding third pixel driving power supply pad PPP3 among the plurality of third pixel driving power supply pads PPP3 and the connection portion 250.

[0321] The plurality of third data pads DP3 and the plurality of third pixel driving power pads PPP3 may be arranged in parallel in the first region of the third pad portion 230 in the same order as the arrangement order of the plurality of second data pads DP2 and the plurality of second pixel driving power pads PPP2 arranged in the second pad portion 210 .

[0322] The third gate pad portion may be electrically connected to the second gate pad portion of the second pad portion 210 through the wiring portion 250 .

[0323] The third gate pad portion according to an embodiment may include a plurality of third gate pads GP3 , which may be disposed in parallel along the first direction X and spaced apart from each other in the second region of the third pad portion 230 .

[0324] Each of the plurality of third gate pads GP3 according to an embodiment may be individually (or separately) connected to a corresponding second gate pad GP2 among the plurality of second gate pads GP2 provided in the second pad portion 210 through the wiring portion 250. For example, each of the plurality of third gate pads GP3 may be provided with a gate control signal from the timing controller 570 of the driving circuit unit 500. The gate control signal according to an embodiment may be provided to each of the plurality of second gate pads GP2 provided in the second pad portion 210 through the corresponding third gate pad GP3 among the plurality of third gate pads GP3 and the wiring portion 250.

[0325] The plurality of third gate pads GP3 according to an embodiment may be divided (or classified) into a third start signal pad, a plurality of third shift clock pads, at least one third gate driving power pad, and at least one third gate common power pad.

[0326] The third start signal pad may be electrically connected to the second start signal pad provided in the second pad portion 210 through the connection portion 250. For example, the third start signal pad may be provided with a start signal (or pulse) from the timing controller 570 of the driving circuit unit 500. The start signal according to an embodiment may be provided to the second start signal pad provided in the second pad portion 210 through a corresponding third start signal pad among the plurality of third start signal pads and the connection portion 250.

[0327] Each of the plurality of third shift clock pads may be electrically connected to a corresponding second shift clock pad among the plurality of second shift clock pads provided in the second pad portion 210 through the wiring portion 250. For example, each of the plurality of third shift clock pads may be individually provided with one of the plurality of gate shift clocks from the timing controller 570 of the driving circuit unit 500. Each of the plurality of gate shift clocks according to an embodiment may be provided to the second shift clock pad provided in the second pad portion 210 through the corresponding third shift clock pad among the plurality of third shift clock pads and the wiring portion 250.

[0328] At least one third gate driving power supply pad may be electrically connected to at least one second gate driving power supply pad provided in second pad portion 210 via connection portion 250. For example, at least one third gate driving power supply pad may be supplied with gate driving power from power supply circuit unit 590 of driving circuit unit 500. The gate driving power according to an embodiment may be supplied to the second gate driving power supply pad provided in second pad portion 210 via corresponding third gate driving power supply pads among the plurality of third gate driving power supply pads and connection portion 250.

[0329] At least one third gate common power pad may be electrically connected to at least one second gate common power pad provided in the second pad portion 210 through the wiring portion 250. For example, the at least one third gate common power pad may be supplied with a gate common power supply from the power supply circuit unit 590 of the driving circuit unit 500. The gate common power supply according to an embodiment may be supplied to the second gate common power pad provided in the second pad portion 210 through a corresponding third gate common power pad among the plurality of third gate common power pads and the wiring portion 250.

[0330] The third pixel common power pad portion may include at least one third pixel common power pad CPP3 . The at least one third pixel common power pad CPP3 may be disposed in the third region of the third pad portion 230 .

[0331] At least one third pixel common power pad CPP3 may be individually (or separately) connected to a corresponding second pixel common power pad CPP2 provided in the second pad portion 210 through a connection portion 250. For example, the at least one third pixel common power pad CPP3 may be supplied with a pixel common power from the power circuit unit 590 of the driving circuit unit 500. The pixel common power according to an embodiment may be supplied to each of the plurality of second pixel common power pads CPP2 provided in the second pad portion 210 through a corresponding third pixel common power pad CPP3 among the plurality of third pixel common power pads CPP3 and the connection portion 250.

[0332] The third pad portion 230 may further include a first dummy region disposed between the first region and the second region and including a plurality of dummy pads, and a second dummy region disposed between the first region and the third region and including a plurality of dummy pads.

[0333] The third pad portion 230 according to an embodiment may further include a third reference power source pad portion.

[0334] The third reference power source pad portion may be electrically connected to the second reference power source pad portion of the second pad portion 210 through the wiring portion 250 .

[0335] The third reference power pad portion according to an embodiment may include a plurality of third reference power pads RPP3 , which may be arranged in parallel along the first direction X and spaced apart from each other in the first region of the third pad portion 230 .

[0336] Each of the plurality of third reference power supply pads RPP3 according to an embodiment may be individually (or separately) connected to a corresponding second reference power supply pad RPP2 among the plurality of second reference power supply pads RPP2 provided in the second pad portion 210 through the connection portion 250. For example, each of the plurality of third reference power supply pads RPP3 may be supplied with a reference power supply from the driving IC 530 of the driving circuit unit 500. The reference power supply according to an embodiment may be supplied to each of the plurality of second reference power supply pads RPP2 provided in the second pad portion 210 through the corresponding third reference power supply pad RPP3 among the plurality of third reference power supply pads RPP3 and the connection portion 250.

[0337] Each of the multiple third pixel driving power pads PPP3, the multiple third data pads DP3 and the multiple third reference power pads RPP3 in the first area of ​​the third pad portion 230 can be arranged in parallel in the same order as the arrangement order of the multiple second pixel driving power pads PPP2, the multiple second data pads DP2 and the multiple second reference power pads RPP2 arranged in the second pad portion 210.

[0338] The connection portion 250 may be disposed between the second pad portion 210 and the third pad portion 230. The connection portion 250 may include a plurality of connection lines that individually (or separately) connect the second pad of the second pad portion 210 to the third pad of the third pad portion 230.

[0339] According to one embodiment, the plurality of lines may be divided (or classified) into a plurality of data lines 251, a plurality of gate lines 253, a plurality of pixel driving power lines 255, and a pixel common power line 257. Therefore, the line portion 250 may include a plurality of data lines 251, a plurality of gate lines 253, a plurality of pixel driving power lines 255, and a pixel common power line 257.

[0340] According to another embodiment, the connection portion 250 may include a data connection portion, a gate connection portion, a pixel driving power connection portion, and a pixel common power connection portion.

[0341] The data connection line portion (or the first connection line portion) may electrically connect the second data pad portion of the second pad portion 210 to the third data pad portion of the third pad portion 230 .

[0342] The data connection line portion according to one embodiment may include a plurality of data connection lines 251. Each of the plurality of data connection lines (or first connection lines) 251 may individually (or separately) connect a corresponding second data pad among the plurality of second data pads DP2 provided in the second pad portion 210 to a corresponding third data pad among the plurality of third data pads DP3 provided in the third pad portion 230. Therefore, a data signal provided to each of the plurality of third data pads DP3 may be provided to the corresponding second data pad DP2 through the corresponding data connection line 251 and may be provided to the corresponding data lines DLo and DLe through the corresponding data wiring line 410 and the corresponding first data pad DP1.

[0343] The gate wiring portion (or the second wiring portion) may electrically connect the second gate pad portion of the second pad portion 210 to the third gate pad portion of the third pad portion 230 .

[0344] The gate wiring portion according to an embodiment may include a plurality of gate wiring lines 253. Each of the plurality of gate wiring lines (or second wiring lines) 253 may individually (or separately) connect a corresponding second gate pad among a plurality of second gate pads DP2 provided in the second pad portion 210 to a corresponding third gate pad among a plurality of third gate pads GP3 provided in the third pad portion 230. Therefore, a gate control signal provided to each of the plurality of third gate pads GP3 may be provided to the corresponding second gate pad GP2 through the corresponding gate wiring line 253 and may be provided to the corresponding gate wiring line included in the gate control line group GCL through the corresponding gate wiring 430 and the corresponding first gate pad GP1.

[0345] According to one embodiment, the plurality of gate lines 253 may be divided (or classified) into a start signal line 253a, a plurality of shift clock lines 253b, at least one gate drive power line 253c, and at least one gate common power line 253d. Therefore, the gate line portion may include the start signal line 253a, the plurality of shift clock lines 253b, the at least one gate drive power line 253c, and the at least one gate common power line 253d.

[0346] The start signal connection line 253a may electrically connect the second start signal pad provided in the second pad portion 210 to the third start signal pad provided in the third pad portion 230. Therefore, the start signal provided to the third start signal pad may be provided to the second start signal pad through the start signal connection line and may be provided to the corresponding start signal line included in the gate control line group GCL through the start signal wiring and the first start signal pad.

[0347] Each of the plurality of shift clock connection lines 253b may electrically connect a corresponding second shift clock pad among the plurality of second shift clock pads provided in the second pad section 210 to a corresponding third shift clock pad among the plurality of third shift clock pads provided in the third pad section 230. Therefore, the gate shift clock supplied to each of the plurality of third shift clock pads may be supplied to the corresponding second shift clock pad through the corresponding shift clock connection line 253b and may be supplied to the corresponding shift clock line included in the gate control line group GCL through the shift clock wiring and the first shift clock pad.

[0348] At least one gate driving power connection line 253c may electrically connect at least one second gate driving power pad provided in the second pad portion 210 to at least one third gate driving power pad provided in the third pad portion 230. Therefore, the gate driving power supplied to the third gate driving power pad may be supplied to the second gate driving power pad through the gate driving power connection line 253c and may be supplied to the gate driving power lines included in the gate control line group GCL through the gate driving power wiring and the first gate driving power pad.

[0349] At least one gate common power connection line 253d may electrically connect at least one second gate common power pad provided in the second pad portion 210 to at least one third gate common power pad provided in the third pad portion 230. Therefore, the gate common power supplied to the third gate common power pad may be supplied to the second gate common power pad through the gate common power connection line 253d and may be supplied to the gate common power lines included in the gate control line group GCL through the gate common power wiring and the first gate common power pad.

[0350] The pixel driving power supply connection portion (or the third connection portion) may electrically connect the second pixel driving power supply pad portion of the second pad portion 210 to the third pixel driving power supply pad portion of the third pad portion 230 .

[0351] The pixel driving power supply connection portion according to one embodiment may include a plurality of pixel driving power supply connection lines 255. Each of the plurality of pixel driving power supply connection lines (or third connection lines) 255 may individually (or separately) connect the plurality of second pixel driving power supply pads PPP2 provided in the second pad portion 210 to the plurality of third pixel driving power supply pads PPP3 provided in the third pad portion 230. Therefore, the pixel driving power supplied to each of the plurality of third pixel driving power supply pads PPP3 may be supplied to the corresponding second pixel driving power supply pads PPP2 through the corresponding pixel driving power supply connection line 255 and may be supplied to the corresponding pixel driving power line PL through the pixel driving power supply wiring 450 and the corresponding first pixel driving power supply pad PPP1.

[0352] Each of the plurality of data lines 251, the plurality of gate lines 253, and the plurality of pixel driving power lines 255 may include a first line portion connected to the second pad portion 210, a second line portion connected to the third pad portion 230, and a third line portion connected between the first line portion and the second line portion. Each of the first line portion and the second line portion may have a straight line shape, and the third line portion may have a non-straight line shape. For example, the third line portion may have a disgonal shape corresponding to the shortest path between the first line portion and the second line portion.

[0353] The pixel common power connection line portion (or the fourth connection line portion) may electrically connect the second pixel common power pad portion of the second pad portion 210 to the pixel common power pad portion of the third pad portion 230 .

[0354] The pixel common power connection line portion according to an embodiment may include a pixel common power connection line 257. Each of the plurality of pixel common power connection lines (or fourth connection lines) 257 may commonly connect the plurality of second pixel common power pads CPP2 provided in the second pad portion 210 to the plurality of third pixel common power pads CPP3 provided in the third pad portion 230. Therefore, the pixel common power supplied to each of the at least one third pixel common power pad CPP3 may be supplied to the plurality of second pixel common power pads CPP2 through the pixel common power connection line 257, may be supplied to each of the plurality of pixel common power lines CPL through a corresponding pixel common power wiring line among the plurality of pixel common power wiring lines 470 and a corresponding first pixel common power pad among the plurality of first pixel common power pads CPP1, and may be supplied to the common electrode CE through each of the plurality of common power contact portions CPCP.

[0355] The pixel common power line 257 according to an embodiment may include a first common line 257 a , a second common line 257 b , and a plurality of third common lines 257 c .

[0356] The first common line 257a may be commonly connected to at least one third pixel common power pad CPP3 disposed in the third pad portion 230. For example, the first common line 257a may be disposed at one corner portion of the rear surface 200b of the second substrate 200.

[0357] The first common line 257a may be provided or formed on the rear surface 200b of the second substrate 200 between the second pad portion 210 and the third pad portion 230 to have a relatively wide size (or area) so that the voltage drop of the applied pixel common power is minimized. The size of the first common line 257a according to one embodiment may gradually increase in a direction from one side thereof to the other side thereof. For example, the size of the first common line 257a according to one embodiment may gradually increase in a direction from the third pad portion 230 to the outer surface OS of the second substrate 200.

[0358] In the first common line 257a according to one embodiment, one side adjacent to the third pad portion 230 may be commonly connected to at least one third pixel common power pad CPP3 provided in the third pad portion 230, and the other side adjacent to the second pad portion 210 may overlap with the second common line 257b. For example, the first common line 257a may be provided on the rear surface 200b of the second substrate 200 together with the data line 251 or the gate line 253.

[0359] The second common connection line 257b may be disposed at a first edge portion of the rear surface 200b of the second substrate 200 to overlap with the first edge portion of the first substrate 100 and to be adjacent to the second pad portion 210. The second common connection line 257b according to one embodiment may be disposed parallel to the first direction X to face all pads disposed in the second pad portion 210. For example, the second common connection line 257b may have a relatively wide bar shape (or area) to minimize a voltage drop of a pixel common voltage applied to the pixel common power connection line 257.

[0360] The second common line 257b may overlap with each of the plurality of pixel driving power lines 255, the plurality of data lines 251, and the plurality of gate lines 253. For example, the data lines 251 may be disposed on the gate lines 253, and the second common line 257b may be disposed on the pixel driving power line 255. In addition, the pixel driving power line 255 may be disposed on the gate lines 253 together with the data lines 251.

[0361] One side of the second common line 257b may be electrically connected to the other side of the first common line 257a through a wiring contact hole 257h.

[0362] Each of the plurality of third common lines 257c may be commonly connected to the second common line 257b and may be connected to a corresponding second pad among the plurality of second pads. According to one embodiment, each of the plurality of third common lines 257c may extend (or protrude) in a direction from the other side of the second common line 257b to the plurality of second pixel common power pads CPP2 provided in the second pad portion 210, and may be electrically connected to a corresponding second pixel common power pad among the plurality of second pixel common power pads CPP2. For example, each of the plurality of third common lines 257c may be formed together with the second common line 257b. In addition, the plurality of third common lines 257c and the second common line 257b may be formed together with the pads of the second pad portion 210.

[0363] The connection portion 250 according to an embodiment may further include a reference power connection portion.

[0364] The reference power connection portion (or the fifth connection portion) may electrically connect the second reference power pad portion of the second pad portion 210 to the third reference power pad portion of the third pad portion 230 .

[0365] The reference power supply wiring portion according to one embodiment may include a plurality of reference power supply wiring lines 259. Each of the plurality of reference power supply wiring lines (or fifth wiring lines) 259 may individually (individually) connect a corresponding second reference power supply pad among the plurality of second reference power supply pads RPP2 provided in the second pad portion 210 to a corresponding third reference power supply pad among the plurality of third reference power supply pads RPP3 provided in the third pad portion 230. Therefore, the reference voltage supplied to each of the plurality of third reference power supply pads RPP3 may be supplied to the corresponding second reference power supply pad RPP2 via the corresponding reference power supply wiring line 259 and may be supplied to the corresponding reference power supply line RL via the reference power supply wiring line 490 and the first reference power supply pad RPP1.

[0366] Each of the plurality of reference power supply lines 259 may include a first line portion connected to the corresponding second reference power supply pad RPP2, a second line portion connected to the third reference power supply pad RPP3, and a third line portion connected between the first and second line portions. Each of the first and second line portions may have a straight line shape, and the third line portion may have a non-straight line shape. For example, the third line portion may have a slanted line shape corresponding to the shortest path between the first and second line portions.

[0367] The connection portion 250 according to an embodiment may further include a gate control signal transmitting portion 254 .

[0368] The gate control signal transmitting portion (or the sixth wiring portion) 254 may bypass the third pad portion 230 and may electrically connect the third gate pad portion to the gate wiring portion.

[0369] The gate control signal transmission portion 254 according to an embodiment may include a plurality of gate control signal transmission lines.

[0370] Each of the plurality of gate control signal transmission lines (or sixth connection lines) can selectively connect a corresponding third gate pad among the plurality of third gate pads GP3 provided in the third pad portion 230 to a corresponding gate connection line among the plurality of gate connection lines. For example, the plurality of gate control signal transmission lines and the plurality of gate connection lines 253 can be provided on different layers on the rear surface 200b of the second substrate 200, and a corresponding side of each of the plurality of gate connection lines 253 can be electrically connected to the corresponding gate control signal transmission line through a connection contact hole. Alternatively, the other side of each of the plurality of gate connection lines 253 can pass through an area between two adjacent third pads and can be selectively connected to the plurality of gate control signal transmission lines without overlapping with the third pads provided in the third pad portion 230.

[0371] According to one embodiment, the plurality of gate control signal transmission lines may be divided (or classified) into a start signal transmission line 254a, a plurality of shift clock transmission lines 254b, at least one gate driving power transmission line 254c, and at least one gate common power transmission line 254d. Therefore, the gate control signal transmission portion 254 may include the start signal transmission line 254a, the plurality of shift clock transmission lines 254b, the at least one gate driving power transmission line 254c, and the at least one gate common power transmission line 254d.

[0372] The start signal transmission line 254a may electrically connect the third start signal pad to the start signal connection line 253a. The start signal transmission line 254a according to one embodiment may include one line portion electrically connected to the third start signal pad, another line portion electrically connected to the start signal connection line 253a, and an intermediate line portion electrically connected between the one line portion and the other line portion and bypassing the third pad portion 230.

[0373] One line portion of the start signal transmission line 254 a may be disposed parallel to the second direction Y and may be electrically connected to the third start signal pad.

[0374] Another line portion of the start signal transmission line 254a may be disposed adjacent to the third pad portion 230 in parallel with the first direction X and may be electrically connected to the start signal connection line 253a. For example, the other line portion of the start signal transmission line 254a may be electrically connected to the start signal connection line 253a via a connection contact hole. Thus, the start signal provided to the third start signal pad may be provided to the start signal line included in the gate control line group GCL via the start signal transmission line 254a, the start signal connection line 253a, the second start signal pad, the start signal wiring, and the first start signal pad.

[0375] The middle line portion of the start signal transmission line 254a may include a first middle line extending from one line portion in parallel with the first direction X, and a second middle line extending from the first middle line and spaced apart from one end (or left end) of the third pad portion 230 and electrically connected to the other line portion. For example, the middle line portion may have a “┏” shape that bypasses the third pad portion 230.

[0376] The start signal connection line 253a according to one embodiment may pass through the third pad portion 230 and may be electrically connected to another line portion of the start signal transmission line 254a. For example, the start signal connection line 253a may be provided to pass through an area between two adjacent third pads and not overlap with the third pads provided in the third pad portion 230. In this case, the start signal provided to the start signal connection line 253a does not change (or vary) based on the signal provided to the third pad and may be maintained at the original voltage level.

[0377] Each of the plurality of shift clock transmission lines 254b can selectively connect a corresponding third shift clock pad among the plurality of shift clock pads to a corresponding shift clock connection line among the plurality of shift clock connection lines 253b. For example, when the gate control signal transmission section 254 includes first to fourth shift clock transmission lines 254b and the connection section 250 includes first to fourth shift clock connection lines 253b, each of the plurality of first shift clock connection lines 253b can be commonly connected to the first shift clock transmission line 254b, each of the plurality of second shift clock connection lines 253b can be commonly connected to the second shift clock transmission line 254b, each of the plurality of third shift clock connection lines 253b can be commonly connected to the third shift clock transmission line 254b, and each of the plurality of fourth shift clock connection lines 253b can be commonly connected to the fourth shift clock transmission line 254b.

[0378] Each of the plurality of shift clock transmission lines 254b may be shaped to surround the start signal transmission line 254a and may be arranged parallel to the start signal transmission line 254a, bypassing the third pad portion 230. According to one embodiment, each of the plurality of shift clock transmission lines 254b may include one line portion electrically connected to the corresponding third shift clock pad, another line portion electrically connected to the corresponding shift clock connection line 253b, and an intermediate line portion electrically connected between the one line portion and the other line portion, bypassing the third pad portion 230. For example, the other line portion of each of the plurality of shift clock transmission lines 254b may be electrically connected to the corresponding shift clock connection line 253b via a connection contact hole. Therefore, the gate shift clock supplied to each of the plurality of third shift clock pads may be supplied to the shift clock lines included in the gate control line group GCL via the corresponding shift clock transmission line 254b, the corresponding shift clock connection line 253b, the corresponding second shift clock pad, the corresponding gate shift clock wiring, and the corresponding first shift clock pad.

[0379] Each of the plurality of shift clock lines 253b according to one embodiment may pass through the third pad section 230 and may be electrically connected to another line portion of the corresponding shift clock transmission line 254b. For example, each of the plurality of shift clock lines 253b may be provided so as to pass through an area between two adjacent third pads without overlapping with a third pad provided in the third pad section 230. In this case, the gate shift clock supplied to each of the plurality of shift clock lines 253b does not change (or vary) based on the signal supplied to the third pad and may be maintained at the original voltage level.

[0380] At least one gate driving power transmission line 254c may electrically connect at least one gate driving power pad to at least one gate driving power connection line 253c.

[0381] At least one gate drive power transmission line 254c may be shaped to surround the outermost shift clock transmission line 254b and may be arranged parallel to the shift clock transmission line 254b, bypassing the third pad portion 230. According to one embodiment, the at least one gate drive power transmission line 254c may include one line portion electrically connected to the third gate drive power pad, another line portion electrically connected to the gate drive power connection line 253c, and an intermediate line portion electrically connected between the one line portion and the other line portion, bypassing the third pad portion 230. For example, the other line portion of the at least one gate drive power transmission line 254c may be electrically connected to the gate drive power connection line 253c via a connection contact hole. Therefore, the gate drive power supplied to the at least one gate drive power pad can be supplied to the gate drive power lines included in the gate control line group GCL via the gate drive power transmission line 254c, the gate drive power connection line 253c, the second gate drive power pad, the gate drive power wiring, and the first gate drive power pad.

[0382] At least one gate driving power supply line 253c according to one embodiment may pass through the third pad portion 230 and may be electrically connected to another line portion of the gate driving power supply transmission line 254c. For example, at least one gate driving power supply line 253c may be provided to pass through an area between two adjacent third pads without overlapping with the third pads provided in the third pad portion 230. In this case, the gate driving power supplied to the gate driving power supply line 253c does not change (or vary) based on the signal supplied to the third pad and may be maintained at the original voltage level.

[0383] At least one gate common power transmission line 254d may electrically connect at least one gate common power pad to at least one gate common power connection line 253d.

[0384] At least one gate common power transmission line 254d may have a shape surrounding the gate drive power transmission line 254c and may be arranged parallel to the gate drive power transmission line 254c, bypassing the third pad portion 230. According to one embodiment, the at least one gate common power transmission line 254d may include one line portion electrically connected to the third gate common power pad, another line portion electrically connected to the gate common power connection line 253d, and an intermediate line portion electrically connected between the one line portion and the other line portion, bypassing the third pad portion 230. For example, the other line portion of the at least one gate common power transmission line 254d may be electrically connected to the gate common power connection line 253d via a connection contact hole. Therefore, the gate common power supplied to the at least one gate common power pad may be supplied to the gate common power lines included in the gate control line group GCL via the gate common power transmission line 254d, the gate common power connection line 253d, the second gate common power pad, the gate common power wiring, and the first gate common power pad.

[0385] At least one gate common power connection line 253d according to one embodiment may pass through the third pad portion 230 and may be electrically connected to another line portion of the gate common power transmission line 254d. For example, at least one gate common power connection line 253d may be provided to pass through an area between two adjacent third pads without overlapping with the third pads provided in the third pad portion 230. In this case, the gate common power supplied to the gate common power connection line 253d does not change (or vary) based on the signal supplied to the third pad and may be maintained at the original voltage level.

[0386] Figure 11 It is a diagram Figure 7 The circuit diagram of the i-th stage circuit unit is shown in .

[0387] Reference Figures 6 to 8 and Figure 11 , the i-th stage circuit unit 150i according to the present invention may output two scan signals SSi and SSi+1 and a carry signal CSi in response to a gate control signal provided from a gate control line group GCL disposed on the first substrate 100.

[0388] According to one embodiment, the gate control signal may include: a start signal Vst; a plurality of shift clocks including a plurality of scan clocks sCLK and a plurality of carry clocks cCLK; first to third gate drive power supplies GVdd1, GVdd2, and GVdd3; and first and second gate common power supplies GVss1 and GVss2. In this case, the gate control line group GCL may include a start signal line, a plurality of scan clock lines, a plurality of carry clock lines, first to third gate drive power supply lines, and first and second gate common power supply lines.

[0389] The gate control signal according to an embodiment may include first to j-th carry clocks and first to j-th scan clocks. For example, j may be 4, but is not limited thereto, and may be 6, 8, 10, or a greater even number.

[0390] When the gate control signal includes the first to fourth carry clocks, the first carry clock may be applied to the 4k-3 (where k is a natural number) stage circuit unit, the second carry clock may be applied to the 4k-2 stage circuit unit, the third carry clock may be applied to the 4k-1 stage circuit unit, and the fourth carry clock may be applied to the 4k stage circuit unit. When the gate control signal includes the first to fourth scan clocks, the first and second scan clocks may be applied to the odd-numbered stage circuit units, and the third and fourth scan clocks may be applied to the even-numbered stage circuit units.

[0391] In addition, the gate control signal according to an embodiment may further include a forward driving signal FWS and a reverse driving signal BWS. In this case, the gate control line group GCL may further include a forward driving signal line and a reverse driving signal line.

[0392] The gate control signal according to one embodiment may further include an external sensing line selection signal Slss, an external sensing reset signal Srst, and an external sensing control signal Scs for an external sensing mode. In this case, the gate control line group GCL may further include an external sensing selection signal line, an external sensing reset signal line, and an external sensing control signal line.

[0393] The i-th stage circuit unit 150i according to the present invention may include a branch network 153, a node control circuit NCC, a first inverter circuit IC1, a second inverter circuit IC2, a node reset circuit NRC, and an output buffer circuit OBC.

[0394] The branch net 153 may be implemented as a line forming circuit connections between the node control circuit NCC, the first inverter circuit IC1, the second inverter circuit IC2, the node reset circuit NRC, and the output buffer circuit OBC and selectively connectable to the gate control line group GCL.

[0395] The branch net 153 may be selectively connected to lines of the gate control line group GCL. The branch net 153 according to an embodiment may include first to third control nodes Q, QBo, and QBe and a net line NL.

[0396] Each of the first to third control nodes Q, QBo, and QBe may be disposed in an upper edge region (or lower edge region) of each pixel region arranged in the i-th horizontal row of the first substrate 100. Each of the first to third control nodes Q, QBo, and QBe may be disposed parallel to the first direction X or the gate line. For example, each of the first to third control nodes Q, QBo, and QBe may be disposed adjacent to the gate line.

[0397] The net line NL may be selectively connected to the lines of the gate control line group GCL and may be selectively connected to the first to third control nodes Q, QBo, and QBe. In addition, the net line NL may be selectively connected between circuits constituting the stage circuit unit 150i.

[0398] The node control circuit NCC may be implemented to control a voltage of each of the first to third control nodes Q, QBo, and QBe.

[0399] The node control circuit NCC according to one embodiment can be connected to each of the first to third control nodes Q, QBo, and QBe via a network line NL, and can be implemented to control the voltage of each of the first to third control nodes Q, QBo, and QBe in response to a start signal Vst, a reset signal Vrst, and a first gate drive power supply GVdd1 provided via the network line NL. For example, the start signal Vst can be the i-2th carry signal CSi-2 output from the i-2th stage circuit unit 150i-2. The reset signal Vrst can be the i+2th carry signal CSi+2 output from the i+2th stage circuit unit 150i+2.

[0400] According to another embodiment, the node control circuit NCC may be connected to each of the first to third control nodes Q, QBo, and QBe via a network line NL, and may control the voltage of each of the first to third control nodes Q, QBo, and QBe in response to a start signal Vst, a reset signal Vrst, a forward drive signal FWS, a reverse drive signal BWS, and a first gate drive power supply GVdd1 provided via the network line NL. For example, when the forward drive signal FWS has a high voltage level (or a high potential voltage level), the reverse drive signal BWS may have a low voltage level (or a low potential voltage level); and when the forward drive signal FWS has a low voltage level (or a low potential voltage level), the reverse drive signal BWS may have a high voltage level (or a high potential voltage level). For example, when the forward drive signal FWS has a high voltage level, the gate drive circuit 150 may provide a scan signal from the first gate line to the last gate line based on the forward scan drive; and when the reverse drive signal BWS has a high voltage level, the gate drive circuit 150 may provide a scan signal from the last gate line to the first gate line based on the reverse scan drive. Herein, a high voltage level may be referred to as a first voltage level, a high potential voltage level, a gate-on voltage level, or a transistor-on voltage level, and a low voltage level may be referred to as a second voltage level, a low potential voltage level, a gate-off voltage level, or a transistor-off voltage level.

[0401] The first inverter circuit IC1 can control or discharge the voltage of the second control node QBo based on the voltage of the first control node Q. The first inverter circuit IC1 according to one embodiment can be connected to the second gate drive power supply GVdd2, the first control node Q, the second control node QBo, the first gate common power supply GVss1, and the second gate common power supply GVss2 via a network line NL. The first inverter circuit IC1 can supply the first gate common power supply GVss1 to the second control node QBo in response to the second gate drive power supply GVdd2 and the voltage of the first control node Q to discharge the voltage of the second control node QBo.

[0402] The second inverter circuit IC2 can control or discharge the voltage of the third control node QBe based on the voltage of the first control node Q. According to one embodiment, the second inverter circuit IC2 can be connected to the third gate drive power supply GVdd3, the first control node Q, the third control node QBe, the first gate common power supply GVss1, and the second gate common power supply GVss2 via a network line NL. In response to the third gate drive power supply GVdd3 and the voltage of the first control node Q, the second inverter circuit IC2 can supply the first gate common power supply GVss1 to the third control node QBe to discharge the voltage of the third control node QBe.

[0403] The second gate driving power supply GVdd2 and the third gate driving power supply GVdd3 may have voltage levels that are in opposite phases (or opposite to each other). For example, when the second gate driving power supply GVdd2 has a high voltage level, the third gate driving power supply GVdd3 may have a low voltage level; and when the second gate driving power supply GVdd2 has a low voltage level, the third gate driving power supply GVdd3 may have a high voltage level.

[0404] The second gate common power source GVss2 and the first gate common power source GVss1 may have the same voltage level or different voltage levels.

[0405] The node reset circuit NRC may maintain a voltage level of each of the second control node QBo and the third control node QBe while the voltage of the first control node Q has a high voltage level.

[0406] According to one embodiment, the node reset circuit NRC can simultaneously reset the voltages of the second control node QBo and the third control node QBe in response to the start signal Vst and the reset signal Vrst provided via the network line NL. For example, the node reset circuit NRC can provide the first gate common power source GVss1 to the second control node QBo and the third control node QBe in response to the start signal Vst and the reset signal Vrst, thereby maintaining the second control node QBo and the third control node QBe at the voltage level of the first gate common power source GVss1.

[0407] According to another embodiment, the node reset circuit NRC can simultaneously reset the voltage of the second control node QBo and the voltage of the third control node QBe in response to the start signal Vst, the reset signal Vrst, the forward drive signal FWS, and the reverse drive signal BWS provided via the network line NL. For example, the node reset circuit NRC can provide the first gate common power supply GVss1 to the second control node QBo and the third control node QBe in response to the start signal Vst, the reset signal Vrst, the forward drive signal FWS, and the reverse drive signal BWS, thereby maintaining each of the second control node QBo and the third control node QBe at the voltage level of the first gate common power supply GVss1.

[0408] The output buffer circuit OBC can be implemented as sequentially outputting two scan signals with gate-on voltage levels or sequentially outputting two scan signals with gate-off voltage levels in response to the voltage of each of the first to third control nodes Q, QBo and QBe based on the carry clock cCLK, the scan clock sCLK, the first gate common power supply GVss1 and the third gate common power supply GVss3 provided through the network line NL.

[0409] When the voltage of the first control node Q has a high voltage level and the voltages of the second control node QBo and the third control node QBe have a low voltage level, the output buffer circuit OBC according to one embodiment can output each of the i-th carry signal CSi corresponding to the carry clock cCLK, the i-th scan signal SSi corresponding to the odd scan clock sCLKo, and the i+1-th scan signal SSi+1 corresponding to the even scan clock sCLKe. For example, the i-th carry signal CSi can be provided as the start signal Vst to the i+2-th stage circuit unit, the i-th scan signal SSi can be provided to the odd gate line GLo (or the i-th gate line GLi), and the i+1-th scan signal SSi+1 can be provided to the even gate line GLe (or the i+1-th gate line GLi+1).

[0410] When the voltage of each of the first control node Q and the third control node QBe has a low voltage level and the voltage of the second control node QBo has a high voltage level, the output buffer circuit OBC according to one embodiment can output each of the i-th scan signal SSi and the i+1-th scan signal SSi+1, each having a gate-off voltage level corresponding to the voltage level of the third gate common power supply GVss3, and can output the i-th carry signal CSi having a gate-off voltage level corresponding to the voltage level of the first gate common power supply GVss1.

[0411] When the voltage of each of the first control node Q and the second control node QBo has a low voltage level and the voltage of the third control node QBe has a high voltage level, the output buffer circuit OBC according to one embodiment can output each of the i-th scan signal SSi and the i+1-th scan signal SSi+1, each having a gate-off voltage level corresponding to the voltage level of the third gate common power supply GVss3, and can output the i-th carry signal CSi having a gate-off voltage level corresponding to the voltage level of the first gate common power supply GVss1.

[0412] According to one embodiment, the output buffer circuit OBC may be disposed in a central region of an i-th horizontal line parallel to the first direction X. For example, when the output buffer circuit OBC is disposed adjacent to one end (or the other end) of the horizontal line, the voltage level of the scan signal may decrease along the direction from one end to the other end of the gate line due to the line resistance of the horizontal line. Therefore, to prevent this problem, the output buffer circuit OBC should be disposed in a central region of the i-th horizontal line parallel to the first direction X, but the present invention is not limited thereto. When the total length of the gate lines is relatively short, the output buffer circuit OBC may be disposed on one side or the other side of the i-th horizontal line.

[0413] The first to third gate common power supplies GVss1 , GVss2 , and GVss3 may have the same voltage level or different voltage levels.

[0414] The i-th stage circuit unit 150 i according to the present invention may further include a fourth control node Qm, a first sensing control circuit SCC1 , and a second sensing control circuit SCC2 .

[0415] The fourth control node Qm may be implemented as an electrical connection between the first sensing control circuit SCC1 and the second sensing control circuit SCC2. The fourth control node Qm may be included in the branch network 153 and may be electrically connected between the first sensing control circuit SCC1 and the second sensing control circuit SCC2 via a network line NL.

[0416] The first sensing control circuit SCC1 may be implemented to control the voltage of each of the first control node Q and the fourth control node Qm in response to the i-th carry signal CSi, the external sensing line selection signal Slss, the external sensing control signal Scs, the external sensing reset signal Srst, and the first gate driving power supply GVdd1 provided through the branch network 153. For example, the first sensing control circuit SCC1 may charge the first gate driving power supply GVdd1 into the fourth control node Qm in response to the i-th carry signal CSi having a high voltage level and the external sensing line selection signal Slss having a high voltage level, and may then control the voltage of the first control node Q in response to the voltage charged into the fourth control node Qm, the external sensing control signal Scs having a high voltage level provided in the early stage of the vertical blanking period, and the first gate driving power supply GVdd1. Therefore, the output buffer circuit OBC can output each of the i-th carry signal CSi corresponding to the carry clock cCLK, the i-th scan signal SSi corresponding to the odd scan clock sCLKo, and the i+1-th scan signal SSi+1 corresponding to the even scan clock sCLKe during the vertical blanking period based on the voltage of the first control node Q.

[0417] In addition, the first sensing control circuit SCC1 may discharge the voltage of the first control node Q in response to the external sensing reset signal Srst provided through the branch network 153. For example, the first sensing control circuit SCC1 may supply the first gate common power GVss1 to the first control node Q in response to the external sensing reset signal Srst having a high voltage level provided in the latter part of the vertical blanking period to reset or initialize the voltage of the first control node Q.

[0418] The second sense control circuit SCC2 may be implemented to discharge the voltage of each of the second control node QBo and the third control node QBe in response to the voltage of the fourth control node Qm and the external sense control signal Scs provided through the branch net 153. For example, the second sense control circuit SCC2 may supply the first gate common power source GVss1 to each of the second control node QBo and the third control node QBe in response to the voltage of the fourth control node Qm having a high voltage level and the external sense control signal Scs having a high voltage level to simultaneously discharge the second control node QBo and the third control node QBe.

[0419] Figure 12 It is a diagram Figure 11 A circuit diagram of each of the node control circuit, the first inverter circuit, the second inverter circuit and the first sensing control circuit shown in FIG.

[0420] Reference Figure 11 and Figure 12 , the node control circuit NCC according to an embodiment may include first to fourth node control circuits NCC1 to NCC4 .

[0421] In the forward scan driving, the first node control circuit NCC1 may charge the high voltage level of the forward drive signal FWS into the first control node Q in response to the start signal Vst having a high voltage level and the forward drive signal FWS having a high voltage level. In addition, in the reverse scan driving, the first node control circuit NCC1 may electrically connect the forward drive signal line having a low voltage level to the first control node Q in response to the start signal Vst having a high voltage level and the forward drive signal FWS having a low voltage level to discharge the voltage charged in the first control node Q to a low voltage level.

[0422] The first node control circuit NCC1 may include first to third TFTs T1 to T3 .

[0423] The first TFT T1 may output the forward driving signal FWS to the first connection node Nc1 in response to the start signal Vst. For example, the first TFT T1 may be turned on based on the start signal Vst having a high voltage level and may output the forward driving signal FWS provided through the forward driving signal line to the first connection node Nc1.

[0424] The second TFT T2 may electrically connect the first connection node Nc1 to the first control node Q in response to the start signal Vst. For example, the second TFT T2 may be turned on based on the start signal Vst having a high voltage level and may output the forward driving signal FWS provided through the first TFT T1 and the first connection node Nc1 to the first control node Q.

[0425] The third TFT T3 may supply the first gate driving power GVdd1 provided via the first gate driving power line to the first connection node Nc1 in response to the voltage of the first control node Q. For example, the third TFT T3 may be turned on based on the voltage of the first control node Q having a high voltage level and may transmit the first gate driving power GVdd1 to the first connection node Nc1 between the first TFT T1 and the second TFT T2, thereby preventing leakage of the voltage of the first control node Q. For example, the third TFT T3 may increase the voltage difference between the gate voltage of the second TFT T2 and the voltage of the first connection node Nc1, thereby turning off the second TFT T2, which is turned off based on the start signal Vst having a low voltage level. This may prevent a voltage drop in the first control node Q via the turned-off second TFT T2, thereby stably maintaining the voltage of the first control node Q.

[0426] In the reverse scan driving, the second node control circuit NCC2 may charge the high voltage level of the reverse driving signal BWS into the first control node Q in response to the reset signal Vrst having a high voltage level and the reverse driving signal BWS having a high voltage level. In addition, in the forward scan driving, the second node control circuit NCC2 may electrically connect the reverse driving signal line having a low voltage level to the first control node Q in response to the reset signal Vrst having a high voltage level and the reverse driving signal BWS having a low voltage level to discharge the voltage charged in the first control node Q to a low voltage level.

[0427] The second node control circuit NCC2 according to an embodiment may include a fourth TFT T4 and a fifth TFT T5 .

[0428] The fourth TFT T4 may output the reverse driving signal BWS in response to the reset signal Vrst. For example, the fourth TFT T4 may be turned on based on the reset signal Vrst having a high voltage level and may output the reverse driving signal BWS provided through the reverse driving signal line to the second connection node Nc2.

[0429] The fifth TFT T5 may electrically connect the second connection node Nc2 to the first control node Q in response to the reset signal Vrst. For example, the fifth TFT T5 may be turned on based on the reset signal Vrst having a high voltage level and may output the reverse driving signal BWS provided through the fourth TFT T4 and the second connection node Nc2 to the first control node Q.

[0430] A second connection node Nc2 between the fourth TFT T4 and the fifth TFT T5 can be electrically connected to the first connection node Nc1. Therefore, the first gate drive power supply GVdd1 supplied via the first gate drive power supply line can be supplied to the second connection node Nc2 via the third TFT T3 of the first node control circuit NCC1. Therefore, the third TFT T3 of the first node control circuit NCC1 can increase the voltage difference between the gate voltage of the fifth TFT T5 of the second node control circuit NCC2 and the voltage of the second connection node Nc2, thereby completely turning off the fifth TFT T5, which is turned off based on the reset signal Vrst having a low voltage level. This prevents a voltage drop (or current leakage) from occurring at the first control node Q via the turned-off fifth TFT T5, thereby stably maintaining the voltage of the first control node Q.

[0431] The third node control circuit NCC3 may discharge the voltage of the first control node Q in response to the voltage of the second control node QBo. For example, the third node control circuit NCC3 may form a current path between the first control node Q and the first gate common power line based on the high voltage level of the second control node QBo to discharge the voltage of the first control node Q to the first gate common power line.

[0432] The third node control circuit NCC3 according to an embodiment may include a sixth TFT T6 and a seventh TFT T7.

[0433] The sixth TFT T6 may supply the first gate common power GVss1 provided through the first gate common power line to the second connection node Nc2 in response to the voltage of the second control node QBo. For example, the sixth TFT T6 may be turned on based on the high voltage level of the second control node QBo and may electrically connect the second connection node Nc2 to the first gate common power line.

[0434] The seventh TFT T7 may electrically connect the second connection node Nc2 to the first control node Q in response to the voltage of the second control node QBo. For example, the seventh TFT T7 may be turned on based on the high voltage level of the second control node QBo and may electrically connect the second connection node Nc2 to the first control node Q.

[0435] The seventh TFT T7 may be turned off based on the low voltage level of the second control node QBo, and based on the first gate driving power GVdd1 supplied to the second connection node Nc2 via the third TFT T3 of the first node control circuit NCC1, a voltage difference between the gate voltage of the turned-off seventh TFT T7 and the voltage of the second connection node Nc2 may increase. As a result, the seventh TFT T7, which is turned off based on the low voltage level of the second control node QBo, may be completely turned off based on the first gate driving power GVdd1 supplied to the second connection node Nc2. Therefore, since the seventh TFT T7 is completely turned off, a voltage drop (or current leakage) at the first control node Q via the third node control circuit NCC3 may be prevented, thereby stably maintaining the voltage of the first control node Q.

[0436] The fourth node control circuit NCC4 may discharge the voltage of the first control node Q in response to the voltage of the third control node QBe. For example, the fourth node control circuit NCC4 may form a current path between the first control node Q and the first gate common power line based on the high voltage level of the third control node QBe to discharge the voltage of the first control node Q to the first gate common power line.

[0437] The fourth node control circuit NCC4 according to an embodiment may include an eighth TFT T8 and a ninth TFT T9 .

[0438] The eighth TFT T8 may supply the first gate common power GVss1 provided through the first gate common power line to the second connection node Nc2 in response to the voltage of the third control node QBe. For example, the eighth TFT T8 may be turned on based on the high voltage level of the third control node QBe and may electrically connect the second connection node Nc2 to the first gate common power line.

[0439] The ninth TFT T9 may electrically connect the second connection node Nc2 to the first control node Q in response to the voltage of the third control node QBe. For example, the ninth TFT T9 may be turned on based on the high voltage level of the third control node QBe and may electrically connect the second connection node Nc2 to the first control node Q.

[0440] The ninth TFT T9 may be turned off based on the low voltage level of the third control node QBe, and based on the first gate drive power GVdd1 supplied to the second connection node Nc2 via the third TFT T3 of the first node control circuit NCC1, a voltage difference between the gate voltage of the turned-off ninth TFT T9 and the voltage of the second connection node Nc2 may increase. As a result, the ninth TFT T9, which is turned off based on the low voltage level of the third control node QBe, may be completely turned off based on the first gate drive power GVdd1 supplied to the second connection node Nc2. Therefore, since the ninth TFT T9 is completely turned off, a voltage drop (or current leakage) at the first control node Q via the fourth node control circuit NCC4 may be prevented, thereby stably maintaining the voltage of the first control node Q.

[0441] The first inverter circuit IC1 may discharge the voltage of the second control node QBo in response to the voltage of the first control node Q and the second gate driving power supply GVdd2. For example, the first inverter circuit IC1 may form a current path between the second control node QBo and the first gate common power line based on the high voltage level of the first control node Q to discharge the voltage of the second control node QBo to the first gate common power line.

[0442] The first inverter circuit IC1 according to an embodiment may include tenth to thirteenth TFTs T10 to T13 and a first capacitor C1.

[0443] The tenth TFT T10 may be turned on or off based on the second gate driving power source GVdd2 and may output the second gate driving power source GVdd2 having a high voltage level to the first internal node Ni1 when turned on. The tenth TFT T10 according to an embodiment may be diode-connected between the second gate driving power source GVdd2 and the first internal node Ni1.

[0444] The eleventh TFT T11 may be turned on or off based on the voltage of the first control node Q and may discharge the voltage of the first internal node Ni1 to the second gate common power line when turned on.

[0445] The twelfth TFT T12 may be turned on or off based on the voltage of the first internal node Ni1 and may supply the second gate driving power GVdd2 to the second control node QBo when being turned on.

[0446] The thirteenth TFT T13 may be turned on or off based on the voltage of the first control node Q and may supply the voltage of the second control node QBo to the first gate common power line when being turned on.

[0447] The first capacitor C1 may be formed between the first internal node Ni1 and a node (or the second control node QBo) between the twelfth TFT T12 and the thirteenth TFT T13. For example, the first capacitor C1 may allow bootstrapping to occur in the first internal node Ni1 based on a voltage change of the second gate driving power supply GVdd2. Therefore, when the voltage level of the second gate driving power supply GVdd2 changes, the voltage of the first internal node Ni1 may further change in accordance with the voltage change of the second gate driving power supply GVdd2 due to the bootstrapping caused by the coupling of the first capacitor C1 and the second gate driving power supply GVdd2, thereby further enhancing the output characteristics of the twelfth TFT T12.

[0448] The second inverter circuit IC2 may discharge the voltage of the third control node QBe in response to the voltage of the first control node Q and the third gate driving power supply GVdd3. For example, the second inverter circuit IC2 may form a current path between the third control node QBe and the first gate common power line based on the high voltage level of the first control node Q to discharge the voltage of the third control node QBe to the first gate common power line.

[0449] The second inverter circuit IC2 according to an embodiment may include fourteenth to seventeenth TFTs T14 to T17 and a second capacitor C2.

[0450] The fourteenth TFT T14 may be turned on or off based on the third gate driving power source GVdd3 and may supply the third gate driving power source GVdd3 having a high voltage level to the second internal node Ni2 when turned on. The fourteenth TFT T14 according to an embodiment may be diode-connected between the third gate driving power source GVdd3 and the second internal node Ni2.

[0451] The fifteenth TFT T15 may be turned on or off based on the voltage of the first control node Q and may discharge the voltage of the second internal node Ni2 to the second gate common power line when turned on.

[0452] The sixteenth TFT T16 may be turned on or off based on the voltage of the second internal node Ni2 and may supply the third gate driving power GVdd3 to the third control node QBe when being turned on.

[0453] The seventeenth TFT T17 may be turned on or off based on the voltage of the first control node Q and may provide the voltage of the third control node QBe to the first gate common power line when being turned on.

[0454] The second capacitor C2 may be formed between the second internal node Ni2 and a node (or the third control node QBe) between the sixteenth TFT T16 and the seventeenth TFT T17. For example, the second capacitor C2 may allow bootstrapping to occur in the second internal node Ni2 based on a voltage change of the third gate driving power supply GVdd3. Therefore, when the voltage level of the third gate driving power supply GVdd3 changes, the voltage of the second internal node Ni2 may further change in accordance with the voltage change of the third gate driving power supply GVdd3 due to bootstrapping caused by the coupling of the second capacitor C2 and the third gate driving power supply GVdd3, thereby further enhancing the output characteristics of the sixteenth TFT T16.

[0455] The first sensing control circuit SCC1 may be implemented to control a voltage of each of the first and fourth control nodes Q and Qm in response to an i-th carry signal CSi, an external sensing line selection signal Slss, an external sensing control signal Scs, an external sensing reset signal Srst, and a first gate driving power supply GVdd1.

[0456] The first sensing control circuit SCC1 according to an embodiment may include a fifth node control circuit NCC5 and a sixth node control circuit NCC6 .

[0457] The fifth node control circuit NCC5 may control a voltage of each of the first and fourth control nodes Q and Qm in response to the i-th carry signal CSi, the external sensing line selection signal Slss, the external sensing control signal Scs, and the first gate driving power supply GVdd1 .

[0458] The fifth node control circuit NCC5 according to an embodiment may include thirty-third to thirty-seventh TFTs T33 to T37 and a third capacitor C3 .

[0459] The thirty-third TFT T33 may output the i-th carry signal CSi to the third connection node Nc3 in response to the external sensing line selection signal Slss provided together with the start signal Vst. For example, the thirty-third TFT T33 may be turned on based on the external sensing line selection signal Slss having a high voltage level and may output the i-th carry signal CSi to the third connection node Nc3.

[0460] The 34th TFT T34 may electrically connect the third connection node Nc3 to the fourth control node Qm in response to the external sensing line selection signal Slss. For example, the 34th TFT T34 may be turned on based on the external sensing line selection signal Slss having a high voltage level and may provide the i-th carry signal CSi provided through the 33rd TFT T33 and the third connection node Nc3 to the fourth control node Qm. The third connection node Nc3 may be a connection line between the 33rd TFT T33 and the 34th TFT T34.

[0461] The 35th TFT T35 may supply the first gate driving power source GVdd1 to the third connection node Nc3 in response to the voltage of the fourth control node Qm. For example, the 35th TFT T35 may be turned on based on the voltage of the fourth control node Qm having a high voltage level and may supply the first gate driving power source GVdd1 to the third connection node Nc3, thereby preventing the voltage of the fourth control node Qm from leaking. For example, the 35th TFT T35 may increase the voltage difference between the gate voltage of the 34th TFT T34 and the voltage of the third connection node Nc3, thereby completely turning off the 34th TFT T34, which has been turned off based on the external sensing line selection signal Slss having a low voltage level. This prevents a voltage drop (or current leakage) from occurring at the fourth control node Qm via the turned-off 34th TFT T34, thereby stably maintaining the voltage of the fourth control node Qm.

[0462] The 36th TFT T36 may output the first gate driving power GVdd1 to the 37th TFT T37 in response to the voltage of the fourth control node Qm. For example, the 36th TFT T36 may be turned on based on the voltage of the fourth control node Qm having a high voltage level and may supply the first gate driving power GVdd1 to the 37th TFT T37.

[0463] The thirty-seventh TFT T37 may electrically connect the thirty-sixth TFT T36 to the first control node Q in response to the external sensing control signal Scs. For example, the thirty-seventh TFT T37 may be turned on based on the external sensing control signal Scs having a high voltage level and may supply the first gate driving power GVdd1 supplied through the thirty-sixth TFT T36 to the first control node Q to charge the voltage level of the first gate driving power GVdd1 into the first control node Q.

[0464] The third capacitor C3 may be formed between the fourth control node Qm and the first gate drive power line and may store a differential voltage between the fourth control node Qm and the first gate drive power line. For example, a first electrode of the third capacitor C3 may be electrically connected to the fourth control node Qm, which is commonly connected to the gate electrode of the 35th TFT T35 and the gate electrode of the 36th TFT T36, and a second electrode of the third capacitor C3 may be electrically connected to the first gate drive power line. The third capacitor C3 may store the i-th carry signal CSi in response to the turning on of the 33rd TFT T33, the 34th TFT T34, and the 35th TFT T35. When the 33rd TFT T33, the 34th TFT T34, and the 35th TFT T35 are turned off, the third capacitor C3 may maintain the voltage of the fourth control node Qm at a high voltage level using the stored voltage. For example, the third capacitor C3 may maintain the voltage of the fourth control node Qm at a high voltage level during one horizontal period using the stored voltage.

[0465] The sixth node control circuit NCC6 may discharge the voltage of the first control node Q in response to the external sensing reset signal Srst. For example, the sixth node control circuit NCC6 may provide the first gate common power GVss1 to the first control node Q in response to the external sensing reset signal Srst having a high voltage level, thereby resetting or initializing the voltage of the first control node Q.

[0466] The sixth node control circuit NCC6 according to an embodiment may include a thirty-eighth TFT T38 and a thirty-ninth TFT T39 .

[0467] The thirty-eighth TFT T38 may supply the first gate common power GVss1 supplied through the first gate common power line to the second connection node Nc2 in response to the external sensing reset signal Srst. For example, the thirty-eighth TFT T38 may be turned on based on the external sensing reset signal Srst having a high voltage level and may output the first gate common power GVss1 to the second connection node Nc2.

[0468] The thirty-ninth TFT T39 may electrically connect the second connection node Nc2 to the first control node Q in response to the external sensing reset signal Srst. For example, the thirty-ninth TFT T39 may be turned on based on the external sensing reset signal Srst having a high voltage level and may supply the first gate common power GVss1 supplied through the thirty-eighth TFT T38 and the second connection node Nc2 to the first control node Q.

[0469] A second connection node Nc2 between the 38th TFT T38 and the 39th TFT T39 can be electrically connected to the first connection node Nc1. Therefore, the first gate drive power source GVdd1 can be supplied to the second connection node Nc2 via the third TFT T3 of the first node control circuit NCC1. Therefore, the third TFT T3 of the first node control circuit NCC1 can increase the difference voltage between the gate voltage of the 39th TFT T39 of the sixth node control circuit NCC6 and the voltage of the second connection node Nc2, thereby completely turning off the 39th TFT T39, which has been turned off based on the external sensing reset signal Srst having a low voltage level. This prevents a voltage drop (or current leakage) from occurring at the first control node Q via the turned-off 39th TFT T39, thereby stably maintaining the voltage of the first control node Q.

[0470] Alternatively, the first sensing control circuit SCC1 may be omitted. Specifically, the first sensing control circuit SCC1 may be a circuit for sensing the characteristic value of a driving TFT disposed in a subpixel of the pixel based on the pixel's external sensing mode. When the pixel is not driven in the external sensing mode, the first sensing control circuit SCC1 becomes an unnecessary component and may be omitted.

[0471] Figure 13 It is a diagram Figure 11 , which is a circuit diagram of each of the node reset circuit, the output buffer circuit, and the second sensing control circuit shown in FIG.

[0472] Reference Figure 11 and Figure 13 , the node reset circuit NRC according to an embodiment may maintain the voltage level of each of the second control node QBo and the third control node QBe while the voltage of the first control node Q has a high voltage level.

[0473] The node reset circuit NRC according to an embodiment may include eighteenth to twenty-third TFTs T18 to T23 .

[0474] The eighteenth TFT T18 may electrically connect the fourth connection node Nc4 to the forward driving signal line in response to the start signal Vst and the forward driving signal FWS. For example, the eighteenth TFT T18 may be turned on based on the start signal Vst having a high voltage level and may provide the forward driving signal FWS to the fourth connection node Nc4.

[0475] The nineteenth TFT T19 may electrically connect the second control node QBo to the first gate common power line in response to the voltage of the fourth connection node Nc4. For example, the nineteenth TFT T19 may be turned on based on the voltage of the fourth connection node Nc4 and may form a current path between the second control node QBo and the first gate common power line to discharge the voltage of the second control node QBo to the first gate common power line, thereby resetting the voltage of the second control node QBo to the voltage level of the first gate common power GVss1.

[0476] The twentieth TFT T20 may electrically connect the fourth connection node Nc4 to the first gate common power line in response to the voltage of the second control node QBo. For example, the twentieth TFT T20 may be turned on based on the high voltage level of the second control node QBo and may form a current path between the fourth connection node Nc4 and the first gate common power line to discharge the voltage of the fourth connection node Nc4 to the first gate common power line, thereby resetting the voltage of the fourth connection node Nc4 to the voltage level of the first gate common power line GVss1. Therefore, when the voltage of the second control node QBo has a high voltage level, the twentieth TFT T20 may reset the voltage of the fourth connection node Nc4 to the voltage level of the first gate common power line GVss1, thereby turning off the nineteenth TFT T19, thereby preventing the voltage of the second control node QBo from being discharged to the first gate common power line through the nineteenth TFT T19.

[0477] The twenty-first TFT T21 may electrically connect the fourth connection node Nc4 to the reverse driving signal line in response to the reset signal Vrst and the reverse driving signal BWS. For example, the twenty-first TFT T21 may be turned on based on the reset signal Vrst having a high voltage level and may provide the reverse driving signal BWS having a high voltage level to the fourth connection node Nc4.

[0478] The twenty-second TFT T22 may electrically connect the third control node QBe to the first gate common power line in response to the voltage of the fourth connection node Nc4. For example, the twenty-second TFT T22 may be turned on based on the voltage of the fourth connection node Nc4 and may form a current path between the third control node QBe and the first gate common power line to discharge the voltage of the third control node QBe to the first gate common power line, thereby resetting the voltage of the third control node QBe to the voltage level of the first gate common power GVss1.

[0479] The twenty-third TFT T23 may electrically connect the fourth connection node Nc4 to the first gate common power line in response to the voltage of the third control node QBe. For example, the twenty-third TFT T23 may be turned on based on the high voltage level of the third control node QBe and may form a current path between the fourth connection node Nc4 and the first gate common power line to discharge the voltage of the fourth connection node Nc4 to the first gate common power line, thereby resetting the voltage of the fourth connection node Nc4 to the voltage level of the first gate common power line GVss1. Therefore, when the voltage of the third control node QBe has a high voltage level, the twenty-third TFT T23 may reset the voltage of the fourth connection node Nc4 to the voltage level of the first gate common power line GVss1, thereby turning off the twenty-second TFT T22, thereby preventing the voltage of the third control node QBe from being discharged to the first gate common power line through the twenty-second TFT T22.

[0480] The nineteenth TFT T19 and the twenty-second TFT T22 may be simultaneously turned on or off based on the voltage of the fourth connection node Nc4 .

[0481] For example, in the forward scan drive of the gate driving circuit 150, the nineteenth TFT T19 and the twenty-second TFT T22 may be turned on at the same time based on the high voltage level of the forward driving signal FWS supplied to the fourth connection node Nc4 by the eighteenth TFT T18 turned on according to the start signal Vst having a high voltage level; and may be turned off at the same time based on the first gate common power supply GVss1 supplied to the fourth connection node Nc4 by the twentieth TFT T20 turned on according to the high voltage level of the second control node QBo; or may be turned off at the same time based on the first gate common power supply GVss1 supplied to the fourth connection node Nc4 by the twenty-third TFT T23 turned on according to the high voltage level of the third control node QBe.

[0482] As another example, in the reverse scan drive of the gate driving circuit 150, the nineteenth TFT T19 and the twenty-second TFT T22 may be turned on at the same time based on the high voltage level of the reverse driving signal BWS supplied to the fourth connection node Nc4 by the twenty-first TFT T21 turned on according to the reset signal Vrst having a high voltage level; and may be turned off at the same time based on the first gate common power supply GVss1 supplied to the fourth connection node Nc4 by the twenty-third TFT T23 turned on according to the high voltage level of the third control node QBe; or may be turned off at the same time based on the first gate common power supply GVss1 supplied to the fourth connection node Nc4 by the twentieth TFT T20 turned on according to the high voltage level of the second control node QBo.

[0483] The output buffer circuit OBC may receive a carry clock cCLK, an odd scan clock sCLKo, an even scan clock sCLKe, a first gate common power supply GVss1, a second gate common power supply GVss2, and a third gate common power supply GVss3, and may output an i-th scan signal SSi, an i+1-th scan signal SSi+1, and an i-th carry signal CSi based on the carry clock cCLK, the scan clock sCLK, and the third gate common power supply GVss3 in response to voltages of each of the first to third control nodes Q, QBo, and QBe. For example, when the voltage of the first control node Q has a high voltage level, the output buffer circuit OBC may output an i-th carry signal CSi corresponding to the carry clock cCLK, an i-th scan signal SSi corresponding to the odd scan clock sCLKo, and an i+1-th scan signal SSi+1 corresponding to the even scan clock sCLKe.

[0484] The output buffer circuit OBC according to an embodiment may include first to third output buffer circuits OBC1 to OBC3 .

[0485] The first output buffer circuit OBC1 may output the i-th scan signal SSi having a voltage level of the odd scan clock sCLKo or a voltage level of the third gate common power supply GVss3 based on a voltage of each of the first to third control nodes Q, QBo, and QBe.

[0486] The first output buffer circuit OBC1 according to an embodiment may include twenty-fourth to twenty-sixth TFTs T24 to T26 and a coupling capacitor Cc.

[0487] The twenty-fourth TFT T24 (or the first pull-up TFT) may transmit the odd scan clock sCLKo to the i-th gate line GLi through the first output node No1 based on the voltage of the first control node Q. For example, the twenty-fourth TFT T24 may include a gate electrode connected to the first control node Q, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode connected to the odd scan clock line.

[0488] The twenty-fifth TFT T25 (or the odd-numbered first pull-down TFT) may transmit the third gate common power GVss3 to the i-th gate line GLi through the first output node No1 based on the voltage of the second control node QBo. For example, the twenty-fifth TFT T25 may include a gate electrode connected to the second control node QBo, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode connected to the third gate common power line.

[0489] The twenty-sixth TFT T26 (or the even-numbered first pull-down TFT) may transmit the third gate common power GVss3 to the i-th gate line GLi through the first output node No1 based on the voltage of the third control node QBe. For example, the twenty-sixth TFT T26 may include a gate electrode connected to the third control node QBe, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode connected to the third gate common power line.

[0490] A coupling capacitor Cc may be formed between the first control node Q and the first output node No1. For example, the coupling capacitor Cc may be a parasitic capacitor between the gate electrode of the twenty-fourth TFT T24 and the first output node No1. The coupling capacitor Cc may allow bootstrapping to occur in the first control node Q based on a phase shift (or change) of the odd-numbered scan clock sCLKo. Therefore, when the odd-numbered scan clock sCLKo transitions from a low voltage level to a high voltage level, the voltage of the first control node Q may increase to a higher voltage due to the high voltage level of the odd-numbered scan clock sCLKo based on bootstrapping caused by coupling between the coupling capacitor Cc and the odd-numbered scan clock sCLKo having a high voltage level. For example, as the odd-numbered scan clock sCLKo having a high voltage level is supplied to the second source / drain electrode of the twenty-fourth TFT T24, the voltage of the first control node Q, which is precharged with the voltage level of the forward driving signal FWS through the first node control circuit NCC1, may increase to a higher voltage, and thus the twenty-fourth TFT T24 may be fully turned on, and the odd-numbered scan clock sCLKo having a high voltage level may be supplied as the i-th scan signal SSi through the first output node No1 and the turned-on twenty-fourth TFT T24 to the i-th gate line GLi without voltage loss.

[0491] The second output buffer circuit OBC2 may output the (i+1)th scan signal SSi+1 having the voltage level of the even scan clock sCLKe or the third gate common power supply GVss3 based on the voltage of each of the first to third control nodes Q, QBo, and QBe.

[0492] The second output buffer circuit OBC2 according to an embodiment may include twenty-seventh to twenty-ninth TFTs T27 to T29 .

[0493] The twenty-seventh TFT T27 (or the second pull-up TFT) can transmit the even scan clock sCLKe to the (i+1)-th gate line GLi+1 through the second output node No2 based on the voltage of the first control node Q. For example, the twenty-seventh TFT T27 may include a gate electrode connected to the first control node Q, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the even scan clock line. The twenty-seventh TFT T27 can be turned on based on the bootstrap voltage of the first control node Q, and thus can transmit the even scan clock sCLKe having a high voltage level provided through the even scan clock line as the (i+1)-th scan signal SSi+1 to the (i+1)-th gate line GLi+1 through the second output node No2 without voltage loss.

[0494] The twenty-eighth TFT T28 (or the odd-numbered second pull-down TFT) may transmit the third gate common power GVss3 to the (i+1)-th gate line GLi+1 through the second output node No2 based on the voltage of the second control node QBo. For example, the twenty-eighth TFT T28 may include a gate electrode connected to the second control node QBo, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the third gate common power line.

[0495] The twenty-ninth TFT T29 (or the even-numbered second pull-down TFT) may transmit the third gate common power GVss3 to the (i+1)-th gate line GLi+1 through the second output node No2 based on the voltage of the third control node QBe. For example, the twenty-ninth TFT T29 may include a gate electrode connected to the third control node QBe, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the third gate common power line.

[0496] The third output buffer circuit OBC3 may output an i-th carry signal CSi having a voltage level of the carry clock cCLK or a voltage level of the first gate common power supply GVss1 based on a voltage of each of the first to third control nodes Q, QBo, and QBe.

[0497] The third output buffer circuit OBC3 according to an embodiment may include 30th to 32nd TFTs T30 to T32 .

[0498] The 30th TFT T30 (or the third pull-up TFT) may output the carry clock cCLK as the i-th carry signal CSi through the third output node No3 based on the voltage of the first control node Q. For example, the 30th TFT T30 may include a gate electrode connected to the first control node Q, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the carry clock line. The 30th TFT T30 may be turned on based on the bootstrap voltage of the first control node Q and may output the carry clock cCLK having a high voltage level provided through the carry clock line as the i-th carry signal CSi through the third output node No3 without voltage loss.

[0499] The thirty-first TFT T31 (or the odd-numbered third pull-down TFT) may output the first gate common power GVss1 as the i-th carry signal CSi through the third output node No3 based on the voltage of the second control node QBo. For example, the thirty-first TFT T31 may include a gate electrode connected to the second control node QBo, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the first gate common power line.

[0500] The thirty-second TFT T32 (or the even-numbered third pull-down TFT) may output the first gate common power GVss1 as the i-th carry signal CSi through the third output node No3 based on the voltage of the third control node QBe. For example, the thirty-second TFT T32 may include a gate electrode connected to the third control node QBe, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the first gate common power line.

[0501] Alternatively, the coupling capacitor Cc may be formed between the first control node Q and the third output node No3. In addition, the coupling capacitor Cc may be formed in at least one of a region between the first control node Q and the first output node No1, a region between the first control node Q and the second output node No2, and a region between the first control node Q and the third output node No3.

[0502] The second sensing control circuit SCC2 may be implemented to discharge a voltage of each of the second control node QBo and the third control node QBe in response to a voltage of the fourth control node Qm and an external sensing control signal Scs.

[0503] The second sensing control circuit SCC2 according to an embodiment may include a first node discharge circuit NDC1 and a second node discharge circuit NDC2 .

[0504] The first node discharge circuit NDC1 may discharge the voltage of the second control node QBo in response to the voltage of the fourth control node Qm and the external sense control signal Scs. For example, the first node discharge circuit NDC1 may supply the first gate common power GVss1 to the second control node QBo in response to the voltage of the fourth control node Qm having a high voltage level and the external sense control signal Scs having a high voltage level, thereby discharging the voltage of the second control node QBo to the first gate common power line or resetting the voltage of the second control node QBo to the first gate common power GVss1.

[0505] The first node discharge circuit NDC1 according to an embodiment may include a fortieth TFT T40 and a forty-first TFT T41.

[0506] The 40th TFT T40 may transmit the first gate common power GVss1 to the 41st TFT T41 in response to the voltage of the fourth control node Qm. For example, the 40th TFT T40 may be turned on based on the high voltage level of the fourth control node Qm and may form a current path between the 41st TFT T41 and the first gate common power GVss1.

[0507] The forty-first TFT T41 may electrically connect the second control node QBo to the fortieth TFT T40 in response to the external sensing control signal Scs. For example, the forty-first TFT T41 may be turned on based on the external sensing control signal Scs having a high voltage level and may form a current path between the second control node QBo and the fortieth TFT T40. The forty-first TFT T41 may be turned on based on the external sensing control signal Scs having a high voltage level while the fortieth TFT T40 is turned on based on the high voltage level of the fourth control node Qm. Thus, the voltage of the second control node QBo may be discharged to the first gate common power line or reset to the first gate common power source GVss1 through each of the forty-first TFT T41 and the fortieth TFT T40.

[0508] The second node discharge circuit NDC2 may discharge the voltage of the third control node QBe in response to the voltage of the fourth control node Qm and the external sense control signal Scs. For example, the second node discharge circuit NDC2 may supply the first gate common power source GVss1 to the third control node QBe in response to the voltage of the fourth control node Qm having a high voltage level and the external sense control signal Scs having a high voltage level, thereby discharging the voltage of the third control node QBe to the first gate common power source line or resetting the voltage of the third control node QBe to the first gate common power source GVss1.

[0509] The second node discharge circuit NDC2 according to an embodiment may include a forty-second TFT T42 and a forty-third TFT T43.

[0510] The forty-second TFT T42 may transmit the first gate common power GVss1 to the forty-third TFT T43 in response to the voltage of the fourth control node Qm. For example, the forty-second TFT T42 may be turned on based on the high voltage level of the fourth control node Qm and may form a current path between the forty-third TFT T43 and the first gate common power GVss1.

[0511] The forty-third TFT T43 may electrically connect the third control node QBe to the forty-second TFT T42 in response to the external sensing control signal Scs. For example, the forty-third TFT T43 may be turned on based on the external sensing control signal Scs having a high voltage level and may form a current path between the third control node QBe and the forty-second TFT T42. The forty-third TFT T43 may be turned on based on the external sensing control signal Scs having a high voltage level while the forty-second TFT T42 is turned on based on the high voltage level of the fourth control node Qm. Thus, the voltage of the third control node QBe may be discharged to the first gate common power line or reset to the first gate common power source GVss1 through each of the forty-third TFT T43 and the forty-second TFT T42.

[0512] Alternatively, the second sensing control circuit SCC2 may be omitted along with the first sensing control circuit SCC1. That is, each of the first sensing control circuit SCC1 and the second sensing control circuit SCC2 may be a circuit for sensing the characteristic value of the driving TFT provided in the subpixel of the pixel based on the pixel's external sensing mode. When the pixel is not driven in the external sensing mode, each of the first sensing control circuit SCC1 and the second sensing control circuit SCC2 becomes an unnecessary component and may be omitted.

[0513] Figure 12 and Figure 13 The first to forty-third TFTs T1 to T43 shown in FIG. 1 may be separately arranged (or dispersedly arranged) in one horizontal row of the display area AA and may be connected to each other through the branch network 153, thereby forming a display area AA. Figure 7, a plurality of branch circuits 1511 to 151n are provided between a plurality of pixels P along a length direction of a plurality of gate lines and are connected to a gate control line group GCL. For example, each of the plurality of stage circuit units 1501 to 150m may include first to nth (where n is 43) branch circuits 1511 to 151n provided with or provided with one of the first to forty-third TFTs T1 to T43, but is not limited thereto. Based on the number of pixels provided in one horizontal row, each of the plurality of branch circuits 1511 to 151n may be implemented by at least one of the first to forty-third TFTs T1 to T43.

[0514] In addition, Figures 11 to 13 In the stage circuit unit 150i shown in FIG. Figure 8 When the first switching TFT Tsw1 and the second switching TFT Tsw2 in the pixel circuit PC of each of the plurality of sub-pixels SP1 to SP4 are turned on based on different first scanning signals and second scanning signals, the i-th scanning signal SSi may be used as the first scanning signal provided by the first gate line through the odd-numbered gate line GLo, and the i+1-th scanning signal SSi+1 may be used as the first scanning signal provided by the first gate line through the even-numbered gate line GLe. Therefore, Figures 11 to 13 The output buffer circuit OBC of the stage circuit unit 150 i shown in may further include a fourth output buffer circuit and a fifth output buffer circuit.

[0515] The fourth output buffer circuit may be implemented to output the second scan signal to the second gate line of the odd-numbered gate lines GLo, and the fifth output buffer circuit may be implemented to output the second scan signal to the second gate line of the even-numbered gate lines GLe.

[0516] The fourth output buffer circuit according to one embodiment may output the i-th second scan signal having the voltage level of the odd-numbered scan clock for the second scan or the voltage level of the third gate common power supply GVss3 based on the voltage of each of the first to third control nodes Q, QBo, and QBe. In addition to the fourth output buffer circuit outputting the i-th second scan signal based on the odd-numbered scan clock for the second scan, the fourth output buffer circuit may include Figure 13 The first output buffer circuit OBC1 shown in FIG. 1 has substantially the same three TFTs, and thus a detailed description thereof is omitted.

[0517] The fifth output buffer circuit according to one embodiment may output the (i+1)th second scan signal having the voltage level of the even scan clock for the second scan or the voltage level of the third gate common power supply GVss3 based on the voltage of each of the first to third control nodes Q, QBo, and QBe. In addition to the fifth output buffer circuit outputting the (i+1)th second scan signal based on the even scan clock for the second scan, the fifth output buffer circuit may include Figure 13 The second output buffer circuit OBC2 shown in FIG. 1 has substantially the same three TFTs, and thus a detailed description thereof is omitted.

[0518] exist Figure 11 and Figure 13 In the stage circuit unit 150i shown, the odd scan clock sCLKo can be referred to as the odd scan clock for the first scan, and the even scan clock sCLKe can be referred to as the even scan clock for the first scan. For example, the scan clock for the first scan and the scan clock for the second scan can have the same phase or different phases. In addition, the scan clock for the first scan and the scan clock for the second scan can have the same clock width or different clock widths.

[0519] Figure 14 is a description Figure 4 FIG. 1 is a diagram illustrating a gate driving circuit according to another embodiment of the present invention. Figure 6 and Figure 7 The configuration of each stage circuit unit in the gate drive circuit shown in FIG is modified. Figure 14 When, with Figure 6 and Figure 7 The same or corresponding elements are denoted by like reference numerals, and repeated descriptions thereof will be omitted or briefly described below.

[0520] Reference Figure 14 , the gate driving circuit 150 according to another embodiment may include a plurality of stage circuit units 1501 to 150m that are arranged in each horizontal row of the first substrate 100 along the first direction X and are subsidiaryly connected to each other along the second direction Y.

[0521] Each of the plurality of stage circuit units 1501 to 150m according to an embodiment may include a first stage circuit portion 151A and a second stage circuit portion 151B.

[0522] The first-stage circuit portion 151A may be disposed in one region of each horizontal line on the first surface 100 a of the first substrate 100 along the first direction X. The first-stage circuit portion 151A may generate a scan signal in response to a gate control signal provided through each line of the gate control line group GCL and may provide the scan signal to the corresponding gate line GL.

[0523] The first-stage circuit portion 151A according to one embodiment may include Figures 11 to 13 The first stage circuit portion 151A including these elements may include a branch network 153, a node control circuit NCC, a first inverter circuit IC1, a second inverter circuit IC2, a node reset circuit NRC and an output buffer circuit OBC. Figures 11 to 13 1 and 2. The components of the i-th stage circuit unit 150i are the same as those shown in FIG. 1 , and thus repeated description thereof is omitted.

[0524] The branch network 153 of the first-stage circuit portion 151A may include a plurality of first to third control nodes and network lines, and the plurality of first to third control nodes may be shared by the second-stage circuit portion 151B. That is, each of the first to third control nodes may be commonly connected to the first-stage circuit portion 151A and the second-stage circuit portion 151B.

[0525] According to one embodiment, the first-stage circuit portion 151A may include a node control circuit NCC, a first inverter circuit IC1, a second inverter circuit IC2, a node reset circuit NRC, and a plurality of branch circuits 1511 to 151n including at least one of TFTs T1 to T43 constituting an output buffer circuit OBC. Each of the plurality of branch circuits 1511 to 151n may be connected to each other via a branch network 153.

[0526] The second-level circuit portion 151B may be arranged in another area of ​​each horizontal row on the first surface 100a of the first substrate 100. The second-level circuit portion 151B may generate a scan signal in response to a gate control signal provided by each line of the gate control line group GCL and may provide the scan signal to the corresponding gate line GL. For example, the second-level circuit portion 151B may be electrically connected to the same gate line as the first-level circuit portion 151A, and may provide the same scan signal as the first-level circuit portion 151A to the same gate line. In this case, the gate drive circuit 150 may implement a double feeding method of providing a scan signal in one area and another area of ​​one gate line simultaneously through the first-level circuit portion 151A and the second-level circuit portion 151B, thereby preventing or minimizing the delay of the scan signal caused by the line resistance of each gate line.

[0527] Alternatively, when a driving error or failure occurs in the first-stage circuit portion 151A, the second-stage circuit portion 151B may be implemented as a redundant circuit for replacing the first-stage circuit portion 151A.

[0528] The second-stage circuit portion 151B according to an embodiment may include Figures 11 to 13The node control circuit NCC, the first inverter circuit IC1, the second inverter circuit IC2, the node reset circuit NRC and the output buffer circuit OBC shown in FIG. The second stage circuit portion 151B including these elements may include Figures 11 to 13 1 and 2. The components of the i-th stage circuit unit 150i are the same as those shown in FIG. 1 , and thus repeated description thereof is omitted.

[0529] The second-stage circuit portion 151B according to one embodiment may include a node control circuit NCC, a first inverter circuit IC1, a second inverter circuit IC2, a node reset circuit NRC, and a plurality of branch circuits 1511 to 151n including at least one of TFTs T1 to T43 constituting an output buffer circuit OBC. Each of the plurality of branch circuits 1511 to 151n may be connected to each other via a branch network 153.

[0530] Figure 15 It is along Figure 4 The cross-sectional view taken along the line II' shown in FIG. Figure 16 yes Figure 15 An enlarged view of area "B4" is shown in FIG. Figure 15 and Figure 16 is a diagram for describing the cross-sectional structure of each of the first substrate and the second substrate of the display device according to the present invention. Figure 15 and Figure 16 When, with Figure 4 The same or corresponding elements are denoted by like reference numerals, and repeated descriptions thereof will be omitted or briefly described below.

[0531] Reference Figure 4 、 Figure 6 、 Figure 8 、 Figure 15 and Figure 16 , the display apparatus 10 according to the present invention may include a first substrate 100 and a second substrate 200 that are bonded (or coupled) to each other by using a bonding member 300 .

[0532] The first substrate 100 according to an embodiment may include a circuit layer 101 , a planarization layer 102 , a light emitting device layer 103 , a bank 104 , a dam pattern 105 , and an encapsulation layer 106 .

[0533] The circuit layer 101 may be disposed on the first surface 100a of the first substrate 100. The circuit layer 101 may be referred to as a pixel array layer or a TFT array layer.

[0534] The circuit layer 101 according to an embodiment may include a buffer layer 101 a and a circuit array layer 101 b .

[0535] The buffer layer 101a can prevent materials such as hydrogen included in the first substrate 100 from diffusing into the circuit array layer 101b during the high-temperature process of manufacturing the TFT. In addition, the buffer layer 101a can prevent external moisture or humidity from penetrating into the light-emitting device layer 103. According to one embodiment, the buffer layer 101a may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof, but is not limited thereto. For example, the buffer layer 101a may include a first buffer layer BL1 provided on the first substrate 100 and including SiNx, and a second buffer layer BL2 provided on the first buffer layer BL1 and including SiOx.

[0536] The circuit array layer 101b may include a plurality of pixel driving lines GL, DL, PL, RL, CPL, PSL, RDL, and LCP disposed on the buffer layer 101a; and a pixel circuit PC including a driving TFT Tdr in each of a plurality of pixel areas PA disposed on the buffer layer 101a.

[0537] The driving TFT Tdr disposed in each pixel area PA may include an active layer ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer 101 c , first source / drain electrodes SD1 , second source / drain electrodes SD2 , and a passivation layer 101 d .

[0538] An active layer ACT may be disposed on the buffer layer 101a in each pixel area PA. The active layer ACT may include a channel region overlapping the gate electrode GE, and first and second source / drain regions parallel to each other between adjacent channel regions. The active layer ACT may become conductive during the conductive process and thus may serve as a bridge line for a jumper structure that directly connects wires in the display area AA or electrically connects wires disposed on different layers.

[0539] The gate insulating layer GI may be disposed in the channel region of the active layer ACT. The gate insulating layer GI may insulate the active layer ACT from the gate electrode GE. For example, the gate insulating layer GI may include SiOx, SiNx, SiON, or a multilayer thereof, but is not limited thereto.

[0540] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap with the channel region of the active layer ACT with the gate insulating layer GI therebetween.

[0541] The gate electrode GE may have a single-layer structure or a multi-layer structure including at least one of molybdenum (Mo), titanium (Ti), a Mo-Ti alloy (MoTi), and copper (Cu). The gate electrode GE according to one embodiment may include a first gate metal layer provided on the gate insulating layer GI and a second gate metal layer provided on the first gate metal layer. For example, the first gate metal layer may include Ti or MoTi. The second gate metal layer may include Cu. In this case, the gate electrode GE may have a two-layer structure of Cu / MoTi or Cu / Ti.

[0542] Each of the gate line GL, the power common line PSL, the line connection pattern LCP and the reference branch line RDL among the pixel driving lines GL, DL, PL, RL, CPL, PSL, RDL and LCP may have the same material as the gate electrode GE, but is not limited thereto.

[0543] An interlayer insulating layer 101c may be provided on the first substrate 100 to cover the gate electrode GE and the active layer ACT. The interlayer insulating layer 101c may electrically insulate (or isolate) the gate electrode GE from the source / drain electrodes SD1 and SD2. For example, the interlayer insulating layer 101c may include SiOx, SiNx, SiON, or a multilayer thereof, but is not limited thereto.

[0544] The first source / drain electrode SD1 may be disposed on the interlayer insulating layer 101 c overlapping the first source / drain region of the active layer ACT and may be electrically connected to the first source / drain region of the active layer ACT through a first source / drain contact hole disposed in the interlayer insulating layer 101 c. For example, the first source / drain electrode SD1 may be a source electrode of the driving TFT Tdr, and the first source / drain region of the active layer ACT may be a source region.

[0545] The second source / drain electrode SD2 may be disposed on the interlayer insulating layer 101 c overlapping the second source / drain region of the active layer ACT and may be electrically connected to the second source / drain region of the active layer ACT through a second source / drain contact hole disposed in the interlayer insulating layer 101 c. For example, the second source / drain electrode SD2 may be a drain electrode of the driving TFT Tdr, and the second source / drain region of the active layer ACT may be a drain region.

[0546] The source / drain electrodes SD1 and SD2 according to an embodiment may have a single-layer structure or a multi-layer structure including the same material as the gate electrode GE.

[0547] Each of the data line DL, the pixel driving power line PL, and the reference power line RL among the pixel driving lines GL, DL, PL, RL, CPL, PSL, RDL, and LCP may include the same material as the source / drain electrodes SD1 and SD2, but is not limited thereto. Each line of the gate control line group GCL may include the same material as the source / drain electrodes SD1 and SD2, but is not limited thereto.

[0548] The passivation layer 101d may be disposed on the first surface 100a of the first substrate 100 to cover the pixel circuit PC including the driving TFT Tdr. The passivation layer 101d according to an embodiment may include SiOx, SiNx, SiON, or a multilayer thereof, but is not limited thereto.

[0549] Each of the first and second switching TFTs Tsw1 and Tsw2 constituting the pixel circuit PC may be formed together with the driving TFT Tdr, and thus a detailed description thereof is omitted.

[0550] The circuit layer 101 according to an embodiment may further include a light shielding layer 101 e disposed under the active layer ACT of each of the TFTs Tdr, Tsw1 , and Tsw2 constituting the pixel circuit PC.

[0551] A light shielding layer (or light shielding pattern) 101e may be provided in an island shape between the first substrate 100 and the active layer ACT. The light shielding layer 101e may be covered by the buffer layer 101a. The light shielding layer 101e may block light incident on the active layer ACT through the first substrate 100, thereby preventing or minimizing the threshold voltage variation of each TFT caused by external light. Alternatively, the light shielding layer 101e may be electrically connected to the first source / drain electrode SD1 of the corresponding TFT and thus may serve as the lower gate electrode of the corresponding TFT. In this case, the characteristic variation of each TFT caused by light and the threshold voltage variation of each TFT caused by the bias voltage may be minimized or prevented.

[0552] In addition, the light shielding layer 101e may function as at least one of the power common line PSL, the line connection pattern LCP, and the reference branch line RDL among the pixel driving lines GL, DL, PL, RL, CPL, PSL, RDL, and LCP.

[0553] Figure 4 and Figure 6The gate driving circuit 150 shown in FIG can be formed together with the driving TFT Tdr of the pixel circuit PC. For example, a plurality of TFTs constituting each of the stage circuit units 1501 to 150m of the gate driving circuit 150 can be formed together with the driving TFT Tdr, thereby realizing a plurality of branch circuits 1511 to 151n arranged in each horizontal row on the first substrate 100. The first to fourth control nodes Q, QBo, QBe, and Qm of the branch network 153 constituting each of the stage circuit units 1501 to 150m can be formed together with the gate line GL. In addition, based on the position of the connection portion of each of the branch circuits 1511 to 151n to be connected, the network line NL of the branch network 153 constituting each of the stage circuit units 1501 to 150m can be formed together with at least one of the light shielding layer 101e, the gate line GL, and the data line DL, but is not limited thereto.

[0554] The planarization layer 102 may be disposed on the first surface 100a of the first substrate 100 and may provide a flat surface on the circuit layer 101. The planarization layer 102 may cover the circuit layer 101 including the driving TFT Tdr disposed in each of the plurality of pixel areas PA. The planarization layer 102 according to an embodiment may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

[0555] The planarization layer 102 according to an embodiment may be formed to cover the circuit layer 101 except for the edge portion of the first surface 100a of the first substrate 100. Therefore, the passivation layer 101d of the circuit layer 101 disposed at the edge portion of the first surface 100a of the first substrate 100 may be exposed without being covered by the planarization layer 102.

[0556] The light emitting device layer 103 may be disposed on the planarization layer 102 and may emit light toward the first surface 100 a of the first substrate 100 based on a top emission type.

[0557] The light emitting device layer 103 according to an embodiment may include a pixel electrode PE, a light emitting device ED, and a common electrode CE.

[0558] The pixel electrode PE may be referred to as an anode electrode, a reflective electrode, a lower electrode, or a first electrode of the light emitting device ED.

[0559] The pixel electrode PE may be disposed on the planarization layer 102, overlapping the emission area EA of each of the plurality of pixel areas PA. The pixel electrode PE may be patterned and disposed in an island shape in each pixel area PA and may be electrically connected to the first source / drain electrode SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. One side of the pixel electrode PE may extend from the emission area EA of the pixel area PA to the first source / drain electrode SD1 of the driving TFT Tdr disposed in the circuit area CA and may be electrically connected to the first source / drain electrode SD1 of the driving TFT Tdr through a contact hole CH disposed in the planarization layer 102.

[0560] The pixel electrode PE according to an embodiment may include a metal material having a low work function and excellent reflection efficiency.

[0561] For example, the pixel electrode PE may have a three-layer structure including first to third pixel electrode layers. The first pixel electrode layer may serve as an adhesive layer corresponding to the planarization layer 102 and may serve as an auxiliary electrode of the light-emitting device ED, and the first pixel electrode layer may include indium tin oxide (ITO) or indium zinc oxide (IZO). The second pixel electrode layer may serve as a reflector and may perform a function for reducing the resistance of the pixel electrode PE, and the second pixel electrode layer may include one of aluminum (Al), silver (Ag), Mo, Ti, and MoTi. The third pixel electrode layer may serve as an electrode of the light-emitting device ED and may include ITO or IZO. For example, the pixel electrode PE according to one embodiment may be formed into a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0562] As another example, the pixel electrode PE may have a four-layer structure including first to fourth pixel electrode layers. The first pixel electrode layer may serve as an adhesive layer corresponding to the planarization layer 102 and may serve as an auxiliary electrode of the light-emitting device ED, and the first pixel electrode layer may include one of ITO, Mo, and MoTi. The second pixel electrode layer may perform a function of reducing the resistance of the pixel electrode PE and may include Cu. The third pixel electrode layer may serve as a reflector and may include one of Al, Ag, Mo, Ti, and MoTi. The fourth pixel electrode layer may serve as an electrode of the light-emitting device ED and may include ITO or IZO. For example, the pixel electrode PE according to another embodiment may be formed as a four-layer structure of ITO / Cu / MoTi / ITO.

[0563] Alternatively, the line connection pattern LCP among the pixel driving lines GL, DL, PL, RL, CPL, PSL, RDL, and LCP may be formed of the same material as the pixel electrode PE, but is not limited thereto. In addition, the first pad of the first pad portion 110 provided on the first substrate 100 may be formed of the same material as the pixel electrode PE, but is not limited thereto.

[0564] The light-emitting device ED may be formed on the pixel electrode PE and may directly contact the pixel electrode PE. The light-emitting device ED may be a common layer formed in each of the plurality of sub-pixels SP without being differentiated per sub-pixel SP. The light-emitting device ED may respond to current flowing between the pixel electrode PE and the common electrode CE, thereby emitting white light. The light-emitting device ED according to one embodiment may include an organic light-emitting device or an inorganic light-emitting device, or may include a stacked or combined structure of an organic light-emitting device (or an inorganic light-emitting device) and a quantum dot light-emitting device.

[0565] An organic light-emitting device according to an embodiment may include two or more light-emitting material layers (or light-emitting portions) for emitting white light. For example, the organic light-emitting device may include a first light-emitting material layer and a second light-emitting material layer that emit white light based on a combination of a first light and a second light. Here, the first light-emitting material layer may include at least one of a blue light-emitting material, a green light-emitting material, a red light-emitting material, a yellow light-emitting material, and a yellow-green light-emitting material. The second light-emitting material layer may include at least one of a blue light-emitting material, a green light-emitting material, a red light-emitting material, a yellow light-emitting material, and a yellow-green light-emitting material for emitting a second light that is combined with the first light to generate white light.

[0566] The organic light emitting device according to one embodiment may further include one or more functional layers for improving luminous efficiency and / or lifespan. For example, the functional layer may be disposed above and / or below the light emitting material layer.

[0567] The inorganic light emitting device according to an embodiment may include a semiconductor light emitting diode, a micro light emitting diode, or a quantum dot light emitting diode. For example, when the light emitting device ED is an inorganic light emitting device, the light emitting device ED may have a size of 1 μm to 100 μm, but is not limited thereto.

[0568] The common electrode CE may be referred to as a cathode electrode, a transparent electrode, an upper electrode, or a second electrode of the light-emitting device ED. The common electrode CE may be formed on the light-emitting device ED and may directly contact the light-emitting device ED or may directly electrically contact the light-emitting device ED. The common electrode CE may include a transparent conductive material for transmitting light emitted from the light-emitting device ED.

[0569] The common electrode CE according to one embodiment may be formed into a single-layer structure or a multi-layer structure including at least one of graphene having a relatively high work function and a transparent conductive material. For example, the common electrode CE may include a metal oxide such as ITO or IZO, or may include a combination of an oxide and a metal, such as ZnO:Al or SnO2:Sb.

[0570] In addition, a capping layer that improves light emitting efficiency of light by adjusting a refractive index of light emitted from the light emitting device ED may be further disposed on the common electrode CE.

[0571] The bank 104 may be provided on the planarization layer 102 to cover the edge portion of the pixel electrode PE. The bank 104 may define the emission area EA (or opening portion) of each of the plurality of sub-pixels SP and may electrically isolate the pixel electrodes PE provided in adjacent sub-pixels SP. The bank 104 may be formed to cover the contact hole CH provided in each of the plurality of pixel areas PA. The bank 104 may be covered by the light-emitting device ED.

[0572] For example, the bank 104 may include a transparent material (eg, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin), in which case the bank 104 may be a transparent bank.

[0573] As another example, the embankment 104 may include a light-absorbing material or an opaque material containing a black pigment such as carbon black, and may include, for example, a polyimide resin, an acrylic resin, or benzocyclobutene (BCB), in which case the embankment 104 may be a black embankment that prevents or minimizes color mixing between adjacent sub-pixels SP.

[0574] The weir pattern 105 may be provided on the circuit layer 101 at the edge portion of the first substrate 100 to have a closed loop shape or a closed loop line shape. For example, the weir pattern 105 may be provided on the passivation layer 101d of the circuit layer 101. The weir pattern 105 may prevent diffusion or overflow of the encapsulation layer 106. The weir pattern 105 may be included in the outermost pixel Po (or outermost pixel area PAo) provided at the edge portion of the first substrate 100 among the plurality of pixels P (or the plurality of pixel areas PA). In this case, a portion of the weir pattern 105 may be provided (or implemented) between the first pad portion 110 located in the first substrate 100 and the emission area EA of each outermost pixel Po (or the outermost pixel area PAo).

[0575] The dam pattern 105 according to an embodiment may include the same material as the planarization layer 102. The dam pattern 105 may have the same height (or thickness) as the planarization layer 102, or may have a height greater than the planarization layer 102. For example, the height (or thickness) of the dam pattern 105 may be twice the height (or thickness) of the planarization layer 102.

[0576] According to another embodiment, the dam pattern 105 may include a lower dam pattern formed of the same material as the planarization layer 102, and an upper dam pattern stacked on the lower dam pattern and including the same material as the bank 104. The lower dam pattern may have the same height (or thickness) as the planarization layer 102, or may have a height greater than the planarization layer 102. For example, the height (or thickness) of the lower dam pattern may be twice the height (or thickness) of the planarization layer 102.

[0577] The light-emitting device ED including an organic light-emitting device may be implemented only in the inner region (or inner region) surrounded by the dam pattern 105. That is, the light-emitting device ED including the organic light-emitting device may be provided at a portion of the first surface 100a of the first substrate 100 except for a portion between the outer surface OS of the first substrate 100 and the dam pattern 105, and may not be provided between the outer surface OS of the first substrate 100 and the dam pattern 105, nor may it be provided on the top surface of the dam pattern 105. In addition, the common electrode CE of the light-emitting device layer 103 may be implemented to cover the light-emitting device ED and the dam pattern 105.

[0578] The first substrate 100 according to an embodiment may further include a first margin area MA1 , a second margin area MA2 , and a bank pattern area DPA.

[0579] The first margin area MA1 may be provided between the emission area EA of the outermost pixel Po and the dam pattern 105. Due to the shadow area of ​​the light-emitting device ED (or the tail portion of the light-emitting device) that inevitably appears during the process of forming the light-emitting device ED, the first margin area MA1 may have a first width between the end of the emission area EA (or the bank 104) of the outermost pixel Po and the dam pattern 105. Therefore, the dam pattern 105 may be implemented to be spaced apart from the end of the emission area EA by the first width of the first margin area MA1 relative to the first direction X.

[0580] The second margin area MA2 may be provided between the outer surface OS of the first substrate 100 and the dam pattern 105. Based on the reliability margin of the light emitting device ED against moisture, the second margin area MA2 may have a second width between the outer surface OS of the first substrate 100 and the dam pattern 105. Therefore, the dam pattern 105 may be implemented to be spaced apart from the outer surface OS of the first substrate 100 with respect to the first direction X by the second width of the second margin area MA2.

[0581] The second margin area MA2 according to an embodiment may include a pad margin area overlapping the first pad part 110 disposed at a first edge portion of the first surface 100 a of the first substrate 100 .

[0582] The bank pattern area DPA may be disposed between the first margin area MA1 and the second margin area MA2 , and may have a third width corresponding to a width of a lowermost bottom surface (or bottom surface) of the bank pattern 105 .

[0583] The width of each of the first margin area MA1, the second margin area MA2 and the weir pattern area DPA can be implemented so that relative to the first direction X, the second interval D2 between the central portion of the outermost pixel area and the outer surface OS of the first substrate 100 is half or less of the first interval (or pixel pitch) D1 between two adjacent pixel areas PA.

[0584] For example, when half of the first spacing (or pixel pitch) D1 between two adjacent pixel areas PA is 700 μm within a process error range, the total width of the first margin area MA1, the second margin area MA2, and the dam pattern area DPA can be implemented as approximately 670 μm based on the shadow mask margin based on the shadow mask area of ​​the light-emitting device ED and the packaging margin based on ensuring the reliability of the light-emitting device ED against moisture. In this case, within the process error range, the second spacing D2 between the outermost outer surface VL of the first substrate 100 and the center portion of the outermost pixel including the first pad portion 110 can be implemented as 700 μm. Here, the outermost outer surface VL of the first substrate 100 can be the outermost outer wall or outer side wall of the display device (or display panel).

[0585] The first margin area MA1 and the second margin area MA2 may have the same width or different widths. The weir pattern area DPA may have a relatively narrower width than each of the first margin area MA1 and the second margin area MA2. For example, with respect to the first direction X, the first margin area MA1 may be implemented to have a width of 300 μm or less, the second margin area MA2 may be implemented to have a width of 300 μm or less, and the weir pattern area DPA may be implemented to have a width of 70 μm. In addition, with respect to the first direction X, the pad margin area (or lateral wiring area) included in the second margin area MA2 may be implemented to have a width of 100 μm or less.

[0586] The encapsulation layer 106 may be provided on the first surface 100a of the first substrate 100 except for the outermost edge portion thereof to cover the light emitting device layer 103. For example, the encapsulation layer 106 may be implemented to surround the entire front and side surfaces of the light emitting device layer 103.

[0587] The encapsulation layer 106 according to an embodiment may include first to third encapsulation layers 106 a to 106 c .

[0588] The first encapsulation layer 106a may be implemented to prevent oxygen or moisture from penetrating into the light emitting device layer 103. The first encapsulation layer 106a may be provided on the common electrode CE to surround the light emitting device layer 103. Therefore, the entire front surface and side surface of the light emitting device layer 103 may be surrounded by the first encapsulation layer 106a. For example, an end portion of the first encapsulation layer 106a may be provided in a second margin area MA2 adjacent to the dam pattern 105. The first encapsulation layer 106a may directly contact the top surface of the passivation layer 101d at the periphery of the dam pattern 105 and may cover a boundary portion (or interface) between the common electrode CE and the passivation layer 101d, and the dam pattern 105 may directly contact the top surface of the passivation layer 101d, thereby preventing or minimizing lateral moisture penetration.

[0589] According to one embodiment, the first encapsulation layer 106a may include an inorganic material. For example, the first encapsulation layer 106a may be referred to as a first inorganic encapsulation layer. For example, the first encapsulation layer 106a may include a single layer structure including one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof.

[0590] The second encapsulation layer 106b may be implemented on the first encapsulation layer 106a to have a relatively thicker thickness than the first encapsulation layer 106a. The second encapsulation layer 106b may have a thickness sufficient to cover particles (or undesirable materials or undesirable structures) that may be present or absent on the first encapsulation layer 106a. Due to the relatively thick thickness, the second encapsulation layer 106b may diffuse to the edge portion of the first surface 100a of the first substrate 100, but the diffusion of the second encapsulation layer 106b may be blocked by the dam pattern 105. For example, the end of the second encapsulation layer 106b may directly contact the first encapsulation layer 106a on the dam pattern 105. Therefore, the second encapsulation layer 106b may be provided only on the first encapsulation layer 106a in the inner region (or inner region) surrounded by the dam pattern 105. The second encapsulation layer 106b may be referred to as a particle covering layer.

[0591] The second encapsulation layer 106 b according to an embodiment may include an organic material such as SiOCz acrylic or epoxy-based resin.

[0592] The third encapsulation layer 106c may be implemented to primarily prevent oxygen or moisture from penetrating into the light-emitting device layer 103. The third encapsulation layer 106c may be implemented to surround the second encapsulation layer 106b and the entire first encapsulation layer 106a that is not covered by the second encapsulation layer 106b. For example, an end portion of the third encapsulation layer 106c may be disposed between an end portion of the first encapsulation layer 106a and the outer surface OS of the first substrate 100 and may directly contact the passivation layer 101d. The third encapsulation layer 106c may directly contact the top surface of the passivation layer 101d and may cover a boundary portion (or interface) between the first encapsulation layer 106a and the passivation layer 101d, thereby additionally preventing or minimizing lateral moisture penetration.

[0593] According to one embodiment, the third encapsulation layer 106c may include an inorganic material. For example, the third encapsulation layer 106c may be referred to as a second inorganic encapsulation layer. For example, the third encapsulation layer 106c may include a single layer structure including one of SiOx, SiNx, SiONx, TiOx, and AlOx, or a stacked structure thereof.

[0594] The first substrate 100 according to one embodiment may further include a wavelength conversion layer 107 .

[0595] The wavelength conversion layer 107 may convert the wavelength of light incident from the emission area EA of each of the plurality of pixel areas PA. For example, the wavelength conversion layer 107 may convert white light incident from the emission area EA into color light corresponding to the corresponding pixel P.

[0596] The wavelength conversion layer 107 according to an embodiment may include a plurality of wavelength conversion patterns 107 a and a protective layer 107 b .

[0597] A plurality of wavelength conversion patterns 107a may be disposed on the encapsulation layer 106 in the emission area EA of each of the plurality of pixel areas PA. The plurality of wavelength conversion patterns 107a may be divided (or classified) into a red filter that converts white light into red light, a green filter that converts white light into green light, and a blue filter that converts white light into blue light. For example, the plurality of wavelength conversion patterns 107a may be divided (or classified) into a red filter (or first filter) disposed in the first sub-pixel SP1, a green filter (or second filter) disposed in the second sub-pixel SP2, and a blue filter (or third filter) disposed in the fourth sub-pixel SP4.

[0598] According to one embodiment, each of the plurality of wavelength conversion patterns 107a may be implemented to have a size wider than the emission area EA of each of the plurality of pixel areas PA. That is, to prevent color mixing between adjacent sub-pixels SP, each of the plurality of wavelength conversion patterns 107a may have the same size as the pixel electrode PE or may have a size wider than the pixel electrode PE, and thus may overlap with a portion of the bank 104 covering the edge portion of the pixel electrode PE. For example, each of the plurality of wavelength conversion patterns 107a may be arranged to overlap the entire emission area EA of each of the plurality of pixel areas PA and overlap with a portion of the circuit area CA adjacent to the emission area EA. In this case, to prevent external light incident through the area of ​​each of the plurality of pixel areas PA that does not overlap with the wavelength conversion pattern 107a from being reflected by the pixel driving lines or to minimize reflection of external light, the bank 104 may include a light-absorbing material or a black pigment.

[0599] According to another embodiment, each of the plurality of wavelength conversion patterns 107a may be implemented to have the same size as each of the plurality of pixel areas PA. That is, each of the plurality of wavelength conversion patterns 107a may be arranged to fully overlap each of the plurality of pixel areas PA to prevent or minimize reflection of external light caused by the pixel drive lines. For example, each of the plurality of wavelength conversion patterns 107a may be arranged to fully cover the emission area EA and circuit area CA of each of the plurality of pixel areas PA. In this case, the bank 104 may be a black bank or a transparent bank.

[0600] In addition, each of the plurality of wavelength conversion patterns 107a may include quantum dots that re-emit light based on white light or blue light incident from the light-emitting device layer 103 to additionally illuminate the color light corresponding to the corresponding pixel. Here, the quantum dots may be selected from CdS, CdSe, CdZnSeS, CdTe, ZnS, ZnSe, GaAs, GaP, GaAs-P, Ga-Sb, InAs, InP, InSb, AlAs, AlP, and AlSb. For example, the red filter provided in the first subpixel SP1 may include red quantum dots such as CdSe or InP that emit red light, the green filter provided in the second subpixel SP2 may include green quantum dots such as CdZnSeS that emit green light, and the blue filter provided in the fourth subpixel SP4 may include blue quantum dots such as ZnSe that emit blue light. As described above, when each of the plurality of wavelength conversion patterns 107a includes quantum dots, the color reproducibility of the light-emitting display device can be enhanced.

[0601] According to another embodiment, a plurality of wavelength conversion patterns 107a may be implemented to overlap with each other in the circuit area CA of each of the plurality of pixel areas PA. In this case, the circuit area CA of each of the plurality of pixel areas PA may be covered by at least two wavelength conversion patterns 107a that overlap with each other. For example, the circuit area CA of each of the plurality of pixel areas PA may be covered by a two-layer stack portion including a red filter and a green filter. As another example, the circuit area CA of each of the plurality of pixel areas PA may be covered by a three-layer stack portion including a red filter, a green filter, and a blue filter. The two-layer stack portion including two filters or the three-layer stack portion including three filters may perform the function of a black matrix for preventing color mixing between adjacent sub-pixels SP or preventing or minimizing reflection of external light.

[0602] The protective layer 107b may be implemented to cover the wavelength conversion pattern 107a and provide a flat surface on the wavelength conversion pattern 107a. The protective layer 107b may be provided to cover the wavelength conversion pattern 107a and the encapsulation layer 106 where the wavelength conversion pattern 107a is not provided. According to one embodiment, the protective layer 107b may include an organic material. For example, the protective layer 107b may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but is not limited thereto. Optionally, the protective layer 107b may further include a getter material for absorbing moisture and / or oxygen.

[0603] Alternatively, the wavelength conversion layer 107 may be a sheet-like wavelength conversion sheet and may be disposed on the encapsulation layer 106. In this case, the wavelength conversion sheet (or quantum dot sheet) may include a wavelength conversion pattern 107a disposed between a pair of films. For example, when the wavelength conversion layer 107 includes quantum dots that re-emit the color light set in the sub-pixel, the light-emitting device layer 103 of the sub-pixel may be configured to emit white light or blue light.

[0604] The first substrate 100 according to an embodiment may further include a functional film 108 .

[0605] The functional film 108 may be disposed on the wavelength conversion layer 107. For example, the functional film 108 may be bonded to the wavelength conversion layer 107 by a transparent adhesive member. The transparent adhesive member may include a pressure sensitive adhesive (PSA), an optically clear adhesive (OCA), or an optically clear resin (OCR).

[0606] The functional film 108 according to an embodiment may include an anti-reflection layer (or anti-reflection film) for preventing reflection of external light to improve outdoor visibility and contrast of an image displayed by the display device 10. For example, the anti-reflection layer may include a circular polarization layer (or circular polarization film) for preventing external light reflected by the TFTs and / or pixel driving lines provided on the first substrate 100 from propagating to the outside.

[0607] The functional film 108 according to an embodiment may further include a barrier layer (or barrier film) for mainly preventing the permeation of moisture or oxygen. The barrier layer may include a material with a low moisture permeability (eg, a polymer material).

[0608] The functional film 108 according to one embodiment may further include a light path control layer (or light path control film) for controlling the path of light output from each pixel P to the outside. The light path control layer may include a stacked structure in which high refractive index layers and low refractive index layers are alternately stacked and may change the path of light incident from each pixel P to minimize color shift based on viewing angle.

[0609] The first substrate 100 according to an embodiment may further include a side sealing member 109 .

[0610] The side sealing member (or edge sealing member) 109 may be formed between the first substrate 100 and the functional film 108 and may cover all side (or lateral) surfaces of each of the circuit layer 101, the planarization layer 102, and the wavelength conversion layer 107. That is, the side sealing member 109 may cover the entire side surface of each of the circuit layer 101, the planarization layer 102, and the wavelength conversion layer 107 between the functional film 108 and the first substrate 100, which is exposed to the outside of the display device 10. In addition, the side sealing member 109 may cover the first chamfer 100c formed (or provided) at the corner portion between the first surface 100a of the first substrate 100 and the outer surface OS by a chamfering process. For example, each of the outermost outer surface of the first substrate 100, the outer surface of the side sealing member 109, and the outer surface of the functional film 108 may be provided (or aligned) on the same vertical line VL.

[0611] The side sealing member 109 according to one embodiment may include a silicon-based or ultraviolet (UV) curable sealant (or resin), but considering the tack process time, the side sealing member 109 may include a UV curable sealant. In addition, the side sealing member 109 may have a color (for example, blue, red, cyan or black), but is not limited thereto, and the side sealing member 109 may include a colored resin or a light-shielding resin for preventing lateral light leakage. The side sealing member 109 can prevent lateral light leakage by using the light emitted from the light-emitting device ED of each sub-pixel SP, which propagates from the inside of the wavelength conversion layer 107 to its outer surface. In particular, the side sealing member 109 overlapping the first pad portion of the first substrate 100 can prevent or minimize the reflection of external light caused by the pad in the first pad portion.

[0612] Optionally, the side sealing member 109 may further include a getter material for absorbing moisture and / or oxygen.

[0613] The first substrate 100 according to an embodiment may further include a front coating layer.

[0614] The front coating layer may be provided between the wavelength conversion layer 107 and the functional film 108 to cover the top surface of the wavelength conversion layer 107 and the entire side surface of each of the circuit layer 101, the planarization layer 102, and the wavelength conversion layer 107. That is, the front coating layer may be implemented to cover the entire side surface of each of the circuit layer 101, the planarization layer 102, and the wavelength conversion layer 107 between the functional film 108 and the first substrate 100, which is exposed to the outside of the display device 10, and may be implemented to cover a portion of each of the top and side surfaces of the wiring portion 400 connected to the first pad portion of the first substrate 100. The front coating layer according to one embodiment may be implemented by an atomic layer deposition process. For example, the front coating layer may be implemented to have a thickness of several μm.

[0615] In the present embodiment, the side sealing member 109 may be implemented as a front coating layer covering an edge portion of the first surface 100 a of the first substrate 100 , or the side sealing member 109 may be omitted.

[0616] The second substrate 200 according to an embodiment may include a metal pattern layer connected to the wiring portion 400 and an insulating layer insulating the metal pattern layer.

[0617] The metal pattern layer (or conductive pattern layer) may include multiple metal layers. According to one embodiment, the metal pattern layer may include a first metal layer 201, a second metal layer 203, and a third metal layer 205. The insulating layer may include multiple insulating layers. For example, the insulating layer may include a first insulating layer 202, a second insulating layer 204, and a third insulating layer 206. The insulating layer may be referred to as a rear insulating layer or a patterned insulating layer.

[0618] The first metal layer 201 may be implemented on the rear surface 200b of the second substrate 200. According to an embodiment, the first metal layer 201 may include a first metal pattern. For example, the first metal layer 201 may be referred to as a first connection layer or a wiring layer.

[0619] The first metal pattern according to one embodiment may have a two-layer structure of Cu and MoTi (Cu / MoTi). The first metal pattern may be used as Figure 9 For example, the first metal pattern may be used as each of the plurality of data lines 251, the plurality of pixel driving power lines 255, the plurality of gate control signal transmission lines, and the first common line 257a of the pixel common power line 257, but is not limited thereto.

[0620] The first insulating layer 202 may be formed on the rear surface 200b of the second substrate 200 to cover the first metal layer 201. The first insulating layer 202 according to one embodiment may include an inorganic material. For example, the first insulating layer 202 may include one of SiOx, SiNx, and SiONx, but is not limited thereto.

[0621] The second metal layer 203 may be implemented on the first insulating layer 202. According to an embodiment, the second metal layer 203 may include a second metal pattern. For example, the second metal layer 203 may be referred to as a second connection layer, a jumper layer, or a bridge layer.

[0622] The second metal pattern according to one embodiment may have a two-layer structure of Cu and MoTi (Cu / MoTi). The second metal pattern may be used as Figure 10 The plurality of gate lines 253 in the plurality of lines of the wiring portion 250 are shown in FIG. , but are not limited thereto. For example, the second metal layer 203 can be used as a jumper (or bridge) for electrically connecting lines in the wiring portion 250 formed of different metal materials on different layers.

[0623] Optionally, the wiring (e.g., multiple first wirings) set on the second metal layer 203 can be modified to be set on the first metal layer 201, and the wiring (e.g., multiple second wirings) set on the first metal layer 201 can be modified to be set on the second metal layer 203.

[0624] The second insulating layer 204 may be formed on the rear surface 200b of the second substrate 200 to cover the second metal layer 203. According to an embodiment, the second insulating layer 204 may include an inorganic material. For example, the second insulating layer 204 may include one of SiOx, SiNx, and SiONx.

[0625] The third metal layer 205 may be implemented on the second insulating layer 204. The third metal layer 205 according to an embodiment may include a third metal pattern. For example, the third metal layer 205 may be referred to as a third connection layer or a pad electrode layer.

[0626] The third metal pattern according to one embodiment may have a stacked structure of at least two materials among ITO (or IZO), Mo, Ti, and MoTi. For example, the third metal pattern may have a three-layer structure of ITO / Mo / ITO, ITO / MoTi / ITO, IZO / Mo / ITO, or IZO / MoTi / ITO. The third metal pattern may be used as Figure 9 , the second pad of the second pad portion 210 , the third pad of the third pad portion 230 , and each of the second common line 257 b and the plurality of third common lines 257 c of the pixel common power supply line 257 .

[0627] A third insulating layer 206 may be formed on the rear surface 200b of the second substrate 200 to cover the third metal layer 205. According to one embodiment, the third insulating layer 206 may include an organic material. For example, the third insulating layer 206 may include an insulating material such as optical acrylic. The third insulating layer 206 may cover the third metal layer 205 to prevent the third metal layer 205 from being exposed to the outside. The third insulating layer 206 may also be referred to as an organic insulating layer, a protective layer, a rear protective layer, an organic protective layer, a rear coating layer, or a rear cover layer.

[0628] The third insulating layer 206 may further include a pad exposure hole exposing a portion of each of the second pad including the second pad part 210 and the third pad of the third pad part 230 in the third metal layer 205 .

[0629] The bonding member 300 may be disposed between the first substrate 100 and the second substrate 200. Thus, the first substrate 100 and the second substrate 200 may be bonded relative to each other via the bonding member 300. The bonding member 300 according to one embodiment may be a transparent adhesive member including OCA or OCR or a double-sided tape. According to another embodiment, the bonding member 300 may include glass fiber.

[0630] The bonding member 300 according to one embodiment may be provided in the entire space between the first substrate 100 and the second substrate 200. For example, the entire second surface 100b of the first substrate 100 may be bonded to the entire one surface of the bonding member 300, and the entire front surface 200a of the second substrate 200 may be bonded to the entire other surface of the bonding member 300.

[0631] According to another embodiment, the bonding member 300 may be provided between the first substrate 100 and the second substrate 200 in a patterned structure. For example, the bonding member 300 may have a line pattern structure or a mesh pattern structure. The mesh pattern structure may further include a bent portion for discharging air bubbles generated between the first substrate 100 and the second substrate 200 to the outside during the process of bonding the first substrate 100 to the second substrate 200.

[0632] Alternatively, the bonding member 300 may further include a heat...

Claims

1. A display device, comprising: a first substrate including a plurality of pixels disposed in a display portion; a second substrate bonded to the first substrate; and a wiring portion provided on an outer surface of the first substrate and an outer surface of the second substrate, The first substrate comprises: a first pad portion connected to the wiring portion and the plurality of pixels; and a gate driving circuit provided in the display portion and including a shift register, the shift register including a plurality of stage circuit units for respectively providing scanning signals to the plurality of pixels, The entire gate drive circuit is arranged inside the display part. Each of the plurality of stage circuit units includes a plurality of branch circuits, and the plurality of branch circuits are arranged in a horizontal row and separated from each other. wherein each of the plurality of branch circuits is disposed between two adjacent pixels among the plurality of pixels, wherein the first pad portion includes a plurality of first gate pads, the plurality of first gate pads being disposed in outermost pixels located at one edge portion of the first substrate among the plurality of pixels and connected to the plurality of branch circuits, wherein at least one of the plurality of first gate pads is disposed in a pixel region corresponding to a pixel, and at least one of the gate pads in the pixel region is connected to a corresponding branch circuit of the plurality of branch circuits, The first pad portion further includes a plurality of first data pads, the plurality of first data pads are disposed adjacent to the plurality of first gate pads and connected to the plurality of pixels, The plurality of first gate pads and the plurality of first data pads are disposed only at a first horizontal row including the outermost pixels.

2. The display device according to claim 1, wherein: The first substrate further includes a gate control line group, the gate control line group is individually disposed between the plurality of pixels and connected to the shift register, The gate control line group is electrically connected to the plurality of first gate pads.

3. The display device according to claim 2, wherein the first substrate further comprises a plurality of gate lines, the plurality of gate lines being arranged in the display portion to provide the scanning signals to the plurality of pixels, wherein the shift register comprises a plurality of stage circuit units, and the plurality of stage circuit units are arranged in the display part to respectively provide the scanning signals to the plurality of gate lines, Each of the plurality of stage circuit units comprises: the plurality of branch circuits being disposed between the plurality of pixels in the one horizontal row and spaced apart from each other along the length direction of the plurality of gate lines and connected to the gate control line group; and A branch network is electrically connected to the plurality of branch circuits. 4 . The display device according to claim 3 , wherein the gate control line group comprises a start signal line, a plurality of shift clock lines, at least one gate driving power line, and at least one gate common power line. 5 . The display device according to claim 3 , wherein each of the plurality of branch circuits includes at least one thin film transistor for generating the scan signal.

6. The display device according to claim 3, wherein the branch network comprises: a plurality of control nodes arranged in parallel with the plurality of gate lines; as well as A mesh line is selectively connected to the lines of the gate control line group and selectively connected to the plurality of control nodes. 7 . The display device according to claim 6 , wherein each of the plurality of branch circuits comprises at least one thin film transistor connected to at least one of the plurality of control nodes and the mesh line.

8. The display device according to claim 3, wherein the branch network comprises: a first control node, a second control node, and a third control node disposed in parallel with corresponding gate lines of the plurality of gate lines; as well as a mesh line selectively connected to the lines of the gate control line group and selectively connected to the first control node, the second control node and the third control node, Each of the plurality of stage circuit units comprises: a node control circuit for controlling a voltage of each of the first control node, the second control node, and the third control node; a first inverter circuit, the first inverter circuit being used to control a voltage of the second control node based on a voltage of the first control node provided through the network line; a second inverter circuit, the second inverter circuit being configured to control a voltage of the third control node based on a voltage of the first control node provided through the network line; and An output buffer circuit is configured to output the scan signal based on a voltage of each of the first control node, the second control node, and the third control node.

9. The display device according to claim 8, wherein a plurality of thin film transistors in the node control circuit, the first inverter circuit, the second inverter circuit, and the output buffer circuit are dispersedly arranged in one horizontal line to constitute each of the plurality of branch circuits.

10. The display device according to claim 6, wherein: Each of the plurality of stage circuit units includes a first stage circuit unit and a second stage circuit unit, The plurality of control nodes are shared by the first-stage circuit unit and the second-stage circuit unit. 11 . The display device according to claim 10 , wherein the second-stage circuit unit and the first-stage circuit unit are electrically connected to the same gate line to provide the same scan signal to the same gate line.

12. A display device comprising: A first substrate including a display area; a plurality of pixel regions arranged at a first interval in the display region; a gate driving circuit including a shift register, the gate driving circuit being configured to provide a scanning signal to a plurality of pixels, the shift register being configured to include a plurality of stage circuit units arranged in each horizontal row of the display area, each of the plurality of stage circuit units including a plurality of branch circuits arranged spaced apart from each other in one horizontal row; a gate control line group, the gate control line group being disposed between one or more pixel regions and connected to the plurality of stage circuit units; a plurality of first gate pads, the plurality of first gate pads being disposed in the display area and electrically connected to the gate control line group; as well as a plurality of first data pads disposed adjacent to the plurality of first gate pads and configured to provide data voltages to the plurality of pixels, wherein each of the plurality of branch circuits is disposed between two adjacent pixels among the plurality of pixels, wherein the outermost pixel region among the plurality of pixel regions comprises the plurality of first gate pads and the plurality of first data pads, The entire gate drive circuit is arranged inside the display area. wherein at least one of the plurality of first gate pads is disposed in a pixel region corresponding to a pixel, and at least one of the gate pads in the pixel region is connected to a corresponding branch circuit of the plurality of branch circuits, The plurality of first gate pads and the plurality of first data pads are disposed only at a first horizontal row including the outermost pixel region.

13. The display device according to claim 12, wherein each of the plurality of stage circuit units further comprises a branch network for electrically connecting the plurality of branch circuits, Each of the plurality of branch circuits is connected to the gate control line group through the branch network.

14. The display device according to claim 13, wherein the branch network comprises: a first control node, a second control node, and a third control node disposed in a horizontal row; as well as a mesh line selectively connected to the lines of the gate control line group and selectively connected to the first control node, the second control node and the third control node, Each of the plurality of stage circuit units comprises: a node control circuit for controlling a voltage of each of the first control node, the second control node, and the third control node; a first inverter circuit, the first inverter circuit being used to control a voltage of the second control node based on a voltage of the first control node provided through the network line; a second inverter circuit, the second inverter circuit being configured to control a voltage of the third control node based on a voltage of the first control node provided through the network line; and An output buffer circuit is configured to output the scan signal based on a voltage of each of the first control node, the second control node, and the third control node.

15. The display device according to claim 14, wherein a plurality of thin film transistors in the node control circuit, the first inverter circuit, the second inverter circuit, and the output buffer circuit are dispersedly arranged in one horizontal line to constitute each of the plurality of branch circuits.

16. The display device according to claim 12, further comprising: a second substrate bonded to the rear surface of the first substrate by a bonding member; as well as A wiring portion is provided on an outer surface of the first substrate and an outer surface of the second substrate.

17. The display device according to any one of claims 1 to 11 and 16, wherein the second substrate comprises: a second pad portion including a plurality of second gate pads connected to the plurality of first gate pads through the wiring portions, respectively; a third pad portion including a plurality of third gate pads respectively connected to the plurality of second gate pads; and A plurality of gate connection lines connect the plurality of second gate pads to the plurality of third gate pads respectively.

18. The display device according to claim 17, wherein the second substrate further comprises a gate control signal transmission portion, which is configured to bypass the third pad portion and selectively connect each of the plurality of third gate pads to a corresponding gate line among the plurality of gate lines.

19. The display device according to claim 18, wherein the gate control signal transmission part comprises a plurality of gate control signal transmission lines, the plurality of gate control signal transmission lines electrically connecting each of the plurality of third gate pads to a corresponding gate connection line among the plurality of gate connection lines, Each of the plurality of gate connection lines passes through a region between the plurality of third gate pads and is selectively connected to the plurality of gate control signal transmission lines.

20. The display device according to claim 18, wherein: The gate control signal transmission part includes a plurality of gate control signal transmission lines, and the plurality of gate control signal transmission lines electrically connect each of the plurality of third gate pads to a corresponding gate connection line among the plurality of gate connection lines, The plurality of gate control signal transmission lines and the plurality of gate connection lines are arranged on different layers on the rear surface of the second substrate, A corresponding side of each of the plurality of gate connection lines is electrically connected to a corresponding gate control signal transmission line through a connection contact hole.

21. A multi-screen display device, comprising: a plurality of display modules arranged along at least one of a first direction and a second direction crossing the first direction, Each of the plurality of display modules comprises the display device according to any one of claims 1 to 16.

22. The multi-screen display device according to claim 21, wherein: In two adjacent display modules among the plurality of display modules respectively including side surfaces contacting each other, a second interval between adjacent outermost pixels in different display modules is equal to or smaller than a first interval between two adjacent pixels in the same display module.

Images