A Schottky barrier diode and a method for forming the same

Abstract

Embodiments of the present invention relate to a Schottky barrier diode and a method of forming the same. A method of manufacturing a Schottky barrier diode includes forming a first well region over a substrate; forming a first dielectric layer over the first well region; patterning the first dielectric layer by reducing a first thickness of the first dielectric layer; removing the first dielectric layer to expose a surface of the first well region; and forming a conductive layer over the first well region to obtain a Schottky barrier interface. A Schottky barrier diode manufactured based on the above method is also provided.

Description

Technical Field

[0001] Embodiments of the present invention relate to a Schottky barrier diode with reduced leakage current and a method for forming the same. Background Art

[0002] Schottky barrier diodes (or simply Schottky diodes) are commonly used in modern semiconductor devices. Schottky diodes have many advantages, such as low forward voltage drop and high switching speed, and therefore play an important role in radio frequency circuits, power devices and other semiconductor devices. In addition, Schottky diodes are often combined with other semiconductor circuits to produce integrated semiconductor devices. The performance of integrated semiconductor devices often depends largely on the successful process integration of Schottky diodes with other circuits to reduce processing costs while maintaining device performance. The electrical properties of Schottky diodes (for example, switching speed and leakage current) can be affected to some extent by the integration process.

[0003] Although extensive research has been conducted to improve the process integration technology for manufacturing Schottky diodes, these technologies still fall short in many aspects. Therefore, there is a need to further improve the structure and manufacturing method of existing Schottky diodes. Summary of the Invention

[0004] According to an embodiment of the present invention, a method for manufacturing a Schottky barrier diode includes: forming a first well region above a substrate; forming a first dielectric layer above the first well region; patterning the first dielectric layer by reducing a first thickness of the first dielectric layer; removing the first dielectric layer to expose a surface of the first well region; and forming a conductive layer above the first well region to obtain a Schottky barrier interface.

[0005] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a first well region and a second well region above a substrate, the second well region being configured as part of a transistor device; forming a dielectric layer above the first well region and the second well region; patterning the dielectric layer by reducing the thickness of a first portion of the dielectric layer above the first well region while leaving a second portion of the dielectric layer above the second well region unchanged; etching the dielectric layer to expose a first surface of the first well region and a second surface of the second well region; and forming a silicide layer on the exposed surface of the first well region to obtain a Schottky barrier interface.

[0006] According to another embodiment of the present invention, a Schottky barrier diode includes: a well region located in a substrate; a silicide layer located above the well region, the silicide layer and the well region forming a Schottky barrier interface; an isolation region disposed in the substrate and defining the well region; and a dielectric layer located above the substrate and the silicide layer; wherein the dielectric layer includes a stepped shape at the periphery of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figures 1 to 17 is a cross-sectional view of an intermediate stage in a method of fabricating a Schottky barrier diode according to some embodiments.

[0009] Figure 18 Shown is a graph illustrating the performance of a Schottky barrier diode device according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed on or formed on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not inherently dictate the relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0012] Although the numerical ranges and parameters set forth herein describe the broad scope of the present disclosure, the numerical values ​​set forth in the specific examples should be reported as precisely as possible. However, any numerical value inherently necessarily contains some errors, typically due to variations in individual test measurements. Furthermore, as used herein, the terms "about," "substantial," and "substantially" generally mean within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, one skilled in the art will recognize that the terms "about," "substantial," and "substantially" mean within an acceptable standard error of the mean. Except in the operating / working examples or unless expressly provided otherwise, all numerical ranges, amounts, values, and percentages disclosed herein (e.g., amounts of materials, durations, temperatures, operating conditions, quantitative ratios, etc.) should be understood as being modified in all instances by the terms "about," "substantial," and "substantially." Therefore, unless otherwise indicated, the numerical parameters set forth in this disclosure and the appended claims are approximate values ​​that may vary as necessary. At the very least, each numerical parameter should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to the other or between two endpoints. All ranges disclosed herein are inclusive unless otherwise specified.

[0013] Leakage current is one of the factors used to measure the performance of Schottky barrier diodes (SBDs), where the current level under reverse bias should be kept as low as possible to reduce power loss. However, due to poor process control, the measured leakage current of the manufactured SBD may be greater than the specification. One possible reason why the leakage current cannot meet the specification is that the Schottky barrier formed at the interface between the metal region and the semiconductor region in the anode of the SBD is not high enough. The Schottky barrier height may be lower than expected because there are defects in the contact between the metal region and the semiconductor region. For example, some process materials with a work function lower than that of the metal region may contaminate the interface between the metal region and the semiconductor region. In view of the above, it is crucial to ensure that unnecessary materials of the SBD are completely removed during the manufacturing process.

[0014] The present disclosure provides an SBD with low leakage current and a method for manufacturing a low-leakage SBD. The proposed solution discusses a common process that can improve SBDs and other circuits, such as forming a metal oxide semiconductor (MOS) transistor on a substrate. For example, one or more oxide layers formed as gate oxide layers of different types of MOS transistors can also be used to form an SBD. The oxide layer may not function in the final SBD, but is temporarily left in the SBD structure to assist in removing one or more unnecessary layers left after the MOS transistor is formed. Therefore, the MOS transistor and the SBD share an oxide layer, eliminating the need for a separate oxide layer step for the SBD. After removing the unnecessary layers in the SBD, the oxide layer should then be at least partially removed from the SBD structure. However, as technology evolves to earlier generations, the specifications of the oxide layer change, and therefore the oxide layer in the SBD structure may not be completely removed. The residual oxide layer remaining in the SBD structure can degrade the SBD performance.

[0015] The proposed oxide layer removal scheme offers the benefit of improved removal capabilities without the use of additional masks. In some cases, existing masks used to clean other features can be used to simultaneously remove all or part of the oxide layer in the SBD. This maintains the performance of the SBD, ensuring that forward current and leakage current meet specified levels. At the same time, due to the efficiency of process integration, manufacturing costs and cycle time are not increased. An embodiment of a method for manufacturing an SBD is described in detail below.

[0016] Figures 1 to 8 、 Figure 9A and Figures 10 to 14 is a cross-sectional view of an intermediate stage in a method of fabricating a Schottky diode 10 according to some embodiments. Figure 9B and Figure 9C is a cross-sectional view of an intermediate stage of an alternative method of manufacturing a Schottky diode 10 according to some embodiments, the alternative method comprising Figure 9B or Figure 9C rather than Figure 9A The operation is illustrated. Figures 15 to 17 is a cross-sectional view of an intermediate stage of another method of manufacturing a Schottky diode 10 according to some embodiments. Figures 1 to 8 、 Figure 9B or Figure 9C 、 Figure 10 and Figure 11 After the illustrated operation. It should be understood that Figures 1 to 17Additional operations are provided before, during, and after the processes shown in the figures, and some of the operations described below may be replaced or removed to form additional embodiments of the method. The order of the operations and processes may be interchanged. Furthermore, the configuration, structure, materials, operations, or processes employed in one embodiment may be the same or similar to those employed in other embodiments and may not be described in detail.

[0017] refer to Figure 1 , forming or providing a substrate 100. The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Typically, an SOI substrate includes a semiconductor material layer formed on an insulator layer. For example, the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate layer, typically formed of silicon or glass. Other substrates, such as multilayer substrates or gradient substrates, may also be used. The substrate 100 may be doped (e.g., with a p-type dopant or an n-type dopant) or undoped. In some embodiments, the semiconductor material of the substrate 100 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0018] The substrate 100 can be divided into different device zones in which various types of semiconductor devices are formed. For example, the first device zone Z1, the second device zone Z2, the third device zone Z3 and the fourth device zone Z4 can be referred to as an SBD zone, a high voltage (HV) zone, an input / output (I / O) zone and a core zone, respectively. In the first device zone Z1, one or more SBD devices are manufactured. In addition, MOS transistors operating at a high voltage (e.g., 12 volts or higher), a medium voltage (e.g., between about 5 volts and 6 volts) and a low voltage (e.g., about 3 volts or lower) are formed in the device zones Z2, Z3 and Z4, respectively. The device zones Z1 to Z4 can be processed using a common process or a separate process described in subsequent paragraphs. In the substrate 100, the device zones Z1 to Z4 may or may not be adjacent to each other. Provided for illustrative purposes only Figure 1 , and other numbers or configurations of device zones are also within the scope of this disclosure.

[0019] The substrate 100 includes a first well region 106 of a first conductivity type in the first device zone Z1. In some embodiments, the first conductivity type is n-type and the first well region 106 is an n-well (NW). In some embodiments, the dopant concentration of the first well region 106 is between about 10E11 ions / cm 3 With about 10E14 ions / cm 3In some embodiments, first well region 106 is formed by implantation. Implanted impurities of the first conductivity type may be selected from phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants. In some embodiments, first well region 106 is formed by epitaxially growing a semiconductor layer on substrate 100 and then implanting n-type impurities.

[0020] In some embodiments, first device zone Z1 further includes a second well region 104 (referred to as a deep well region) of the first conductivity type located below first well region 106. In some embodiments, second well region 104 is a deep n-well (DNW). In some embodiments, second well region 104 has a width substantially equal to or less than that of first well region 106, as viewed in cross-section. In other embodiments, second well region 104 is omitted. In some embodiments, second well region 104 is formed by implanting n-type impurities into substrate 100. The implanted impurities of the first conductivity type can be selected from phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants. In some embodiments, second well region 104 is formed by epitaxially growing a semiconductor layer on substrate 100 and then performing n-type impurity implantation.

[0021] In some embodiments, in substrate 100, first device zone Z1 further includes a third well region 108 of a second conductivity type opposite to the first conductivity type. Third well region 108 is formed adjacent to or surrounding first well region 106. In some embodiments, the second conductivity type is p-type and third well region 108 is a p-well (PW). In some embodiments, the dopant concentration of third well region 108 is between approximately 10E11 ions / cm 3 With about 10E14 ions / cm 3 In some embodiments, the third well region 108 is formed by implanting p-type impurities into the substrate 100. The p-type impurities can be selected from boron, boron difluoride, and other suitable p-type dopants. In some embodiments, the third well region 108 can be formed by epitaxially growing a semiconductor layer on the substrate 100 and then implanting p-type impurities.

[0022] The second device zone Z2 may include a first well region 206. In some embodiments, the first well region 206 is an n-well of a p-channel MOS (PMOS) transistor or a p-well of an n-channel MOS (NMOS) transistor. In some embodiments, the dopant concentration of the first well region 206 is between about 10E11 ions / cm 3 With about 10E14 ions / cm 3In some embodiments, the first well region 206 is formed by an implantation operation. The implanted impurities of the first conductivity type may be selected from phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants, while the implanted impurities of the second conductivity type may be selected from boron, boron difluoride, and other suitable p-type dopants. Similarly, the third device zone Z3 may include a first well region 306, and the fourth device zone Z4 may include a first well region 406. In some embodiments, the first well region 306 or 406 is an n-well for a PMOS transistor, or a p-well for an NMOS transistor. The materials, configurations, and formation methods of the first well regions 206, 306, and 406 in each of the device zones Z2 to Z4 may be similar to those of the first well region 106 in the first device zone Z1, and are not further described herein.

[0023] In some embodiments, each of device zones Z2 through Z4 includes a second well region 204, 304, and 404 located below the respective first well region 206, 306, and 406. The second well regions 204, 304, and 404 are referred to as deep well regions. In some embodiments, the second well region 204, 304, or 404 comprises the same conductivity type as the corresponding first well region 206, 306, or 406 and can be a deep n-well or a deep p-well. In some embodiments, the second well region 204, 304, and 404 can be omitted from the respective second device zones. In some embodiments, the materials, configurations, and formation methods of the second well regions 204, 304, and 404 in the respective device zones Z2 through Z4 can be similar to those of the second well region 104 in the first device zone Z1 and are not further described herein.

[0024] In some embodiments, device zone Z2 further includes a third well region 205 within first well region 206. First well region 206 and third well region 205 have opposite conductivity types. In some embodiments, first well region 206 is a high-voltage p-well and third well region 205 is a high-voltage n-well. Third well region 205 extends from upper surface 100S of substrate 100 to second well region 204 of device zone Z2. In some embodiments, third well region 205 extends through first well region 206. In some embodiments, third well region 205 divides first well region 206 into two parts. In some embodiments, third well region 205 is formed by implanting n-type or p-type impurities into substrate 100. The first conductivity type of implanted impurities can be selected from phosphorus, arsenic, antimony, bismuth, selenium, tellurium, and other suitable n-type dopants, while the second conductivity type of implanted impurities can be selected from boron, boron difluoride, and other suitable p-type dopants.

[0025] In some embodiments, substrate 100 further includes isolation regions 102 that define device zones Z1 through Z4. Isolation regions 102 may laterally surround device zones Z1 through Z4. In some embodiments, isolation regions 102 are referred to as trench-front isolation (STI). Isolation regions 102 may be formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or a combination thereof. In some embodiments, isolation regions 102 are formed by etching trenches in the top surface of substrate 100 and filling these trenches with dielectric material by thermal oxidation, thermal nitridation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof.

[0026] An isolation region 102 may be formed in the first device zone Z1 to delineate the well regions of the respective device zones. For example, the isolation region 102 is formed to define a first well region 106 and a third well region 108 of the first device zone Z1. The isolation region 102 formed in the first device zone Z1 (which is an SBD zone in the depicted embodiment) is further configured to define an anode region 101a, a cathode region 101b adjacent to the anode region 101a, and a bulk region 101c, the bulk region 101c being located on both sides of the cathode region 101b, opposite to the anode region 101a. The anode region 101a, the cathode region 101b, and the bulk region 101c are separated from each other by the isolation region 102 in their upper portions close to the upper surface 100S of the substrate 100, and are coupled to each other through their lower portions. In Figure 1 In the embodiment depicted in FIG, the anode region 101a is formed between the two cathode regions 101b in a cross-sectional view. However, in some embodiments, the cathode region 101b has a ring shape surrounding the anode region 101a in a plan view. In alternative embodiments, the cathode region 101b is composed of two strips, which are located on opposite sides of the anode region 101a in a plan view. In some embodiments, the bulk region 101c is formed in a ring shape surrounding the anode region 101a and the cathode region 101b in a plan view, or the bulk region 101c is composed of two separate strips on the outside relative to the cathode region 101b.

[0027] In some embodiments, isolation region 103 is formed in second device zone Z2 and exposed from surface 100S. In some embodiments, isolation region 103 is formed in first well region 206 between isolation region 102 and second well region 205. Isolation region 103 may have a depth equal to that of isolation region 102. In some embodiments, isolation region 103 has a width less than that of isolation region 102. In some embodiments, isolation region 103 is formed in the source / drain regions of an HV transistor in second device zone Z2 to enhance transistor performance at high operating voltages. The materials and methods used to form isolation region 103 are similar to those used to form isolation region 102.

[0028] In some embodiments, isolation regions 102 and 103 are formed first, followed by sequential implantation of deep well regions 104 / 204 / 304 / 404, first well regions 106 / 206 / 306 / 406, and third well regions 108 / 205. However, the order of forming isolation regions 102 and 103, deep well regions 104 / 204 / 304 / 404, first well regions 106 / 206 / 306 / 406, and third well regions 108 / 205 may be varied and is not limited to the embodiments described herein.

[0029] refer to Figure 2 , a surface doping layer 112 is formed in the first well region 106. The surface doping layer 112 is formed in the anode region 101a of the first well region 106. In some embodiments, the surface doping layer 112 is further formed in the cathode region 101b of the first well region 106. In some embodiments, the surface doping layer 112 is not formed in the bulk region 101c. In some embodiments, the surface doping layer 112 is not formed in the third device zone Z3 or the fourth device zone Z4. In some embodiments, the surface doping layer 112 includes a p-type dopant, such as boron, boron difluoride, or another suitable p-type dopant. In some embodiments, a surface doping layer 112 is also formed in the first well region 206 and the second well region 205 to form a PMOS transistor in the second device zone Z2.

[0030] The p-type dopant of the surface doping layer 112 is implanted into the n-type channel region of the PMOS transistor to tune the threshold voltage (Vt) of the PMOS transistor. In some embodiments, the surface doping layer 112 is formed in the n-type first well region 106 of the first device zone Z1 at the same time as the surface doping layer 112 is formed in the PMOS transistor or NMOS transistor in the second device zone Z2. In some embodiments, the surface doping layer 112 formed in the first well region 106 reduces the forward current performance of the SBD in the first device zone Z1. Introducing an additional mask to block the surface doping layer 112 from forming in the first device zone Z1 can help solve the problem but also incurs additional processing time and cost.

[0031] refer to Figure 3 After forming the surface doped layer 112, a dielectric layer 114 is formed over the substrate 100 and the surface doped layer 112. The dielectric layer 114 is further patterned to remove portions of the dielectric layer 114 in the first device zone Z1 and the second device zone Z2. In some embodiments, the dielectric layer 114 comprises a nitride, such as silicon nitride. In some embodiments, the dielectric layer 114 serves as an etch stop layer and is subsequently removed in subsequent processing steps. The dielectric layer 114 can be formed using PVD, CVD, ALD, thermal nitridation, or other suitable deposition methods.

[0032] Figure 4 The diagram illustrates the formation of a dielectric layer 116 over substrate 100. Dielectric layer 116 is formed over substrate 100 across device zones Z1 through Z4. Dielectric layers 114 and 116 can be formed of different materials. In some embodiments, dielectric layer 116 comprises silicon oxide. In some embodiments, dielectric layer 116 serves as a gate dielectric layer for a PMOS transistor or an NMOS transistor in a second device zone Z2 (not shown separately). Figure 11 ). In some embodiments, dielectric layer 116 is formed on substrate 100 without using a mask, so dielectric layer 116 also extends in first device zone Z1, third device zone Z3, and fourth device zone Z4. In some embodiments, dielectric layer 116 covers the entire first well region 106 and the entire third well region 108. In some embodiments, dielectric layer 116 is formed using PVD, CVD, plasma-assisted CVD (PECVD), low pressure CVD (LPCVD) or atmospheric pressure CVD (APCVD), ALD, spin coating, thermal growth process, or any suitable formation process. In some embodiments, dielectric layer 116 is formed using thermal oxidation. In some embodiments, dielectric layer 116 has a thickness D0 suitable for HV transistors operating at high voltage, and the thickness D0 of dielectric layer 116 may be about With In some embodiments, the thickness D0 of the dielectric layer 116 is about With Between or about With In the range between.

[0033] refer to Figure 5In some embodiments, a thermal treatment 111 is performed on the substrate 100 to drive dopants from the surface doped layer 112 into the dielectric layer 116. As previously discussed, dopants from the surface doped layer 112 of the opposite dopant type (e.g., the second conductivity) in the first well region 106 can reduce the performance of the SBD device. Thus, the oxide-containing dielectric layer 116 serves as an absorber for the surface doped layer 112, wherein the dopants in the surface doped layer 112 are driven to diffuse into the dielectric layer 116 with the aid of the thermal treatment 111, thereby partially or completely driving the dopants from the surface doped layer 112 away from the well regions 106, 205, and 206. On the other hand, the nitride-containing dielectric layer 114 cannot serve as an absorber due to the difficulty in diffusing p-type dopants into the nitride material. In some embodiments, the thermal treatment 111 is performed at a temperature greater than or equal to 400°C. In some embodiments, the thermal treatment 111 is performed at a temperature less than or equal to 1200°C, although higher temperatures may also be used. Since the dopants in the surface doping layer 112 are absorbed by the dielectric layer 116, the SBD device formed in the first device zone Z1 has a reduced turn-on voltage and thus the performance of the SBD device is improved. In some embodiments, the effect of the thermal treatment 111 is taken into consideration to determine Figure 1 The doping concentration arrangement of the well region in the second device zone Z2 is shown in , and thus the performance of the transistors in the second device zone Z2 is substantially unaffected by the thermal treatment 111 .

[0034] In some embodiments where thermal oxidation is used to form the dielectric layer 116, the thermal treatment 111 accompanies the thermal oxidation and can help drive the dopants of the surface doped layer 112 into the dielectric layer 116. Thus, the additional cost and time of a separate thermal treatment can be eliminated. In other words, the thermal treatment 111 can be performed on the surface doped layer 112 during the formation of the dielectric layer 116. Alternatively, in some embodiments, the thermal treatment 111 can be performed separately and independently during subsequent operations.

[0035] refer to Figure 6 , a fourth well region 118 is formed in the first well region 106. The fourth well region 118 includes dopants having a conductivity type opposite to that of the dopants in the first well region 106 (e.g., p-type). In some embodiments, the fourth well region 118 serves as a protective layer for improving the breakdown voltage of the SBD device and may include a ring shape when viewed from a plan view, wherein the ring surrounds the anode region 101a of the first well region 106. In some embodiments, in a plan view, the fourth well region 118 surrounds the silicide layer ( Figure 6 Not shown in; Figure 13 In some embodiments, the dopant concentration of the fourth well region 118 is between about 10E11 ions / cm 3 With about 10E14 ions / cm3 The fourth well region 118 may be formed using an implantation operation followed by an annealing process (e.g., a rapid thermal annealing (RTA) process). In some embodiments, the annealing process for forming the fourth well region 118 is performed at a temperature greater than or equal to 400° C. In some embodiments, the temperature of the heat treatment is less than or equal to 1200° C., although higher temperatures may also be used.

[0036] During the formation of the fourth well region 118, the subsequent annealing process can help drive the residual dopants of the surface doped layer 112 into the dielectric layer 116. The annealing processes used in forming the dielectric layer 116 and the fourth well region 118 work together to remove the surface doped layer 112 from the first well region 106 without additional thermal processing.

[0037] refer to Figure 7 The dielectric layer 116 is patterned to remove portions of the dielectric layer 116 covering the third device zone Z3 and the fourth device zone Z4. The dielectric layer 116 above the first device zone Z1 and the second device zone Z2 remains above the substrate 100. In some embodiments, a patterned mask layer is formed over the dielectric layer 116 to pattern the dielectric layer 116 according to the patterned mask layer. The dielectric layer 116 can be removed using dry etching, wet etching, or a combination thereof (e.g., reactive ion etching (RIE)). Furthermore, the dielectric layer 114 can serve as an etch mask during the etching operation. The patterned mask layer can be stripped after the patterning of the dielectric layer 116 is completed.

[0038] Next, the dielectric layer 114 is removed from the third device zone Z3 and the fourth device zone Z4. The removal of the dielectric layer 114 may be performed using dry etching, wet etching, or RIE.

[0039] Subsequently, another dielectric layer 120 is formed over the substrate 100 in the third device zone Z3, as shown in FIG. Figure 8 The dielectric layer 120 is used as a gate dielectric layer of a PMOS transistor or an NMOS transistor in the third device zone Z3 (not shown separately; Figure 11). In some embodiments, a dielectric layer 120 is formed on the substrate 100 using a mask so that the dielectric layer 120 extends over the first device zone Z1, the second device zone Z2, and the fourth device zone Z4. In some embodiments, the dielectric layer 120 completely covers the entire first well regions 306 and 406 in the third device zone Z3 and the fourth device zone Z4. In some embodiments, the dielectric layer 120 is formed using PVD, CVD, PECVD, LPCVD, APCVD, ALD, spin coating, thermal growth process, or any suitable formation process. In some embodiments, the dielectric layer 120 includes silicon oxide. In some embodiments, the dielectric layer 120 is formed of the same material as the dielectric layer 116. In some embodiments, the dielectric layer 120 has a thickness D1 suitable for the I / O transistor to operate at a medium voltage and may be about With In the range between, or about With In the range between, or about With , but larger or smaller thicknesses may also be used. In some embodiments, the thickness D1 of dielectric layer 120 is less than the thickness of dielectric layer 116. In some embodiments, the thickness ratio D0 / D1 is between approximately 6.0 and approximately 12.0, or between approximately 8.0 and approximately 10.0. Furthermore, since the material of dielectric layer 116 is the same as that of dielectric layer 120, the growth rate of dielectric layer 120 over dielectric layer 116 in first device zone Z1 and second device zone Z2 is less than the thickness D1 in third device zone Z3 and fourth device zone Z4. Therefore, the added thickness of dielectric layer 120 over dielectric layer 116 in first device zone Z1 and second device zone Z2 may be less than the thickness D1 of dielectric layer 120 in third device zone Z3 and fourth device zone Z4.

[0040] refer to Figure 9A The dielectric layers 116 and 220 are patterned to remove the portion of the dielectric layer 120 covering the fourth device zone Z4. In addition, the portion of the dielectric layer 120 above the first device zone Z1 is also recessed to a depth D11. Thus, a recess 121 is formed. The depth D11 may be about With In the range between, or can be about With In the range between, or can be about With In some embodiments, the recess depth D11 may be equal to or greater than the thickness D1. The recess 121 may span to cover the anode region 101a, the cathode region 101b, and the bulk region 101c. The recess 121 has sidewalls 121S formed on the dielectric layer 116 at a position aligned with the isolation region 102S that separates the first device zone Z1 from the adjacent device zone. The dielectric layer 116 above the second device zone Z2 and the dielectric layer 120 above the third device zone Z3 remain substantially unchanged above the substrate 100. In some embodiments, a patterned mask layer is formed above the substrate 100 to expose portions of the dielectric layers 116 and 120 according to the patterned mask layer. The exposed portions are then removed using dry etching, wet etching, or RIE. After the patterning of the dielectric layers 116 and 120 is completed, the patterned mask layer may be stripped.

[0041] In some embodiments, the ratio of the depth D11 to the thickness D0 of the dielectric layer 116 is greater than zero and less than about 30%. In some embodiments, the ratio of the recess depth D11 to the thickness D0 of the dielectric layer 116 is between about 10% and about 20%, such as about 15%.

[0042] Figure 9A The diagram illustrates sidewalls 121S and exposed bottom surface 121R of recess 121, with sidewalls 121S forming an angle α with exposed bottom surface 121R. In some embodiments, angle α is greater than or equal to 90°. In some embodiments, exposed bottom surface 121R connects to upper surface 116S of dielectric layer 116 via a smooth slope (not shown). In some embodiments, sidewalls 121S are aligned with the exposed surface of bulk region 101c and cover isolation region 102S between first device zone Z1 and other device zones. In some embodiments, recessed bottom surface 121R includes an area of ​​third well region 108 extending beyond first device zone Z1. In some embodiments, at least one side of recess 121 extends beyond isolation region 102S at the periphery of first device zone Z1, such that sidewalls 121S are located within device zones other than first device zone Z1.

[0043] The groove 121 may be formed as Figure 9B and Figure 9C Alternative shapes and configurations are shown in . Figure 9B The dielectric layers 116 and 220 are patterned so that the groove 121 spans to cover only the anode region 101a while preventing portions of the dielectric layer 116 aligned with the cathode region 101b and the bulk region 101c from being etched. Figure 9BThe recess 121 in the substrate 100 has sidewalls 121S formed in the dielectric layer 116 at a position aligned with the isolation region 102S separating the anode region 101a from the cathode region 101b. The dielectric layer 116 above the second device zone Z2 and the dielectric layer 120 above the third device zone Z3 remain substantially unchanged above the substrate 100. In some embodiments, the sidewalls 121S are aligned with the exposed surface of the anode region 101a, and the recess 121 covers the entire isolation region 102S between the anode region 101a and the cathode region 101b. In some embodiments, the exposed bottom surface 121R has a width 121B that is greater than a width Da of the upper surface of the anode region 101a surrounded by the fourth well region 118. Width 121B is determined to be greater than width Da because during the patterning operation of dielectric layer 116, the thickness of dielectric layer 116 above anode region 101a is sufficiently reduced by etching so that no residual dielectric layer 116 remains on the surface of first region 106 of the Schottky diode device in first device zone Z1. In some embodiments, width 121B is greater than approximately 0.1 μm, for example, in a range between approximately 0.1 μm and approximately 10 μm, in a range between approximately 0.5 μm and approximately 8 μm, or in a range between approximately 1 μm and approximately 5 μm.

[0044] Figure 9C Illustrated is yet another embodiment of patterning dielectric layers 116 and 220 such that recess 121 is formed to cover only anode region 101a and cathode region 101b while preventing portions of dielectric layer 116 aligned with bulk region 101c from being etched. Figure 9C Recess 121 in the substrate 100 has sidewalls 121S formed in dielectric layer 116 at locations aligned with isolation regions 102S separating cathode region 101b from bulk region 101c. Dielectric layer 116 above second device zone Z2 and dielectric layer 120 above third device zone Z3 remain substantially unchanged above substrate 100. In some embodiments, sidewalls 121S are aligned with the exposed surface of cathode region 101b, and recess 121 covers the entire isolation region 102S between cathode region 101b and bulk region 101c. In some embodiments, exposed bottom surface 121R has a width 121B that is greater than a width Db of the upper surface of first well region 106 between adjacent isolation regions 102S. In some embodiments, exposed bottom surface 121R has a width 121B that is less than width Db.

[0045] exist Figure 9A After the operations shown in FIG. 1 , another dielectric layer 122 is formed over the fourth device zone Z4. The dielectric layer 122 serves as a gate dielectric layer for a PMOS transistor or an NMOS transistor in the fourth device zone Z4 (not shown separately). Figure 11, the gate structure 408 of this transistor is shown in FIG. In some embodiments, dielectric layer 122 is formed on substrate 100 using a mask so that dielectric layer 122 also extends over first device zone Z1, second device zone Z2, and third device zone Z3. In some embodiments, dielectric layer 122 covers the entire first well region 406 in fourth device zone Z4. In some embodiments, dielectric layer 122 is formed using PVD, CVD, PECVD, LPCVD, APCVD, ALD, spin coating, thermal growth, or any other suitable formation process. In some embodiments, dielectric layer 122 comprises silicon oxide. In some embodiments, dielectric layer 122 is formed of the same material as dielectric layer 120 or 116.

[0046] In some embodiments, the dielectric layer 122 has a thickness D2 suitable for the core transistor to operate at a low voltage, and may be less than about or between approximately With between or about With In some embodiments, the thickness D2 of the dielectric layer 122 is less than the thickness of the dielectric layer 116 or 120. In some embodiments, the thickness ratio D0 / D2 is between about 30.0 and about 60.0 or between about 40.0 and about 50.0. In some embodiments, the thickness ratio D1 / D2 is between about 2.0 and about 6.0, or between about 3.0 and about 5.0. In addition, given that the material of the dielectric layer 122 is the same as the material of the dielectric layers 116 and 120, the growth rate of the dielectric layer 122 over the dielectric layers 116 and 120 is less than the growth rate of growing the dielectric layer 122 only in the fourth device zone Z4. Therefore, the added thickness of the dielectric layer 122 over the dielectric layer 116 or 120 in the respective device zones Z1 to Z3 may be less than the thickness D2 of the dielectric layer 122 in the fourth device zone Z4, and thus Figure 10 Portions of the dielectric layer 122 in the device zones Z1 to Z3 are omitted.

[0047] refer to Figure 11 , gate structures are formed in device zones Z2 through Z4. These gate structures can be metal gate structures or sacrificial gate structures used to form transistor devices in device zones Z2 through Z4. For example, gate structure 208 is formed to include gate electrode 212 and sidewall spacers 214 above dielectric layer 116. Similarly, gate structure 308 is formed to include gate electrode 312 and sidewall spacers 314 above dielectric layer 120, and gate structure 408 is formed to include gate electrode 412 and sidewall spacers 414 above dielectric layer 122.

[0048] In some embodiments, the gate electrode 212, 312, or 412 may include a stack formed of an oxide layer, a nitride layer, and a hard mask layer for a sacrificial gate structure, or may include a stack formed of a glue layer, a cap layer, one or more work function tuning layers, and a conductive fill layer for a metal gate structure. In some embodiments, the gate electrode 212, 312, or 412 is formed by depositing the layer stack using CVD, PVD, ALD, or other suitable deposition processes and etching the layer stack into the shape of the gate electrode using dry etching, wet etching, or a combination thereof, as needed.

[0049] In some embodiments, the sidewall spacers 214, 314, or 414 may be formed of a dielectric material (e.g., an oxide, a nitride, an oxynitride, a carbide, a high-k dielectric material, a combination thereof, or the like). In some embodiments, the sidewall spacers 214, 314, or 414 are formed by conformally forming a dielectric material on the top surface and along the sidewalls of the respective gate electrodes 212, 312, and 412, and performing an etching operation to remove horizontal portions of the dielectric material, thereby leaving vertical portions along the sidewalls of the respective gate electrodes. In some embodiments, the etching operation used to form the sidewall spacers 214, 314, and 414 is an anisotropic etch.

[0050] In some embodiments, portions of the dielectric layers 116, 120, and 122 may be etched away during an etching operation used to pattern the gate electrodes 212, 312, and 412 and the sidewall spacers 214, 314, and 414. For example, the dielectric layer 122 may be patterned during the etching operation so that portions of the dielectric layer 122 covered by the gate structure 408 remain, while other portions are removed, exposing the surface 100S. The portion of the dielectric layer 122 remaining below the gate electrode 412 serves as the gate dielectric layer for the gate structure 408. In some embodiments, the portion of the dielectric layer 116 or 120 not covered by the gate electrode 212 or 312 in the respective device zone Z2 or Z3 is thinned by the spacer etching operation. In some embodiments, the dielectric layer 120 is further patterned so that portions of the dielectric layer 120 not covered by the gate electrode 312 are further removed, exposing the surface 100S. Therefore, the portion of the dielectric layer 120 remaining below the gate electrode 312 serves as a gate dielectric layer for the gate structure 308 .

[0051] Figure 12 The graphic illustration will Figure 9A. In some embodiments, the dielectric layer 116 is patterned to form an opening that exposes the surface 100S in the anode region 101a of the first well region 106 in the first device zone Z1. In some embodiments, the dielectric layer 116 is patterned to form an opening that exposes the surface 100S in the cathode region 101b of the first well region 106. In some embodiments, the dielectric layer 116 is patterned to form an opening that exposes the surface 100S in the bulk region 101c of the third well region 108. In addition, the dielectric layer 116 is patterned to expose the source / drain regions 201S of the transistor in the second device zone Z2. The portion of the patterned dielectric layer 116 located below the gate electrode 212 serves as a gate dielectric layer for the gate structure 208. The gate structure 208 can be used as an etch mask during the patterning operation to expose the source / drain regions 201S. In some embodiments, the opening formed by the patterning operation may have an area that is larger or smaller than the exposed anode region 101a and cathode region 101b in the first well region 106 or the exposed bulk region 101c in the third well region 108. In some embodiments, the patterning operation still leaves a portion of the anode region 101a, cathode region 101b, or bulk region 101c covered by the dielectric layer 116. In some embodiments, the patterned dielectric layer 116 is overetched and exposes a portion of the underlying isolation region 102. In some embodiments, the patterning operation of the dielectric layer 116 in the first device zone Z1 and the second device zone Z2 is performed using a single etching process. In some embodiments, the dielectric layer 116 is patterned using a photolithography / etching process, a laser drilling process, or another suitable material removal process.

[0052] After the patterning of the underlying isolation region 102, the patterning operation forms a pattern in the dielectric layer 116. In some embodiments, the dielectric layer 116 includes a stepped shape or a smooth slope at a location on the periphery of the first device zone Z1. The stepped or sloped sidewalls 121S of the dielectric layer 116 face the inner region (e.g., the anode region 101a) of the first device zone Z1. In some embodiments, the upper surface of the patterned dielectric layer 116 includes an upper level and a lower level, wherein the upper level and the lower level are represented by the unetched upper surface 116S and the recessed bottom surface 121R, respectively. In some embodiments, in a plan view, the upper level 116S laterally surrounds the lower level 121R. In some embodiments, the upper level 116S of the patterned dielectric layer 116 is connected to the lower level 121R of the dielectric layer 116 by a slope. In some embodiments, the dielectric layer 116 includes a stepped shape or slope at a location aligned with the sidewalls 121S, such as Figures 9A to 9C This step shape or slope left in the patterned dielectric layer 116 is caused by Figure 9A(or another option is Figure 9B and Figure 9C )and Figure 12 . This two-step patterning operation results in a complete removal of the relatively thick dielectric layer 116 in the anode region 101a, and optionally in the cathode region 101b or bulk region 101c. Furthermore, no additional etching operations are required to achieve the two-step patterning because these two patterning operations are performed together with other patterning operations on at least one of the device zones Z2 to Z4. Consequently, processing costs and time can be reduced.

[0053] The dielectric layer 116 is patterned to ensure that the dielectric material of the dielectric layer 116 is completely removed from the surface 100S of the anode region 101a to improve the performance of the SBD device. In some embodiments, a portion of the dielectric layer 116 is subjected to Figure 12 The single patterning operation in the embodiment is not a two-step patterning operation, and thus, remnants of the dielectric layer 116 may be left on the surface 100S of the cathode region 101b or the bulk region 101c. For example, the bump 116R ( Figure 15 ) is formed in the opening of the cathode region 101b (or in the bulk region 101c, but not shown) and exposes a portion of the substrate 100. Alternatively, the residual layer 116T ( Figure 15 101c (or in cathode region 101b, but not shown) and covers substrate 100. In some embodiments, patterning of dielectric layer 116 completely removes the residue so that no residue remains on surface 100S of cathode region 101b or bulk region 101c.

[0054] Figure 13 The diagram illustrates an enlarged cross-sectional view of the first device zone Z1 of the subsequent process. A heavily doped layer 126 is formed in the cathode region 101b of the first well region 106. The heavily doped layer 126 can help enhance the electrical properties of the SBD device, such as reducing the contact resistance of the cathode terminal of the SBD device. The heavily doped layer 126 contains a dopant of a first conductivity type (e.g., an n-type dopant), wherein the dopant concentration is greater than the dopant concentration of the first well region 106. The heavily doped layer 126 can be formed by an ion implantation operation and the implantation dose can be between about 1E15 atoms / cm 3 and about 1E17 atoms / cm 3 In some embodiments, a portion of the heavily doped layer 126 (not shown) is used as a doping region for NMOS transistors or PMOS transistors in device zones Z2 to Z4. For example, during the formation of the heavily doped layer 126, a heavily doped n-type region is formed as a source / drain region in the NMOS transistor in the second device zone Z2.

[0055] In some embodiments, another heavily doped layer 128 is formed in the bulk region 101c of the first well region 106. The heavily doped layer 128 can help enhance the electrical properties of the SBD device, such as reducing the contact resistance of the bulk terminals of the SBD device. The heavily doped layer 128 contains a dopant of the second conductivity type (e.g., a p-type dopant), wherein the dopant concentration is greater than the dopant concentration of the third well region 108. The heavily doped layer 128 can be formed by an ion implantation operation, and the implantation dose can be between about 1E15 atoms / cm 3 and about 1E17 atoms / cm 3 In some embodiments, a portion of the heavily doped layer 128 (not shown) is used as a doping region for NMOS transistors or PMOS transistors in device zones Z2 to Z4. For example, during the formation of the heavily doped layer 128, a heavily doped p-type region is formed as a source / drain region in the PMOS transistor in the second device zone Z2.

[0056] Subsequently, a conductive layer (e.g., a silicide layer) 130 is formed on the exposed surfaces 100S in the anode region 101a, cathode region 101b, and bulk region 101c. In some embodiments, the silicide layer 130 is formed over the heavily doped layers 126 and 128. The silicide layer 130 is formed in contact with the exposed surface 100S of the anode region 101a. Furthermore, the silicide layer 130 may be formed in contact with the exposed cathode region 101b and the exposed bulk region 101c. In some embodiments, the silicide layer 130 may include cobalt silicide, titanium silicide, tungsten silicide, nickel silicide, or the like. An exemplary process for forming the silicide layer 130 includes forming a metal-containing layer (not shown) to cover the substrate 100 and the dielectric layer 116. In this embodiment, the metal-containing layer includes cobalt; however, in other embodiments, the metal-containing layer may also include titanium, tungsten, nickel, or a combination thereof. An annealing process is performed on the metal-containing layer to react the metal with silicon in substrate 100 to form silicide material of silicide layer 130. In some embodiments, after forming silicide layer 130, portions of the metal-containing layer on dielectric layer 116 that have not reacted with silicon are removed.

[0057] A dielectric layer 132 is deposited over dielectric layer 116, the exposed portion of fourth well region 118, and silicide layer 130. Dielectric layer 132 may serve as a contact etch stop layer (CESL) for subsequent processing. In some embodiments, dielectric layer 132 comprises a dielectric material such as silicon nitride, silicon oxynitride, silicon carbon nitride, any other suitable insulating material, or a combination thereof. In some embodiments, dielectric layer 132 is formed using PVD, CVD, ALD, spin coating, thermal growth, or other suitable formation processes.

[0058] refer to Figure 14An interlayer dielectric (ILD) layer 134 is formed over the contact etch stop layer 132. In some embodiments, the ILD layer 134 comprises oxide, oxynitride, silicon nitride, a nitrogen-containing oxide, a nitrogen-doped oxide, silicon oxynitride, a polymer, any other suitable insulating material, or a combination thereof. In some embodiments, the ILD layer 134 is formed using PVD, CVD, ALD, spin coating, or other deposition processes. Subsequently, the ILD layer 134 is patterned to form through-holes through the ILD layer 134 to expose portions of the silicide layer 130 in the anode region 101a, cathode region 101b, and bulk region 101c. Conductive material is formed in these through-holes to form conductive plugs 136 that electrically couple the underlying anode region 101a, cathode region 101b, and bulk region 101c to features in the underlying layers. For example, conductive plug 136a is electrically coupled to anode region 101a, and conductive plugs 136b and 136c are electrically coupled to cathode region 101b and bulk region 101c, respectively. Conductive plug 136 has a multilayer structure and may be formed from one or more materials. For example, in this embodiment, the one or more materials are titanium, titanium nitride, and tungsten. In other embodiments, other metal elements such as tantalum, tantalum nitride, copper, copper alloys, nickel, tin, gold, or combinations thereof may also be used. In some embodiments, a titanium layer is formed to serve as a glue layer for conductive plug 136, bonding the underlying silicide layer 130 to the remaining layers of conductive plug 136.

[0059] Figures 15 to 17 The diagram shows Figures 1 to 8 、 Figure 9B (or another option is Figure 9C ), Figure 10 and Figure 11 As previously discussed, a two-step patterning is performed on the dielectric layer 116 to ensure that the dielectric material of the dielectric layer 116 is completely removed from the surface 100S of the anode region 101a to improve the performance of the SBD device. Figure 9B , the patterning operation does not thin the portions of the dielectric layer 116 in the cathode region 101b and the bulk region 101c. This non-thinning thickness can make it difficult to form openings in the dielectric layer 116 using a single patterning operation and without leaving residues in the openings. In some embodiments, residues of the dielectric layer 116 may remain on the surface 100S of the cathode region 101b or the bulk region 101c. For example, a bump 116R is formed in the opening in the cathode region 101b (or in the bulk region 101c, but not shown) and exposes a portion of the substrate 100. Alternatively, a residual layer 116T is formed in the opening in the bulk region 101c (or in the cathode region 101b, but not shown) and covers the entire substrate 100. In Figure 9B The operations in Figure 9CIn another embodiment of the operation alternative, the groove 121 does not extend to the bulk region 101c. Figure 15 During the patterning operation in FIG. 1 , bumps 116R or residual layers 116T may be formed in the bulk region 101 c .

[0060] Figure 16 The diagram shows Figure 15 After the operation of forming heavily doped layers 126 and 128, a silicide layer 130 and an ILD layer 132. The materials, configurations and formation methods of the heavily doped layers 126 and 128, the silicide layer 130 and the ILD layer 132 are similar to those of the reference Figure 13 The materials, configurations, and formation methods described in the foregoing. Figure 15 In embodiments where the bump 116R or thin layer 116T in the silicon-containing layer 100S remains on the surface 100S, the silicide layer 130 cannot be successfully formed on the surface 100S due to the residue. The residue blocks the silicon from reacting with the metal-containing layer, and thus the silicide layer 130 is partially formed or absent where the residue exists.

[0061] Figure 17 The diagram shows Figure 16 After the operation of forming the ILD layer 134 and the conductive plug 136. The materials, configuration and formation method of the ILD layer 134 and the conductive plug 136 are similar to those of the reference Figure 14 Described materials, configurations, and methods of formation.

[0062] In some embodiments, after forming the conductive plug 136 in the through-hole of the ILD layer 134, a pre-cleaning process may be performed to remove unwanted particles, contaminants, or material residues (including residues of the dielectric layer 116) from the through-hole. The pre-cleaning process may be performed using a wet etching operation to facilitate the removal of these unwanted materials from the surface 100S. In this way, if residues remain on the surface 100S and are exposed by the through-hole, they will be further removed by the pre-cleaning process. At the same time, the silicide layer 132 may be left in place during the pre-cleaning process. Figure 17, the pre-cleaning process creates openings in the silicide layer 130 that are aligned with the conductive plugs 136b in the right-hand cathode region 101b. Similarly, the pre-cleaning process creates openings in the thin layer 116T that are aligned with the conductive plugs 136c in the right-hand bulk region 101c. Therefore, the subsequently formed conductive plugs 136b and 136c can be in direct contact with the underlying heavily doped layers 126 and 128, respectively. Due to the presence of these openings in the cathode region 101b or the bulk region 101c due to the unsuccessful removal of the dielectric layer 116, the SBD performance may not be significantly degraded. This is because the interface between the cathode region 101b (or bulk region 101c) and its underlying first well region 106 (or third well region 108) is formed as an ohmic contact, and the electrical properties of the SBD device will not be negatively affected.

[0063] However, in some conventional methods, if this opening of the silicide layer 130 exists in the anode region 101a, the first well region 106 will contact the conductive plug 136a through this opening, and at least a portion of the Schottky barrier interface will be established by the conductive material (e.g., titanium) in the conductive plug 136a, and will not be established by the silicide layer 130 (e.g., cobalt silicide). Because the work function of the conductive material of the conductive plug 136a can be lower than the work function of the silicide layer, the Schottky barrier height formed by the conductive material of the conductive plug 136a and the first well region 106 is lower than the Schottky barrier height formed by the silicide layer 130 and the first well region. As a result, the leakage current performance of the SBD device can be reduced. In contrast, by using the proposed two-step patterning scheme for the dielectric layer 116 for completely removing the remnants of the dielectric layer 116 in the anode region 101a before forming the conductive plug 136a, the surface 100S will be completely covered by the silicide layer 130, no opening will be generated during the formation of the conductive plug 136a, and the metal side of the Schottky barrier interface will be formed only by the silicide layer 130. Therefore, leakage current performance can be improved.

[0064] Figure 18 Graphs illustrating the performance of an SBD device according to some embodiments are shown. Graphs (a) and (b) show the forward current and leakage current of the SBD device in forward bias mode and reverse bias mode, respectively, in terms of cumulative probability of current measurement. Figure 9A (or another option is Figure 9B and Figure 9C )and Figure 12 The two-step patterning scheme illustrated in Figure 12The conventional one-step patterning scheme patterns the dielectric layer 116 in a single patterning operation. The current measurement diagrams of graphs (a) and (b) illustrate that although the proposed scheme method performs slightly better than the conventional method in forward current measurement under forward bias mode, the leakage current performance of the proposed scheme is significantly better than that of the conventional method.

[0065] According to an embodiment, a method for manufacturing a Schottky barrier diode includes: forming a first well region above a substrate; forming a first dielectric layer above the first well region; patterning the first dielectric layer by reducing a first thickness of the first dielectric layer; removing the first dielectric layer to expose a surface of the first well region; and forming a conductive layer above the first well region to obtain a Schottky barrier interface.

[0066] According to an embodiment, a method for manufacturing a semiconductor device includes: forming a first well region and a second well region above a substrate, wherein the second well region is configured as part of a transistor device; forming a dielectric layer above the first well region and the second well region; patterning the dielectric layer by reducing the thickness of a first portion of the dielectric layer above the first well region while leaving a second portion of the dielectric layer above the second well region unchanged; etching the dielectric layer to expose a first surface of the first well region and a second surface of the second well region; and forming a silicide layer on the exposed surface of the first well region to obtain a Schottky barrier interface.

[0067] According to an embodiment, a Schottky barrier diode includes a well region located in a substrate; a silicide layer located above the well region. The silicide layer, together with the well region, forms a Schottky barrier interface. The Schottky barrier diode further includes an isolation region disposed in the substrate and defining the well region; and a dielectric layer located above the substrate and the silicide layer. The dielectric layer includes a stepped shape at its periphery.

[0068] The foregoing summarizes the features of several embodiments to enable those skilled in the art to better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

[0069]

Symbol Description

[0070] 10: Schottky diode

[0071] 100: substrate

[0072] 100S: Upper surface / surface

[0073] 101a: Anode area

[0074] 101b: cathode area

[0075] 101c: Block area

[0076] 102: Quarantine

[0077] 102S: Quarantine

[0078] 103: Quarantine

[0079] 104: Second well region / deep well region

[0080] 106: First well region / first region

[0081] 108: Third well region

[0082] 111: Heat Treatment

[0083] 112: Surface doping layer

[0084] 114: Dielectric layer / nitride-containing dielectric layer

[0085] 116: Dielectric layer / patterned dielectric layer

[0086] 116R: Bump

[0087] 116S: Upper surface / higher level

[0088] 116T: Residual layer / thin layer

[0089] 118: Fourth well region

[0090] 120: Dielectric layer

[0091] 121: Groove

[0092] 121B: Width

[0093] 121S: Sidewall

[0094] 121R: Exposed bottom surface / recessed bottom surface / lower level

[0095] 122: Dielectric layer

[0096] 126: Heavily doped layer

[0097] 128: Heavily doped layer

[0098] 130: Conductive layer / silicide layer

[0099] 132: Dielectric layer / contact etch stop layer / silicide layer

[0100] 134: Interlayer dielectric layer

[0101] 136a: Conductive plug

[0102] 136b: Conductive plug

[0103] 136c: Conductive plug

[0104] 201S: Source / drain region

[0105] 204: Second well region / deep well region

[0106] 205: Third well region

[0107] 206: First well region / well region

[0108] 208: Gate structure

[0109] 212: Gate electrode

[0110] 214: Sidewall spacer

[0111] 304: Second well region / deep well region

[0112] 306: First well region

[0113] 308: Gate structure

[0114] 312: Gate electrode

[0115] 314: Sidewall spacer

[0116] 404: Second well region / deep well region

[0117] 406: First well region

[0118] 408: Gate structure

[0119] 412: Gate electrode

[0120] 414: Sidewall spacer

[0121] D0: thickness

[0122] D1: Thickness

[0123] D2: Thickness

[0124] D11: Depth / recessed depth

[0125] Db: width

[0126] Z1: First device zone / device zone

[0127] Z2: Second device zone / device zone

[0128] Z3: The third device zone / device zone

[0129] Z4: Fourth device zone / device zone

[0130] α: Angle

Claims

1. A method for manufacturing a Schottky barrier diode, comprising: forming a first well region above the substrate; forming a first dielectric layer over the first well region; patterning the first dielectric layer by reducing a first thickness of the first dielectric layer, comprising: depositing a second dielectric layer over a third well region in the substrate, the third well region being an n-well of a PMOS transistor or a p-well of an NMOS transistor; and removing the second dielectric layer from the third well region and reducing the first thickness of the first dielectric layer using the same patterning operation; further etching the portion of the first dielectric layer whose first thickness has been reduced to expose a surface of the first well region; and A conductive layer is formed above the first well region to obtain a Schottky barrier interface. 2 . The method of claim 1 , further comprising forming a doped layer in the first well region before forming the first dielectric layer over the first well region, the doped layer having a conductivity type opposite to that of the first well region. 3 . The method of claim 2 , further comprising performing a thermal treatment on the doping layer to diffuse dopants in the doping layer into the first dielectric layer. 4 . The method of claim 1 , wherein forming the first dielectric layer over the first well region comprises forming the first dielectric layer to extend over a second well region on the substrate, the first dielectric layer being configured as a gate dielectric layer for a transistor device in the second well region. 5 . The method of claim 1 , wherein the first dielectric layer has a second thickness before being reduced in thickness, wherein a ratio of the first thickness to the second thickness is greater than zero and less than 30%.

6. The method of claim 1 , wherein depositing a second dielectric layer over a third well region in the substrate comprises extending the second dielectric layer over a fourth well region in the substrate, and wherein removing the second dielectric layer from the third well region comprises preventing the second dielectric layer over the fourth well region from being removed, the fourth well region being an n-well of a PMOS transistor or a p-well of an NMOS transistor. The method of claim 1 , wherein the second dielectric layer comprises a second thickness that is less than the first thickness of the first dielectric layer. 8 . The method of claim 6 , further comprising depositing a third dielectric layer over the third well region after removing the second dielectric layer from the third well region, wherein the third dielectric layer comprises a third thickness that is less than the first thickness of the first dielectric layer. 9 . The method of claim 8 , wherein depositing the third dielectric layer over the third well region comprises extending the third dielectric layer over the first well region and the fourth well region.

10. The method of claim 1, further comprising forming an isolation region defining the first well region, and wherein patterning the first dielectric layer by reducing the first thickness of the first dielectric layer comprises creating a slope of the first dielectric layer at a location aligned with the isolation region.

11. The method of claim 1 , further comprising forming an isolation region above the first well region, and wherein patterning the first dielectric layer by reducing the first thickness of the first dielectric layer comprises preventing a portion of the first dielectric layer aligned with a cathode region of the Schottky barrier diode from being removed.

12. The method according to claim 1, wherein forming the conductive layer comprises: depositing a metal-containing layer over the substrate and the etched first dielectric layer, and The metal-containing layer is reacted with silicon of the substrate to form the conductive layer. 13 . The method of claim 1 , wherein removing the first dielectric layer to expose a surface of the first well region comprises leaving a remnant of the first dielectric layer at a cathode region on the substrate. 14 . The method of claim 13 , further comprising performing a cleaning operation to remove the residual portion of the first dielectric layer, and forming a conductive plug in contact with the first well region at a location where the residual portion is removed.

15. A method of manufacturing a semiconductor device, comprising: forming a first well region and a second well region over the substrate, the second well region being configured as part of a transistor device; forming a first dielectric layer over the first well region and the second well region; depositing a second dielectric layer over a third well region in the substrate, the third well region being an n-well of a PMOS transistor or a p-well of an NMOS transistor; patterning the first dielectric layer using the same patterning operation to remove the second dielectric layer from the third well region and reduce the thickness of a first portion of the first dielectric layer over the first well region while leaving a second portion of the first dielectric layer over the second well region unchanged; further etching the first portion of the first dielectric layer whose thickness has been reduced to expose a first surface of the first well region and a second surface of the second well region; and A silicide layer is formed on the exposed surface of the first well region to obtain a Schottky barrier interface. 16 . The method of claim 15 , further comprising forming an interlayer dielectric layer over the etched first dielectric layer, and forming a conductive plug electrically coupled to the silicide layer through the interlayer dielectric layer. 17 . The method of claim 15 , further comprising forming a gate structure over the substrate and aligned with the second well region. 18 . The method of claim 15 , further comprising forming a fourth well region in the first well region, the fourth well region comprising a conductivity type opposite to that of the first well region.

19. A semiconductor device comprising: a well region located in the substrate; a silicide layer located above the well region, wherein the silicide layer and the well region together form a Schottky barrier interface; an isolation region disposed in the substrate and defining the well region; a transistor device adjacent to the isolation region; and a dielectric layer having a first portion located above the substrate and the silicide layer and a second portion serving as a gate dielectric layer for the transistor device, The dielectric layer is formed into a stepped shape at the periphery of the dielectric layer by reducing a first thickness of the dielectric layer, patterning the dielectric layer, and further etching the portion of the dielectric layer where the first thickness has been reduced to expose a surface of the well region.

20. The semiconductor device according to claim 19, further comprising a conductive plug located above the silicide layer, wherein a Schottky barrier height formed by the silicide layer and the well region is greater than a Schottky barrier height formed by a conductive material of the conductive plug and the well region.

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