Semiconductor chip packaging structure and preparation method thereof

Abstract

The present invention provides a semiconductor chip packaging structure and a preparation method thereof. The packaging structure includes a semiconductor chip, a conductive column, an epoxy resin layer, a first polymer resin layer, a metal wiring layer, a second polymer resin layer, an under-bump metal layer, a solder ball and a protective film; the conductive column is located on the upper surface of the semiconductor chip; the epoxy resin layer plastic-seales the semiconductor chip and the conductive column and covers the side wall of the semiconductor chip, and the conductive column is exposed on the upper surface of the epoxy resin layer; the first polymer resin layer is located on the upper surface of the epoxy resin layer; the metal wiring layer is located on the upper surface of the conductive column; the second polymer resin layer is located on the side wall and upper surface of the metal wiring layer; the under-bump metal layer is located in the groove of the metal wiring layer and extends to the upper surface of the second polymer resin layer; the solder ball is located on the upper surface of the under-bump metal layer; and the protective film is located on the lower surface of the semiconductor chip and the epoxy resin layer. Compared with the prior art, the present invention helps to reduce device size, reduce power consumption and improve production yield.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor chip packaging manufacturing, and in particular to a semiconductor chip packaging structure and a preparation method thereof. Background Art

[0002] With the rapid development of electronic information technology and the continuous improvement of consumer demand, electronic products are constantly moving towards lightweight, multifunctional and low-power development. In order to accommodate more pins in a smaller packaging area, various new packaging methods have emerged, and wafer-level chip packaging (Wafer Level Chip Scale Packaging, referred to as WLCSP) is one of them. The so-called wafer-level chip packaging, as the name suggests, is to first package and test the entire wafer, and then cut it into individual chip particles. Existing wafer-level chip packaging usually forms a rewiring layer on the wafer first, and then forms a plastic encapsulation material layer on the rewiring layer, and then forms a through hole in the plastic encapsulation material layer and fills the through hole with metal electrically connected to the rewiring layer to achieve electrical extraction of the device. This traditional packaging method is relatively complicated, resulting in an increase in production costs and easily leading to device defects. In the process of forming the rewiring layer and the process of forming the opening in the plastic packaging material layer, it is easy to cause misalignment and difficulty in accurately connecting to the chip. In the process of filling the metal in the opening, it is easy to cause filling defects, resulting in a large resistance of the device and a decrease in device performance. The adhesion between the structural layers is not strong, which makes it easy for water vapor to penetrate into the packaging structure, resulting in a decrease in the reliability and service life of the device. At the same time, the structure encapsulated by the traditional method is generally too large, which not only runs counter to the market demand for device miniaturization, but also easily leads to shortcomings such as high power consumption of the device. In addition, in the existing wafer-level chip packaging process, it is usually necessary to use a carrier to cut and separate the chip, which leads to an increase in production costs. Summary of the invention

[0003] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a semiconductor chip packaging structure and a preparation method thereof, so as to solve the problems that the wafer-level chip packaging method in the prior art has a complex process flow, resulting in high production costs, and the prepared device structure is relatively large, the resistance and power consumption are relatively high, and the device reliability is reduced.

[0004] To achieve the above-mentioned purpose and other related purposes, the present invention provides a semiconductor chip packaging structure, the semiconductor chip packaging structure includes a semiconductor chip, a conductive column, an epoxy resin layer, a first polymer resin layer, a metal wiring layer, a second polymer resin layer, an under-bump metal layer, a solder ball and a protective film; the conductive column is located on the upper surface of the semiconductor chip, and the conductive column is electrically connected to the semiconductor chip; the epoxy resin layer plastic-seales the semiconductor chip and the conductive column and covers the side wall of the semiconductor chip, the lower surface of the epoxy resin layer is flush with the lower surface of the semiconductor chip, and the conductive column is exposed on the upper surface of the epoxy resin layer; the first polymer resin layer is located on the upper surface of the epoxy resin layer, and the first polymer resin The layer has an opening, and the opening exposes the conductive column; the metal wiring layer is located on the upper surface of the conductive column and extends to the upper surface of the first polymer resin layer, and the metal wiring layer has a groove formed on the surface corresponding to the conductive column; the second polymer resin layer is located on the side wall and the upper surface of the metal wiring layer; the second polymer resin layer has an opening, and the opening exposes the groove of the metal wiring layer; the under-bump metal layer is located in the groove of the metal wiring layer and extends to the upper surface of the second polymer resin layer; the solder ball is located on the upper surface of the under-bump metal layer, and the upper surface of the solder ball is higher than the upper surface of the second polymer resin layer; the protective film is located on the lower surface of the semiconductor chip and the epoxy resin layer.

[0005] Optionally, the semiconductor chip packaging structure further includes a metal seed layer located between the semiconductor chip and the conductive pillar.

[0006] Optionally, the under-bump metal layer includes a first metal layer and a second metal layer, the first metal layer is located on the upper surface of the conductive column and extends to the upper surface of the second polymer resin layer, and the second metal layer is located on the upper surface of the first metal layer; the first metal layer includes one of copper and titanium, and the second metal layer includes electroplated copper.

[0007] Optionally, the material of the protective film includes one or both of epoxy resin and polyimide, and the thickness of the protective film is 8-50 μm.

[0008] The present invention also provides a method for preparing a semiconductor chip packaging structure, the method for preparing a semiconductor chip packaging structure comprising the following steps:

[0009] 1) Providing a semiconductor substrate, wherein a plurality of semiconductor chips are formed in the semiconductor substrate;

[0010] 2) forming a conductive column on the upper surface of the semiconductor substrate, wherein the conductive column is electrically connected to the semiconductor chip;

[0011] 3) forming a trench in the semiconductor substrate, wherein the trench is located between the semiconductor chips and surrounds the semiconductor chips;

[0012] 4) forming an epoxy resin layer on the surface of the structure obtained in step 3), wherein the epoxy resin layer plastic-encapsulates the semiconductor chip and the conductive pillar and fills the groove, and the conductive pillar is exposed on the upper surface of the epoxy resin layer;

[0013] 5) forming a first polymer resin layer on the upper surface of the epoxy resin layer and forming an opening in the first polymer resin layer, wherein the opening exposes the conductive pillar;

[0014] 6) forming a metal wiring layer on the upper surface of the conductive pillar, wherein the metal wiring layer extends to the upper surface of the first polymer resin layer, and a groove is formed in the metal wiring layer;

[0015] 7) forming a second polymer resin layer on the sidewall and the upper surface of the metal wiring layer, and forming an opening in the second polymer resin layer, wherein the opening exposes the groove of the metal wiring layer;

[0016] 8) forming an under bump metallurgy layer in the groove of the metal wiring layer, wherein the under bump metallurgy layer extends to the upper surface of the second polymer resin layer;

[0017] 9) forming a solder ball on the upper surface of the under bump metal layer, wherein the upper surface of the solder ball is higher than the upper surface of the second polymer resin layer;

[0018] 10) thinning the lower surface of the semiconductor substrate until the epoxy resin layer in the groove is exposed;

[0019] 11) forming a protective film on the lower surfaces of the semiconductor substrate and the epoxy resin layer;

[0020] 12) Cutting the structure obtained in step 11) from the grooves of the semiconductor substrate to obtain a plurality of independent semiconductor chip packaging structures.

[0021] Optionally, before forming the conductive pillar, the method further includes forming a metal seed layer on the upper surface of the semiconductor substrate, and the conductive pillar is formed on the upper surface of the metal seed layer.

[0022] Optionally, step 4) includes:

[0023] Forming an epoxy resin layer on the surface of the structure obtained in step 3), wherein the epoxy resin layer plastic-encapsulates the semiconductor chip and the conductive pillar and fills the groove, and the thickness of the epoxy resin layer is 50-100 μm higher than the height of the conductive pillar;

[0024] The epoxy resin layer is ground until the conductive pillars are exposed, and the surface roughness of the ground epoxy resin layer is less than or equal to 0.2 μm.

[0025] Optionally, the method of forming the metal wiring layer includes:

[0026] Sputtering to form a first metal layer in the opening and on the upper surface of the first polymer resin layer, wherein the first metal layer is connected to the conductive column, and the material of the first metal layer includes one or both of titanium and copper;

[0027] Forming a second metal layer by electroplating on the upper surface of the first metal layer, wherein the material of the second metal layer includes copper;

[0028] The second metal layer and the first metal layer are etched to disconnect the metal wiring layers in corresponding different openings from each other, and the metal wiring layers extend from the openings to the upper surface of the first polymer resin layer.

[0029] Optionally, the step of forming the solder ball includes:

[0030] forming a metal bump on the upper surface of the underbump metal layer;

[0031] Reflowing the metal bump to form the solder ball;

[0032] The obtained structure is cleaned.

[0033] Optionally, the depth of the groove formed in step 3) is 1 / 4 to 1 / 2 of the thickness of the semiconductor substrate.

[0034] Compared with the prior art, the semiconductor chip packaging structure and preparation method of the present invention fully encapsulate the chip on six sides (front, back, left, right, top and bottom) within the wafer size range and through optimized process design, it not only helps to reduce device size, reduce device power consumption, and improve production yield, but also helps to reduce packaging processes, reduce production costs and improve production efficiency. The present application performs a process of metal wiring layer before forming solder balls, which is conducive to the spatial arrangement of solder balls, and can comprehensively consider the positions of metal wiring layers and solder balls in combination with electrical properties. In addition, multi-layer polymer resin enhances the adhesion of metal wiring layers, solder balls and epoxy resin layers, and protects the back of the device through a protective film to avoid water vapor infiltration, which helps to improve device reliability and device performance and extend the service life of the device. The chip packaging structure prepared based on the preparation method of the present invention has the advantages of miniaturization, low power consumption and high reliability, and has great commercial value. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The flowchart shows the method for preparing the semiconductor chip packaging structure provided by the present invention.

[0036] Figure 2 to Figure 15 Display as Figure 1 A schematic diagram of the cross-sectional structure presented in each step of the preparation method, wherein: Fig.15 At the same time, it shows the structural schematic diagram of the semiconductor chip packaging structure finally prepared by the present invention.

[0037] Component number description

[0038] 11 Semiconductor substrate

[0039] 12 Semiconductor Chip

[0040] 121 Solder pad

[0041] 13 Conductive column

[0042] 14 Groove

[0043] 15 Epoxy resin layer

[0044] 16 First polymer resin layer

[0045] 161 Opening

[0046] 17 Metal wiring layer

[0047] 171 First Metal Layer

[0048] 172 Second Metal Layer

[0049] 18 Solder balls

[0050] 19 Protective film

[0051] 20 Metal seed layer

[0052] 21 Second polymer resin layer

[0053] 22 Under Bump Metallurgy

[0054] Steps S1 to S12 DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] See also Figure 1 to Figure 15It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed at will, and the component layout may also be more complicated. It should also be noted that the upper surface and the lower surface in this embodiment are only a relative position representation rather than a specific limitation on the device.

[0057] like Figure 1 As shown, the present invention provides a method for preparing a semiconductor chip packaging structure, and the method for preparing a semiconductor chip packaging structure comprises the following steps:

[0058] S1: Provide a semiconductor substrate 11, wherein a plurality of semiconductor chips 12 are formed in the semiconductor substrate 11, specifically Figure 2 As shown;

[0059] S2: forming a conductive column 13 on the upper surface of the semiconductor substrate 11 (more precisely, on the upper surface of the semiconductor chip 12), wherein the conductive column 13 is electrically connected to the semiconductor chip 12, as shown in FIG. Figure 3 As shown;

[0060] S3: forming a groove 14 in the semiconductor substrate 11, wherein the groove 14 is located between the semiconductor chips 12 and surrounds the semiconductor chips 12, as shown in FIG. Figure 4 As shown;

[0061] S4: forming an epoxy resin layer 15 on the surface of the structure obtained in step 3), wherein the epoxy resin layer 15 plastic-encapsulates the semiconductor chip 12 and the conductive pillar 13 and fills the groove 14, wherein the conductive pillar 13 is exposed on the upper surface of the epoxy resin layer 15, i.e., the upper surface of the conductive pillar 13 is flush with the upper surface of the epoxy resin layer 15, as shown in FIG. Figure 5 and Figure 6 As shown;

[0062] S5: forming a first polymer resin layer 16 on the upper surface of the epoxy resin layer 15 and forming an opening 161 in the first polymer resin layer 16, wherein the opening 161 exposes the conductive pillar 13, as shown in FIG. Figure 7 As shown;

[0063] S6: forming a metal wiring layer 17 on the upper surface of the conductive pillar 13, wherein the metal wiring layer 17 extends to the upper surface of the first polymer resin layer 16, and a groove is formed in the metal wiring layer 17, as shown in FIG. Figure 8 As shown;

[0064] S7: forming a second polymer resin layer 21 on the sidewall and the upper surface of the metal wiring layer 17, and forming an opening in the second polymer resin layer 21, wherein the opening exposes the groove of the metal wiring layer 17, as shown in FIG. Fig. 9 As shown;

[0065] S8: forming an under bump metallization layer 22 in the groove of the metal wiring layer 17, wherein the under bump metallization layer 22 extends to the upper surface of the second polymer resin layer 21, as shown in FIG. Fig.10 As shown;

[0066] S9: forming a solder ball 18 on the upper surface of the under bump metal layer 22, wherein the upper surface of the solder ball 18 is higher than the upper surface of the second polymer resin layer 21, as shown in FIG. Fig.11 As shown;

[0067] S10: Thinning the lower surface of the semiconductor substrate 11 until the epoxy resin layer 15 in the groove 14 is exposed. Fig.12 As shown;

[0068] S11: forming a protective film 19 on the lower surfaces of the semiconductor substrate 11 and the epoxy resin layer 15, specifically as follows Fig.13 As shown;

[0069] S12: Cutting the structure obtained in step 11) from the groove 14 of the semiconductor substrate 11 to obtain a plurality of mutually independent semiconductor chip packaging structures, specifically as follows: Fig.14 and 15 shown.

[0070] As an example, the semiconductor substrate 11 may be a silicon substrate, a germanium substrate, a germanium-silicon composite substrate, an SOI substrate, a sapphire substrate or a gallium nitride substrate, etc.; preferably, in this embodiment, the semiconductor substrate 11 is a silicon wafer. It should be particularly noted that hundreds or thousands of semiconductor chips 12 are usually formed on the semiconductor substrate 11, and only a partial structure is shown in this schematic diagram. The semiconductor chips 12 are independent of each other, and a scribe groove is usually formed between two adjacent semiconductor chips 12. Active and / or passive devices are formed on the semiconductor chip 12, and a pad 121 for electrically leading out its internal functional device may be formed on its surface to electrically connect the semiconductor chip 12 to an external device, and the upper surface of the pad 121 is exposed on the upper surface of the semiconductor chip 12, and the upper surface of the pad 121 is flush with the upper surface of the semiconductor chip 12. In this embodiment, a single semiconductor chip 12 having two pads 121 is taken as an example, but it is not limited thereto.

[0071] As an example, before forming the conductive pillar 13, the step of forming a metal seed layer 20 on the upper surface of the semiconductor substrate 11 (more accurately, on the upper surface of the semiconductor chip 12) is also included. The conductive pillar 13 is formed on the upper surface of the metal seed layer 20. The material of the metal seed layer 20 includes but is not limited to one or both of copper and titanium. The method of forming the metal seed layer 20 includes but is not limited to sputtering. The formation of the metal seed layer 20 is conducive to the subsequent formation of the conductive pillar 13 and helps to improve the conductive performance of the conductive pillar 13. In this embodiment, as an example, the thickness of the metal seed layer 20 is 1 to 10 μm. Because the inventors have found through many experiments that when the thickness of the metal seed layer 20 is too small, the insufficient conductivity and adhesion of the metal seed layer 20 will cause gaps in the subsequent conductive pillars 13, and when the thickness is too large, the metal seed layer 20 itself is prone to holes, resulting in device defects.

[0072] The conductive pillar 13 is directly formed on the surface of the semiconductor chip 12. Since there is no obstacle, there is no need to worry about adverse effects on other structures during the preparation process, and alignment with the semiconductor chip 12 can be achieved, such as accurate alignment with the pad 121. Compared with the traditional method of first forming a dielectric layer and then forming a through hole in the dielectric layer and then depositing metal, the process is greatly simplified, which is conducive to improving production yield. As an example, the material of the conductive pillar 13 includes but is not limited to copper. When the conductive pillar 13 is a copper pillar, the method of forming the conductive pillar 13 includes but is not limited to electroplating. The use of electroplated copper is not only conducive to shortening the process time, but also helps to enhance the bonding force between the conductive pillar 13 and the metal seed layer 20 and the conductivity of the conductive pillar 13 itself. In addition, it also helps to enhance the corrosion resistance and water vapor resistance of the conductive pillar 13, which helps to reduce device resistance, reduce device power consumption, and improve device performance. And in a further example, after the conductive column 13 is formed, high temperature annealing can be performed. Through annealing, the lattice defects of the conductive column 13 can be improved, stress and holes can be eliminated, and holes at the interface of electroplated copper and sputtered copper can be eliminated, which helps to improve the conductivity of the conductive column 13 and the metal wiring layer 17 and improve device performance. Of course, in other examples, the conductive column 13 can also be one or a combination of two or more other metal materials such as aluminum, nickel, gold, silver, and titanium, and its formation method can also be one or more of deposition methods, chemical plating, etc., which is not strictly limited in this embodiment. The height and width of the conductive column 13 can be set as needed, such as 10 to 50 μm.

[0073] As an example, the method of forming the groove 14 in the semiconductor substrate 11 includes but is not limited to one or more of photolithography and laser etching. In the present embodiment, as an example, a laser is selected to form the groove 14 from the aforementioned scribe groove between adjacent semiconductor chips 12. Compared with photolithography, laser etching helps to simplify the preparation process and reduce production costs. And as an example, the depth of the groove 14 is 1 / 4 to 1 / 2 of the thickness of the semiconductor substrate 11, which can not only avoid damage or even fragmentation of the semiconductor substrate 11 during the cutting process, but also facilitate subsequent cutting, ensuring that the subsequently formed epoxy resin layer 15 is sufficient to protect the semiconductor chip 12.

[0074] As an example, the step 4) includes the steps of:

[0075] An epoxy resin layer 15 is formed on the surface of the structure obtained in step 3) by one or more methods including but not limited to compression molding, transfer molding, liquid sealing molding, molded bottom filling, capillary bottom filling, vacuum lamination or spin coating, wherein the epoxy resin layer 15 plastic-encapsulates the semiconductor chip 12 and the conductive column 13 and fills the groove 14, and the thickness of the epoxy resin layer 15 is 50 to 100 μm higher than the height of the conductive column 13 (including the endpoint value, when the numerical range is involved in this specification, unless otherwise specified, the endpoint value is included); setting the thickness of the epoxy resin layer 15 to 50 to 100 μm higher than the height of the conductive column 13 helps to ensure the uniformity of the overall thickness of the semiconductor substrate 11 and fully meet the subsequent process requirements;

[0076] The epoxy resin layer 15 is ground until the conductive pillar 13 is exposed, and the surface roughness of the epoxy resin layer 15 after grinding is less than or equal to 0.2 μm; the surface roughness of the epoxy resin layer 15 after grinding is less than or equal to 0.2 μm, which is beneficial to the adhesion of the metal wiring layer 17 and the solder ball 18 formed in the subsequent process to the surface of the epoxy resin layer 15.

[0077] Of course, in other examples, the epoxy resin layer 15 can also be formed based on the top of the conductive column 13, so that the height of the formed epoxy resin layer 15 is exactly the same as the height of the conductive column 13 (if there is the metal seed layer 20, it is the sum of the heights of the metal seed layer 20 and the conductive column 13). In this way, the subsequent process of grinding the epoxy resin layer 15 can be omitted, which is conducive to reducing process steps and reducing production costs.

[0078] As an example, the method of forming the first polymer resin layer 16 includes but is not limited to one or more of compression molding, transfer molding, liquid sealing molding, molded bottom filling, capillary bottom filling, vacuum lamination or spin coating. The first polymer resin layer 16 is preferably polyimide (PI for short). Polyimide has a higher heat resistance temperature than epoxy resin. Forming the first polymer resin layer 16 before forming the metal wiring layer 17 helps to enhance the adhesion between the metal wiring layer 17 and the epoxy resin layer 15 (EMC), helps to improve the reliability and durability of the device, and thus helps to extend the service life of the device. As an example, the thickness of the first polymer resin layer 16 is less than the thickness of the epoxy resin layer 15. The material and formation method of the second polymer resin layer 21 are preferably the same as the material and formation method of the first polymer resin layer 16. The structure of the multi-layer polymer resin layer helps to enhance the adhesion between the metal wiring layer 17, the solder ball 18 and the epoxy resin layer 15, and helps to improve the durability of the device.

[0079] As an example, the method of forming the opening 161 in the first polymer resin layer 16 includes but is not limited to photolithography and etching. The opening 161 formed in the first polymer resin layer 16 gradually increases from bottom to top, that is, it is funnel-shaped, which is conducive to the formation of the subsequent metal wiring layer 17.

[0080] As an example, a method of forming the metal wiring layer 17 includes:

[0081] A first metal layer 171 is formed by sputtering in the opening 161 of the first polymer resin layer 16 and on the upper surface of the first polymer resin layer 16. The first metal layer 171 is connected to the conductive pillar 13. The material of the first metal layer 171 includes one or both of titanium and copper. The method of forming the first metal layer 171 includes but is not limited to physical vapor deposition.

[0082] A second metal layer 172 is formed by electroplating on the upper surface of the first metal layer 171. The material of the second metal layer 172 includes copper. Methods for forming the second metal layer 172 include but are not limited to electroplating. For example, the first metal layer 171 may include stacked titanium layers and copper layers from bottom to top, and the second metal layer 172 includes a copper layer. The titanium layer may serve as an adhesion layer. The fact that both the first metal layer 171 and the second metal layer 172 include copper helps to enhance the adhesion between the first metal layer 171 and the second metal layer 172, which is beneficial to improving the conductivity and stability of the metal wiring layer 17. In a further example, high-temperature annealing may be performed after the second metal layer 172 is formed. Annealing may improve lattice defects, eliminate stress and holes, and improve metal conductivity.

[0083] Since the first metal layer 171 and the second metal layer 172 are formed on the entire surface of the first polymer resin layer 16 in the first two steps, the second metal layer 172 and the first metal layer 171 are subsequently etched to disconnect the metal wiring layers 17 in the corresponding different openings from each other, and the metal wiring layer 17 extends from the opening 161 to the upper surface of the first polymer resin layer 16, or in other words, the first metal layer 171 and the second metal layer 172 are partially located on the upper surface of the first polymer resin layer 16, which is helpful for the subsequent electrical connection between the metal wiring layer 17 and the solder ball 18. The metal wiring layer 17 does not fill the entire opening but is only located on the sidewall and bottom of the opening, so there is still a certain space in the opening, that is, there is a groove in the metal wiring layer 17. Of course, the groove can also be formed by etching a part of the metal wiring layer 17 in the groove after the metal wiring layer 17 is formed. The groove is not only a space for accommodating the under bump metal layer 22, but also provides convenience for subsequent processes, such as playing a positioning role.

[0084] Of course, in other examples, a mask or other structure may be used to shield the non-metal deposition area to ensure that the metal wiring layer 17 is only formed in a predetermined area, which is not strictly limited in this embodiment.

[0085] As an example, the method of forming the UBM layer 22 includes but is not limited to electroplating. The electroplating method is conducive to accurately controlling the position of the UBM layer 22. For example, in this example, the horizontal surface area of ​​the UBM layer 22 on the second polymer resin layer 21 is the same as the horizontal surface area of ​​the metal wiring layer 17 on the first polymer resin layer 16. As an example, the material of the UBM layer 22 includes one or more metals such as titanium, copper, nickel, tin and silver. In a further example, the UBM layer 22 includes a titanium layer, a copper layer, a nickel layer and a silver-tin layer (not shown) from bottom to top. The titanium layer can act as an adhesion layer, and the nickel layer can protect the copper layer from being oxidized and contaminated. The silver-tin layer is conducive to the connection of the UBM layer 22 with subsequent bonding. The arrangement of this composite structure helps to enhance the conductivity and stability of the UBM layer 22, thereby helping to improve device performance. After the UBM layer 22 is formed, annealing can be performed to improve crystal defects, eliminate stress, and improve the conductivity of the UBM layer 22.

[0086] As an example, the steps of forming the solder ball 18 include:

[0087] A metal bump is formed on the upper surface of the underbump metal layer 22, and the material of the metal bump includes but is not limited to one or two or a combination of more than two of copper, aluminum, nickel, gold, silver, and titanium; nickel is preferred in this embodiment to facilitate subsequent heating and reflow;

[0088] Reflowing the metal bump to form the solder ball 18, during which the metal reflows to the recess of the under bump metal layer 22, which is beneficial to enhancing the adhesion between the solder ball 18 and the under bump metal layer 22;

[0089] The obtained structure is cleaned.

[0090] As an example, the lower surface of the semiconductor substrate 11 may be thinned by methods including but not limited to chemical mechanical polishing until the epoxy resin layer 15 in the groove 14 is exposed. After polishing, the lower surface of the semiconductor substrate 11 and the lower surface of the epoxy resin layer 15 are flush.

[0091] As an example, the method for forming the protective film 19 varies according to the material of the protective film 19. In this embodiment, as an example, the material of the protective film 19 includes one or both of epoxy resin and polyimide, which is conducive to enhancing the adhesion between the protective film 19 and the epoxy resin layer 15. The thickness of the protective film 19 is 8 to 50 μm, and the protective film 19 can effectively prevent water vapor and the like from penetrating into the semiconductor device, which helps to improve the reliability of the device.

[0092] As an example, the structure obtained in step 11) can be cut from the groove 14 by a method including but not limited to laser cutting to obtain a plurality of mutually independent semiconductor chip packaging structures. Since the groove 14 is filled with an epoxy resin layer 15, after cutting, the side of the semiconductor chip 12 is covered by the epoxy resin layer 15, which can effectively prevent water vapor from penetrating, and help improve the reliability and durability of the device.

[0093] Compared with the prior art, the preparation method of the present invention performs six-sided full encapsulation of the chip within the wafer size range and through optimized process design, it not only helps to reduce the device size, reduce the device power consumption, and improve the production yield, but also helps to reduce the packaging process, reduce the production cost and improve the production efficiency. In addition, no carrier is required in the preparation process of the present invention, which helps to reduce the production cost. The present application performs the process of the metal wiring layer before forming the solder ball, which is conducive to the spatial arrangement of the solder ball, and the position of the metal wiring layer and the solder ball can be comprehensively considered in combination with the electrical performance. In addition, the multi-layer polymer resin enhances the adhesion of the metal wiring layer, the solder ball and the epoxy resin layer, and the back of the device is protected by a protective film to avoid water vapor infiltration, which helps to improve the device reliability and device performance and extend the service life of the device.

[0094] like Fig.15As shown, the present invention also provides a semiconductor chip packaging structure, which is prepared based on the above-mentioned preparation method, so the above-mentioned content can be fully quoted here, and the same content will not be repeated as much as possible for the purpose of brevity. The semiconductor chip packaging structure includes a semiconductor chip 12, a conductive column 13, an epoxy resin layer 15, a first polymer resin layer 16, a metal wiring layer 17, a second polymer resin layer 21, an under-bump metal layer 22, a solder ball 18 and a protective film 19; the conductive column 13 is located on the upper surface of the semiconductor chip 12, and the conductive column 13 is electrically connected to the semiconductor chip 12; the epoxy resin layer 15 plastic-seales the semiconductor chip 12 and the conductive column 13 and covers the side wall of the semiconductor chip 12, the lower surface of the epoxy resin layer 15 is flush with the lower surface of the semiconductor chip 12, and the conductive column 13 is exposed on the upper surface of the epoxy resin layer 15; the first polymer resin layer 16 is located on the upper surface of the epoxy resin layer 15, and the first polymer resin layer 16 has an opening 161, and the opening 1 61 exposes the conductive column 13; the metal wiring layer 17 is located on the upper surface of the conductive column 13 and extends to the upper surface of the first polymer resin layer 16, and the metal wiring layer 17 has a groove formed on the surface corresponding to the conductive column 13; the second polymer resin layer 21 is located on the side wall and the upper surface of the metal wiring layer 17; the second polymer resin layer 21 has an opening, and the opening exposes the groove of the metal wiring layer 17; the under-bump metal layer 22 is located in the groove of the metal wiring layer 17 and extends to the upper surface of the second polymer resin layer 21; the solder ball 18 is located on the upper surface of the under-bump metal layer 22, and the upper surface of the solder ball 18 is higher than the upper surface of the second polymer resin layer 21; the protective film 19 is located on the lower surface of the semiconductor chip 12 and the epoxy resin layer 15.

[0095] As an example, the openings 161 in the first polymer resin layer 16 gradually increase in size from bottom to top.

[0096] As an example, the semiconductor chip packaging structure further includes a metal seed layer 20 located between the semiconductor chip 12 and the conductive pillar 13 .

[0097] As an example, the metal wiring layer 17 includes a first metal layer 171 and a second metal layer 172, the first metal layer 171 is located on the upper surface of the conductive column 13 and extends to the upper surface of the first polymer resin layer 16, and the second metal layer 172 is located on the upper surface of the first metal layer 171; the first metal layer 171 includes one of copper and titanium, and the second metal layer 172 includes electroplated copper.

[0098] In a further example, the first metal layer 171 includes a titanium layer and a copper layer stacked one above the other, and the copper layer is located on the upper surface of the titanium layer.

[0099] As an example, the material of the protective film 19 includes one or both of epoxy resin and polyimide, and the thickness of the protective film 19 is 8-50 μm.

[0100] In summary, the present invention provides a semiconductor chip packaging structure and a preparation method thereof. The semiconductor chip packaging structure includes a semiconductor chip, a conductive column, an epoxy resin layer, a first polymer resin layer, a metal wiring layer, a second polymer resin layer, an under-bump metal layer, a solder ball and a protective film; the conductive column is located on the upper surface of the semiconductor chip, and the conductive column is electrically connected to the semiconductor chip; the epoxy resin layer plastic-encapsulates the semiconductor chip and the conductive column and covers the side wall of the semiconductor chip, the lower surface of the epoxy resin layer is flush with the lower surface of the semiconductor chip, and the conductive column is exposed on the upper surface of the epoxy resin layer; the first polymer resin layer is located on the upper surface of the epoxy resin layer, and the first polymer resin layer has an opening, and the opening exposes the Conductive pillar; the metal wiring layer is located on the upper surface of the conductive pillar and extends to the upper surface of the first polymer resin layer, and the metal wiring layer has a groove formed on the surface corresponding to the conductive pillar; the second polymer resin layer is located on the side wall and upper surface of the metal wiring layer; the second polymer resin layer has an opening, and the opening exposes the groove of the metal wiring layer; the under-bump metal layer is located in the groove of the metal wiring layer and extends to the upper surface of the second polymer resin layer; the solder ball is located on the upper surface of the under-bump metal layer, and the upper surface of the solder ball is higher than the upper surface of the second polymer resin layer; the protective film is located on the lower surface of the semiconductor chip and the epoxy resin layer. Compared with the prior art, the semiconductor chip packaging structure and the preparation method thereof of the present invention perform six-sided full encapsulation of the chip within the wafer size range and through optimized process design, it not only helps to reduce device size, reduce device power consumption, and improve production yield, but also helps to reduce packaging processes, reduce production costs and improve production efficiency. The present application performs a process of manufacturing a metal wiring layer before forming solder balls, which is beneficial to the spatial arrangement of solder balls, and the positions of the metal wiring layer and solder balls can be comprehensively considered in combination with electrical properties. In addition, the multi-layer polymer resin enhances the adhesion of the metal wiring layer, solder balls and epoxy resin layer, and the back of the device is protected by a protective film to prevent water vapor from penetrating, which helps to improve device reliability and device performance and extend device service life. The chip packaging structure prepared based on the preparation method of the present invention has the advantages of miniaturization, low power consumption and high reliability, and has great commercial value. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor chip packaging structure, characterized in that: The method for preparing the semiconductor chip packaging structure comprises the following steps: 1) Providing a semiconductor substrate, wherein a plurality of semiconductor chips are formed in the semiconductor substrate; 2) forming a conductive column on the upper surface of the semiconductor substrate, wherein the conductive column is electrically connected to the semiconductor chip; 3) forming a trench in the semiconductor substrate, wherein the trench is located between the semiconductor chips and surrounds the semiconductor chips; 4) forming an epoxy resin layer on the surface of the structure obtained in step 3), wherein the epoxy resin layer plastic-encapsulates the semiconductor chip and the conductive pillar and fills the groove, and the conductive pillar is exposed on the upper surface of the epoxy resin layer; 5) forming a first polymer resin layer on the upper surface of the epoxy resin layer and forming an opening in the first polymer resin layer, wherein the opening exposes the conductive pillar; 6) forming a metal wiring layer on the upper surface of the conductive pillar, wherein the metal wiring layer extends to the upper surface of the first polymer resin layer, and a groove is formed in the metal wiring layer; 7) forming a second polymer resin layer on the sidewall and the upper surface of the metal wiring layer, and forming an opening in the second polymer resin layer, wherein the opening exposes the groove of the metal wiring layer; 8) forming an under bump metallurgy layer in the groove of the metal wiring layer, wherein the under bump metallurgy layer extends to the upper surface of the second polymer resin layer; 9) forming a solder ball on the upper surface of the under bump metal layer, wherein the upper surface of the solder ball is higher than the upper surface of the second polymer resin layer; 10) thinning the lower surface of the semiconductor substrate until the epoxy resin layer in the groove is exposed; 11) forming a protective film on the lower surfaces of the semiconductor substrate and the epoxy resin layer; 12) Cutting the structure obtained in step 11) from the grooves of the semiconductor substrate to obtain a plurality of mutually independent semiconductor chip packaging structures.

2. The method for preparing a semiconductor chip packaging structure according to claim 1, characterized in that: Before forming the conductive pillar, the method further includes forming a metal seed layer on the upper surface of the semiconductor substrate, and the conductive pillar is formed on the upper surface of the metal seed layer.

3. The method for preparing a semiconductor chip packaging structure according to claim 1, characterized in that: Step 4) includes: Forming an epoxy resin layer on the surface of the structure obtained in step 3), wherein the epoxy resin layer plastic-encapsulates the semiconductor chip and the conductive pillar and fills the groove, and the thickness of the epoxy resin layer is 50-100 μm higher than the height of the conductive pillar; The epoxy resin layer is ground until the conductive pillars are exposed, and the surface roughness of the ground epoxy resin layer is less than or equal to 0.2 μm.

4. The method for preparing a semiconductor chip packaging structure according to claim 1, characterized in that: The method of forming the metal wiring layer includes: Sputtering to form a first metal layer in the opening and on the upper surface of the first polymer resin layer, wherein the first metal layer is connected to the conductive column, and the material of the first metal layer includes one or both of titanium and copper; Forming a second metal layer by electroplating on the upper surface of the first metal layer, wherein the material of the second metal layer includes copper; The second metal layer and the first metal layer are etched to disconnect the metal wiring layers in corresponding different openings from each other, and the metal wiring layers extend from the openings to the upper surface of the first polymer resin layer.

5. The method for preparing a semiconductor chip packaging structure according to claim 2, wherein: The steps of forming the solder ball include: forming a metal bump on the upper surface of the underbump metal layer; Reflowing the metal bump to form the solder ball; The obtained structure is cleaned.

6. The method for preparing a semiconductor chip packaging structure according to any one of claims 2 to 5, characterized in that: The depth of the groove formed in step 3) is 1 / 4 to 1 / 2 of the thickness of the semiconductor substrate.

7. A semiconductor chip packaging structure, characterized in that: The semiconductor chip packaging structure is prepared by the method for preparing a semiconductor chip packaging structure according to claim 1, and the semiconductor chip packaging structure comprises: Semiconductor chips; A conductive column, located on the upper surface of the semiconductor chip, the conductive column being electrically connected to the semiconductor chip; An epoxy resin layer, wherein the epoxy resin layer plastic-encapsulates the semiconductor chip and the conductive pillars and covers the sidewalls of the semiconductor chip, wherein the lower surface of the epoxy resin layer is flush with the lower surface of the semiconductor chip, and the conductive pillars are exposed on the upper surface of the epoxy resin layer; A first polymer resin layer, located on the upper surface of the epoxy resin layer, wherein the first polymer resin layer has an opening, and the opening exposes the conductive column; A metal wiring layer, located on the upper surface of the conductive column and extending to the upper surface of the first polymer resin layer, wherein the metal wiring layer is formed with a groove corresponding to the surface of the conductive column; A second polymer resin layer is located on the sidewall and upper surface of the metal wiring layer; the second polymer resin layer has an opening therein, and the opening exposes the groove of the metal wiring layer; an under bump metallization layer, located in the groove of the metal wiring layer and extending to the upper surface of the second polymer resin layer; A solder ball is located on the upper surface of the under-bump metal layer, and the upper surface of the solder ball is higher than the upper surface of the second polymer resin layer; A protective film is located on the lower surfaces of the semiconductor chip and the epoxy resin layer.

8. The semiconductor chip packaging structure according to claim 7, wherein: The semiconductor chip packaging structure further includes a metal seed layer located between the semiconductor chip and the conductive pillar.

9. The semiconductor chip packaging structure according to claim 7, characterized in that: The metal wiring layer includes a first metal layer and a second metal layer, the first metal layer is located on the upper surface of the conductive column and extends to the upper surface of the second polymer resin layer, and the second metal layer is located on the upper surface of the first metal layer; the first metal layer includes one of copper and titanium, and the second metal layer includes electroplated copper.

10. The semiconductor chip packaging structure according to any one of claims 7 to 9, characterized in that: The material of the protective film includes one or both of epoxy resin and polyimide, and the thickness of the protective film is 8-50 μm.

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