semiconductor packages

Abstract

A semiconductor package is provided. The semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a covering portion surrounding a side surface of the contact portion. A first conductive barrier layer surrounds the side surface of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2019-0179975 filed on December 31, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more embodiments of the inventive concept are directed to a semiconductor package. Background Art

[0003] In recent developments in the electronics industry, demand for portable electronic devices has rapidly increased. Consequently, there has been an increasing demand for electronic components of portable electronic devices to be compact in size and reduced in weight. Semiconductor packages mounted on portable electronic devices can process data at high capacity and provide compact size and reduced weight for electronic components.

[0004] In semiconductor packages with compact size and reduced weight, stress can concentrate on the underbump pads (also known as "pads") and redistribution insulation layers of the semiconductor package due to external stress. This stress can cause cracks to propagate along the side surfaces of the underbump pads. Consequently, the underbump pads and redistribution insulation layers frequently peel off due to the cracks. The underbump pads and redistribution insulation layers can also peel off due to heat generated from the semiconductor package. Summary of the Invention

[0005] One or more exemplary embodiments of the inventive concept provide a semiconductor package having improved reliability.

[0006] According to an exemplary embodiment of the present invention, a semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite to the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a covering portion surrounding a side surface of the contact portion. A first conductive barrier layer surrounds the side surface of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.

[0007] According to another exemplary embodiment of the present invention, a semiconductor package includes a semiconductor chip, a redistribution insulating layer including an opening, and an external connection bump including a first portion filling the opening. The lower bump pad includes a first surface and a second surface opposite to the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a covering portion that surrounds the side surface of the contact portion and is covered by the redistribution insulating layer. The first conductive barrier layer surrounds the side surface of the lower bump pad and is arranged between the side surface of the lower bump pad and the redistribution insulating layer in the horizontal direction. The second conductive barrier layer is arranged on the covering portion of the lower bump pad and surrounds the side wall of the external connection bump. The surface of the contact portion of the external connection bump that contacts the lower bump pad is coplanar with the surface of the covering portion of the second conductive barrier layer that directly contacts the lower bump pad in the vertical direction. The vertical direction is perpendicular to the horizontal direction.

[0008] According to another exemplary embodiment of the present inventive concept, a semiconductor package includes a semiconductor chip, a redistribution insulation layer including an opening, and an external connection bump including a first portion filling the opening. A lower bump pad includes a first conductive layer directly contacting the first portion of the external connection bump, a diffusion barrier layer disposed on the first conductive layer, and a second conductive layer disposed on the diffusion barrier layer and vertically spaced apart from the first conductive layer. The first conductive barrier layer surrounds a side surface of the lower bump pad and is disposed between the lower bump pad and the redistribution insulation layer in a horizontal direction perpendicular to the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments of the present inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept;

[0011] Figure 2 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 1 An enlarged cross-sectional view of region II in FIG.

[0012] Figure 3 It is along Figure 1 A cross-sectional view showing a lower bump pad and a first conductive barrier layer according to an exemplary embodiment of the inventive concept, taken along line III-III';

[0013] Figure 4 is a cross-sectional view illustrating a semiconductor module according to an exemplary embodiment of the present inventive concept;

[0014] Figure 5 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 4 an enlarged cross-sectional view of region V;

[0015] Figure 6 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept;

[0016] Figure 7 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 6 An enlarged cross-sectional view of region VII in FIG.

[0017] Figure 8 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept; and

[0018] Figures 9 to 23 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0019] Hereinafter, exemplary embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings. In the accompanying drawings, like reference numerals will be used for like elements, and redundant descriptions thereof will be omitted.

[0020] Figure 1 is a cross-sectional view illustrating a semiconductor package 10 according to an exemplary embodiment of the inventive concept. Figure 2 It shows Figure 1 Magnified view of region II. Figure 3 It is along Figure 1 A cross-sectional view taken along line III-III′ showing the lower bump pad 150 and the first conductive barrier layer 160 .

[0021] Reference Figures 1 to 3 , a semiconductor package 10 according to an exemplary embodiment of the inventive concept may include a redistribution structure 100 , a semiconductor chip 200 , a mold layer 300 , and external connection bumps 400 .

[0022] The redistribution structure 100 may include a redistribution insulating layer 110 , first to third redistribution patterns 120 , 130 , and 140 , an under bump pad 150 , a first conductive barrier layer 160 , and a second conductive barrier layer 170 .

[0023] In an exemplary embodiment, the redistribution insulating layer 110 may include first to fourth redistribution insulating layers 111, 113, 115, and 117. For example, Figure 1As shown in the exemplary embodiment of the present invention, the first redistribution insulating layer 111, the second redistribution insulating layer 113, the third redistribution insulating layer 115 and the fourth redistribution insulating layer 117 of the redistribution insulating layer 110 can be sequentially stacked in a vertical direction parallel to the thickness direction of the redistribution insulating layer 110 (for example, a direction extending from the lower surface 119 of the redistribution insulating layer 110 to the upper surface 118 of the redistribution insulating layer 110). In an exemplary embodiment, each of the first to fourth redistribution insulating layers 111, 113, 115 and 117 can be formed of a material film made of an organic compound. For example, each of the first to fourth redistribution insulating layers 111, 113, 115 and 117 can be formed of a material film made of an organic polymer material. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0024] For example, in another exemplary embodiment, each of the first to fourth redistribution insulating layers 111, 113, 115, and 117 may include an insulating material made of a photoimageable dielectric (PID) material capable of performing a photolithography process. Alternatively, each of the first to fourth redistribution insulating layers 111, 113, 115, and 117 may be made of photosensitive polyimide (PSPI).

[0025] However, exemplary embodiments of the present inventive concept are not limited thereto. Each of the first to fourth redistribution insulating layers 111, 113, 115, and 117 may further include oxide or nitride. For example, each of the first to fourth redistribution insulating layers 111, 113, 115, and 117 may include a compound selected from silicon oxide or silicon nitride.

[0026] Each of the first to third redistribution patterns 120, 130, and 140 may include first to third conductive thread patterns 121, 131, and 141 and first to third conductive via patterns 123, 133, and 143. The first to third conductive thread patterns 121, 131, and 141 may be disposed on at least one of the upper and lower surfaces of each of the first to fourth redistribution insulation layers 111, 113, 115, and 117. The first to third conductive via patterns 123, 133, and 143 may penetrate at least one of the first to fourth redistribution insulation layers 111, 113, 115, and 117. The first to third conductive via patterns 123, 133, and 143 may be connected to at least one of the first to third conductive thread patterns 121, 131, and 141 or to the lower bump pad 150.

[0027] The first to third redistribution patterns 120, 130, and 140 may include first to third redistribution pattern seed layers 125, 135, and 145. The first to third redistribution pattern seed layers 125, 135, and 145 may be disposed between any one of the first to fourth redistribution insulation layers 111, 113, 115, and 117 and any one of the first to third conductive thread patterns 121, 131, and 141, and between any one of the first to fourth redistribution insulation layers 111, 113, 115, and 117 and any one of the first to third conductive via patterns 123, 133, and 143. For example, as Figure 1 As shown in the exemplary embodiment of FIG, the first redistribution pattern seed layer 125 may be disposed in a vertical direction between the first conductive line pattern 121 and the second redistribution insulation layer 113 and may be disposed between the second redistribution insulation layer 113 and the first conductive via pattern 123. The second redistribution pattern seed layer 135 may be disposed in a vertical direction between the second conductive line pattern 131 and the third redistribution insulation layer 115 and may be disposed between the third redistribution insulation layer 115 and the second conductive via pattern 133. The third redistribution pattern seed layer 145 may be disposed in a vertical direction between the third conductive line pattern 141 and the fourth redistribution insulation layer 117 and may be disposed between the fourth redistribution insulation layer 117 and the third conductive via pattern 143.

[0028] In an exemplary embodiment, the first to third redistribution pattern seed layers 125, 135, and 145 may be formed by physical vapor deposition, and the first to third conductive thread patterns 121, 131, and 141 and the first to third conductive via patterns 123, 133, and 143 may be formed by electroless plating. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0029] In an exemplary embodiment, the first to third redistribution pattern seed layers 125, 135, and 145 may be made of copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), or a combination thereof. For example, the first to third redistribution pattern seed layers 125, 135, and 145 may be made of Cu / Ti in which Cu is stacked on Ti or Cu / TiW in which Cu is stacked on TiW. However, exemplary embodiments of the present inventive concept are not limited thereto, and in other exemplary embodiments, the first to third redistribution pattern seed layers 125, 135, and 145 may be made of various different compounds.

[0030] In an exemplary embodiment, the first to third conductive thread patterns 121, 131, and 141 and the first to third conductive via patterns 123, 133, and 143 may include metals such as Cu, Al, W, Ti, Ta, indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or alloys thereof. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0031] In an exemplary embodiment where the first to third conductive thread patterns 121 , 131 , and 141 and the first to third conductive via patterns 123 , 133 , and 143 are made of Cu, at least some portions of the first to third redistribution pattern seed layers 125 , 135 , and 145 may serve as diffusion barriers.

[0032] In an exemplary embodiment, the under bump pad 150 may be disposed in the redistribution insulating layer 110. For example, Figure 1 As shown in the exemplary embodiment of the present invention, the lower bump pad 150 can be provided in the second redistribution insulating layer 113. However, the exemplary embodiments of the present inventive concept are not limited thereto. The external connection bump 400 can be attached to a portion of the lower bump pad 150. The lower bump pad 150 can serve as an under bump metallurgy (UBM) on which the external connection bump 400 is arranged. The semiconductor package 10 according to the exemplary embodiment of the present inventive concept can be electrically connected to a module substrate, a system board, etc. of an electronic product through the external connection bump 400 and mounted on the module substrate, the system board, etc. of the electronic product.

[0033] In an exemplary embodiment, the under bump pad 150 may be made of a metal such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, Ru, or an alloy thereof. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0034] In an exemplary embodiment, the lower bump pad 150 may include a first surface 158 and a second surface 159 opposite to each other. Figure 2 As shown in the exemplary embodiment of FIG, the first surface 158 and / or the second surface 159 of the under bump pad 150 may be flat. For example, the first surface 158 and / or the second surface 159 of the under bump pad 150 may extend substantially in a horizontal direction that is perpendicular to the vertical direction and parallel to the direction in which the redistribution insulating layer 110 extends.

[0035] A portion of the first surface 158 of the lower bump pad 150 may directly contact the external connection bump 400 , and a portion of the second surface 159 of the lower bump pad 150 may contact the first redistribution pattern seed layer 125 .

[0036] like Figure 2 As shown in the exemplary embodiment of , the first surface 158 of the lower bump pad 150 may include a contact portion 158a and a covering portion 158b. The contact portion 158a may be a portion of the first surface 158 of the lower bump pad 150 that is in direct contact with the external connection bump 400, and the covering portion 158b may be a portion of the first surface 158 that surrounds the contact portion 158a and directly contacts the second conductive barrier layer 170 to be described below. The covering portion 158b may not directly contact the external connection bump 400. For example, as Figure 2 As shown in the exemplary embodiment of , the contact portion 158a may be a bottom portion of the lower bump pad 150 in a central portion (e.g., a central portion in a horizontal direction) of the lower bump pad 150, and the covering portion 158b may be provided on a lateral side of the lower bump pad 150 to surround a side surface (e.g., a lateral end portion) of the contact portion 158a. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0037] In an exemplary embodiment, the length of the under-bump pad 150 in the vertical direction may have a generally uniform value. For example, the length of the under-bump pad 150 in the vertical direction may be substantially constant from one lateral edge to an opposite lateral edge along the horizontal direction. In an exemplary embodiment, the length of the under-bump pad 150 in the vertical direction may have a generally uniform value within a range of about 5 μm to about 10 μm.

[0038] like Figure 1 and Figure 2 As shown in the exemplary embodiment of FIG, the redistribution structure 100 may include a first conductive barrier layer 160 surrounding the side surface of the under bump pad 150. For example, the first conductive barrier layer 160 may be disposed between the side surface of the under bump pad 150 and the second redistribution insulating layer 113 (e.g., in a horizontal direction).

[0039] like Figure 3 As shown in the exemplary embodiment of , the first conductive barrier layer 160 may have a ring shape extending along the side surface of the lower bump pad 150. For example, the first conductive barrier layer 160 may contact the side surface (e.g., the outer periphery) of the lower bump pad 150 to surround the side surface of the lower bump pad 150. The first conductive barrier layer 160 may also surround the side surface (e.g., the lateral end) of the second conductive barrier layer 170. For example, as Figure 2As shown in the exemplary embodiment of FIG, the inner surface of the first conductive barrier layer 160 may directly contact the lateral end portion of the second conductive barrier layer 170 .

[0040] In an exemplary embodiment, the length of the first conductive barrier layer 160 in the vertical direction may be substantially the same as the length of the lower bump pad 150 in the vertical direction. For example, in an exemplary embodiment, the length of the first conductive barrier layer 160 in the vertical direction may be substantially the same as the length of the lower bump pad 150 in the vertical direction and may be in a range of about 5 μm to about 10 μm. The vertical direction may be parallel to the thickness direction of the redistribution insulating layer 110 (e.g., a direction extending from the lower surface 119 of the redistribution insulating layer 110 toward the upper surface 118 of the redistribution insulating layer 110).

[0041] In an exemplary embodiment, the thickness (eg, length in the horizontal direction) of the first conductive barrier layer 160 may be in the range of about 0.02 μm to about 0.07 μm. However, exemplary embodiments of the present inventive concept are not limited thereto, and the length of the first conductive barrier layer 160 in the horizontal direction may vary.

[0042] In exemplary embodiments, the first conductive barrier layer 160 may be made of Cu, Ni, Ti, TiW, TiN, Ta, TaN, Cr, Al, or a combination thereof.

[0043] In addition, the material of the first conductive barrier layer 160 may include a material having excellent adhesion to the second redistribution insulating layer 113. For example, in an exemplary embodiment, the adhesion between the material of the first conductive barrier layer 160 and the material of the second redistribution insulating layer 113 may be stronger than the adhesion between the material of the under bump pad 150 and the material of the second redistribution insulating layer 113. For example, in an exemplary embodiment in which the second redistribution insulating layer 113 includes a PID material, the under bump pad 150 may include Cu, and the first conductive barrier layer 160 covering the side surface of the under bump pad 150 may include Ni or Ti.

[0044] In common semiconductor packages, the side surfaces of the underbump pad (e.g., the lateral ends of the underbump pad) may directly contact the redistribution insulation layer. Due to heat generated from the semiconductor package or external stress applied to the semiconductor package, stress tends to concentrate at the portion where the side surfaces of the underbump pad and the redistribution insulation layer contact each other. Such stress can cause cracks to propagate along the side surfaces of the underbump pad, and the underbump pad and the redistribution insulation layer frequently delaminate due to the cracks.

[0045] However, since the semiconductor package 10 according to an exemplary embodiment of the present invention may include the first conductive barrier layer 160 covering the side surface of the lower bump pad 150 and having excellent adhesion to the second redistribution insulation layer 113, the semiconductor package 10 can prevent cracks from propagating along the side surface of the lower bump pad 150 and can prevent peeling of the lower bump pad 150 and the second redistribution insulation layer 113.

[0046] The redistribution structure 100 may include a second conductive barrier layer 170 disposed between the covering portion 158 b of the first surface 158 of the under bump pad 150 and the upper surface of the first redistribution insulation layer 111 (eg, in a vertical direction).

[0047] In exemplary embodiments, the second conductive barrier layer 170 may be made of Cu, Ni, Ti, TiW, TiN, Ta, TaN, Cr, Al, or a combination thereof.

[0048] In an exemplary embodiment, the second conductive barrier layer 170 may have a ring shape that continuously extends along the lateral edge of the lower bump pad 150. The second conductive barrier layer 170 directly contacts the sidewall on the upper surface of the external connection bump 400 and may surround the sidewall on the upper surface of the external connection bump 400. For example, Figure 2 As shown in the exemplary embodiment of , lateral ends of the second conductive barrier layer 170 (eg, lateral ends of the second conductive barrier layer 170 opposite to the lateral ends contacting the first conductive barrier layer 160 ) directly contact sidewalls of upper portions of the external connection bumps 400 .

[0049] In an exemplary embodiment, the surface of the contact portion 158a of the external connection bump 400 that contacts the first surface 158 of the lower bump pad 150 can be substantially coplanar (e.g., in the vertical direction) with the surface (e.g., the upper surface) of the covering portion 158b of the second conductive barrier layer 170 that contacts the first surface 158 of the lower bump pad 150.

[0050] In an exemplary embodiment of the present inventive concept, since the edge portion of the first surface 158 of the lower bump pad 150 of the semiconductor package 10 is covered by the redistribution insulating layer 110, stress concentration at the interface between the lower bump pad 150 and the external connection bump 400 can be reduced. Therefore, since cracks are prevented from forming around the lower bump pad 150, damage to the lower bump pad 150 and the first to third redistribution patterns 120, 130, and 140 can be prevented, and the bonding reliability between the semiconductor package 10 and the module substrate and board-level reliability can be increased.

[0051] Hereinafter, the redistribution structure 100 of the semiconductor package 10 according to the present inventive concept will be described in more detail.

[0052] In exemplary embodiments, the first redistribution insulating layer 111 may include a pad opening 1110 (refer to FIG. 1 ) exposing the lower bump pad 150. Figure 20 The external connection bump 400 is formed to fill the pad opening 111O and may directly contact the lower bump pad 150 exposed through the pad opening 111O.

[0053] In an exemplary embodiment, the contact portion 158 a of the first surface 158 of the lower bump pad 150 may be in direct contact with the external connection bump 400 (e.g., the top surface of the external connection bump 400 ), and a portion of the second surface 159 of the lower bump pad 150 may be in direct contact with the first redistribution pattern seed layer 125 .

[0054] A portion of the external connection bump 400 that fills the pad opening 111O of the first redistribution insulating layer 111 and includes the portion of the external connection bump 400 that contacts the first surface 158a of the lower bump pad 150 may be defined as a first portion of the external connection bump 400. In an exemplary embodiment, the first portion of the external connection bump 400 may have a shape in which its width in the horizontal direction gradually increases from a portion coplanar with the upper surface of the first redistribution insulating layer 111 to a portion coplanar with the lower surface 119 of the redistribution insulating layer 110. For example, the first portion of the external connection bump 400 may have a shape in which its width in the horizontal direction gradually increases in a direction away from the first surface 158 of the lower bump pad 150. Similarly, the pad opening 111O of the first redistribution insulating layer 111 may have a shape in which its width in the horizontal direction gradually increases in a direction away from the first surface 158 of the lower bump pad 150.

[0055] The covering portion 158b of the first surface 158 of the lower bump pad 150 may be covered (eg, in a vertical direction) by the second conductive barrier layer 170. The second conductive barrier layer 170 may be covered (eg, in a vertical direction) by the first redistribution insulating layer 111. Figure 2 As shown in the exemplary embodiment of FIG, a lower surface of the second conductive barrier layer 170 may directly contact an upper surface of the first redistribution insulating layer 111 .

[0056] In an exemplary embodiment, the distance between the second conductive barrier layer 170 and the lower surface 119 of the redistribution insulating layer 110 (e.g., in the vertical direction) may be in the range of about 3 μm to about 20 μm. For example, when the distance between the second conductive barrier layer 170 and the lower surface 119 of the redistribution insulating layer 110 is less than 3 μm, since the lower bump pad 150 is not sufficiently covered by the first redistribution insulating layer 111, the possibility of cracks occurring around the lower bump pad 150 due to stress increases. In addition, when the distance between the second conductive barrier layer 170 and the lower surface 119 of the redistribution insulating layer 110 is greater than 20 μm, the possibility of the pad opening 111O not being sufficiently filled with the external connection bump 400 increases, and the adhesion between the external connection bump 400 and the lower bump pad 150 or between the external connection bump 400 and the sidewall of the pad opening 111O may be reduced.

[0057] In an exemplary embodiment, a first via opening VO1 (refer to FIG. 1 ) exposing a portion of the second surface 159 of the lower bump pad 150 is included. Figure 14 ) may be stacked (e.g., in a vertical direction) on the first redistribution insulating layer 111. The first redistribution pattern seed layer 125 may be formed on a partial portion of the upper surface of the second redistribution insulating layer 113, a sidewall of the first via opening VO1, and a portion of the second surface 159 of the lower bump pad 150 exposed through the first via opening VO1.

[0058] A portion of the first redistribution pattern seed layer 125 can be disposed between the first conductive line pattern 121 and the upper surface of the second redistribution insulation layer 113, and another portion of the first redistribution pattern seed layer 125 can surround the sidewall of the first conductive via pattern 123 and can be disposed between the first conductive via pattern 123 and the second surface 159 of the lower bump pad 150.

[0059] The first conductive line pattern 121 and the first conductive via pattern 123 may be disposed on the first redistribution pattern seed layer 125 (e.g., in a vertical direction). In an exemplary embodiment, the first conductive line pattern 121 and the first conductive via pattern 123 may be formed simultaneously by a plating process and may be integral with each other. The first conductive line pattern 121 may be disposed on a portion of the first redistribution pattern seed layer 125 disposed on the upper surface of the second redistribution insulation layer 113. The first conductive line pattern 121 is also disposed on the first conductive via pattern 123. The first conductive via pattern 123 may cover a portion of the first redistribution pattern seed layer 125 located in the first via opening VO1 and fill the first via opening VO1. The first conductive via pattern 123 may extend in the vertical direction and penetrate the second redistribution insulation layer 113, and may be connected to the first conductive line pattern 121 and the lower bump pad 150, respectively. For example, as Figure 2 As shown in the exemplary embodiment of , the upper surface of the first conductive via pattern 123 can directly contact the lower surface of the first conductive line pattern 121, and the lower surface of the first conductive via pattern 123 can directly contact the first redistribution pattern seed layer 125 for connecting to the lower bump pad 150.

[0060] In an exemplary embodiment, the first conductive via pattern 123 may have a shape in which its width in the horizontal direction gradually increases upward. For example, the first conductive via pattern 123 may have a shape in which its cross-sectional surface area in the horizontal direction gradually increases away from the second surface 159 of the lower bump pad 150 and toward the first conductive thread pattern 121. Similarly, the first via opening VO1 may have a shape in which its width in the horizontal direction gradually increases in a direction away from the second surface 159 of the lower bump pad 150 and toward the first conductive thread pattern 121.

[0061] Including the second via opening VO2 (refer to Figure 16 The third redistribution insulating layer 115, which covers a portion of the first conductive thread pattern 121 and thereby exposes another portion of the first conductive thread pattern 121, may be stacked (e.g., in a vertical direction) on the second redistribution insulating layer 113. The second redistribution pattern seed layer 135 may be disposed on a partial portion of the upper surface of the third redistribution insulating layer 115, the sidewall of the second via opening VO2, and a portion of the upper surface of the first conductive thread pattern 121 exposed through the second via opening VO2. A portion of the second redistribution pattern seed layer 135 may be disposed (e.g., in a vertical direction) between the second conductive thread pattern 131 and the upper surface of the third redistribution insulating layer 115, and another portion of the second redistribution pattern seed layer 135 may surround the sidewall of the second conductive via pattern 133 and may be disposed between the second conductive via pattern 133 and the first conductive thread pattern 121.

[0062] The second conductive via pattern 133 and the second conductive thread pattern 131 may be disposed on the second redistribution pattern seed layer 135 (e.g., in the vertical direction). In an exemplary embodiment, the second conductive via pattern 133 and the second conductive thread pattern 131 may be formed by a plating process and may be integral with each other. The second conductive thread pattern 131 may be disposed on a portion of the second redistribution pattern seed layer 135 that is disposed on the upper surface of the third redistribution insulation layer 115. The second conductive thread pattern 131 is also disposed on the second conductive via pattern 133. The second conductive via pattern 133 may cover a portion of the second redistribution pattern seed layer 135 in the second via opening VO2 and fill the second via opening VO2. The second conductive via pattern 133 may extend in the vertical direction and penetrate the third redistribution insulation layer 115, and may be connected to the second conductive thread pattern 131 and the first conductive thread pattern 121, respectively. For example, as Figure 1 As shown in the exemplary embodiment of , the upper surface of the second conductive via pattern 133 may directly contact the lower surface of the second conductive thread pattern 131 and the lower surface of the second conductive via pattern 133 may directly contact the second redistribution pattern seed layer 135 for connecting to the first conductive thread pattern 121.

[0063] In an exemplary embodiment, the second conductive via pattern 133 may have a shape in which its horizontal cross-sectional surface area gradually increases upward. For example, the second conductive via pattern 133 may have a shape in which its horizontal cross-sectional surface area gradually increases in a direction from the lower surface of the second conductive via pattern 133 toward the second conductive line pattern 131.

[0064] Including the third via opening VO3 (refer to Figure 16 The fourth redistribution insulation layer 117, which covers a portion of the second conductive thread pattern 131 and thereby exposes another portion of the second conductive thread pattern 131, may be stacked (e.g., in a vertical direction) on the third redistribution insulation layer 115. The third redistribution pattern seed layer 145 may be disposed on a partial portion of the upper surface of the fourth redistribution insulation layer 117, the sidewall of the third via opening VO3, and a portion of the upper surface of the second conductive thread pattern 131 exposed through the third via opening VO3. A portion of the third redistribution pattern seed layer 145 may be disposed (e.g., in a vertical direction) between the third conductive thread pattern 141 and the upper surface of the fourth redistribution insulation layer 117, and another portion of the third redistribution pattern seed layer 145 may surround the sidewall of the third conductive via pattern 143 and may be disposed between the third conductive via pattern 143 and the second conductive thread pattern 131.

[0065] The third conductive via pattern 143 and the third conductive thread pattern 141 may be disposed on the third redistribution pattern seed layer 145. In an exemplary embodiment, the third conductive via pattern 143 and the third conductive thread pattern 141 may be formed by a plating process and may be integral with each other. The third conductive thread pattern 141 may be disposed on a portion of the third redistribution pattern seed layer 145 that is disposed on the upper surface of the fourth redistribution insulation layer 117 and on the third conductive via pattern 143 (e.g., the upper surface of the third conductive via pattern 143). The third conductive via pattern 143 may cover a portion of the third redistribution pattern seed layer 145 in the third via opening VO3, thereby filling the third via opening VO3. The third conductive via pattern 143 may extend in the vertical direction and penetrate the fourth redistribution insulation layer 117, and may be connected to the third conductive thread pattern 141 and the second conductive thread pattern 131, respectively. For example, as Figure 1 As shown in the exemplary embodiment of , the upper surface of the third conductive via pattern 143 may directly contact the lower surface of the third conductive thread pattern 141 and the lower surface of the third conductive via pattern 143 may directly contact the third redistribution pattern seed layer 145 for connecting to the second conductive thread pattern 131.

[0066] In an exemplary embodiment, the third conductive via pattern 143 may have a shape in which its horizontal cross-sectional surface area gradually increases upward. For example, the third conductive via pattern 143 may have a shape in which its horizontal cross-sectional surface area gradually increases from the lower surface of the third conductive via pattern 143 to the third conductive line pattern 141.

[0067] At least partial portions of the third conductive wire patterns 141 of the third redistribution pattern 140 may be disposed under the semiconductor chip 200 and may serve as pads to which the chip connection terminals 230 are attached.

[0068] Figure 1 1 , the redistribution structure 100 is shown to include first to fourth redistribution insulation layers 111, 113, 115, and 117, first to third conductive line patterns 121, 131, and 141, and first to third conductive via patterns 123, 133, and 143. However, exemplary embodiments of the present inventive concept are not limited thereto. For example, in other exemplary embodiments, the number of redistribution insulation layers, conductive line patterns, and conductive via patterns may be modified in various ways depending on the design of circuit wiring in the redistribution structure 100.

[0069] The semiconductor chip 200 may be attached to the redistribution structure 100. For example, in an exemplary embodiment, the semiconductor chip 200 may be mounted on the redistribution structure 100 in a flip-chip method.

[0070] The semiconductor chip 200 may include a memory chip or a logic chip. Examples of memory chips may include volatile memory chips (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or non-volatile memory chips (such as phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM) or resistive random access memory (RRAM)). In an exemplary embodiment, the memory chip may include a high bandwidth memory (HBM) DRAM semiconductor chip. In addition, the logic chip may include, for example, a microprocessor, an analog device, or a digital signal processor. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0071] The semiconductor chip 200 may include a semiconductor substrate 210 and a chip pad 220 disposed on one side of the semiconductor substrate 210 .

[0072] In an exemplary embodiment, the semiconductor substrate 210 may include silicon (Si). Alternatively, the semiconductor substrate 210 may include a semiconductor element (such as germanium (Ge)) or a compound semiconductor (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). The semiconductor substrate 210 may include an active surface and an inactive surface opposite to the active surface. In an exemplary embodiment, the active surface of the semiconductor substrate 210 may face the redistribution structure 100. Semiconductor devices including a plurality of individual devices of various types may be formed on the active surface of the semiconductor substrate 210 within the semiconductor chip 200.

[0073] In an exemplary embodiment, the semiconductor package 10 may be a fan-out structure semiconductor package, and the footprint occupied by the semiconductor chip 200 may be smaller than the footprint of the redistribution structure 100. In this embodiment, at least one of the plurality of lower bump pads 150 may be disposed at a position spaced outward from a side surface of the semiconductor chip 200 (e.g., a lateral side edge of the semiconductor chip 200). For example, at least one of the external connection bumps 400 contacting the lower bump pad 150 may not overlap the semiconductor chip 200 in a vertical direction.

[0074] The chip connection terminal 230 may be disposed (e.g., vertically) between the chip pad 220 of the semiconductor chip 200 and the third conductive line pattern 141. The chip connection terminal 230 may electrically connect the chip pad 220 of the semiconductor chip 200 to the third conductive line pattern 141. In an exemplary embodiment, the chip connection terminal 230 may include at least one of a pillar structure, a solder bump, a solder ball, and a solder layer. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0075] The semiconductor chip 200 can be provided with at least one of a control signal, a power signal and a ground signal for the operation of the semiconductor chip 200 or a data signal to be stored in the semiconductor chip 200 from the outside through the chip connection terminal 230, the first to third redistribution patterns 120, 130 and 140, the lower bump pad 150 and the external connection bump 400, or the data stored in the semiconductor chip 200 can be provided to the outside through the chip connection terminal 230, the first to third redistribution patterns 120, 130 and 140, the lower bump pad 150 and the external connection bump 400.

[0076] An underfill material layer 240 covering the side surfaces of the chip connection terminals 230 and the third conductive line patterns 141 may be provided between the semiconductor chip 200 and the redistribution structure 100. In an exemplary embodiment, the underfill material layer 240 may be made of an epoxy resin formed by a capillary underfill method. In an exemplary embodiment, the underfill material layer 240 may include a non-conductive film (NCF). However, exemplary embodiments of the present inventive concept are not limited thereto.

[0077] like Figure 1 As shown in the exemplary embodiment of FIG, the mold layer 300 may be provided on the upper surface 118 of the redistribution insulating layer 110, thereby covering at least a portion of the semiconductor chip 200. In the exemplary embodiment, the mold layer 300 may be made of epoxy molding compound (EMC). However, the exemplary embodiments of the present inventive concept are not limited thereto, and the mold layer 300 may be made of various other materials (such as epoxy-based materials, thermosetting materials, thermoplastic materials, UV-curable materials, etc.).

[0078] like Figure 1 As shown in the exemplary embodiment of the present invention, the mold layer 300 may cover a portion of the upper surface 118 of the redistribution insulation layer 110 and the lateral side surfaces of the semiconductor chip 200. However, the mold layer 300 may expose the upper surface of the semiconductor chip 200 to the outside. In an exemplary embodiment, the upper surface of the mold layer 300 may be coplanar with the upper surface of the semiconductor chip 200. For example, the upper surface of the mold layer 300 may have the same height as the upper surface of the semiconductor chip 200 (for example, the distance from the lower surface 119 of the redistribution insulation layer 110 in the vertical direction). In this embodiment, the upper surface of the semiconductor chip 200 may be exposed to the outside. Since the upper surface of the semiconductor chip 200 is exposed to the outside, the heat dissipation performance of the semiconductor package 10 can be improved. However, exemplary embodiments of the present inventive concept are not limited thereto. For example, in another exemplary embodiment, the mold layer 300 may cover both the lateral side surfaces and the upper surface of the semiconductor chip 200.

[0079] Figure 4is a cross-sectional view illustrating a semiconductor module 1 according to an exemplary embodiment of the present inventive concept. Figure 5 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 4 Magnified view of region V.

[0080] Reference Figure 4 and Figure 5 In an exemplary embodiment, the semiconductor module 1 may include a module substrate 500 and a semiconductor package 10 mounted on the module substrate 500 .

[0081] The module substrate 500 may include a main body portion 510 and wiring 520. A portion of the wiring 520 may be used as a substrate pad on which the external connection bump 400 is mounted. Figure 5 As shown in the exemplary embodiment of FIG5 , the bottom surface of the external connection bump 400 may be directly mounted on the top surface of the wiring 520. In an exemplary embodiment, the module substrate 500 may include a printed circuit board (PCB).

[0082] In an exemplary embodiment where the module substrate 500 includes a PCB, the main body 510 of the module substrate 500 can be formed into a thin shape by compressing a polymer material (such as a thermosetting resin), an epoxy resin (such as flame retardant 4 (FR-4), bismaleimide triazine (BT), ajinomoto build-up film (ABF), etc.), or a phenolic resin to a certain thickness. Wiring 520, which serves as a transmission path for electrical signals, can be formed by applying copper foil on the surface of the main body 510 and patterning it.

[0083] exist Figure 4 In the exemplary embodiment of the present invention, the module substrate 500 has been illustrated as a single-layer PCB on which the wiring 520 is formed only on one surface (e.g., the upper surface) of the main body portion 510 of the module substrate 500. However, the module substrate 500 may be implemented using a double-layer PCB on which the wiring 520 is formed on both the upper and lower surfaces of the main body portion 510 of the module substrate 500. However, exemplary embodiments of the present inventive concept are not limited thereto, and in other exemplary embodiments, the module substrate 500 may include various different structures and / or materials.

[0084] like Figure 4As shown in the exemplary embodiment of FIG, the semiconductor package 10 may be mounted on the upper surface of the module substrate 500. The external connection bumps 400 may be disposed (e.g., in a vertical direction) between the wiring 520 and the lower bump pad 150 on the upper surface of the main body portion 510 of the module substrate 500. The external connection bumps 400 may contact the wiring 520 and the lower bump pad 150 of the module substrate 500, respectively, thereby electrically connecting the wiring 520 of the module substrate 500 to the lower bump pad 150. For example, as Figure 4 and Figure 5 As shown in the exemplary embodiment of FIG, the upper surface of the external connection bump 400 may directly contact the lower surface of the lower bump pad 150, and the lower surface of the external connection bump 400 may directly contact the upper surface of the wiring 520. An underfill layer 410 covering the side surfaces of the external connection bump 400 may be provided between the semiconductor package 10 and the module substrate 500. However, exemplary embodiments of the present inventive concept are not limited thereto, and the underfill layer 410 may be omitted in some exemplary embodiments.

[0085] In common semiconductor packages, a portion of the lower surface of the underbump pad, to which the external connection bumps are attached, is exposed by the adjacent redistribution insulation layer, and the side surface of the underbump pad may directly contact the redistribution insulation layer. Due to heat generated from the semiconductor package and / or the shrinkage or relaxation of the solder balls, stress tends to concentrate at the contact portion of the underbump pad and the redistribution insulation layer. Such stress can cause cracks to propagate along the side surface of the underbump pad, and as a result, the underbump pad and the redistribution insulation layer are frequently delaminated by cracks.

[0086] However, in an exemplary embodiment of the present inventive concept, the semiconductor module 1 includes the first conductive barrier layer 160, which covers the side surface of the lower bump pad 150 and has excellent adhesion to the second redistribution insulating layer 113. Therefore, the semiconductor module 1 can prevent cracks from propagating along the side surface of the lower bump pad 150 and can prevent delamination of the lower bump pad 150 and the second redistribution insulating layer 113.

[0087] In an exemplary embodiment of the present inventive concept, since the edge portion of the first surface 158 of the lower bump pad 150 of the semiconductor module 1 is covered by the redistribution insulating layer 110, stress concentration at the interface between the lower bump pad 150 and the external connection bump 400 can be reduced. Therefore, since cracks are prevented from forming around the lower bump pad 150, damage to the lower bump pad 150 and the first to third redistribution patterns 120, 130, and 140 can be prevented, and the bonding reliability between the semiconductor package 10 and the module substrate 500 and board-level reliability can be increased.

[0088] Figure 6is a cross-sectional view illustrating a semiconductor package 20 according to an exemplary embodiment of the inventive concept. Figure 7 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 6 In addition to the structure of the lower bump pad 150a, Figure 6 and Figure 7 The semiconductor package 20 shown in the exemplary embodiment is similar to the semiconductor package 20 shown in FIG. Figures 1 to 3 Therefore, for the convenience of description, the foregoing description of substantially similar or identical elements will be briefly mentioned or omitted, and the following description will focus on the semiconductor package 10 described in the exemplary embodiment of FIG. Figures 1 to 3 The semiconductor package 10 is different from the exemplary embodiment described in FIG.

[0089] Reference Figure 6 and Figure 7 In an exemplary embodiment, the lower bump pad 150a may include a first conductive layer 151 that is in direct contact with the external connection bump 400, a second conductive layer 153 that is in direct contact with the first conductive via pattern 123, and a diffusion barrier layer 152 arranged between the first conductive layer 151 and the second conductive layer 153 (e.g., in a vertical direction).

[0090] In exemplary embodiments, the first and second conductive layers 151 and 153 may include a metal such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, Ru, etc., or an alloy thereof.

[0091] In an exemplary embodiment, the first conductive layer 151 and the second conductive layer 153 may include the same material as each other. For example, the first conductive layer 151 and the second conductive layer 153 may both include Cu.

[0092] In an exemplary embodiment, the first conductive layer 151 and the second conductive layer 153 may each have an overall uniform thickness. For example, the lengths of the first conductive layer 151 and the second conductive layer 153 in the vertical direction may be constant. Figure 6 and Figure 7 As shown in the exemplary embodiment of FIG, the thickness of the first conductive layer 151 may be greater than the thickness of the second conductive layer 153.

[0093] The diffusion barrier layer 152 may be disposed (e.g., in a vertical direction) between the first conductive layer 151 and the second conductive layer 153. The first conductive layer 151 and the second conductive layer 153 may be separated from each other by the diffusion barrier layer 152. The diffusion barrier layer 152 may be configured to prevent diffusion of material between the first conductive layer 151 and the second conductive layer 153.

[0094] In an exemplary embodiment, the diffusion barrier layer 152 may be made of Ni, Ti, TiN, Ta, TaN, or a combination thereof. The diffusion barrier layer 152 may be configured to suppress an increase in resistance and current leakage between the second conductive layer 153 and the first conductive via pattern 123 by preventing the material constituting the second conductive layer 153 from diffusing toward the external connection bump 400.

[0095] In exemplary embodiments, the length of the diffusion barrier layer 152 in the horizontal direction may be substantially the same as the lengths of the first and second conductive layers 151 and 153 in the horizontal direction.

[0096] The side surface of the diffusion barrier layer 152, the side surface of the first conductive layer 151, and the side surface of the second conductive layer 153 may constitute the side surface of the lower bump pad 150a. Figure 6 and Figure 7 As shown in the exemplary embodiment of FIG. 5 , side surfaces (eg, lateral ends) of the diffusion barrier layer 152 , the first conductive layer 151 , and the second conductive layer 153 may be coplanar with each other.

[0097] In an exemplary embodiment, a surface (eg, a top surface) of the external connection bump 400 that directly contacts the first conductive layer 151 may be substantially coplanar (eg, in a vertical direction) with a surface (eg, a top surface) of the second conductive barrier layer 170 that directly contacts the first conductive layer 151. Figure 7 As shown in the exemplary embodiment of FIG, the surface (e.g., bottom surface) of the first conductive layer 151 that directly contacts the external connection bump 400 may be flat (e.g., substantially extending in the horizontal direction). In the exemplary embodiment, the distance in the vertical direction between the portion of the first conductive layer 151 that directly contacts the external connection bump 400 and the lower surface 119 of the redistribution insulation layer 110 may be as previously described. Figures 1 to 3 Exemplary embodiments are described as being in the range of about 3 μm to about 20 μm.

[0098] In an exemplary embodiment, the first conductive barrier layer 160 may surround the lower bump pad 150a and the second conductive barrier layer 170. For example, the first conductive barrier layer 160 may contact the side surface (e.g., lateral end) of the first conductive layer 151, the side surface (e.g., lateral end) of the second conductive layer 153, the side surface (e.g., lateral end) of the diffusion barrier layer 152, and the side surface (e.g., lateral end) of the second conductive barrier layer 170, thereby surrounding the first conductive layer 151, the second conductive layer 153, the diffusion barrier layer 152, and the second conductive barrier layer 170.

[0099] The length of the first conductive barrier layer 160 in the vertical direction may be substantially the same as the sum of the lengths of the first conductive layer 151, the second conductive layer 153, the diffusion barrier layer 152, and the second conductive barrier layer 170. For example, in an exemplary embodiment, the length of the first conductive barrier layer 160 in the vertical direction may be about 5 μm to about 10 μm.

[0100] Figure 8 1 is a cross-sectional view illustrating a semiconductor package 30 according to an exemplary embodiment of the present inventive concept. For ease of description, the foregoing descriptions of substantially similar or identical elements previously described are briefly mentioned or omitted, and the following description will focus on the components related to FIG. Figures 1 to 3 The semiconductor package 10 is different from the exemplary embodiment described in FIG.

[0101] Reference Figure 8 In an exemplary embodiment, the semiconductor package 30 may include a plurality of semiconductor chips 200. For example, Figure 8 As shown in the exemplary embodiment of FIG, the semiconductor package 30 may include two semiconductor chips 200. However, exemplary embodiments of the present inventive concept are not limited thereto, and in other exemplary embodiments, the semiconductor package 30 may include three or more semiconductor chips 200. The semiconductor chips 200 included in the semiconductor package 30 may be semiconductor chips of the same or different types.

[0102] The semiconductor package 30 may be a system-in-package (SIP) in which heterogeneous types of semiconductor chips 200 are electrically connected to each other, thus operating as one system.

[0103] In an exemplary embodiment, the upper surface of the semiconductor chip 200 may be substantially coplanar (eg, in a vertical direction) with the upper surface of the mold layer 300. For example, Figure 8 As shown in the exemplary embodiment of FIG. 5 , the mold layer 300 surrounds side surfaces (eg, lateral ends) of the semiconductor chip 200 , but may not surround an upper surface of the semiconductor chip 200 .

[0104] In an exemplary embodiment, the heat dissipation member 550 may be attached to the upper surface of the semiconductor chip 200 and the upper surface of the mold layer 300. In an exemplary embodiment, the heat dissipation member 550 may include a heat sink or a heat sink. For example, the heat sink or the heat sink may have a concave-convex structure in which concave and convex portions are repeated to increase their surface area. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0105] like Figure 8As shown in the exemplary embodiment of , the adhesive member 560 may be disposed under the heat dissipation member 550. For example, the adhesive member 560 may be disposed between the lower surface of the heat dissipation member 550 and the upper surfaces of the semiconductor chip 200 and the mold layer 300 to be attached thereto.

[0106] In an exemplary embodiment, the adhesive member 560 may include a thermal interface material (TIM). For example, the TIM may include mineral oil, grease, caulk putty, phase change gel, phase change material pad, or particle-filled epoxy. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0107] In an exemplary embodiment, the adhesive member 560 may further include a non-conductive film (NCF). The adhesive member 560 may include an insulating polymer film. However, exemplary embodiments of the present inventive concept are not limited thereto. The adhesive member 560 may include a film having adhesive properties. For example, the adhesive member 560 may include a double-sided adhesive film.

[0108] Figures 9 to 23 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package 10 according to an exemplary embodiment of the present inventive concept. Figures 9 to 23 , the fabrication will be described in more detail Figure 1 An exemplary embodiment of a method of manufacturing a semiconductor package 10 is provided.

[0109] Reference Figure 9 The method of manufacturing a semiconductor package 10 according to the inventive concept may include forming a first redistribution insulating layer 111 on a carrier substrate 310 to which a release film 311 is attached. Figure 9 As shown in the exemplary embodiment of FIG, the release film 311 and the first redistribution insulation layer 111 may be sequentially disposed on the carrier substrate 310 in a vertical direction.

[0110] In an exemplary embodiment, the carrier substrate 310 may be made of any material that is stable to a baking process, an etching process, and the like. In an embodiment where the carrier substrate 310 is separated and removed by laser ablation in a subsequent process, the carrier substrate 310 may include a translucent substrate. In an embodiment where the carrier substrate 310 is separated and removed by heating in a subsequent process, the carrier substrate 310 may include a heat-resistant substrate.

[0111] In an exemplary embodiment, the carrier substrate 310 may include a glass substrate. Alternatively, in another exemplary embodiment, the carrier substrate 310 may be made of a heat-resistant organic polymer material (such as at least one compound selected from polyimide (PI), polyetheretherketone (PEEK), polyethersulfone (PES), polyphenylene sulfide (PPS), etc.). However, exemplary embodiments of the present inventive concept are not limited thereto.

[0112] In an exemplary embodiment, the release film 311 may include a laser-reactive layer capable of allowing the carrier substrate 310 to be separated by vaporization in response to irradiation with a laser. Alternatively, the release film 311 may include a carbon-based material layer. For example, the release film 311 may include an amorphous carbon layer (ACL). However, exemplary embodiments of the present inventive concept are not limited thereto.

[0113] Reference Figure 10 In an exemplary embodiment, a method of manufacturing a semiconductor package 10 according to the present inventive concept may include forming a first preliminary conductive barrier layer 170a and a lower bump pad 150 on a first redistribution insulating layer 111. For example, Figure 10 As shown in the exemplary embodiment of FIG. 2 , the first preliminary conductive barrier layer 170 a and the under bump pad 150 may be continuously disposed on the first redistribution insulating layer 111 (eg, in a vertical direction).

[0114] In an exemplary embodiment, the first preliminary conductive barrier layer 170a may be formed by physical vapor deposition. The first preliminary conductive barrier layer 170a may conformally extend on the upper surface of the first redistribution insulating layer 111. The first preliminary conductive barrier layer 170a may form a second conductive barrier layer 170 (see FIG. 1 ) to be described below. Figure 11 ).

[0115] After forming the first preliminary conductive barrier layer 170a described above, a mask pattern MP including a mask opening MO may be formed on the first preliminary conductive barrier layer 170a. The mask opening MO of the mask pattern MP exposes a portion of the first preliminary conductive barrier layer 170a and may define an area where the under bump pad 150 is formed in a subsequent process.

[0116] Then, the under bump pad 150 may be formed on a portion of the first preliminary conductive barrier layer 170a exposed by the mask opening MO of the mask pattern MP after forming the mask pattern MP. In exemplary embodiments, the under bump pad 150 may be formed through a plating process using the first preliminary conductive barrier layer 170a as a seed.

[0117] Reference Figure 11 According to an exemplary embodiment, a method of manufacturing the semiconductor package 10 according to the present inventive concept may include removing the mask pattern MP and removing the portion of the first preliminary conductive barrier layer 170 a exposed to the outside from the removal of the mask pattern MP.

[0118] In an exemplary embodiment, a portion of the first preliminary conductive barrier layer 170 a exposed to the outside as the mask pattern MP is removed may be removed in the same process. The first preliminary conductive barrier layer 170 a disposed under the under bump pad 150 may remain to form the second conductive barrier layer 170 .

[0119] Reference Figure 12 In an exemplary embodiment, a method of manufacturing a semiconductor package 10 according to the present inventive concept may include forming a second preliminary conductive barrier layer 160 a .

[0120] In an exemplary embodiment, the second preliminary conductive barrier layer 160a may be formed by physical vapor deposition. However, exemplary embodiments of the present inventive concept are not limited thereto. The second preliminary conductive barrier layer 160a may conformally extend over a portion of the upper surface of the first redistribution insulating layer 111, the side surfaces (e.g., lateral ends) of the second conductive barrier layer 170, and the side and upper surfaces of the lower bump pad 150. The second preliminary conductive barrier layer 160a may form the first conductive barrier layer 160.

[0121] In an exemplary embodiment, the second initial conductive barrier layer 160a may extend to a thickness in a range of about 0.05 μm to about 0.10 μm over a portion of the upper surface of the first redistribution insulating layer 111, side surfaces (e.g., lateral ends) of the second conductive barrier layer 170, and side and upper surfaces of the lower bump pad 150.

[0122] Reference Figure 13 In an exemplary embodiment, the method of manufacturing the semiconductor package 10 according to the present inventive concept may include removing a portion of the second preliminary conductive barrier layer 160a. For example, Figure 13 As shown in the exemplary embodiment of FIG. 5 , a portion of the second preliminary conductive barrier layer 160 a disposed on the upper surface of the first redistribution insulating layer 111 and the upper surface of the lower bump pad 150 may be removed.

[0123] In an exemplary embodiment, a portion of the second preliminary conductive barrier layer 160a may be removed by wet etching. For example, a portion of the second preliminary conductive barrier layer 160a disposed on the upper surface of the first redistribution insulating layer 111 and the upper surface of the lower bump pad 150 may be removed by a chemical reaction of an etching solution. Thus, the upper surface of the first redistribution insulating layer 111 and the upper surface of the lower bump pad 150 may be exposed.

[0124] However, exemplary embodiments of the present inventive concept are not limited thereto. For example, in another exemplary embodiment, a portion of the second preliminary conductive barrier layer 160a disposed on the upper surface of the first redistribution insulating layer 111 and the upper surface of the lower bump pad 150 may be removed by a dry etching process. For example, the second preliminary conductive barrier layer 160a located on the upper surface of the first redistribution insulating layer 111 and the upper surface of the lower bump pad 150 may be removed by a chemical and / or physical reaction of an etching gas in a plasma state.

[0125] In an exemplary embodiment, the second preliminary conductive barrier layer 160a located on the side surface of the lower bump pad 150 may not be etched. The second preliminary conductive barrier layer 160a located on the side surface of the lower bump pad 150 may be the first conductive barrier layer 160 described above. However, exemplary embodiments of the present inventive concept are not limited thereto. In an exemplary embodiment, a partial portion of the second preliminary conductive barrier layer 160a located on the side surface of the lower bump pad 150 may be removed by an etching process. For example, the partial portion of the second preliminary conductive barrier layer 160a located on the side surface of the lower bump pad 150 may be removed by an etching process, thereby being formed to a thickness in the range of approximately 0.02 μm to approximately 0.07 μm.

[0126] In an exemplary embodiment, the first conductive barrier layer 160 may be formed in a ring shape extending along the side surface of the lower bump pad 150. For example, the first conductive barrier layer 160 may contact the side surface of the lower bump pad 150 and the side surface of the second conductive barrier layer 170 to surround the lower bump pad 150 and the second conductive barrier layer 170.

[0127] Reference Figure 14 In an exemplary embodiment, a method of manufacturing a semiconductor package 10 according to the present inventive concept may include forming a second redistribution insulating layer 113 including a first via opening VO1 exposing a portion of the lower bump pad 150 .

[0128] In an exemplary embodiment, in forming the second redistribution insulating layer 113, the first via opening VO1 may be formed by forming an insulating material film covering the lower bump pad 150 and the first redistribution insulating layer 111 and performing an exposure process and a development process to remove a portion of the insulating material film. Figure 2 ) may be exposed through the first via opening VO1.

[0129] In an exemplary embodiment, a reactive ion etching (RIE) process using plasma, laser drilling, or the like may be performed to form the first via opening VO1. However, exemplary embodiments of the present inventive concept are not limited thereto. The first via opening VO1 may have a shape in which a cross-sectional surface area thereof in a horizontal direction gradually increases upward in a direction away from the second surface 159 of the lower bump pad 150.

[0130] Reference Figure 15 In an exemplary embodiment, a method of manufacturing a semiconductor package 10 according to the present inventive concept may include: Figure 14 A first redistribution pattern seed layer 125 , a first conductive line pattern 121 , and a first conductive via pattern 123 are formed on the structure shown in the exemplary embodiment of FIG.

[0131] In an exemplary embodiment, the first redistribution pattern seed layer 125 may be formed to cover an upper surface of the second redistribution insulation layer 113, an inner wall of the second redistribution insulation layer 113 provided by the first via opening VO1, and a second surface 159 of the lower bump pad 150 (refer to FIG. Figure 2 ) is exposed through the first via opening VO1.

[0132] In an exemplary embodiment, the first conductive thread pattern 121 may extend along the upper surface of the second redistribution insulation layer 113 , and the first conductive via pattern 123 may fill the first via opening VO1 . The first redistribution pattern seed layer 125 , the first conductive thread pattern 121 , and the first conductive via pattern 123 may constitute the first redistribution pattern 120 .

[0133] Reference Figure 16 According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor package 10 may include: Figure 14 and Figure 15 The exemplary embodiments provided herein describe substantially the same or similar processes as those described in Figure 15 A third redistribution insulation layer 115 including second via openings VO2 , a second redistribution pattern 130 , a fourth redistribution insulation layer 117 including third via openings VO3 , and a third redistribution pattern 140 are sequentially formed on the structure shown in the exemplary embodiment.

[0134] In an exemplary embodiment, the second redistribution pattern seed layer 135 may be formed to cover the upper surface of the third redistribution insulation layer 115, the inner wall of the third redistribution insulation layer 115 provided by the second via opening VO2, and a portion of the first conductive thread pattern 121 exposed by the second via opening VO2. The second conductive thread pattern 131 may extend along the upper surface of the third redistribution insulation layer 115, and the second conductive via pattern 133 may fill the second via opening VO2. The second redistribution pattern seed layer 135, the second conductive thread pattern 131, and the second conductive via pattern 133 may constitute the second redistribution pattern 130.

[0135] The third redistribution pattern seed layer 145 may be formed to cover the upper surface of the fourth redistribution insulation layer 117 , inner walls of the fourth redistribution insulation layer 117 provided by the third via opening VO3 , and a portion of the second conductive wire pattern 131 exposed through the third via opening VO3 .

[0136] In an exemplary embodiment, the third conductive thread pattern 141 may extend along the upper surface of the fourth redistribution insulation layer 117, and the third conductive via pattern 143 may fill the third via opening VO3. The third redistribution pattern seed layer 145, the third conductive thread pattern 141, and the third conductive via pattern 143 may constitute a third redistribution pattern 140.

[0137] Reference Figure 17 According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor package 10 may include attaching a semiconductor chip 200 to Figure 16 The chip pad 220 of the semiconductor chip 200 may be connected to the third conductive line pattern 141 through the chip connection terminal 230. For example, the chip pad 220 of the semiconductor chip 200 may be electrically connected to the third conductive line pattern 141 of the third redistribution pattern 140 through the chip connection terminal 230.

[0138] The semiconductor chip 200 may be electrically connected to the third conductive line pattern 141 and the semiconductor chip 200 may be attached to form a redistribution structure 100 (see Figure 22 ) is formed on the element 110 and then forms an underfill material layer 240 filling the space (e.g., in the vertical direction) between the semiconductor chip 200 and the upper surface 118 of the redistribution insulation layer 110. The underfill material layer 240 may cover the side surfaces of the chip connection terminals 230. In an exemplary embodiment, the underfill material layer 240 may be formed by a capillary underfill method. In an exemplary embodiment, the underfill material layer 240 may be formed by attaching an NCF to the chip pad 220 of the semiconductor chip 200 and then attaching the semiconductor chip 200 to the upper surface 118 of the redistribution insulation layer 110. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0139] Reference Figure 18 In an exemplary embodiment, a method of manufacturing a semiconductor package 10 according to the present inventive concept may include forming a mold layer 300 for molding the semiconductor chip 200. The mold layer 300 covers side surfaces (e.g., lateral side surfaces) of the semiconductor chip 200 and may expose the upper surface of the semiconductor chip 200. The mold layer 300 may also cover a portion of the upper surface 118 of the redistribution insulation layer 110 and side surfaces of the underfill material layer 240.

[0140] However, exemplary embodiments of the present inventive concept are not limited thereto. For example, in another exemplary embodiment, the mold layer 300 may be formed to further cover the upper surface of the semiconductor chip 200. In this exemplary embodiment, the semiconductor chip 200 may not be exposed to the outside.

[0141] Reference Figure 19 In an exemplary embodiment, the method of manufacturing the semiconductor package 10 according to the present inventive concept may include removing the carrier substrate 310. In an exemplary embodiment, the carrier substrate 310 to which the release film 311 is attached may be Figure 18For example, to separate the carrier substrate 310, the release film 311 may be irradiated with laser or heat. After the carrier substrate 310 is separated, the first redistribution insulating layer 111 may be exposed.

[0142] Reference Figure 20 According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor package 10 may include: Figure 19 The structure shown in the exemplary embodiment is reversed, and then a portion of the first redistribution insulating layer 111 is removed to form a pad opening 111O exposing the second conductive barrier layer 170 .

[0143] In exemplary embodiments, the pad opening 1110 may be formed by performing an RIE process using plasma, laser drilling, etc. However, exemplary embodiments of the inventive concept are not limited thereto.

[0144] In an exemplary embodiment, the pad opening 1110 may have a shape in which its width in the horizontal direction gradually increases upward. For example, the pad opening 1110 may have a width that increases in the horizontal direction in a direction away from the lower bump pad 150. Figure 20 As shown in the exemplary embodiment of FIG, the inner wall of the first redistribution insulating layer 111 provided by the pad opening 111O may have an inclined sidewall portion. In the exemplary embodiment, the angle formed by the inclined sidewall portion and the lower surface of the first redistribution insulating layer 111 may be in a range of greater than about 65 degrees to less than about 90 degrees.

[0145] Reference Figure 21 In an exemplary embodiment, a method of manufacturing a semiconductor package 10 according to the present inventive concept may include removing a portion of the second conductive barrier layer 170 exposed through the pad opening 1110. As a portion of the second conductive barrier layer 170 is removed, the contact portion 158a of the first surface 158 of the under bump pad 150 may be exposed through the pad opening 1110.

[0146] In an exemplary embodiment, a wet etching process may be performed to remove the portion of the second conductive barrier layer 170 exposed by the pad opening 1110. However, exemplary embodiments of the present inventive concept are not limited thereto. The portion of the second conductive barrier layer 170 covered by the first redistribution insulating layer 111 may remain.

[0147] In exemplary embodiments, as described above, the first to fourth redistribution insulation layers 111 , 113 , 115 , and 117 , the first to third redistribution patterns 120 , 130 , and 140 , the under bump pad 150 , the first conductive barrier layer 160 , and the second conductive barrier layer 170 may form the redistribution structure 100 .

[0148] Reference Figure 22 In an exemplary embodiment, a method of manufacturing a semiconductor package 10 according to the present inventive concept may include attaching an external connection bump 400 to a lower bump pad 150. For example, Figure 22 As shown in the exemplary embodiment of FIG, the external connection bump 400 may include a plurality of external connection bumps attached to the plurality of lower bump pads 150. The external connection bump 400 may be formed to fill the pad opening 111O in the first redistribution insulating layer 111, and the first portion may directly contact the first surface 158 of the lower bump pad 150 exposed through the pad opening 111O. In an exemplary embodiment, the external connection bump 400 may include a solder ball or a solder bump. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0149] In an exemplary embodiment, arranging solder balls on the first surface 158 of the lower bump pad 150 exposed by the pad opening 1110 may be performed by a solder ball attaching process. Forming the external connection bump 400 bonded to the lower bump pad 150 may then be performed by melting the solder balls by a reflow process.

[0150] Reference Figure 23 In an exemplary embodiment, a method of manufacturing a semiconductor package 10 according to the present inventive concept may include cutting along scribe lines SL. Figure 22 The structure shown in the exemplary embodiment of FIG. Figure 1 As shown in the exemplary embodiment of FIG. 1 , a customized semiconductor package 10 may be formed by a sawing process.

[0151] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor package, comprising: semiconductor chips; A redistribution insulating layer having a first opening; an external connection bump including a first portion filling the first opening; a lower bump pad including a first surface and a second surface opposite to the first surface, the first surface including a contact portion directly contacting a first portion of the external connection bump and a covering portion surrounding a side surface of the contact portion; a first conductive barrier layer surrounding a side surface of the lower bump pad and disposed between the lower bump pad and the redistribution insulating layer, wherein the first conductive barrier layer exposes the second surface of the lower bump pad; as well as The redistribution pattern directly contacts the second surface of the under bump pad and is configured to electrically connect the under bump pad to the semiconductor chip.

2. The semiconductor package according to claim 1, wherein The length of the lower bump pad in the vertical direction is substantially the same as the length of the first conductive barrier layer in the vertical direction.

3. The semiconductor package according to claim 2, wherein A length of the under bump pad in a vertical direction and a length of the first conductive barrier layer in a vertical direction are in a range of 5 μm to 10 μm.

4. The semiconductor package according to claim 1, wherein: The underbump pad comprises copper; and The first conductive barrier layer includes at least one selected from nickel and titanium. 5 . The semiconductor package of claim 1 , further comprising a second conductive barrier layer disposed on a covering portion of the lower bump pad. The semiconductor package according to claim 5 , wherein: The second conductive barrier layer surrounds sidewalls of the external connection bump.

7. The semiconductor package according to claim 1, further comprising: A molding layer is provided on the redistribution insulating layer, and the molding layer surrounds the semiconductor chip. The external connection bump includes a plurality of external connection bumps, and At least one of the plurality of external connection bumps does not overlap with the semiconductor chip in a vertical direction.

8. The semiconductor package according to claim 7, wherein: The mold layer surrounds the side surfaces of the semiconductor chip and exposes the upper surface of the semiconductor chip, The upper surface of the molding layer is coplanar with the upper surface of the semiconductor chip.

9. The semiconductor package according to claim 1, wherein: The redistribution insulating layer further includes a second opening; and The redistribution pattern further includes a conductive via pattern filling the second opening of the redistribution insulation layer and directly contacting the second surface of the under bump pad.

10. The semiconductor package according to claim 9, wherein: The first opening of the redistribution insulation layer has a width in a horizontal direction that increases in a direction away from the first surface of the lower bump pad; and The second opening of the redistribution insulation layer has a width that increases in a direction away from the second surface of the under bump pad.

11. A semiconductor package, comprising: semiconductor chips; a redistribution insulating layer including an opening; an external connection bump including a first portion filling the opening; a lower bump pad including a first surface and a second surface opposite to the first surface, the first surface including a contact portion directly contacting a first portion of the external connection bump and a covering portion surrounding a side surface of the contact portion and covered by a redistribution insulating layer; a first conductive barrier layer surrounding a side surface of the lower bump pad and disposed between the side surface of the lower bump pad and the redistribution insulating layer in a horizontal direction; as well as a second conductive barrier layer disposed on the covering portion of the lower bump pad and surrounding the sidewall of the upper portion of the external connection bump, The surface of the contact portion of the external connection bump that contacts the lower bump pad is coplanar with the surface of the covering portion of the second conductive barrier layer that directly contacts the lower bump pad in a vertical direction, and the vertical direction is perpendicular to the horizontal direction.

12. The semiconductor package according to claim 11, wherein The first conductive barrier layer also surrounds side surfaces of the second conductive barrier layer.

13. The semiconductor package according to claim 11, wherein A length of the first conductive barrier layer in a horizontal direction is in a range of 0.02 μm to 0.07 μm.

14. The semiconductor package according to claim 11, wherein: The length of the lower bump pad in the vertical direction is substantially the same as the length of the first conductive barrier layer in the vertical direction; and A length of the under bump pad in a vertical direction and a length of the first conductive barrier layer in a vertical direction are in a range of 5 μm to 10 μm.

15. A semiconductor package, comprising: semiconductor chips; a redistribution insulating layer including an opening; an external connection bump including a first portion filling the opening; a lower bump pad comprising a first conductive layer directly contacting a first portion of the external connection bump, a diffusion barrier layer disposed on the first conductive layer, and a second conductive layer disposed on the diffusion barrier layer and spaced apart from the first conductive layer in a vertical direction; as well as a first conductive barrier layer surrounding a side surface of the lower bump pad and disposed between the lower bump pad and the redistribution insulating layer in a horizontal direction perpendicular to the vertical direction, The side surface of the lower bump pad includes a side surface of the first conductive layer, a side surface of the diffusion barrier layer, and a side surface of the second conductive layer.

16. The semiconductor package according to claim 15, wherein: The first conductive layer of the lower bump pad includes a contact portion directly contacting the first portion of the external connection bump and a covering portion surrounding a side surface of the contact portion; and The semiconductor package further includes a second conductive barrier layer disposed on the covering portion of the first conductive layer in a vertical direction and surrounding a sidewall of the external connection bump.

17. The semiconductor package according to claim 16, wherein: A length of the first conductive layer in the horizontal direction, a length of the diffusion barrier layer in the horizontal direction, and a length of the second conductive layer in the horizontal direction are substantially the same as each other; The side surface of the second conductive barrier layer, the side surface of the first conductive layer, the side surface of the diffusion barrier layer, and the side surface of the second conductive layer are coplanar with each other in a horizontal direction; and The first conductive barrier layer directly contacts side surfaces of the second conductive barrier layer, side surfaces of the first conductive layer, side surfaces of the diffusion barrier layer, and side surfaces of the second conductive layer.

18. The semiconductor package according to claim 15, wherein A surface of a contact portion of the first conductive layer directly contacting the first portion of the external connection bump is flat.

19. The semiconductor package according to claim 15, wherein: The redistribution insulating layer includes an upper surface facing the semiconductor chip and a lower surface opposite to the upper surface; and A distance in a vertical direction between a contact portion of the first conductive layer of the under bump pad directly contacting the first portion of the external connection bump and a lower surface of the redistribution insulating layer is in a range of 3 μm to 20 μm.

20. The semiconductor package according to claim 15, further comprising: a molding layer disposed on the redistribution insulating layer, the molding layer exposing an upper surface of the semiconductor chip and surrounding a side surface of the semiconductor chip; an adhesive member disposed on an upper surface of the semiconductor chip and on an upper surface of the molding layer; as well as The heat dissipation member is attached to the upper surface of the semiconductor chip and the upper surface of the mold layer through an adhesive member.

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