semiconductor devices

Abstract

The present invention provides a semiconductor device. The semiconductor device includes a transistor element, multiple input wires, and multiple output wires. The transistor element has multiple input pads arranged along one side and multiple output pads arranged along another side opposite the one side. The multiple input wires are respectively connected to the input pads. The multiple output wires are respectively connected to the output pads and have a longer wire length than the multiple input wires. Adjacent input wires are arranged parallel to each other, while adjacent output wires are arranged non-parallel to each other.

Description

Technical Field

[0001] This application claims the benefit of priority based on Japanese Application No. 2020-004425, filed on January 15, 2020, and incorporates by reference all the contents described in the aforementioned Japanese Application.

[0002] The present disclosure relates to a semiconductor device. Background Art

[0003] Japanese Patent Application Laid-Open No. 2011-239338 describes a high-frequency circuit, and Japanese Patent Application Laid-Open No. 2012-146910 describes a semiconductor device including a high-frequency semiconductor chip. Summary of the Invention

[0004] The present disclosure provides a semiconductor device. The semiconductor device includes a transistor element, multiple input wires, and multiple output wires. The transistor element has multiple input pads arranged along one side and multiple output pads arranged along another side opposite the one side. The multiple input wires are respectively connected to the input pads. The multiple output wires are respectively connected to the output pads and are longer than the multiple input wires. Adjacent input wires are arranged parallel to each other, while adjacent output wires are arranged non-parallel to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 It is a plan view showing the structure of a semiconductor device according to one embodiment.

[0006] Figure 2 It is a plan view showing an enlarged main portion of a semiconductor device.

[0007] Figure 3 This is an enlarged view of a transistor element.

[0008] Figure 4 yes Figure 2 FIG. 1 is a cross-sectional view of the semiconductor device taken along line IV-IV.

[0009] Figure 5 It is a plan view showing an enlarged portion of the output circuit substrate and the transistor element.

[0010] Figure 6 It is a plan view showing a case where a plurality of conductive wires are parallel to each other as a comparative example.

[0011] Figure 7 This is a graph showing simulation results of the relationship between signal frequency and phase when the number of output pads included in each transistor element is two.

[0012] Figure 8This is a graph showing simulation results of the relationship between signal frequency and phase when the number of output pads included in each transistor element is four.

[0013] Figure 9 This is a graph showing the results of adding an inductor (0.08 nH) in series to each of the wires connected to the two outer output pads in the above-mentioned simulation when the number of output pads is four.

[0014] Figure 10 This is a diagram showing a method of making the lengths of the respective wires connected to a plurality of output pads different from each other.

[0015] Figure 11 This figure shows a case where the connection position between the wires and the metal pattern is offset from the center of the metal pattern in the direction D1 in a system in which the lengths of the wires connected to the plurality of output pads are different from each other.

[0016] Figure 12 This is a graph showing signal phases when the connection position between the wire and the metal pattern is offset from the center of the metal pattern in the above simulation when the number of output pads is four.

[0017] Figure 13 This shows that in the above simulation, when the number of drain pads is 4, the shape of the wire is made Figure 5 A graph showing the relationship between signal frequency and phase in the case of the illustrated configuration.

[0018] Figure 14 It is a top view of a modified example, showing a portion of the output matching circuit substrate and the transistor element in an enlarged manner.

[0019] Figure 15 This means that in the above simulation (when the number of drain pads is 4), the shape of the wire is made Figure 14 A graph showing the relationship between signal frequency and phase in the case of the illustrated configuration.

[0020] Figure 16 This is a graph showing signal phases when the connection position between the wire and the metal pattern is offset from the center of the metal pattern in the above simulation when the number of drain pads is four.

[0021] Figure 17 Graph 1 is a graph showing the relationship between the signal frequency and the phase when the angle θ is changed in a modified example, and shows the case where θ=30°.

[0022] Figure 18 Graph 1 is a graph showing the relationship between the signal frequency and the phase when the angle θ is changed in a modified example, and shows the case where θ=50°.

[0023] Figure 19 Graph 1 is a graph showing the relationship between the signal frequency and the phase when the angle θ is changed in a modified example, and shows the case where θ=60°.

[0024] Figure 20 Graph 1 is a graph showing the relationship between the signal frequency and the phase when the angle θ is changed in a modified example, and shows the case where θ=90°. DETAILED DESCRIPTION

[0025] [Problems to be Solved by the Present Disclosure]

[0026] A semiconductor device is known that includes: a transistor element comprising a plurality of transistors; and a matching circuit substrate disposed at least on the output side of the transistor element. Such a semiconductor device is used, for example, as a device for amplifying high-frequency signals. In such a device, the plurality of output pads (drain pads) of the transistor element and the matching circuit substrate are electrically connected to each other via conductive wires (e.g., bonding wires).

[0027] Multiple output pads are arranged in a row along one side of the transistor element, and multiple wires corresponding to each output pad are also arranged in a row along one side of the transistor element. In such a structure, each wire generates mutual inductance due to the current flowing in the other wires. In particular, when multiple wires are parallel to each other, mutual inductance is significantly generated. The magnitude of the mutual inductance varies depending on the position of each wire. Typically, the mutual inductance generated by the wire located closest to the end in the arrangement direction of the wires is the smallest, and the mutual inductance generated by the wire located in the center is the largest. Therefore, fluctuations in inductance are generated between the multiple wires, which causes phase differences between the multiple signals. Such phase differences cause degradation of the waveform of the signal obtained by synthesizing the multiple signals.

[0028] [Effects of the Present Disclosure]

[0029] According to the present disclosure, it is possible to provide a semiconductor device capable of reducing fluctuations in inductance between a plurality of conductive lines.

[0030] [Description of Embodiments of the Present Disclosure]

[0031] A semiconductor device according to one embodiment includes a transistor element, multiple input wires, and multiple output wires. The transistor element has multiple input pads arranged along one side and multiple output pads arranged along another side opposite the one side. The multiple input wires are connected to the input pads, respectively. The multiple output wires are connected to the output pads, respectively, and have a longer wire length than the multiple input wires. Adjacent input wires are arranged parallel to each other, while adjacent output wires are arranged non-parallel to each other.

[0032] In this semiconductor device, adjacent output wires are not parallel to each other. The mutual inductance generated by the output wires is greatest when the adjacent output wires are parallel to each other and decreases when the adjacent output wires are not parallel to each other. Therefore, the semiconductor device can reduce the mutual inductance generated by the output wires and minimize fluctuations in inductance between the output wires.

[0033] Alternatively, the semiconductor device may further include an output circuit substrate having a metal pattern. The metal pattern is connected to at least two output pads via output conductors. The spacing between adjacent output conductors connecting the metal pattern to the at least two output pads is smaller on the metal pattern side than on the output pad side. This configuration, for example, facilitates disparity between adjacent output conductors.

[0034] In the semiconductor device, one end of each output wire extending from at least two output pads may contact each other at a connection point with the metal pattern.

[0035] In the semiconductor device described above, the angle between the output leads extending from at least two output pads may be greater than or equal to 45° and less than or equal to 55°. According to simulation results, in this case, the fluctuation in inductance between the output leads can be more effectively reduced.

[0036] Alternatively, the semiconductor device may further include an input circuit substrate having another metal pattern. The other metal pattern is connected to at least two input pads via input conductors. This allows impedance matching of the input signal input to the input pads of the transistor element to be performed using the input circuit substrate.

[0037] Alternatively, the semiconductor device may further include an input circuit substrate, a base, a frame, input terminals, and output terminals. The input circuit substrate has other metal patterns. The base carries a transistor element, an input circuit substrate, and an output circuit substrate. The frame is disposed on the base and surrounds the transistor element, the input circuit substrate, and the output circuit substrate. The input terminal is disposed in the frame and connected to the input circuit substrate. The output terminal is disposed in the frame and connected to the output circuit substrate. The other metal patterns of the input circuit substrate are connected to at least two input pads via input wires. Thus, the semiconductor device can constitute a high-frequency device.

[0038] The semiconductor device may include a plurality of transistor elements, an input circuit substrate, and an output circuit substrate. This allows the semiconductor device to include a plurality of transistor elements and form a high-output, high-frequency device.

[0039] The semiconductor device may further include an input branch circuit substrate and an output coupling circuit substrate. The input branch circuit substrate includes a branch pattern with one end connected to an input terminal and the other end connected to multiple input circuit substrates. The output coupling circuit substrate includes a coupling pattern with one end connected to multiple output circuit substrates and the other end connected to an output terminal. The input branch circuit substrate can distribute input signals into signals of the same level. The output coupling circuit substrate can couple and output a high-level output signal.

[0040] Alternatively, the semiconductor device may further include a base on which the transistor element and the output circuit substrate are mounted. Alternatively, the output circuit substrate may include a metal pattern on the upper surface of a dielectric substrate, the back surface of the dielectric substrate being connected to the base, and a capacitance component being present between the metal pattern and the base. The capacitance component of the output circuit substrate enables impedance matching. Furthermore, using a dielectric substrate as the output circuit substrate allows for miniaturization of the output circuit substrate.

[0041] The semiconductor device may further include a base on which the transistor element and the input circuit substrate are mounted. Alternatively, the input circuit substrate may include another metal pattern on the upper surface of a dielectric substrate, with the back surface of the dielectric substrate connected to the base, and a capacitance component between the other metal pattern and the base. The capacitance component of the input circuit substrate enables impedance matching. Furthermore, using a dielectric substrate as the input circuit substrate allows for miniaturization of the input circuit substrate.

[0042] In the aforementioned semiconductor device, the input branch circuit substrate may include a branch pattern on the upper surface of a dielectric substrate, the back surface of the dielectric substrate being connected to a base, and a capacitance component being present between the branch pattern and the base. The capacitance component of the input branch circuit substrate enables impedance matching. Furthermore, using a dielectric substrate as the input branch circuit substrate allows for miniaturization of the input branch circuit substrate.

[0043] In the aforementioned semiconductor device, the output coupling circuit substrate may include a coupling pattern on the upper surface of a dielectric substrate, the back surface of the dielectric substrate being connected to a base, and a capacitance component being present between the coupling pattern and the base. The capacitance component of the output coupling circuit substrate enables impedance matching. Furthermore, using a dielectric substrate as the output coupling circuit substrate allows for miniaturization of the output coupling circuit substrate.

[0044] In the above-described semiconductor device, the output pad may be a drain pad.

[0045] In the above-mentioned semiconductor device, the input pad may be a gate pad.

[0046] In the above-mentioned semiconductor device, the semiconductor portion of the transistor element may be formed of a gallium nitride-based semiconductor.

[0047] [Details of Embodiments of the Invention]

[0048] Specific examples of the semiconductor device disclosed herein are described below with reference to the accompanying drawings. The present invention is not limited to these examples but is defined by the appended claims, which are intended to encompass all modifications within the meaning and scope of the appended claims. In the following description, identical elements are denoted by the same reference numerals throughout the accompanying drawings, and duplicate descriptions are omitted.

[0049] Figure 1 It is a plan view showing the structure of a semiconductor device 1 according to one embodiment. Figure 2 It is a plan view showing an enlarged main portion of the semiconductor device 1 . Figure 3 This is an enlarged view of the transistor element 5 . Figure 4 yes Figure 2 The cross-sectional view along line IV-IV is shown. Figure 1 and Figure 2 In the figure, the cover (lid) 33 of the housing 3 is omitted for ease of understanding. The semiconductor device 1 of this embodiment inputs a high-frequency signal, amplifies the high-frequency signal, and outputs it. Figures 1 to 4 As shown, the semiconductor device 1 includes a housing 3 , two transistor elements 5 , input branch circuit substrates 6 and 7 , two input circuit substrates 8 , two output circuit substrates 9 , and output coupling circuit substrates 10 and 11 .

[0050] The housing 3 includes a metal base 31, an insulating frame 32 provided on the base 31, and a cover 33 (see FIG. Figure 4 The base 31 has a transistor element 5, input branch circuit substrates 6 and 7, input circuit substrate 8, output circuit substrate 9, and output coupling circuit substrates 10 and 11 mounted on its surface 31d. The base 31 is a plate-shaped member having a planar shape that is approximately rectangular, with its longitudinal direction being direction D1. Two semicircular threaded receiving members 31c for securing the semiconductor device 1 by screwing are formed on each of a pair of end sides 31a and 31b that oppose each other in direction D1. The base 31 is fixed to a conductive mounting member that is set to a reference potential by screwing, thereby setting the reference potential.

[0051] The frame 32 has a closed planar shape, such as a substantially rectangular frame, and is made of, for example, a multilayer ceramic material. The frame 32 is fixed to the plate surface 31d of the base 31, with the normal direction of the plate surface 31d as the height direction. The frame 32 surrounds the transistor element 5, the input branch circuit substrates 6 and 7, the input circuit substrate 8, the output circuit substrate 9, and the output coupling circuit substrates 10 and 11. The frame 32 defines a space 36 on the base 31 for accommodating the transistor element 5 and the substrates 6 to 11. Figure 4 As shown, the upper surface of the frame 32 (the surface opposite the base 31) is covered by a cover 33, thereby hermetically sealing the space 36. The cover 33 is made of, for example, ceramic or metal. The frame 32 includes portions 32a and 32b that face each other in direction D1, and portions 32c and 32d that face each other in direction D2 that intersects (e.g., is perpendicular to) direction D1. Portions 32a and 32b extend along direction D2, while portions 32c and 32d extend along direction D1.

[0052] The frame 32 is provided with an input terminal 34 and an output terminal 35. The input terminal 34 and the output terminal 35 are formed of a metal film formed on a ceramic layer and each extend along direction D2. The input terminal 34 extends along direction D2 through the center of the portion 32c of the frame 32 in direction D1, with a portion thereof exposed outside the housing 3. The end of the input terminal 34 exposed outside the housing 3 is conductively bonded to a lead (not shown) extending along direction D2. The input terminal 34 receives a high-frequency signal from outside the semiconductor device 1 via the lead. The high-frequency signal input to the input terminal 34 is a signal based on a multi-carrier transmission system. The high-frequency signal input to the input terminal 34 is a superposition of multiple carrier signals with different frequencies. The frequency band of the carrier signal is, for example, below 500 MHz. The output terminal 35 extends along direction D2 through the center of the portion 32d of the frame 32 in direction D1, with a portion thereof exposed outside the housing 3. The end of the output terminal 35 exposed outside the housing 3 is conductively bonded to another lead (not shown) extending along direction D2. The output terminal 35 outputs the amplified high-frequency signal to the outside of the semiconductor device 1 via other pins.

[0053] The transistor element 5 is electrically bonded to the base 31 via metal 21 containing sintered Ag, thereby securing it to the base 31. The input circuit board 8 and the output circuit board 9 are adjacent to the transistor element 5. The input circuit board 8 and the output circuit board 9 are also electrically bonded to the base 31 via metal 21 containing sintered Ag, thereby securing them to the base 31. The metal 21 is formed by heating a sintered conductive paste containing Ag to vaporize the solvent and sinter it. The input branch circuit boards 6 and 7 and the output coupling circuit boards 10 and 11 near the frame 32 are electrically bonded to the base 31 via AuSn eutectic solder 22, thereby securing them to the base 31.

[0054] Reference Figure 2 , the internal structure of the semiconductor device 1 of this embodiment is described in detail. As mentioned above, the semiconductor device 1 has two transistor elements 5. The output of each transistor element 5 is, for example, 30W, and the overall output is, for example, 60W. Each transistor element 5 has a plurality of transistors built in. These transistors are, for example, field effect transistors (FET). Each transistor element 5 has a plurality of gate combs, a plurality of source combs, and a plurality of drain combs. In the direction D1, the source combs and the drain combs are alternately arranged, and a gate comb is arranged between each source comb and the drain comb. As Figure 3 As shown, each transistor element 5 has a side 5d on the input terminal 34 side and another side 5b on the output terminal 35 side opposite to the side 5d. Along the side 5d on the input terminal 34 side of each transistor element 5, a plurality of gate pads (input pads) 50 and a plurality of source pads (not shown) are alternately arranged. Along the other side 5b on the output terminal 35 side of each transistor element 5, a plurality of drain pads (output pads) 51 are arranged. Each source pad is connected to the transistor element 5 via a conductive hole and a metal 21 (see FIG. 2 ) that penetrates the transistor element 5 in the thickness direction. Figure 4 ) is electrically connected to the base 31 and becomes a reference potential. Each transistor element 5 amplifies the high-frequency signal input to each gate pad 50 and outputs the amplified high-frequency signal from each drain pad 51.

[0055] The semiconductor portion of transistor element 5 is composed of, for example, a GaAs-based compound semiconductor or a gallium nitride-based semiconductor with a GaAs substrate. The length of transistor element 5 in direction D1 is, for example, 1 mm, and the length in direction D2 is, for example, 6 mm. The thickness of transistor element 5 is, for example, 0.1 mm.

[0056] Input branch circuit substrates 6 and 7 are arranged along direction D2 alongside input terminal 34 and transistor element 5, and are located between input terminal 34 and transistor element 5. Input branch circuit substrate 6 includes a dielectric substrate 61, for example, made of ceramic, and branch circuits 62 provided on the upper surface of dielectric substrate 61. Similarly, input branch circuit substrate 7 includes a dielectric substrate 71, for example, made of ceramic, and branch circuits 72 provided on the upper surface of dielectric substrate 71. In one example, dielectric substrates 61 and 71 are made of Al2O3 (aluminum oxide). The planar shape of dielectric substrates 61 and 71 is, for example, a rectangle, with one long side facing input terminal 34 and the other long side facing transistor element 5 across input circuit substrate 8. The long side of dielectric substrate 61 is, for example, 7.8 mm long, and the short side is, for example, 2.0 mm long. The long side of dielectric substrate 71 is, for example, 12.5 mm long, and the short side is, for example, 3.8 mm long. The thickness of dielectric substrates 61 and 71 is, for example, approximately 0.3 mm to 0.5 mm. A metal film (not shown) is fixed to the back surface of dielectric substrates 61 and 71, and this metal film is connected to base 31 via AuSn eutectic solder 22. One short side of dielectric substrate 71 is located near portion 32a of frame 32, and the other short side of dielectric substrate 71 is located near portion 32b of frame 32. In other words, dielectric substrate 71 extends from near one end of frame 32 to near the other end in direction D1.

[0057] Branch circuits 62 and 72 are branch circuits relative to the input circuit of the input circuit substrate 8. The branch circuit 62 includes a branch pattern 63 provided on the upper surface of the dielectric substrate 61. One end of the branch pattern 63 is electrically connected to the input terminal 34 via the wire 2a. The branch pattern 63 branches in two directions with the connection point connected to the wire 2a as the starting point. The branch circuit 72 includes two branch patterns 73 provided on the upper surface of the dielectric substrate 71. Each branch pattern 73 is electrically connected to the two ends of the branch of the branch pattern 63 via the wire 2b. Each branch pattern 73 repeatedly branches with the connection point connected to the wire 2b as the starting point, and finally reaches four metal pads 73a respectively. A total of 8 metal pads 73a are arranged along the long side of the transistor element 5 side of the dielectric substrate 71. Adjacent metal pads 73a are connected to each other via the membrane resistor 74 to form a Wilkinson coupler. This ensures isolation between the plurality of gate pads 50 of the transistor element 5 and achieves matching of the input impedance of the transistor element 5 viewed from the input terminal 34. The resistance value of the film resistor 74 is, for example, 50Ω.

[0058] Two input circuit substrates 8 are arranged between the input branch circuit substrate 7 and the transistor element 5 in direction D2 and are arranged along direction D1. These input circuit substrates 8 include input circuits (input matching circuits) corresponding to the transistor element 5. Each input circuit substrate 8 has a dielectric substrate 81. Each input circuit substrate 8 is, for example, a bare chip capacitor, and has one or more (four in this embodiment) metal patterns 82 on the upper surface of the dielectric substrate 81. The total number of metal patterns 82 is, for example, the same as the number of metal pads 73a. The multiple metal patterns 82 are arranged in a row along direction D1. Each metal pattern 82 is electrically connected to the corresponding metal pad 73a via a wire 2c, and is electrically connected to at least two corresponding gate pads 50 of the transistor element 5 via at least two wires 2d (input wires). The number of wires 2d is, for example, two per metal pattern 82 (16 in total). Adjacent wires 2d are arranged parallel to each other. The number of gate pads 50 connected to a single metal pattern 82 is, for example, two. A metal film (not shown) is fixed to the back surface of the input circuit substrate 8 , and the metal film is connected to the base 31 via the metal 21 .

[0059] Input circuit substrate 8 has an inductance component based on conductors 2c and 2d. A capacitance component (capacitance) exists between the node between these inductance components, namely metal pattern 82, and the reference potential point, namely base 31. These inductance components and capacitance form a T-type filter circuit. Input circuit substrate 8 performs impedance conversion using this T-type filter circuit. Typically, in transistor element 5, the impedance inside the transistor, as estimated from gate pad 50, differs from the characteristic impedance of the transmission line (e.g., 50Ω). Input circuit substrate 8 uses the T-type filter circuit to convert this impedance to 50Ω, as estimated from input terminal 34, inside housing 3.

[0060] The dielectric substrate 81 of the input circuit board 8 is made of, for example, AlN. The length of the input circuit board 8 in direction D1 is, for example, 5.4 mm, and the length in direction D2 is, for example, 2.0 mm. The thickness of the input circuit board 8 is, for example, approximately 0.2 mm to 0.3 mm. The capacitance of the bare chip capacitor of the input circuit board 8 is, for example, 30 pF per metal pattern 82.

[0061] Two output circuit substrates 9 are arranged between the transistor element 5 and the output coupling circuit substrates 10 and 11 in direction D2 and arranged along direction D1. These output circuit substrates 9 include output matching circuits (output matching circuits) for the transistor element 5. Like the input circuit substrate 8, the output circuit substrate 9 is, for example, a parallel plate capacitor (bare chip capacitor). Each output circuit substrate 9 includes a dielectric substrate 91. Each output circuit substrate 9 has one or more (four in this embodiment) metal patterns 92 on the top surface of the dielectric substrate 91. The total number of metal patterns 92 is, for example, the same as the number of metal patterns 82 on the input circuit substrate 8. The multiple metal patterns 92 are arranged in a row along direction D1. Each metal pattern 92 is electrically connected to at least two corresponding drain pads 51 of the transistor element 5 via two or more wires 2e (output wires), and is also electrically connected to corresponding metal pads 103a (described later) of the output coupling circuit substrate 10 via wires 2f. The number of wires 2e is, for example, two per metal pattern 92 (16 in total). A metal film (not shown) is fixed to the back surface of the output circuit substrate 9 , and the metal film is connected to the base 31 via the metal 21 .

[0062] Output circuit board 9 also has an inductance component based on conductors 2e and 2f. A capacitance component (capacitance) exists between the node between these inductance components, namely metal pattern 92, and the reference potential point, namely base 31. These inductance components and capacitance constitute a T-type filter circuit. Output circuit board 9 performs impedance conversion using this T-type filter circuit. Typically, in transistor element 5, the impedance inside the transistor, as estimated from drain pad 51, differs from the characteristic impedance of the transmission line (e.g., 50Ω), and is generally smaller than 50Ω. Output circuit board 9 uses the T-type filter circuit to convert this impedance to 50Ω, as estimated from output terminal 35, inside housing 3.

[0063] The dielectric substrate 91 of the output circuit board 9 is made of, for example, AlN. The length of the output circuit board 9 in direction D1 is, for example, 5.4 mm, and the length in direction D2 is, for example, 2.0 mm. The thickness of the output circuit board 9 is, for example, approximately 0.2 mm to 0.3 mm. The capacitance of the bare chip capacitor of the output circuit board 9 is, for example, 20 pF per metal pattern 92.

[0064] Output coupling circuit substrates 10 and 11 are arranged along direction D2 alongside transistor element 5 and output terminal 35, and are located between transistor element 5 and output terminal 35. Output coupling circuit substrate 10 includes a dielectric substrate 101, for example, made of ceramic, and a combining circuit 102 disposed on the upper surface of dielectric substrate 101. Similarly, output coupling circuit substrate 11 includes a dielectric substrate 111, for example, made of ceramic, and a combining circuit 112 disposed on the upper surface of dielectric substrate 111. In one example, dielectric substrates 101 and 111 are made of Al2O3 (aluminum oxide). The planar shape of dielectric substrates 101 and 111 is, for example, a rectangle, with one long side facing transistor element 5 across output circuit substrate 9 and the other long side facing output terminal 35. The long side of dielectric substrate 101 is, for example, 12.5 mm long, and the short side is, for example, 4.5 mm long. The length of the long side of the dielectric substrate 111 is, for example, 7.8 mm, and the length of the short side is, for example, 2.0 mm. The thickness of the dielectric substrates 101 and 111 is, for example, approximately 0.3 mm to 0.5 mm. A metal film (not shown) is fixed to the back surface of the dielectric substrates 101 and 111, and this metal film is connected to the base 31 via the AuSn eutectic solder 22. One short side of the dielectric substrate 101 is located near the portion 32a of the frame 32, and the other short side of the dielectric substrate 101 is located near the portion 32b of the frame 32. In other words, the dielectric substrate 101 extends from near one end of the frame 32 to near the other end in the direction D1.

[0065] Combining circuits 102 and 112 are circuits for combining signals relative to the output circuit of output circuit substrate 9. Specifically, combining circuits 102 and 112 combine the signals output from the multiple drain pads 51 of transistor element 5 into a single output signal. Combining circuit 102 includes two coupling patterns 103 provided on the upper surface of dielectric substrate 101. Each coupling pattern 103 includes four metal pads 103a at one end. The four metal pads 103a are arranged along the long side of the output coupling circuit substrate 10 on the side of the transistor element 5. Adjacent metal pads 103a are connected to each other via film resistors 104, forming a Wilkinson coupler. This ensures isolation between the multiple drain pads 51 of transistor element 5 and achieves matching of the output impedance of transistor element 5 as viewed from output terminal 35. The resistance value of film resistor 104 is, for example, 50Ω. Each metal pad 103a is electrically connected to the corresponding metal pattern 92 of output circuit substrate 9 via a wire 2f.

[0066] Each coupling pattern 103 repeatedly couples from four metal pads 103a and ultimately reaches a connection point with a wire 2g. Each coupling pattern 103 is electrically connected to both ends of a coupling pattern 113 of a synthesizing circuit 112 via a wire 2g. The center portion of coupling pattern 113 is located at the other end of coupling pattern 113 in direction D2 and is electrically connected to output terminal 35 via a wire 2h.

[0067] The connection method between the output circuit substrate 9 and the transistor element 5 will be described in detail. Figure 5 FIG is a plan view showing a portion of the output circuit substrate 9 and the transistor element 5 in an enlarged manner. Figure 5 As shown, transistor element 5 has a top surface 5a, long sides 5b extending along direction D1 on top surface 5a, and short sides 5c extending along direction D2 intersecting direction D1. Top surface 5a is the surface opposite to the back surface facing base 31. Long sides 5b are the end sides of transistor element 5 on the output terminal 35 side. As described above, transistor element 5 has N (N is an integer greater than or equal to 3) drain pads 51 arranged along long sides 5b on top surface 5a. In one example, each transistor element 5 has eight drain pads 51.

[0068] The output circuit substrate 9 has a top surface 9a that is spaced apart from the long side 5b of the transistor element 5 in direction D2 and extends along direction D1. The output circuit substrate 9 has a long side 9b extending along direction D1 and a short side 9c extending along direction D2. The long side 9b faces the long side 5b of the transistor element 5 in direction D2. The output circuit substrate 9 has one or more (four in this embodiment) metal patterns 92 described above on its top surface 9a. These metal patterns 92 are arranged along the long side 9b.

[0069] Each drain pad 51 is electrically connected to at least one of the metal patterns 92 via a wire 2e mainly containing, for example, gold (Au). In the illustrated example, one wire 2e is connected to each drain pad 51, and the number of wires 2e is N. In addition, without being limited to this example, multiple wires 2e may be connected to each drain pad 51. In addition, at least two drain pads 51 are connected via a wire 2e for each metal pattern 92. In the illustrated example, two drain pads 51 are connected via a wire 2e for each metal pattern 92. Without being limited to this example, at least three drain pads 51 may be connected via a wire 2e for each metal pattern 92. The lengths of these wires 2e are equal to each other and are longer than the wire 2d.

[0070] like Figure 5As shown, adjacent wires 2e are non-parallel when viewed from the normal direction of each upper surface 5a, 9a. Non-parallel here means that the extension direction of a wire 2e connected to a drain pad 51, when projected onto the D1-D2 plane, and the extension direction of a wire 2e connected to another drain pad 51 adjacent to the drain pad 51, when projected onto the D1-D2 plane, form an angle greater than 0° relative to each other. More practically, these extension directions form a relative angle that exceeds the manufacturing tolerance (e.g., ±5°).

[0071] In one example, the shape of the wires 2e connected to adjacent drain pads 51, as viewed from the direction normal to top surfaces 5a and 9a (in other words, the shape projected onto the D1-D2 plane), is line-symmetric about an axis Q perpendicular to both direction D1 and the direction normal to top surfaces 5a and 9a (i.e., along direction D2). Furthermore, on each metal pattern 92, the ends of the wires 2e extending from the two drain pads 51 are separated by a gap Wa. The gap between adjacent wires is smaller on the metal pattern 92 side than on the drain pad 51 side. That is, the gap Wa between the ends of the wires 2e on the metal pattern 92 is smaller than the gap Wb between the other ends of the wires 2e on the drain pad 51. In one example, the gap Wa is greater than 100 μm and less than 150 μm, and the gap Wb is greater than 600 μm and less than 1200 μm. An angle θ formed by the wires 2 e extending from the two drain pads 51 as viewed in the normal direction of the upper surfaces 5 a and 9 a is, for example, not less than 20° and not more than 145°, and more preferably not less than 45° and not more than 55°.

[0072] On each metal pattern 92, one end of the wire 2e extending from the two drain pads 51 is located at the center of the metal pattern 92 in direction D1. More specifically, the midpoint between the ends of the wires 2e extending from the two drain pads 51 is located at the center line of the metal pattern 92 along direction D2. One end of the wire 2f connected to each metal pattern 92 is also located at the center of the metal pattern 92 in direction D1 (more specifically, on the center line of the metal pattern 92 along direction D2).

[0073] The effects obtained by the semiconductor device 1 of the present embodiment described above will be described together with comparative examples. Figure 6This is a top view showing a case where adjacent wires 2e are parallel to each other as a comparative example. Furthermore, it is assumed that the lengths of adjacent wires 2e are equal to each other. In this case, if an RF (radio frequency) signal flows from the transistor element 5 to the plurality of wires 2e, the inductance of each wire 2e fluctuates due to mutual inductance. Specifically, the inductance of the wire 2e connected to the drain pad 511 located closest to the end in the arrangement direction of the drain pads 51 (direction D1) is the smallest, and the inductance of the wire 2e connected to the drain pad 512 located in the center is the largest. In other words, the maximum amplitude of the inductance fluctuation is the difference between the inductance of the wire 2e connected to the drain pad 511 and the inductance of the wire 2e connected to the drain pad 512.

[0074] Figure 7 This is a graph showing simulation results of the relationship between the signal frequency (unit: GHz) and the phase (unit: degree) when each transistor element 5 has two drain pads 51 . Figure 7 In FIG. 5 , a solid line G11 shows a relationship with respect to the wire 2 e connected to one of the two drain pads 51 , and a broken line G12 shows a relationship with respect to the wire 2 e connected to the other of the two drain pads 51 . Figure 8 This is a graph showing simulation results of the relationship between the signal frequency (unit: GHz) and the phase (unit: degree) in a case where each transistor element 5 has four drain pads 51 . Figure 8 In FIG. 1 , the solid line G21 shows the relationship of the wire 2e connected to one of the two drain pads 51 located on the outside among the four drain pads 51. The dotted line G22 shows the relationship of the wire 2e connected to one of the two drain pads 51 located on the inside among the four drain pads 51. Figure 7 As shown in FIG. 5 , when the number of drain pads 51 is 2, there is almost no phase difference in the signals transmitted through the respective wires 2e. Figure 8 As shown in FIG. 4 , when there are four drain pads 51, a significant phase difference occurs between the signal transmitted through the wire 2e connected to the outer drain pad 51 and the signal transmitted through the wire 2e connected to the inner drain pad 51. This means that when there are four drain pads 51, the inductance of the wire 2e fluctuates. Such fluctuations in inductance occur when there are three or more drain pads 51.

[0075] Figure 9This graph shows the results of adding an inductor (0.08 nH) in series with each wire 2e connected to the two outer drain pads 51 in the simulation described above, when there are four drain pads 51. In this case, the solid line G21 and the dashed line G22 approach each other, eliminating the phase difference. This shows that, in the simulation described above, when there are four drain pads 51, the difference in inductance between the wire 2e connected to the outer drain pads 51 and the wire 2e connected to the inner drain pads 51 is 0.08 nH.

[0076] As a method of eliminating the fluctuation of inductance value, Figure 10 As shown in FIG. 1 , it is considered to make the lengths of the wires 2e connected to the plurality of drain pads 51 different from each other. That is, the closer to the end of the arrangement direction of the drain pads 51, the longer the wire 2e connected to the drain pad 51 is, and the greater the inductance. However, each wire 2e constitutes a part of the circuit element, and therefore, the length needs to be adjusted in order to optimize the high-frequency characteristics. Therefore, the setting of the length of each wire 2e is extremely complicated, which impairs the ease of manufacturing. In addition, as Figure 11 As shown in FIG. 1 , the connection position between the wire 2 f and the metal pattern 92 may be offset from the center of the metal pattern 92 in the direction D1 due to manufacturing errors, etc. In this case, the length of the current path J within the metal pattern 92 differs, causing the phases of the signals from the two drain pads 51 connected to the respective metal patterns 92 to be misaligned. Figure 12 This graph shows the signal phases when the connection position between wire 2f and metal pattern 92 is offset from the center of metal pattern 92 in the above simulation, where the number of drain pads 51 is four. As shown in this graph, the offset position of wire 2f causes a large phase difference between the signal phase (solid line G21) on the side where current path J is shortened and the signal phase (dashed line G22) on the side where current path J is lengthened.

[0077] To address the above problem, in semiconductor device 1 of this embodiment, the wires 2e connected to adjacent drain pads 51 are not parallel to each other. The mutual inductance generated by the wires 2e is greatest when the wires 2e are parallel to each other and decreases when the wires 2e are not parallel to each other. Therefore, semiconductor device 1 of this embodiment can reduce the mutual inductance generated by the wires 2e and minimize fluctuations in inductance between the wires 2e.

[0078] Figure 13 This shows that in the above simulation, when the number of drain pads 51 is 4, the shape of the wire 2e is made Figure 5The graph of the relationship between the signal frequency (unit: GHz) and the phase (unit: degree) in the case of the form shown. The solid line G21 shows the relationship for the wire 2e connected to the drain pad 51 located on the outside among the four drain pads 51. The dotted line G22 shows the relationship for the wire 2e connected to the drain pad 51 located on the inside among the four drain pads 51. Figure 13 As shown, it can be seen that by making the conductors 2e non-parallel to each other, the conductors 2e are parallel to each other ( Figure 8 ), both the solid line G21 and the dotted line G22 move toward the low phase side and approach each other (ie, the phase difference becomes smaller). In other words, according to this embodiment, the mutual inductance generated by each wire 2e can be reduced, reducing the fluctuation of the inductance between the wires 2e.

[0079] As in this embodiment, the lengths of the plurality of wires 2e may be equal, and the shapes of the wires 2e connected to adjacent drain pads 51, as viewed from the normal to upper surfaces 5a and 9a, may be line-symmetrical about an axis Q perpendicular to both direction D1 and the normal to upper surfaces 5a and 9a. In this case, fluctuations in the angle between adjacent wires 2e can be suppressed, thereby more effectively reducing fluctuations in the inductance between the wires 2e.

[0080] As in the present embodiment, the semiconductor device 1 may further include an output circuit substrate 9 having a metal pattern 92. The metal pattern 92 is connected to at least two drain pads 51 via a wire 2e. The interval between adjacent wires 2e connecting the metal pattern 92 to at least two drain pads 51 is smaller on the metal pattern 92 side than on the drain pad 51 side. With such a structure, it is easy to make adjacent wires 2e non-parallel to each other. In addition, compared with the case where the wires 2e are parallel to each other, one end of the wires 2e is close to each other. Therefore, even in the case where the connection position of the wire 2f to the metal pattern 92 deviates from the center of the metal pattern 92 (see Figure 11 ), it is also possible to reduce the fluctuation in the length of the current path J and reduce the phase difference of the signals from the two drain pads 51.

[0081] As in this embodiment, the angle θ formed by the wires 2e extending from the two drain pads 51, as viewed from the normal to the upper surfaces 5a and 9a, may be greater than or equal to 45° and less than or equal to 55°. Simulation results described below show that in this case, the inductance fluctuation between the wires 2e can be more effectively reduced.

[0082] As in this embodiment, semiconductor device 1 may further include input circuit substrate 8 having metal pattern 82. Metal pattern 82 is connected to at least two gate pads 50 via wire 2d. Thus, input circuit substrate 8 can achieve impedance matching for input signals input to gate pads 50 of transistor element 5.

[0083] As in this embodiment, semiconductor device 1 may include input circuit substrate 8, base 31, frame 32, input terminal 34, and output terminal 35. Input circuit substrate 8 has a metal pattern 82. Base 31 carries transistor element 5, input circuit substrate 8, and output circuit substrate 9. Frame 32 is provided on base 31 and surrounds transistor element 5, input circuit substrate 8, and output circuit substrate 9. Input terminal 34 is provided in frame 32 and connected to input circuit substrate 8. Output terminal 35 is provided in frame 32 and connected to output circuit substrate 9. Metal pattern 82 of input circuit substrate 8 is connected to at least two gate pads 50 via wire 2d. Thus, semiconductor device 1 can constitute a high-frequency device.

[0084] As in this embodiment, a plurality of transistor elements 5, input circuit substrate 8, and output circuit substrate 9 may be provided. This allows a plurality of transistor elements 5 to be provided, and the semiconductor device 1 can constitute a high-output, high-frequency device.

[0085] As in this embodiment, the semiconductor device 1 may include input branch circuit boards 6 and 7 and output coupling circuit boards 10 and 11. The input branch circuit boards 6 and 7 have branch patterns 63 and 73 connected at one end to the input terminal 34 and at the other end to the plurality of input circuit boards 8. The output coupling circuit boards 10 and 11 have coupling patterns 103 and 113 connected at one end to the plurality of output circuit boards 9 and at the other end to the output terminal 35. The input branch circuit boards 6 and 7 can distribute input signals to signals of the same level. The output coupling circuit boards 10 and 11 can couple and output high-level output signals.

[0086] As in this embodiment, the semiconductor device 1 may include a base 31 on which the transistor element 5 and the output circuit substrate 9 are mounted. Alternatively, the output circuit substrate 9 may include a metal pattern 92 on the upper surface of a dielectric substrate 91, with the back surface of the dielectric substrate 91 connected to the base 31, and a capacitance component between the metal pattern 92 and the base 31. The capacitance component of the output circuit substrate 9 enables impedance matching. Furthermore, using the dielectric substrate 91 as the output circuit substrate 9 allows for miniaturization of the output circuit substrate 9.

[0087] As in this embodiment, the input circuit board 8 may include a metal pattern 82 on the upper surface of a dielectric substrate 81, with the back surface of the dielectric substrate 81 connected to the base 31. A capacitance component may be present between the metal pattern 82 and the base 31. The presence of a capacitance component in the input circuit board 8 enables impedance matching. Furthermore, the use of the dielectric substrate 81 in the input circuit board 8 allows for miniaturization of the input circuit board 8.

[0088] As in this embodiment, the input branch circuit boards 6 and 7 may have input branch patterns 63 and 73 on the top surfaces of dielectric substrates 61 and 71, respectively. The back surfaces of the dielectric substrates 61 and 71 may be connected to the base 31, and a capacitance component may be present between the input branch patterns 63 and 73 and the base 31. The presence of a capacitance component in the input branch circuit boards 6 and 7 enables impedance matching. Furthermore, the use of dielectric substrates 61 and 71 as the input branch circuit boards 6 and 7 allows for miniaturization of the input branch circuit boards 6 and 7.

[0089] As in this embodiment, the output coupling circuit substrates 10 and 11 may include coupling patterns 103 and 113 on the top surfaces of dielectric substrates 101 and 111, respectively. The back surfaces of the dielectric substrates 101 and 111 are connected to the base 31, and a capacitance component exists between the coupling patterns 103 and 113 and the base 31. The capacitance component enables impedance matching in the output coupling circuit substrates 10 and 11. Furthermore, using dielectric substrates 101 and 111 as the output coupling circuit substrates 10 and 11 allows for miniaturization of the output coupling circuit substrates 10 and 11.

[0090] (Variation)

[0091] Figure 14 FIG1 is a top view of a modified example of the above embodiment, and shows a portion of the output circuit substrate 9 and the transistor element 5 in an enlarged manner. Figure 14 As shown, in this modified example, when viewed from the normal direction of each upper surface 5a, 9a, the adjacent wires 2e are not parallel to each other. In the above embodiment, on each metal pattern 92, one end of the wires 2e extending from the two drain pads 51 is separated from each other by a gap Wa (see Figure 5 ). In this modification, the above-mentioned one ends are in contact with each other at the connection points connected to each metal pattern 92. Here, the one ends being in contact with each other includes the following three forms. One form is a form in which the wire 2e on one side and the wire 2e on the other side are continuous with each other at their respective one ends. Another form is a form in which one end of the wire 2e on one side and one end of the wire 2e on the other side are arranged along the direction D1 and in contact with each other. And still another form is a form in which one end of the wire 2e on one side and one end of the wire 2e on the other side overlap with each other.

[0092] In one example, the shapes of wires 2e connected to adjacent drain pads 51, as viewed from the direction normal to upper surfaces 5a and 9a (in other words, their shapes projected onto the D1-D2 plane), are line-symmetric about an axis Q, which is perpendicular to both direction D1 and the direction normal to upper surfaces 5a and 9a. In this variation, when viewed from the direction normal to upper surfaces 5a and 9a, the angle θ formed between the wires 2e extending from the two drain pads 51 is, for example, not less than 20° and not more than 145°, and more preferably not less than 45° and not more than 55°.

[0093] Figure 15 This shows that the shape of the wire 2e is changed to Figure 14 The graph of the relationship between the signal frequency (unit: GHz) and the phase (unit: degree) in the case of the form shown. The solid line G21 represents the relationship for the wire 2e connected to the drain pad 51 located on the outside among the four drain pads 51. The dotted line G22 represents the relationship for the wire 2e connected to the drain pad 51 located on the inside among the four drain pads 51. Figure 15 As shown, in this modification, the solid line G21 and the dotted line G22 move toward the low phase side and approach each other (i.e., the phase difference becomes smaller). In other words, according to this modification, the mutual inductance generated by each wire 2e can be reduced, reducing the fluctuation of the inductance between the wires 2e.

[0094] As in this modified example, on each metal pattern 92, one end of the wire 2e extending from the two drain pads 51 may contact each other at the connection point with the metal pattern 92. With such a structure, for example, it is easy to make the wires 2e non-parallel to each other. In addition, since each end of the wire 2e extending from the two drain pads 51 is set at almost the same position, it is possible to almost eliminate the situation where the connection position between the wire 2f and the metal pattern 92 deviates from the center of the metal pattern 92 (see FIG. 1 ). Figure 11 ) The fluctuation of the length of the current path J under the condition of . Therefore, the phase difference of the signals from the two drain pads 51 can be suppressed more effectively. Figure 16 This is a graph showing the signal phase when the connection position between the wire 2f and the metal pattern 92 is deviated from the center of the metal pattern 92 in the above simulation when the number of drain pads 51 is 4. Figure 12 In contrast, the phase difference between the signal phase (solid line G21) on the side where the current path J is shortened due to the positional deviation of the wire 2f and the signal phase (dashed line G22) on the side where the current path J is lengthened is significantly reduced.

[0095] A study was conducted to determine a preferred size of the angle θ formed between the wires 2 e extending from the two drain pads 51 . Figures 17 to 20 Graph showing the relationship between signal frequency and phase when the angle θ is changed in this modification. Figure 17 The case where θ=30° is shown. Figure 18 The case where θ=50° is shown. Figure 19 The case where θ=60° is shown. Figure 20 The case of θ = 90° is shown. Comparing these graphs, it can be seen that the distance (i.e., the phase difference) between the solid line G21 and the dashed line G22 is minimized when θ = 50°. In other words, the optimal value for angle θ is 50°. In practical terms, an angle θ near 50° (e.g., within the range of 50° ± 5°) is preferable. This is also true in the aforementioned embodiment, where one end of the wires 2e extending from the two drain pads 51 is separated from each other.

[0096] The semiconductor device disclosed herein is not limited to the above-described embodiment and can be modified in various other ways. For example, in the above-described embodiment, the present disclosure is applied to a semiconductor device 1 including a transistor element 5, input branch circuit substrates 6 and 7, an input circuit substrate 8, an output circuit substrate 9, and output coupling circuit substrates 10 and 11. However, the present disclosure is not limited to this embodiment and can also be applied to a semiconductor device including a transistor element and a circuit substrate arranged in parallel with the transistor element.

Claims

1. A semiconductor device, wherein: have: A transistor element having a plurality of input pads arranged along one side and a plurality of output pads arranged along another side opposite to the one side; A plurality of input wires are respectively connected to the input pads; and a plurality of output wires, respectively connected to the output pads and having a wire length longer than the plurality of input wires; The adjacent input conductive lines are arranged in parallel with each other, and the adjacent output conductive lines are arranged non-parallel with each other.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes an output circuit substrate having a metal pattern. The metal pattern is connected to at least two of the output pads via the output wires. The adjacent output conductive lines connecting the metal pattern to the at least two output pads are spaced closer to each other on the metal pattern side than on the output pad side.

3. The semiconductor device according to claim 2, wherein One ends of the output conductive lines extending from the at least two output pads contact each other at connection points with the metal pattern.

4. The semiconductor device according to claim 2 or 3, wherein The output conductive lines extending from the at least two output pads form an angle of not less than 45° and not more than 55°.

5. The semiconductor device according to any one of claims 1 to 3, wherein The semiconductor device further includes an input circuit substrate having another metal pattern. The other metal pattern is connected to at least two of the input pads via the input conductive lines. The semiconductor device according to claim 2 , wherein: The semiconductor device further comprises: an input circuit substrate having a plurality of other metal patterns; a base on which the transistor element, the input circuit substrate, and the output circuit substrate are mounted; a frame body, provided on the base and surrounding the transistor element, the input circuit substrate and the output circuit substrate; an input terminal, provided on the frame body and connected to the input circuit substrate; and The output terminal is provided in the frame and connected to the output circuit substrate. The other metal patterns of the input circuit substrate are connected to at least two of the input pads via the input wires, respectively.

7. The semiconductor device according to claim 6, wherein A plurality of the transistor elements, the input circuit substrate, and the output circuit substrate are provided.

8. The semiconductor device according to claim 7, wherein The semiconductor device further comprises: an input branch circuit substrate having a branch pattern connected to the input terminal at one end and connected to a plurality of input circuit substrates at the other end; and The output coupling circuit substrate has a coupling pattern having one end connected to the plurality of output circuit substrates and the other end connected to the output terminal.

9. The semiconductor device according to claim 2, wherein The semiconductor device further includes a base on which the transistor element and the output circuit substrate are mounted. The output circuit substrate includes the metal pattern on the upper surface of a dielectric substrate. The back surface of the dielectric substrate is connected to the base, and a capacitance component exists between the metal pattern and the base.

10. The semiconductor device according to claim 5, wherein The semiconductor device further includes a base on which the transistor element and the input circuit substrate are mounted. The input circuit substrate includes the other metal pattern on the upper surface of a dielectric substrate. The back surface of the dielectric substrate is connected to the base. A capacitance component exists between the other metal pattern and the base.

11. The semiconductor device according to claim 8, wherein The input branch circuit substrate has the branch pattern on the upper surface of a dielectric substrate. The back surface of the dielectric substrate is connected to the base, and a capacitance component exists between the branch pattern and the base.

12. The semiconductor device according to claim 8, wherein The output coupling circuit substrate includes the coupling pattern on the upper surface of a dielectric substrate. The rear surface of the dielectric substrate is connected to the base. A capacitance component exists between the coupling pattern and the base.

13. The semiconductor device according to any one of claims 1 to 3 or 6 to 12, wherein The output pad is a drain pad.

14. The semiconductor device according to any one of claims 1 to 3 or 6 to 12, wherein The input pad is a gate pad.

15. The semiconductor device according to any one of claims 1 to 3 or 6 to 12, wherein The semiconductor portion of the transistor element is composed of a gallium nitride-based semiconductor.

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