Display panel and large display device having the same

Abstract

The present disclosure relates to a display panel and a large display device having the display panel, and in particular to a display panel and a large display device including the same display panel and a connecting member. The large-area display device according to the present disclosure includes: a cover plate; a plurality of unit display panels arranged on one surface of the cover plate, each of the unit display panels including: a substrate; a display area defined at a middle portion of the substrate; a non-display area surrounding the display area; a pad portion arranged in the non-display area; a first terminal, which is arranged outside the pad portion in the non-display area; and a second terminal separated from the first terminal, which is arranged outside the pad portion in the non-display area; and a connecting member, which is arranged between two unit display panels, and the connecting member connects the first terminal of the unit display panel and the second terminal of the unit display panel, respectively.

Description

Technical Field

[0001] The present disclosure relates to a display panel and a large display device including the same display panel and a connecting member (or a tile connector). In particular, the present disclosure relates to a large display device that maintains a high-level voltage and a low-level voltage at a constant value over the entire area of ​​the display device, and the large display device includes a connecting member, through which a plurality of display panels are combined in a matrix manner on the same plane, thereby being able to be expanded without being restricted by shape and size. Background Art

[0002] As the information society develops, the demand for display devices is also developing in various ways. For example, various flat panel display devices such as liquid crystal displays (or LCDs), organic light emitting displays (or OLEDs), and micro LED displays have been developed.

[0003] Flat panel display devices are being developed in various sizes and uses, from small electronic devices such as mobile phones to large electronic devices such as outdoor advertising panels. In particular, the demand for large display devices is increasing. For example, it is installed in a stadium and displays information related to the game, and is used for various purposes such as a large billboard that displays and broadcasts the main game scenes.

[0004] Such a large display device can be manufactured in a size comparable to the outer wall of a building. However, it is very difficult to manufacture an ultra-large flat panel display device using conventional technology. To solve this problem, a plurality of display panels can be arranged and assembled in a tiling manner to realize a large display device, rather than manufacturing a large display device with a single panel.

[0005] This type of display device is called a tiled display device. Since a tiled large display device can be manufactured by assembling multiple display panels, a seam area (which is a connecting portion of the display panel) is identified when the gap between the display panels is greater than a specific gap. In addition, since multiple display panels can be arranged and combined on the same plane, it may be necessary to minimize the spacing between the panels on the XY plane and have no height difference on the Z axis. In a large display device that can freely change the size by combining multiple display panels in a matrix manner, the display panels to be combined are arranged on a plane at the same height, and they can be combined on the same plane without spacing errors. Therefore, a new connection structure is required to easily achieve this condition. Summary of the invention

[0006] In order to solve the above problems, an object of the present disclosure is to provide a display device formed over a large area by assembling a plurality of unit display devices (or unit display panels) in a tiled manner. Another object of the present disclosure is to provide a large-area display device, wherein a uniform low-level voltage and a high-level voltage are maintained over the entire area of ​​the large display device by connecting each power supply terminal provided in the plurality of unit display panels. Yet another object of the present disclosure is to provide an excellent display quality without luminance or brightness deviation in a large-area display device formed by tiling a plurality of unit display panels.

[0007] Another object of the present disclosure is to provide a large-area display device including a connecting member, which can uniformly align the height of the display panel and assemble a plurality of display panels with a uniform seam portion. Still another object of the present disclosure is to provide a display device including a connecting member, by which, after assembling a plurality of display panels in a tiled manner, any one defective display panel can be easily disassembled and then easily replaced with a new display panel in the position of the removed panel.

[0008] In order to achieve the above-mentioned purpose of the present disclosure, the unit display panel according to the present disclosure includes: a substrate; a display area defined at the middle part of the substrate and a non-display area surrounding the display area; a pad portion arranged at the non-display area; an emission layer, which is arranged in the display area on the substrate; and a plurality of power terminals arranged outside the pad portion in the non-display area, wherein the plurality of power terminals are arranged at the outermost side of the substrate and are configured to supply voltage to drive the emission layer.

[0009] In one example, the power terminal includes: a first terminal connected to a low-level pad in the pad portion; and a second terminal connected to a high-level pad in the pad portion.

[0010] In one example, the first terminal is divided into a plurality of first terminals, and the plurality of first terminals are arranged at a predetermined distance on at least one side of the substrate. The second terminal is divided into a plurality of second terminals, and the plurality of second terminals are arranged between two adjacent first terminals.

[0011] In one example, at least one pair of first terminals and second terminals is disposed on each of four sides of the substrate.

[0012] In one example, the first terminal is disposed along a periphery of the substrate. The second terminal is parallel to the first terminal.

[0013] In one example, the first terminal has a closed line along a perimeter of the substrate, and the second terminal has another closed line along a perimeter of the substrate.

[0014] In one example, the unit display panel also includes: an encapsulation layer covering the emission layer; a circuit board including a timing controller and disposed on the encapsulation layer; and a flexible film including a source driver integrated circuit, one side of the flexible film being connected to the circuit board and the other side being connected to the pad portion.

[0015] In addition, the large-area display device according to the present disclosure includes: a cover plate; a plurality of unit display panels, the plurality of unit display panels being arranged on one surface of the cover plate, each of the unit display panels including: a substrate; a display area defined at a middle portion of the substrate; a non-display area surrounding the display area; a pad portion arranged in the non-display area; a first terminal, which is arranged outside the pad portion in the non-display area; and a second terminal separated from the first terminal, which is arranged outside the pad portion in the non-display area; and a connecting member, which is arranged between two unit display panels, the connecting member respectively connecting the first terminal of the unit display panel and the second terminal of the unit display panel.

[0016] In one example, the plurality of unit display panels are arranged in a matrix including n rows and m columns (where n and m are natural numbers greater than 1). The connecting member includes: a first member disposed between two unit display panels adjacent to each other in a column direction; and a second member disposed between two unit display panels adjacent to each other in a row direction.

[0017] In one example, the first member includes: a first link line connecting first terminals of two adjacent unit display panels; and a second link line connecting second terminals of two adjacent unit display panels and electrically isolated from the first terminal.

[0018] In one example, the second member includes: a first link line connecting first terminals of two adjacent unit display panels; and a second link line connecting second terminals of two adjacent unit display panels and electrically isolated from the first terminal.

[0019] In one example, the first member and the second member are assembled in an "X" shape at corners where four unit display panels are joined.

[0020] In one example, the first member and the second member have a rod shape disposed between two adjacent unit display panels. The connecting member further includes: a central member having a "+" shape, the central member being fastened together with the first member and the second member and being disposed at a corner where four unit display panels are joined.

[0021] In one example, the first terminal is divided into a plurality of first terminals, and the plurality of first terminals are arranged at a predetermined distance on at least one side of the substrate. The second terminal is divided into a plurality of second terminals, and the plurality of second terminals are arranged between two adjacent first terminals. The connecting member includes: a substrate having a certain width and a certain length; a first link line extending from one end to the other end across the width to correspond to the first terminal; a second link line extending from one end to the other end across the width to correspond to the second terminal; and a passivation layer covering the middle (middle) of the first link line and the second link line, and exposing both ends of the first link line and the second link line.

[0022] In one example, the first terminal is arranged along the periphery of the substrate. The second terminal is arranged parallel to the first terminal. The connecting member includes: a substrate having a certain width and a certain length; a first link line on the substrate, which extends from one end to the other end across the width to correspond to the first terminal; an insulating layer, which covers the first link line and exposes both ends of the first link line; a second link line on the insulating layer, which extends from one end to the other end across the width to correspond to the second terminal; and a passivation layer, which covers the second link line and exposes both ends of the first link line and the second link line.

[0023] In one example, the large-area display device also includes: a first extension line under the insulating layer, the first extension line spanning the length to connect the two ends of the first link line, and corresponding to the first terminal; and a second extension line under the insulating layer, the second extension line spanning the length to connect the two ends of the second link line, and corresponding to the second terminal.

[0024] A large-area display device according to the present disclosure includes an assembly mechanism, wherein, after a plurality of display panels having power terminals on the outermost sides are arranged in a matrix manner, a connecting member can be used to connect the power terminals of adjacent display panels. Therefore, in a large-area display device formed by tiling a plurality of unit display panels, all power terminals of all unit display panels are connected to each other. As a result, there is no voltage drop or voltage fluctuation in the high-level voltage and the low-level voltage over the entire display area of ​​the large-area display device. Therefore, the present disclosure can provide a large-area display device with excellent image quality, which has uniform brightness over the entire display screen.

[0025] In addition to the effects of the present disclosure described above, other features and advantages of the present disclosure may be described below or may be clearly understood by those skilled in the art from the following description and explanation below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0027] Figure 1 is a perspective view for illustrating the overall appearance of a large-area display device assembled in a tiled manner according to the present disclosure.

[0028] Figure 2 is a plan view for illustrating the structure of a unit display panel according to the present disclosure.

[0029] Figure 3 It is along Figure 2 Cross-sectional view along the cutting line II'.

[0030] Figure 4 is a plan view for illustrating the structure of a large-area display device according to a first embodiment of the present disclosure, in which a plurality of unit display panels are assembled in a tiled manner.

[0031] Figure 5 It is along Figure 4 Cross-sectional view along cutting line II-II'.

[0032] Figure 6 is an enlarged perspective view for illustrating the structure of a joining portion in the large-area display device according to the first embodiment of the present disclosure.

[0033] Figure 7 It is along Figure 6 Cross-sectional view along the cutting line III-III'.

[0034] Figure 8is a plan view for illustrating the structure of a unit display panel according to a second embodiment of the present disclosure.

[0035] Fig. 9 is a plan view for illustrating the structure of a large-area display device according to a second embodiment of the present disclosure.

[0036] Fig. 10A and Fig. 10B : is a graph for showing that the problem of a drop in power supply voltage is improved by a connection member in the large display device according to the second embodiment of the present disclosure.

[0037] Fig.11 is a plan view for illustrating the structure of a unit display panel according to a third embodiment of the present disclosure.

[0038] Fig.12 is a plan view for illustrating the structure of a large-area display device according to a third embodiment of the present disclosure.

[0039] Fig.13 is an enlarged perspective view for illustrating the structure of a joining portion in a large-area display device according to a third embodiment of the present disclosure.

[0040] Fig.14A It is along Fig.13 Cross-sectional view along cutting line IV-IV'.

[0041] Fig. 14B It is along Fig.13 Cross-sectional view along the cutting line V-V'.

[0042] Fig.15A According to another example along Fig.13 Cross-sectional view along cutting line IV-IV'.

[0043] Fig. 15B According to another example along Fig.13 Cross-sectional view along the cutting line V-V'.

[0044] Fig.16 is a plan view for illustrating another example of a connection member for connecting a plurality of unit display panels according to the present disclosure. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are shown in the accompanying drawings. In all drawings, the same reference numerals will be used as much as possible to represent the same or similar parts. In the specification, it should be noted that similar reference numerals that have been used to represent similar elements in other drawings will be used for the element as much as possible. In the following description, when functions and configurations known to those skilled in the art are irrelevant to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows. Through the embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and their implementation methods will be clarified. However, the present disclosure can be embodied in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0046] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details illustrated. Throughout the text, like reference numerals refer to like elements. In the following description, when it is determined that a detailed description of a related known function or configuration would unnecessarily obscure the main points of the present disclosure, the detailed description will be omitted.

[0047] In the case where “including,” “having,” and “comprising” described in the present specification are used, another part may also be present unless “only” is used. Terms in the singular form may include plural forms unless otherwise noted.

[0048] When interpreting an element, although there is no explicit description, the element is interpreted as including the error range.

[0049] When describing a positional relationship, for example, when describing the positional order as "on", "above", "below", and "next", a situation where there is no contact between them may be included unless "just" or "directly" is used. If it is mentioned that a first element is positioned "on" a second element, this does not mean that the first element is substantially positioned above the second element in the figure. The upper and lower parts of the relevant objects may change depending on the orientation of the objects. Therefore, the situation where the first element is positioned "on" the second element includes the situation where the first element is positioned "below" the second element in the figure or in the actual configuration and the situation where the first element is positioned "above" the second element.

[0050] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "directly" or "directly" is used.

[0051] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0052] The “X-axis direction”, “Y-axis direction”, and “Z-axis direction” may not only be interpreted as a geometric relationship in which the relationship is perpendicular to each other, but may mean that the configuration of the present disclosure has a wider range in which it can normally operate.

[0053] When describing the elements of the present disclosure, terms such as first, second, A, B, (a) and (b) may be used. These terms are only used to distinguish elements from other elements, and these terms are not limited in the nature, order, sequence or quantity of the elements. When an element is described as "linked", "connected" or "connected" to another element, unless otherwise stated, the element may be directly connected to the other element or indirectly connected to the other element. It should be understood that other elements may be "between" the elements connected or connected.

[0054] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" can include all combinations of two or more elements selected from the first, second, and third elements, as well as each element in the first, second, and third elements.

[0055] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be partially or entirely connected or combined with each other, and can interoperate and be driven technically differently from each other. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0056] The "display device" in this application may include a liquid crystal module (LCM), an organic light emitting display module (OLED module) or a quantum dot module (QD Module), which has a display panel and a driver for driving the display panel. The "display device" may also include a finished product or final product including an LCM, an OLED module or a QD module, such as a notebook computer, a television, a computer monitor, a device device with an automotive device or other modules for a vehicle, a complete set of electronic devices or a complete set of devices (or complete sets of devices), such as a smart phone or a mobile electronic device.

[0057] Therefore, the “display device” may be any of a display device such as an LCM, an OLED module, and a QD module, an application device including the LCM, the OLED module, or the QD module, or a complete device for a final device for an end user.

[0058] In another example, an LCM, an OLED module, or a QD module may be referred to as a "display device," and a final electronic device including the LCM, OLED module, or QD module may be referred to as a "set." For example, a display device may include a display panel of a liquid crystal display or an organic electroluminescent display, and a source printed circuit board (PCB) for driving the display panel. A set may include a display device and a setting PCB or a control PCB that drives the set itself by being connected to the display device and the source PCB.

[0059] The display panel according to the embodiment of the present disclosure may include a liquid crystal display panel, an organic light emitting diode display panel, and an electroluminescent display panel, but is not limited thereto. For example, the display panel may have any structure in which the display panel can vibrate to generate sound. In addition, the display panel applied to the display device according to the embodiment of the present disclosure is not limited to the shape or size of the display panel.

[0060] In the case where the display panel is a liquid crystal display panel, the display panel may include a plurality of gate lines, a plurality of data lines, and a plurality of pixels (or sub-pixels) defined by the gate lines and the data lines. The display panel may include: an array substrate including a thin film transistor as a switch element for controlling the light transmittance of each pixel; an upper substrate including a color filter (color filter) and / or a black matrix; and a liquid crystal layer disposed between the array substrate and the upper substrate.

[0061] In the case where the display panel is an organic light emitting diode display panel, the display panel may include a plurality of gate lines, a plurality of data lines, and a plurality of pixels (or sub-pixels) defined by the gate lines and the data lines. The display panel may include: an array substrate including a thin film transistor for selectively applying a voltage to each pixel; an organic light emitting layer on the array substrate; and an encapsulation substrate disposed on the array substrate for covering the organic light emitting layer. The encapsulation substrate may protect the thin film transistor and the organic light emitting layer from any external impact and prevent moisture and oxygen from penetrating into the organic light emitting layer. In addition, the organic light emitting layer formed on the array substrate may be replaced by an inorganic light emitting layer, a quantum dot light emitting layer, or a micro light emitting diode element.

[0062] Hereinafter, examples of display devices according to the present disclosure will be described in detail with reference to the accompanying drawings. When assigning reference numerals to the elements of each drawing, even if they are shown in different drawings, the same parts are given the same reference numerals as much as possible. Although the drawings represent exemplary embodiments of the present disclosure, the drawings are not necessarily drawn to scale, and certain features may be enlarged or omitted in order to better illustrate and explain the present application.

[0063] refer to Figure 1 , a display device assembled in a tiled manner according to the present disclosure will be described. Figure 1 is a perspective view for illustrating the overall appearance of a large-area display device assembled in a tiled manner according to the present disclosure.

[0064] For the sake of illustration, add Figure 1 The coordinate system shown in FIG. 1 is a coordinate system shown in FIG. 2. For example, the large-area display device WDP can be formed by assembling a plurality of unit display panels SDP on a cover plate CS in a tiling method, and the cover plate CS is arranged on a wall (wall surface) of the XY plane. The large-area display device WDP can provide video information in the Z direction. The viewer can view the video image provided by the large-area display device by viewing the XY plane in the Z direction.

[0065] like Figure 1 As shown, a plurality of unit display panels SDP may be arranged on the wall structure in a matrix manner. Figure 1 The diagram shows a structure in which 30 unit display panels are tiled, with six display panels in the row direction and five display panels in the column direction. It is not limited to this, and a large-area display device WDP of a desired size can be formed using a greater or lesser number of unit display panels SDP. The cover plate CS may be disposed on the top surface of the unit display panel SDP, and may be a reference panel on which a plurality of unit display panels SDP are assembled in a tiled manner. In addition, the cover plate CS may have a protective function or an optical function that enhances the characteristics of the unit display panel SDP.

[0066] Even though not shown in the figure, a plurality of frames (i.e., rear frames) may be applied to arrange the unit display panels SDP in a tiled manner. For example, the rear frames may be fixed or mounted on a wall structure in a matrix manner by a fixing member. The fixing member may have a coupling structure (such as an anchor, a screw, a concrete nail, etc.) for fixing the frame to the wall structure. On each rear frame fixed to the wall structure, each unit display panel SDP may be mounted.

[0067] Hereinafter, various embodiments of a structure for assembling a unit display panel SDP will be described. In particular, with reference to the accompanying drawings, various embodiments according to the present disclosure will be provided for explaining a coupling mechanism (mechanism) in which the difference between a high-level voltage and a low-level voltage applied to the unit display panel SDP is maintained at a constant value by connecting a power terminal, which is the most important element for maintaining display quality.

[0068] <First Embodiment>

[0069] In the following, reference Figures 2 to 7 , the first embodiment of the present disclosure will be described. First, refer to Figure 2 and Figure 3 , the structure of a unit display panel according to a first embodiment of the present disclosure will be described. Figure 2 is a plan view for illustrating the structure of a unit display panel according to the present disclosure. Figure 3 It is along Figure 2 Cross-sectional view along the cutting line II'.

[0070] refer to Figure 2 , the unit display panel SDP according to the present disclosure may include a substrate SUB, a gate driver (or scan driver) 200 , a data pad part 300 , a source driving integrated circuit 410 , a flexible film 430 , a circuit board 450 , and a timing controller 500 .

[0071] The substrate SUB may include an insulating material or a flexible material. The substrate SUB may be made of glass, metal, or plastic, but the embodiment is not limited thereto. When the unit display panel includes a flexible display panel, the substrate SUB may be made of a flexible material such as a plastic material. For example, the substrate SUB may include a polyimide material.

[0072] The substrate SUB may include a display area DA and a non-display area NDA. The display area DA is an area for presenting a video image and may be defined at most of the middle portion of the substrate SUB, but the embodiment is not limited thereto. The display area DA may include a plurality of scan lines (SL) (or gate lines), a plurality of data lines DL, a plurality of drive current lines VD, and a plurality of pixels P. The pixel P may be defined as an area surrounded by the scan lines SL, the data lines DL, and the drive current lines VD. The pixel P may include a plurality of sub-pixels, and each sub-pixel may be surrounded by the scan lines SL and the data lines DL.

[0073] The non-display area NDA may be an area where no video image is provided, and may be defined at a peripheral area of ​​the substrate SUB to surround all or part of the display area DA. In the non-display area NDA, a gate driver 200 and a data pad portion 300 are disposed.

[0074] The gate driver 200 may supply a scan signal (or gate signal) to the scan line SL according to a gate signal received from the timing controller 500. The gate driver 200 may be formed as a GIP (Gate Driver In Panel) type at a non-display area NDA outside a display area DA of a substrate SUB. The GIP type refers to a structure in which the gate driver 200 may be directly formed on a substrate SUB.

[0075] The data pad portion 300 may supply a data signal to the data line DL according to a data control signal received from the timing controller 500. The data pad portion 300 may be manufactured in a driving chip type and mounted on a flexible film 430. The flexible film 430 may be attached at a non-display area NDA surrounding a display area DA in the substrate SUB by a TAP (Tape Automated Bonding) method.

[0076] The source driver integrated circuit 410 may receive digital video data and a source control signal from the timing controller 500. The source driver integrated circuit 410 may convert the digital video data into analog data voltages according to the source control signal and then supply them to the data lines DL. When the source driver integrated circuit 410 is manufactured into a single chip type, it may be mounted on the flexible film 430 by a COF (Chip on Film) or COP (Chip on Plastic) method.

[0077] The flexible film 430 may include a plurality of bus bars that connect the data pad portion 300 and the source driver integrated circuit 410, and connect the data pad portion 300 and the circuit board 450. The flexible film 430 may be attached to the data pad portion 300 using an anisotropic conductive film, so the data pad portion 300 may be connected to the bus bars on the flexible film 430.

[0078] The circuit board 450 may be attached to the flexible film 430. The circuit board 450 may have a plurality of circuits formed in a driving chip type. For example, the timing controller 500 may be mounted on the circuit board 450. The circuit board 450 may be a printed circuit board or a flexible printed circuit board.

[0079] The timing controller 500 may receive digital video data and a timing signal from an external system board through a cable (not shown) attached to the circuit board 450. The timing controller 500 may generate a gate control signal for controlling the operation timing of the gate driver 200 based on the timing signal, and may generate a source control signal for controlling the source driver integrated circuit 410 based on the timing signal. The timing controller 500 may supply the gate control signal to the gate driver 200, and supply the source control signal to the source driver integrated circuit 410. For another example, the timing controller 500 may be formed as a single chip type with the source driver integrated circuit 410, and then mounted on the substrate SUB.

[0080] The unit display panel SDP according to the first embodiment of the present disclosure may further include a power connection terminal TD disposed outside the non-display area NDA. Taking the organic light emitting diode display panel as an example, the connection terminal TD may include a low-level terminal VSS receiving a low-level voltage and a high-level terminal VDD receiving a high-level voltage. The light emitting diode may be driven by a voltage corresponding to a data signal having any voltage value selected between the low-level voltage and the high-level voltage. Therefore, it is very important that the low-level voltage and the high-level voltage may be supplied to the organic light emitting diode display panel at constant values, respectively.

[0081] The low level terminal VSS and the high level terminal VDD may be connected to the data pad portion 300. The data pad portion 300 may include a plurality of pads for receiving a low level voltage and a high level voltage. For example, the low level terminal VSS may be provided at the outside of the substrate SUB to extend from the low level pad provided at the data pad portion 300. In addition, the high level terminal VDD may be provided at the outside of the substrate SUB to extend from the high level pad provided at the data pad portion 300.

[0082] When necessary, the low level terminal VSS and the high level terminal VDD may be further disposed near the gate driver 200 at the outer side of the substrate SUB. For example, when the unit display panel SDP has a rectangular shape, the data pad portion 300 may be disposed on the lower side, and the gate driver 200 may be disposed on the right side. In this case, a plurality of low level terminals VSS and a plurality of high level terminals VDD may be arranged at predetermined intervals on the lower side of the substrate SUB. In addition, a pair of low level terminals VSS and a high level terminal VDD may be disposed at the upper corner of the right side, and another pair of level terminals VSS and a high level terminal VDD may be disposed at the lower corner of the right side.

[0083] refer to Figure 3 , shows a cross-sectional structure of a unit display panel SDP according to a first embodiment of the present disclosure. Figure 3 It is along Figure 2Cross-sectional view along the cutting line II'.

[0084] The emission layer EL may be formed in the display area DA on the substrate SUB. The encapsulation layer EN may be disposed on the emission layer EL. Taking the organic light emitting diode display panel as an example, the emission layer EL may include a thin film transistor and an organic light emitting diode. The thin film transistor may be connected to the organic light emitting diode to drive it. As it is driven by the thin film transistor, the organic light emitting diode may present light corresponding to the video image.

[0085] The unit display panel according to the present disclosure has a structure for realizing a large-area display device by tiling the unit display panels in a matrix manner, and thus a detailed structure of each unit display panel may not be described.

[0086] The encapsulation layer EN, as a member for protecting the emission layer EL, may prevent any foreign matter or gas from invading the emission layer EL from the external environment. The encapsulation layer EN may have a structure in which inorganic layers and organic layers are alternately stacked.

[0087] The circuit board 450 may be located above the encapsulation layer EN. The circuit board 450 may include a timing controller 500. One side of the circuit board 450 may be connected to the data pad portion 300 through a flexible film 430. On the flexible film 430, a source driver integrated circuit 410 may be mounted. One side of the source driver integrated circuit 410 may be connected to the timing controller 500 through the flexible film 430, and the other side of the source driver integrated circuit 410 may be connected to the data pad portion 300 through the flexible film 430.

[0088] In the non-display area NDA of the substrate SUB of the unit display panel SDP, the low level terminal VSS and the high level terminal VDD are arranged at the outermost side. By connecting the low level terminal VSS and the high level terminal VDD of one unit display panel SDP with the low level terminal VSS and the high level terminal VDD of another adjacent unit display panel SDP, the low level voltage and the high level voltage can be respectively maintained at a constant voltage without any fluctuation. Here, the low level terminal VSS and the high level terminal VDD can be elements for supplying a basic voltage to drive the emission layer EL, and can be called "power supply terminals".

[0089] refer to Figure 4 and Figure 5 , the structure of a large-area display device formed by tiling unit display panels according to the first embodiment of the present disclosure will be described. Figure 4 is a plan view for illustrating the structure of a large-area display device according to a first embodiment of the present disclosure, in which a plurality of unit display panels are assembled in a tiled manner. Figure 5 It is along Figure 4Cross-sectional view along cutting line II-II'.

[0090] The large-area display device according to the first embodiment of the present disclosure may have a structure in which a plurality of unit display panels are arranged in a matrix including n rows and m columns. Figure 4 The case where four unit display panels are arranged in a 2×2 matrix to form a large-area display device is shown. For example, by assembling or arranging four unit display panels, each of which has a diagonal length of 80 inches, a large-area display device with a diagonal length of 160 inches can be configured.

[0091] refer to Figure 4 The large area display device WDP according to the first embodiment may include a first unit display panel SDP1, a second unit display panel SDP2, a third unit display panel SDP3, and a fourth unit display panel SDP4. Between each two of the unit display panels SDP1, SDP2, SDP3, and SDP4, a connection member LM may be provided. The connection member LM may include a horizontal member LM1 and a vertical member LM2.

[0092] For example, a horizontal member LM1 may be disposed between the first unit display panel SDP1 and the second unit display panel SDP2. A vertical member LM2 may be disposed between the second unit display panel SDP2 and the third unit display panel SDP3. A horizontal member LM1 may be disposed between the third unit display panel SDP3 and the fourth unit display panel SDP4. A vertical member LM2 may be disposed between the fourth unit display panel SDP4 and the first unit display panel SDP1.

[0093] The horizontal member LM1 and the vertical member LM2 may be joined to each other in an "X" shape at a point where the four unit display panels SDP1, SDP2, SDP3, and SDP4 meet. To this end, ends of the horizontal member LM1 and the vertical member LM2 may have a bracket shape like "<" or ">".

[0094] refer to Figure 5 , the cross-sectional structure of the joint between the first unit display panel SDP1 and the second unit display panel SDP2 will be described. The large-area display device WDP according to the first embodiment of the present disclosure can be formed by tiling four unit display panels SDP1, SDP2, SDP3 and SDP4 on the cover plate CS (by arranging them on the same equal height plane). For example, on the cover plate CS, the first unit display panel SDP1 and the second unit display panel SDP2 are arranged so that their data pad portions 300 are adjacent to each other.

[0095] In this case, each of the first unit display panel SDP1 and the second unit display panel SDP2 may have an emission layer EL formed in the display area DA and an encapsulation layer EN covering the emission layer EL, respectively. In addition, the data pad portions 300 may be respectively disposed outside the encapsulation layer EN. The data pad portions 300 may be respectively connected to one side of the flexible film 430 using an anisotropic conductive film ACF. Each of the other sides of the flexible film 430 may be connected to the circuit board 400. On the flexible film 430, a source driver integrated circuit 410 may be mounted. Here, since the first unit display panel SDP1 and the second unit display panel SDP2 have the same structure, the same reference numerals are used for the same elements in the figure.

[0096] A high level terminal VDD is disposed outside each data pad 300 of the first unit display panel SDP1 and the second unit display panel SDP2. The first unit display panel SDP1 and the second unit display panel SDP2 are arranged so that their sides contact each other on the same level plane. Therefore, the high level terminals VDD are arranged adjacent to each other on the same level plane.

[0097] The connection member LM may be disposed on a junction of the first unit display panel SDP1 and the second unit display panel SDP2. Here, the connection member LM may be a member for connecting the low level terminal VSS of the first unit display panel SDP1 and the low level terminal VSS of the second unit display panel SDP2. Therefore, the connection member LM may include a second link line LK2 for electrically connecting the low level terminal VSS of the first unit display panel SDP1 and the low level terminal VSS of the second unit display panel SDP2. Figure 5 However, the connection member LM may further include a first link line LK1 for electrically connecting the high level terminal VDD of the first unit display panel SDP1 and the high level terminal VDD of the second unit display panel SDP2.

[0098] In the following, reference Figure 6 and Figure 7 , a connection structure of tile parts in a large-area display device according to a first embodiment of the present disclosure will be described. Figure 6 is an enlarged perspective view for illustrating the structure of a joining portion in the large-area display device according to the first embodiment of the present disclosure. Figure 7 It is along Figure 6 Cross-sectional view along the cutting line III-III'.

[0099] refer to Figure 6 and Figure 7, the connecting member LM may include a substrate SB, a lower insulating layer ID, a first link line LK1, a second link line LK2, and a passivation layer IN. The substrate SB may be an element for physically and electrically connecting the unit display panels SDP1, SDP2, SDP3, and SDP4, so it is preferred that the substrate SB may be made of a rigid material. The substrate SB may be a thin and long plate having a width W and a length L. Here, the width W of the substrate SB may have a size for covering all adjacent power terminals VDD and VSS between the unit display panels SDP1, SDP2, SDP3, and SDP4. The length L of the substrate SB may correspond to the length of one side of the unit display panel to cover the power terminals VDD and VSS.

[0100] In detail, the horizontal member LM1 may have a length corresponding to a transverse side of the unit display panel SDP, and the vertical member LM2 may have a length corresponding to a longitudinal side of the unit display panel. Figure 6 and Figure 7 A representative type of the horizontal member LM1 is shown. Since the vertical member LM2 has the same structure as the horizontal member LM1, the reference numerals of the horizontal member and the vertical member are representatively represented as "LM".

[0101] The lower insulating layer ID may cover all surfaces of one side of the substrate SB. In particular, it is preferred that the lower insulating layer ID may cover all surfaces of the substrate SB on which the link lines LK1 and LK2 are formed. In the case where the substrate SB is made of a metal material, in order to ensure the strength of the substrate SB, it is preferred that the lower insulating layer ID include a highly insulating material for insulating the link lines LK1 and LK2 from each other.

[0102] The first link line LK1 may be a line configured to link high-level terminals VDD adjacent to each other. For example, the first link line LK1 may have a segment extending in the width W direction, one end of the segment corresponding to the high-level terminal VDD provided on the first unit display panel SDP1, and the other end corresponding to the high-level terminal VDD provided on the second unit display panel SDP2.

[0103] In addition, the second link line LK2 may be a line provided to link the low-level terminals VSS adjacent to each other. For example, the second link line LK2 may have a section extending in the width W direction, one end of the section corresponding to the low-level terminal VSS provided on the first unit display panel SDP1, and the other end corresponding to the low-level terminal VSS provided on the second unit display panel SDP2. The first link line LK1 and the second link line LK2 may be sections separated from each other to correspond to the interval gap between the high-level terminal VDD and the low-level terminal VSS.

[0104] The passivation layer IN may cover the middle part of the first link line LK1 and the second link line LK2, but expose both ends. The passivation layer IN may be provided to prevent the middle part of the first link line LK1 and the second link line LK2 from being short-circuited by other conductive materials or being broken due to physical damage. Since the first link line LK1 should be connected to the high-level terminal VDD and the second link line LK2 should be connected to the low-level terminal VSS, both ends thereof should be exposed. For other examples, a contact hole may be formed at the passivation layer, and a pad may be formed therein.

[0105] By the above method, a plurality of unit display panels SDP can be assembled in a matrix manner, and the power supply terminals VDD and VSS can be respectively linked by installing the connection member LM. Therefore, all high-level terminals VDD can be electrically connected, and all low-level terminals VSS can be electrically connected, so that they can maintain the same voltage value over the entire area of ​​the assembled unit display panel.

[0106] For an organic light emitting diode display device, the brightness of any one pixel can be limited by a voltage selected between a low level voltage and a high level voltage. Therefore, when the low level voltage and the high level voltage applied to the unit display panel SDP are the same, no brightness difference will occur between the unit display panels SDP. According to a first embodiment of the present disclosure, all low level terminals of all unit display panels are connected, and all high level terminals of all unit display panels are connected, so that the high level voltage and the low level voltage can be maintained as a uniform value over the entire area of ​​the assembled unit display panel. As a result, due to the tiling of the unit display panels, the present disclosure can provide a large-area display device with excellent display quality without luminance (or brightness) deviation.

[0107] <Second Embodiment>

[0108] In the following, reference Figures 8 to 9 as well as Fig. 10A and Fig. 10B , a coupling (or assembling) structure of unit display panels for forming a large-area display device according to a second embodiment of the present disclosure will be described. Figure 8 is a plan view for illustrating the structure of a unit display panel according to a second embodiment of the present disclosure. Fig. 9 is a plan view for illustrating the structure of a large-area display device according to a second embodiment of the present disclosure. Fig. 10A and Fig. 10B : is a graph for showing that the problem of a drop in power supply voltage is improved by a connection member in the large display device according to the second embodiment of the present disclosure.

[0109] First reference Figure 8, the structure of the unit display panel according to the second embodiment will be described. Compared with the first embodiment, the unit display panel according to the second embodiment may further include: a plurality of high-level terminals VDD and a plurality of low-level terminals VSS provided on the upper side of the substrate SUB where the data pad portion 300 is not provided. The high-level terminal VDD may be connected to one end of a high-level line VDDL across the display area DA, wherein the other end of the high-level line VDDL is connected to the data pad portion 300. In addition, the low-level terminal VSS may be connected to one end of a low-level line VSSL across the display area DA, wherein the other end of the low-level line VSSL is also connected to the data pad portion 300.

[0110] In addition, on the left side of the substrate SUB where the gate driver 200 is not provided, a pair of high level terminals VDD and low level terminals VSS are provided at the upper part, and another pair of high level terminals VDD and low level terminals VSS are provided at the lower part. All high level terminals VDD can be connected to each other through high level lines VDDL. The high level lines VDDL can be arranged along the edge of the substrate SUB to form a closed line. In addition, all low level terminals VSS can be connected to each other through low level lines VSSL. The low level lines VSSL can also be arranged along the edge of the substrate SUB to form another closed line.

[0111] Next, refer to Fig. 9 , use the tiling method to place 4 Figure 8 The unit display panels shown are assembled on the same equal height plane. The main feature of the second embodiment different from the first embodiment may be a tiled structure of the first unit display panel SDP1 and the second unit display panel SDP2. For the first embodiment, the sides having the data pad portion 300 are bonded to each other. However, for the second embodiment, the opposite side of the side having the data pad portion 300 in the second unit display panel SDP2 may be bonded to the side having the data pad portion 300 in the first unit display panel SDP1.

[0112] The unit display panel SDP may receive a power supply voltage from the timing controller 500 via the flexible film 430. A low level voltage and a high level voltage are received from the timing controller 500. That is, a high level voltage signal and a low level voltage signal are first supplied to the data pad portion 300. Then, these power supply voltage signals may flow through the display area DA, and thus when these power supply voltage signals flow to the opposite side of the side having the data pad portion 300, a voltage drop may occur.

[0113] However, according to the second embodiment, all high level terminals VDD provided in the first unit display panel SDP1 are connected to the high level line VDDL. In addition, all low level terminals VSS provided in the first unit display panel SDP1 are also connected to the low level line VSSL.

[0114] For example, two high-level terminals VDD facing each other across the unit display panel SDP may have the same voltage value. That is, as the high-level voltage signal is transmitted on the display area DA, the high-level voltage may not drop. Fig. 10A As shown in the curve graph, the voltages at the two high-level terminals VDD opposite to each other have the same high voltage.

[0115] In addition, two low-level terminals VSS facing each other across the unit display panel SDP may have the same voltage value. That is, as the low-level voltage signal is transmitted on the display area DA, the low-level voltage may not drop. Fig. 10B As shown in the curve graph, the voltages at the two low-level terminals VSS opposite to each other have the same high voltage.

[0116] Fig. 10A The curve diagram shown shows the variation curve of the high level voltage in the unit display panel. Fig. 10B The graph shown shows a variation curve of a low level voltage in a unit display panel. The solid line is a curve of a power supply voltage that varies in a unit display panel according to the second embodiment, and the dotted line is a curve of a power supply voltage that varies in a unit display panel according to the prior art.

[0117] Referring to the solid line, the power supply voltage of the upper side ③ of the unit display panel may have the same voltage value as the power supply voltage of the lower side ①. In the middle portion ② of the unit display panel SDP, a voltage drop may occur slightly because of a natural voltage drop that occurs as power is consumed. However, this voltage fluctuation due to the voltage drop occurs naturally in electronic devices, and the overall performance of the electronic device is designed in consideration of this voltage drop. Therefore, it can be regarded as a normal fluctuation that does not affect the image quality.

[0118] Therefore, in the large-area display device according to the second embodiment, the power supply voltage applied to each unit display panel can be maintained at the same high voltage value. As a result, all unit display panels can provide the same luminance or brightness and ensure excellent video image quality. In addition, no matter how large the display device is configured, voltage drop or voltage fluctuation does not occur as the length of the line increases.

[0119] <Third Embodiment>

[0120] In the following, reference Figures 11 to 13 , the third embodiment of the present disclosure will be described. First, refer to Fig.11 , a unit display panel according to a third embodiment will be described. Fig.11 is a plan view for illustrating the structure of a unit display panel according to a third embodiment of the present disclosure.

[0121] Compared with the first embodiment, the unit display panel SDP according to the third embodiment may include a high-level terminal VDD having a closed line, which surrounds the periphery of the substrate SUB. In addition, the unit display panel SDP may also include a low-level terminal VSS having another closed line, which surrounds the periphery of the substrate SUB. The low-level terminal VSS is separated from the high-level terminal VDD by a predetermined distance. For example, the low-level terminal VSS may be arranged at the outermost periphery, and the high-level terminal VDD may be arranged inside the low-level terminal VSS at a predetermined distance.

[0122] The low level terminal VSS and the high level terminal VSS according to the third embodiment may be closed lines with a predetermined width. The low level terminal VSS may be connected to a low voltage line (not shown) disposed in the data pad portion 300 and the display area DA. In addition, the high level terminal VDD may be connected to a driving current line (not shown) disposed in the data pad portion 300 and the display area DA.

[0123] According to the third embodiment, the low level terminal VSS and the high level terminal VDD may be exposed on the substrate SUB, and they may have a closed bus shape (here, "bus" refers to a line wider than other lines) surrounding the periphery of the substrate SUB.

[0124] In the following, reference Fig.12 , Fig.13 , Fig.14A and Fig. 14B , a large-area display device according to a third embodiment of the present disclosure will be described. Fig.12 is a plan view for illustrating the structure of a large-area display device according to a third embodiment of the present disclosure. Fig.13 is an enlarged perspective view for illustrating the structure of a joining portion in a large-area display device according to a third embodiment of the present disclosure. Fig.14A It is along Fig.13 Cross-sectional view along cutting line IV-IV'. Fig. 14B It is along Fig.13 Cross-sectional view along the cutting line V-V'.

[0125] The large-area display device according to the third embodiment may have a structure in which a plurality of unit display panels SDP may be arranged in a matrix manner including n rows and m columns. Fig.12 Focus on the joint of four unit display panels arranged in a 2×2 matrix. For example, by tiling four 80-inch unit display panels in a 2×2 matrix, a 160-inch large-area display device can be configured. For another example, by tiling 64 24-inch unit display panels in an 8×8 matrix, a 192-inch large-area display device can be configured.

[0126] refer to Fig.12 , the large area display device WDP according to the third embodiment may include a first unit display panel SDP1, a second unit display panel SDP2, a third unit display panel SDP3, and a fourth unit display panel SDP4. In addition, a connection member LM may be provided between the unit display panels SDP1, SDP2, SDP3, and SDP4. The connection member LM may include a horizontal member LM1 and a vertical member LM2.

[0127] For example, a horizontal member LM1 may be disposed between the first unit display panel SDP1 and the second unit display panel SDP2. A vertical member LM2 may be disposed between the second unit display panel SDP2 and the third unit display panel SDP3. A horizontal member LM1 may be disposed between the third unit display panel SDP3 and the fourth unit display panel SDP4. A vertical member LM2 may be disposed between the fourth unit display panel SDP4 and the first unit display panel SDP1.

[0128] The horizontal member LM1 and the vertical member LM2 may be joined to each other in an "X" shape at a point where the four unit display panels SDP1, SDP2, SDP3, and SDP4 meet. To this end, ends of the horizontal member LM1 and the vertical member LM2 may have a bracket shape like "<" or ">".

[0129] The cross-sectional structure of the joint portion between the first unit display panel SDP1 and the second unit display panel SDP2 may be similar to Figure 5 The cross-sectional structures shown are the same, so the same description may not be repeated. Fig.12 , Fig.13 , Fig.14A and Fig. 14B , the assembly structure at the tiled portion in the large-area display device according to the third embodiment will be described. Fig.12 The large area display device WDP according to the third embodiment may include four unit display panels SDP1, SDP2, SDP3 and SDP4, which are arranged on the cover substrate CS to be laid on the same equal height plane. For example, on one surface of the cover substrate CS, the data pad portion 300 of the first unit display panel SDP1 may be bonded to the data pad portion 300 of the second unit display panel SDP2.

[0130] The connecting member LM may include a substrate SB, a lower insulating layer ID, a first extension line 1000, a second extension line 2000, an insulating layer IL, a first link line LK1, a second link line LK2, and a passivation layer IN. The substrate SB may be an element for physically and electrically connecting the unit display panels SDP1, SDP2, SDP3, and SDP4, so it is preferred that the substrate SB may be made of a rigid material. The substrate SB may be a thin and long plate having a width W and a length L. Here, the width W of the substrate SB may be a size for covering all adjacent power terminals VDD and VSS between the unit display panels SDP1, SDP2, SDP3, and SDP4. The length L of the substrate SB may correspond to the length of one side of the unit display panel to cover the power terminals VDD and VSS.

[0131] In detail, the horizontal member LM1 may have a length corresponding to a transverse side of the unit display panel SDP, and the vertical member LM2 may have a length corresponding to a longitudinal side of the unit display panel.

[0132] The lower insulating layer ID may cover all surfaces of one side of the substrate SB. In particular, it is preferred that the lower insulating layer ID may cover all surfaces of the substrate SB on which the extension lines 1000 and 2000 and the link lines LK1 and LK2 are formed. In the case where the substrate SB is made of a metal material, in order to ensure the strength of the substrate SB, it is preferred that the lower insulating layer ID may include a highly insulating material for insulating the extension lines 1000 and 2000 and the link lines LK1 and LK2 from each other.

[0133] The first link line LK1 may be a line configured to link high-level terminals VDD adjacent to each other. For example, the first link line LK1 may have a segment extending in the width W direction, one end of the segment corresponding to the high-level terminal VDD provided on the first unit display panel SDP1, and the other end corresponding to the high-level terminal VDD provided on the second unit display panel SDP2.

[0134] In addition, the second link line LK2 may be a line provided to link the low-level terminals VSS adjacent to each other. For example, the second link line LK2 may have a section extending in the width W direction, one end of the section corresponding to the low-level terminal VSS provided on the first unit display panel SDP1, and the other end corresponding to the low-level terminal VSS provided on the second unit display panel SDP2.

[0135] The first link line LK1 and the second link line LK2 may be connected to the high level terminal VDD and the low level terminal VSS, respectively. Therefore, it is preferred that the first link line LK1 and the second link line LK2 may be sections separated from each other.

[0136] A plurality of first link lines LK1 may be arranged at a first predetermined interval along the length direction. In addition, a plurality of second link lines LK2 may be arranged at a second predetermined interval along the length direction. Here, the first link lines LK1 and the second link lines LK2 may be arranged alternately with each other. The first link lines LK1 may be connected to each other through the first extension line 1000, and the second link lines LK2 may be connected to each other through the second extension line 2000.

[0137] For example, the first extension line 1000 may be a bus disposed on the lower insulating layer ID and intersecting the end of the high level terminal VDD. In addition, the second extension line 2000 may be a bus disposed on the lower insulating layer ID and intersecting the end of the low level terminal VSS. The first extension line 1000 may be separated from the second extension line 2000 by a predetermined distance.

[0138] The insulating layer IL may be formed to cover the first extension line 1000 and the second extension line 2000. A plurality of first contact holes CH1 may be formed at the insulating layer IL to expose some portions of the first extension line. In addition, a plurality of second contact holes CH2 may be formed at the insulating layer IL to expose some portions of the second extension line. Preferably, the first contact holes CH1 and the second contact holes CH2 are arranged not to overlap each other but to be staggered along the width W direction.

[0139] On the insulating layer IL, a first link line LK1 and a second link line LK2 are provided. The first link line LK1 may be connected to two first extension lines 1000 separated from each other on the substrate SB through a first contact hole CH1. One of the first extension lines 1000 may be set to correspond to a high level terminal VDD of the first unit display panel SDP1, and the other of the first extension lines 1000 may be set to correspond to a high level terminal VDD of the second unit display panel SDP2. The second link line LK2 may be connected to two second extension lines 2000 separated from each other on the substrate SB through a second contact hole CH2. One of the second extension lines 2000 may be set to correspond to a low level terminal VSS of the first unit display panel SDP1, and the other of the second extension lines 2000 may be set to correspond to a low level terminal VSS of the second unit display panel SDP2.

[0140] The passivation layer IN may cover the middle part of the first link line LK1 and the second link line LK2, but expose both ends. The passivation layer IN may be provided to prevent the middle part of the first link line LK1 and the second link line LK2 from being short-circuited by other conductive materials or being broken due to physical damage. Since the first link line LK1 should be connected to the high-level terminal VDD and the second link line LK2 should be connected to the low-level terminal VSS, both ends thereof should be exposed. For other examples, a contact hole may be formed at the passivation layer, and a pad may be formed therein.

[0141] The first link line LK1 may connect the high level terminal VDD of the first unit display panel SDP1 with the high level terminal VDD of the second unit display panel SDP2. In addition, the first link line LK1 may cross the low level terminal VSS of the first unit display panel SDP1 and the low level terminal VSS of the second unit display panel SDP2. Therefore, the insulating layer IN may be disposed above the first link line LK1, wherein the middle portion of the first link line LK1 may be covered by the insulating layer IN, but both ends of the first link line LK1 may be exposed. In particular, it is preferred that the portion overlapping with the low level terminal VSS may be covered by the insulating layer IN.

[0142] The second link line LK2 can connect the low level terminal VSS of the first unit display panel SDP1 with the low level terminal VSS of the second unit display panel. Since the low level terminals VSS of the first unit display panel SDP1 and the second unit display panel SDP2 are closely adjacent, it is preferred that the insulating layer IN cover the middle portion of the second link line LK2 but expose both ends.

[0143] Here, the insulating layer IN may have a wider width above the first link line LK1 and a narrower width above the second link line LK2. Due to the thickness of the insulating layer IN, the first link line LK1 and the second link line LK2 may have a shape that is sunken from the insulating layer IN. However, when the first link line LK1 is connected to the high-level terminal VDD and the second link line LK2 is connected to the low-level terminal VSS using the anisotropic conductive film ACF, there may be no contact problem. When necessary, in order to ensure contact capability, upper terminals may be further formed at both ends of the first link line LK1 and the second link line LK2 exposed from the insulating layer IN.

[0144] For another example, the connection member LM may have Fig.15A and Fig. 15B The structure shown. Fig.15A According to another example along Fig.13 Cross-sectional view along cutting line IV-IV'. Fig. 15B According to another example along Fig.13 Cross-sectional view along the cutting line V-V'.

[0145] Through Fig.14A and Fig. 14B For comparison, Fig.15A and Fig. 15BIt is shown that the first and second link lines LK1 and LK2 may be disposed under the first and second extension lines 1000 and 2000. The connection member LM may include a substrate SB, a lower insulating layer ID, the first and second link lines LK1 and LK2, an insulating layer IL, the first and second extension lines 1000 and 2000.

[0146] The lower insulating layer ID may be deposited on the substrate SB. The first link line LK1 and the second link line LK2 may be disposed on the lower insulating layer ID. The first link line LK1 may connect two first extension lines 1000 that are adjacent to each other but separated in a tile structure. The second link line LK2 may connect two second extension lines 2000 that are adjacent to each other but separated in a tile structure.

[0147] The first link lines LK1 and the second link lines LK2 may extend across a width W of the substrate SB. A plurality of first link lines LK1 and a plurality of second link lines LK2 may be arranged at a predetermined distance along a length L direction on the substrate SB.

[0148] The insulating layer IL may be deposited on the surface of the substrate SB where the first link line LK1 and the second link line LK2 are formed. The first contact hole CH1 may be formed at the insulating layer IL to expose both ends of the first link line LK1. In addition, the second contact hole CH2 may be formed at the insulating layer IL to expose both ends of the second link line LK2.

[0149] The first extension line 1000 may be formed on the insulating layer IL. The first extension line 1000 may have a segment shape facing the high level terminal VDD of the first unit display panel SDP1. The first extension line 1000 may be connected to one end of the first link line LK1 through the first contact hole CH1. Preferably, the first extension line 1000 may have a segment shape for connecting each of the one ends of the first link line LK1.

[0150] In addition, each of the other ends of the first link lines LK1 may be connected to a first extension line 1000 having a segment shape facing the high level terminal VDD of the second unit display panel SDP2. The first extension lines 1000 of the first unit display panel SDP1 and the second unit display panel SDP2 are separated from each other, but they are connected to each other via the first link lines LK1.

[0151] The two first extension lines 1000 are connected to each other corresponding to the high level terminals VDD of the first and second unit display panels SDP1 and SDP2 , respectively. That is, the high level terminals VDD of the first and second unit display panels SDP1 and SDP2 are electrically connected to each other via the first link line LK1 .

[0152] Likewise, the second extension line 2000 may be formed on the insulating layer IL. The second extension line 2000 may have a segment shape facing the low level terminal VSS of the first unit display panel SDP1. The second extension line 2000 may be connected to one end of the second link line LK2 through the second contact hole CH2. Preferably, the second extension line 2000 may have a segment shape for connecting each of the one ends of the second link line LK2.

[0153] In addition, each of the other ends of the second link lines LK2 can be connected to a second extension line 2000 having a segment shape facing the low level terminal VSS of the second unit display panel SDP2. The second extension lines 2000 of the first unit display panel SDP1 and the second unit display panel SDP2 are separated from each other, but they are connected to each other via the second link lines LK2.

[0154] The two second extension lines 2000 are connected to each other corresponding to the low level terminals VSS of the first and second display panels SDP1 and SDP2, respectively. That is, the low level terminals VSS of the first and second display panels SDP1 and SDP2 are electrically connected to each other via the second link line LK2.

[0155] In reference Fig.15A and Fig. 15B In the example of FIG. 1 , the first extension line 1000 and the second extension line 2000 are connected to the high level terminal VDD and the low level terminal VSS, respectively. Therefore, a passivation layer may not be required.

[0156] The present disclosure provides a structure in which a plurality of unit display panels SDP are assembled in a matrix manner, and power supply terminals VDD and VSS are connected to each other because they are connected to a connection member LK. That is, the high-level terminals VDD of each unit display panel SDP are electrically connected to each other, and the low-level terminals VSS of each unit display panel SDP are also electrically connected to each other. Therefore, the high-level terminals VDD and the low-level terminals VSS respectively maintain constant and consistent voltage levels.

[0157] Since the brightness or luminance of a pixel in an organic light emitting diode display can be defined by a voltage selected between a high level voltage and a low level voltage, when the high level voltage and the low level voltage are uniformly applied to the unit display panel, the luminance or brightness of the same video data will not be different between the unit display panels. According to a first embodiment of the present disclosure, all low level terminals of the unit display panel are connected and all high level terminals of the unit display panel are connected, so that the same low level voltage and the same high level voltage can be supplied to all unit display panels without the problem of voltage drop. Therefore, by tiling a plurality of unit display panels in a matrix manner to realize a large area display device, the present disclosure can provide excellent display quality without differences or changes in luminance or brightness.

[0158] In the following, reference Fig.16 , another structure of a connecting member for joining unit display panels will be described. Fig.16 is a plan view for illustrating another example of a connection member for connecting a plurality of unit display panels according to the present disclosure.

[0159] In the above-mentioned large-area display device, the connecting member may have a bracket shape such as "<" or ">". However, the embodiment is not limited thereto. For example, Fig.16 As shown, the connection member LM may include a horizontal member LM1 , a vertical member LM2 , and a central member LMC.

[0160] The horizontal member LM1 and the vertical member LM2 may have a rod shape disposed between two adjacent sides of the unit display panel SDP. For example, the horizontal member LM1 may be disposed between two unit display panels SDP arranged in a column direction and have a length and width for covering the power supply terminals VDD and VSS. The vertical member LM2 may be disposed between two unit display panels SDP arranged in a row direction and have a length and width for covering the power supply terminals VDD and VSS.

[0161] The central member LMC may be disposed at a cross angle position where the four unit display panels SDP are joined, and may have a "+" shape to be arranged together with the horizontal member LM1 and the vertical member LM2. The central member LMC may not have any electrical linking elements (such as linking wires). The central member LMC may include a fastening element (not shown) for assembling the horizontal member LM1 and the vertical member LM2 so as not to be removed.

[0162] The features, structures, effects, etc. described in the above examples of the present disclosure are included in at least one example of the present disclosure, and are not necessarily limited to one example. In addition, a person of ordinary skill in the art can implement the features, structures, effects, etc. illustrated in at least one example of the present disclosure by combining or modifying other examples. Therefore, the contents related to such combinations and modifications should be interpreted as included in the scope of the present application.

[0163] It will be apparent to those skilled in the art that various modifications and variations may be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, it is intended that the present disclosure covers modifications and variations of the disclosure as long as they fall within the scope of the appended claims and their equivalents. These and other changes may be made to the embodiments in accordance with the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents enjoyed by such claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A unit display panel, comprising: substrate; a display area defined at a middle portion of the substrate and a non-display area surrounding the display area; A pad portion disposed at the non-display area; an emission layer, which is arranged in a display area on the substrate; as well as a plurality of power supply terminals disposed outside the pad portion in the non-display area, The plurality of power terminals are disposed at the outermost side of the substrate and are configured to supply voltage to drive the emission layer.

2. The unit display panel according to claim 1, wherein: The power terminal comprises: a first terminal connected to a low-level pad in the pad portion; and A second terminal connected to a high-level pad in the pad portion.

3. The unit display panel according to claim 2, wherein: The first terminal is divided into a plurality of first terminals, and the plurality of first terminals are arranged at a predetermined distance on at least one side of the substrate; and The second terminal is divided into a plurality of second terminals, and the plurality of second terminals are arranged between two adjacent first terminals.

4. The unit display panel according to claim 3, wherein: At least one pair of first terminals and second terminals is disposed on each of the four sides of the substrate.

5. The unit display panel according to claim 2, wherein: The first terminal is arranged along the periphery of the substrate, and Wherein, the second terminal is parallel to the first terminal.

6. The unit display panel according to claim 5, wherein: The first terminal has a closed line along a perimeter of the substrate, and the second terminal has another closed line along a perimeter of the substrate.

7. The unit display panel according to claim 1, further comprising: A packaging layer covering the emission layer; A circuit board, which includes a timing controller and is disposed on the packaging layer; as well as A flexible film includes a source driver integrated circuit, one side of the flexible film is connected to the circuit board, and the other side of the flexible film is connected to the pad portion.

8. A large-area display device, comprising: Cover plate; A plurality of unit display panels, the plurality of unit display panels are arranged on one surface of the cover plate, each of the unit display panels comprising: substrate; a display area defined at a middle portion of the substrate; a non-display area surrounding the display area; A pad portion disposed in the non-display area; A first terminal disposed outside the pad portion in the non-display area; and a second terminal separated from the first terminal, the second terminal being disposed outside the pad portion in the non-display area; and A connecting member is disposed between two unit display panels, and the connecting member connects first terminals of the unit display panels and second terminals of the unit display panels respectively.

9. The large-area display device according to claim 8, wherein: The plurality of unit display panels are arranged in a matrix including n rows and m columns, where n and m are natural numbers greater than 1, and Wherein, the connecting member comprises: A first member is disposed between two unit display panels adjacent to each other in a column direction; and The second component is arranged between two unit display panels adjacent to each other in a row direction.

10. The large-area display device according to claim 9, wherein: The first component and the second component include: a first link line connecting first terminals of two adjacent unit display panels; and The second link line connects the second terminals of two adjacent unit display panels and is electrically isolated from the first terminal.

11. The large-area display device according to claim 9, wherein: The first member and the second member are assembled in an "X" shape at corners where four unit display panels are joined.

12. The large-area display device according to claim 9, wherein: The first member and the second member have a rod shape disposed between two adjacent unit display panels, and Wherein, the connecting member further comprises: A center member having a "+" shape, the center member being fastened together with the first member and the second member and being disposed at a corner where four unit display panels are joined.

13. The large-area display device according to claim 8, wherein: The first terminal is divided into a plurality of first terminals, and the plurality of first terminals are arranged at a predetermined distance on at least one side of the substrate, wherein the second terminal is divided into a plurality of second terminals, the plurality of second terminals are arranged between two adjacent first terminals, and Wherein, the connecting member comprises: a substrate having a certain width and a certain length; a first link line extending from one end to the other end across the width to correspond to the first terminal; a second link line extending from one end to the other end across the width to correspond to the second terminal; and A passivation layer covers the middle portions of the first link line and the second link line and exposes both ends of the first link line and the second link line.

14. The large-area display device according to claim 8, wherein: The first terminal is arranged along the periphery of the substrate, and Wherein, the second terminal is arranged in parallel with the first terminal, Wherein, the connecting member comprises: a substrate having a certain width and a certain length; A first link line on the substrate, extending from one end to the other end across the width to correspond to the first terminal; an insulating layer covering the first link line and exposing two ends of the first link line; a second link line on the insulating layer, extending from one end to the other end across the width to correspond to the second terminal; and A passivation layer covers the second link line and exposes two ends of the first link line and the second link line.

15. The large-area display device according to claim 14, further comprising: a first extension line under the insulating layer, the first extension line spanning the length to connect two ends of the first link line and corresponding to the first terminal; as well as A second extension line is provided under the insulating layer, the second extension line spans the length to connect two ends of the second link line, and corresponds to the second terminal.

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