Capacitor structure and method of forming the same, semiconductor device and method of manufacturing the same

Abstract

Disclosed are capacitor structures and methods of forming the same, and semiconductor devices and methods of manufacturing the same. The capacitor structures can include a lower electrode on a substrate, a dielectric layer on the substrate, and an upper electrode on the dielectric layer. The lower electrode can include a metal nitride having a chemical formula of M 1 N y (M 1 is a first metal, and y is a positive real number). The dielectric layer can include a metal oxide and nitrogen (N), the metal oxide having a chemical formula of M 2 O x (M 2 is a second metal, and x is a positive real number). A maximum of a detected amount of nitrogen (N) in the dielectric layer can be greater than a maximum of a detected amount of nitrogen (N) in the lower electrode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0177914, filed on December 30, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments of this disclosure relate to a semiconductor device and a method of manufacturing a semiconductor device, and more specifically, to a semiconductor device including a capacitor structure and a method of manufacturing a semiconductor device including a capacitor structure. Background Technology

[0003] In semiconductor device manufacturing methods, a capacitor structure can be formed comprising a lower electrode, a dielectric layer, and a upper electrode sequentially stacked on a substrate, and electrically connected to a contact plug. To improve the electrical characteristics of the capacitor structure, the dielectric constant of the dielectric layer can be improved by increasing the thickness of the dielectric layer; however, this degrades the integration density of the semiconductor device. Summary of the Invention

[0004] An example embodiment provides a capacitor structure with improved electrical characteristics.

[0005] An example embodiment provides a method for forming a capacitor structure with improved electrical properties.

[0006] An example embodiment provides a semiconductor device including a capacitor structure with improved electrical characteristics.

[0007] An example embodiment provides a method for manufacturing a semiconductor device including a capacitor structure having improved electrical properties.

[0008] According to an example embodiment of the inventive concept, a capacitor structure may include: a lower electrode located on a substrate; a dielectric layer located on the substrate; and an upper electrode located on the dielectric layer. The lower electrode may include components having the chemical formula M... 1 N y (M) 1 It is a metal nitride (where y is a positive real number). The dielectric layer may include a metal oxide and nitrogen (N), where the metal oxide has the chemical formula M. 2 O x (M) 2 (It is the second metal, and x is a positive real number). The maximum detectable amount of nitrogen (N) in the dielectric layer can be greater than the maximum detectable amount of nitrogen (N) in the lower electrode.

[0009] According to an example embodiment of the inventive concept, a capacitor structure may include: a lower electrode located on a substrate; a dielectric layer located on the substrate; and an upper electrode located on the dielectric layer. The lower electrode may include components having the chemical formula M...1 N y (M) 1 It is a metal nitride (where y is a positive real number). The dielectric layer may include a metal oxide and nitrogen (N), where the metal oxide has the chemical formula M. 2 O x (M) 2 (where x is a positive real number). The dielectric layer may include a first portion and a second portion located on the first portion, wherein the amount of nitrogen detected in the first portion increases from the bottom to the top of the first portion, and the amount of nitrogen detected in the second portion decreases from the bottom to the top of the second portion.

[0010] According to an example embodiment of the inventive concept, a semiconductor device may include a gate structure, a bit line structure, a contact plug structure, and a capacitor structure. The gate structures may all extend along a first direction parallel to the upper surface of the substrate at an upper portion of the substrate, and may be spaced apart from each other in a second direction parallel to the upper surface of the substrate and intersecting the first direction. The bit line structures may be spaced apart from each other in the first direction, and each of the bit line structures may extend along the second direction on the gate structure. At least one contact plug structure may be adjacent to at least one of the bit line structures. The capacitor structure contacting the upper surface of the at least one contact plug structure may include a lower electrode, a dielectric layer, and an upper electrode sequentially stacked. The lower electrode may include a capacitor having the chemical formula M 1 N y (M) 1 It is a metal nitride (where y is a positive real number). The dielectric layer may include a metal oxide and nitrogen (N), where the metal oxide has the chemical formula M. 2 O x (M) 2 (It is the second metal, and x is a positive real number). The maximum detection intensity of nitrogen in the dielectric layer can be greater than the maximum detection intensity of nitrogen in the lower electrode.

[0011] According to an example embodiment of the inventive concept, a method of forming a capacitor structure may include: forming a lower electrode on a substrate; providing a first metal precursor comprising a central metal and a first ligand and a second ligand bonded to the central metal onto the lower electrode to form a first seed layer; and using a metal precursor comprising a metal having a amino group (-NR) 1 R 2 , where R 1 and R 2 The third ligand substitution of an amino group (-NH2) with a size of 1 to 5 carbon atoms (alkyl groups that are the same or different from each other) includes an amino group (-NR). 1 R 2The process involves: providing a second ligand to form a second seed layer comprising a second metal precursor; providing a third metal precursor comprising a fourth ligand and a fifth ligand onto the second seed layer to form a third seed layer comprising the second metal precursor and the third metal precursor; performing an oxidation process on the third seed layer to form a dielectric layer; and forming an upper electrode on the dielectric layer.

[0012] According to an example embodiment of the inventive concept, a method of manufacturing a semiconductor device may include the steps of: forming a gate structure that can extend along a first direction parallel to the upper surface of a substrate and can be spaced apart from each other in a second direction parallel to the upper surface of the substrate and intersecting the first direction; forming bit line structures that can extend along the second direction and can be spaced apart from each other in the first direction on the gate structure; forming at least one contact plug structure adjacent to at least one of the bit line structures; and forming a capacitor structure that contacts the upper surface of the at least one contact plug structure. The capacitor structure may include a lower electrode, a dielectric layer, and an upper electrode stacked sequentially. The step of forming the capacitor structure may include: providing a first metal precursor including a central metal and a first ligand and a second ligand bonded to the central metal onto the lower electrode to form a first seed layer; using a metal precursor including a metal with a smaller than amino group (-NR) 1 R 2 , where R 1 and R 2 The third ligand substitution of an amino group (-NH2) with a size of 1 to 5 carbon atoms (alkyl groups that are the same or different from each other) includes an amino group (-NR). 1 R 2 The second ligand is used to form a second seed layer including a second metal precursor; a third metal precursor including a fourth ligand and a fifth ligand is provided on the second seed layer to form a third seed layer including the second metal precursor and the third metal precursor; an oxidation process is performed on the third seed layer to form a dielectric layer.

[0013] The capacitor structure according to the example embodiment may include a lower electrode, a dielectric layer, and an upper electrode stacked sequentially. After forming a seed layer including a first metal precursor, empty spaces in the seed layer can be formed by replacing the first ligand included in the first metal precursor with a second ligand with a size smaller than that of the first ligand, and a second metal precursor can be further provided to fill the empty spaces. The dielectric layer can be formed by oxidizing the first metal precursor and the second metal precursor.

[0014] Therefore, the dielectric layer can have an increased density, which can enhance the dielectric constant of the dielectric layer. Even if the density of the dielectric layer is increased to enhance its dielectric constant, the thickness of the dielectric layer does not need to be increased, so as not to degrade the integration of the semiconductor device including the dielectric layer. Attached Figure Description

[0015] Figures 1 to 12 This is a cross-sectional view illustrating a method for forming a capacitor structure according to an example embodiment.

[0016] Figure 13 This is a flowchart illustrating a method for forming a dielectric layer according to an example embodiment.

[0017] Figures 14 to 32 These are plan views and cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0018] The above and other aspects and features of the semiconductor device including a capacitor structure and the method of manufacturing the semiconductor device according to the exemplary embodiments will become readily understood from the following detailed description with reference to the accompanying drawings.

[0019] In the following text, two directions that are substantially parallel to the upper surface of the substrate and substantially perpendicular to each other can be defined as the first direction and the second direction, respectively.

[0020] Figures 1 to 12 This is a cross-sectional view illustrating a method for forming a capacitor structure according to an exemplary embodiment. Specifically, Figures 1 to 4 , Figure 7 , Figure 9 and Figure 11 It is a sectional view. Figure 5 , Figure 6 , Figure 8 , Figure 10 and Figure 12 These are enlarged sectional views of the X region of the corresponding sectional view. For ease of explanation, Figure 5 , Figure 6 , Figure 8 , Figure 10 and Figure 12 The structure of the invisible components is shown.

[0021] Reference Figure 1 A first insulating interlayer 30, including a contact plug 20, can be formed on the substrate 10, and an etch stop layer 40 and a molding layer 50 can be sequentially stacked on the first insulating interlayer 30 and the contact plug 20. The etch stop layer 40 and the molding layer 50 can be partially etched to form a first opening exposing the upper surface of the contact plug 20 and the upper surface of the portion of the first insulating interlayer 30 adjacent to the contact plug 20. A lower electrode layer 60 can be formed on the upper surface of the contact plug 20 and the upper surface of the portion of the first insulating interlayer 30 exposed by the first opening, the sidewall of the first opening, and the upper surface of the molding layer 50.

[0022] The substrate 10 may include silicon, germanium, silicon-germanium, or a group III-V compound semiconductor such as GaP, GaAs, or GaSb. In an example embodiment, the substrate 10 may be a silicon-on-insulator (SOI) wafer or a germanium-on-insulator (GOI) wafer.

[0023] Various types of components can be formed on the substrate 10, such as active patterns, gate structures, bit line structures, source / drain layers, etc. The components can be covered by the first insulating interlayer 30, and the contact plugs 20 can be electrically connected to, for example, the source / drain layer.

[0024] The contact plug 20 may include metals such as tungsten (W), aluminum (Al), copper, and / or polycrystalline silicon doped with impurities. The first insulating interlayer 30 may include oxides such as silicon oxide. The lower electrode layer 60 may include, for example, metal nitrides.

[0025] In an example embodiment, the lower electrode layer 60 can be formed by forming a metal layer and nitriding the metal layer.

[0026] The sequentially stacked etch stop layer 40 and molding layer 50 may each comprise a corresponding material that has etch selectivity relative to each other, such as an oxide such as silicon oxide and a nitride such as silicon nitride.

[0027] In an example embodiment, the plurality of contact plugs 20 may be formed to be spaced apart from each other in each of the first and second directions, and may be arranged in a honeycomb shape in a plan view. Each of the contact plugs 20 may have a circular, elliptical, or polygonal shape in a plan view.

[0028] Reference Figure 2 A sacrificial layer (not shown) can be formed on the lower electrode layer 60 to fill the first opening, and the sacrificial layer and the lower electrode layer 60 can be planarized until the upper surface of the molding layer 50 is exposed, such that the lower electrode layer 60 can be divided into a plurality of lower electrodes 65. Each of the lower electrodes 65 can have a cup-shaped shape.

[0029] Reference Figure 3 It can remove the sacrificial layer and molding layer 50.

[0030] A lower electrode 65 may be formed on the upper surface of the contact plug 20 and the upper surface of the portion of the first insulating interlayer 30 adjacent to the contact plug 20, and the upper surface of the etch stop layer 40 may be exposed. In an example embodiment, the sacrificial layer and the molding layer 50 may be removed by a wet etching process.

[0031] Alternatively, the lower electrode 65 may also be formed in a columnar shape.

[0032] Reference Figure 4 and Figure 5The first seed layer 70 can be conformally formed on the upper surface of the etch stop layer 40 and on the upper surface and sidewall of the lower electrode 65.

[0033] The first seed layer 70 may include, for example, a layer with the chemical formula MC. x N y (M is the central metal, C is carbon, N is nitrogen, and x and y are positive real numbers) a first metal precursor. In an example embodiment, the central metal M may include at least one selected from the group consisting of Li, Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Fr, Ra, and Ac.

[0034] The first metal precursor included in the first seed layer 70 can be derived from the general formula M(L1). n (L2) m (n and m are positive real numbers) indicates that M is the central metal, and L1 and L2 are different ligands that bind to the central metal M. In the following text, L1 may be referred to as the first ligand, L2 as the second ligand, and L3 and L4, which will be described later, may be referred to as the third and fourth ligands, respectively.

[0035] The first ligand L1 can be an alkyl group having 1 to 5 carbon atoms, or an aromatic cyclic group or heterocyclic group having 4 or more carbon atoms, and when the cyclic group has a substituent, the substituent can include at least one alkyl group, such as a methyl group, an ethyl group, etc.

[0036] The second ligand L2 can be an amino group or a nitrogen group including an amino group, and the amino group can include at least one alkyl group, such as a methyl group and an ethyl group, each independently bonded to a nitrogen atom. Therefore, the amino group included in the second ligand L2 can be of the general formula -NR. 1 R 2 It indicates that R 1 and R 2 Independently, it is an alkyl group having 1 to 5 carbon atoms. R 1 and R 2 It can also be H, an alkyl group with more than 6 carbon atoms, an aryl group (aromatic ring group), or a heterocyclic group with 4 or more carbon atoms.

[0037] In one embodiment, the first ligand L1 may be cyclopentane, and the second ligand L2 may be dimethylamine. As used herein, the terms "amino group," "amino group," "amide group," "amino group," "amino," and "amino group" refer to a group that removes hydrogen from the nitrogen of ammonia (NH3) or from the nitrogen of a primary amine compound (R'NH2) or from the nitrogen of a secondary amine compound (R'R'NH), wherein R' and R'' are organic groups. A primary amino group may be represented by the structural formula -NH2, a secondary amino group may be represented by the structural formula -NR'H, and a tertiary amino group may be represented by the structural formula -NR'R''.

[0038] Figure 5 It is shown that a plurality of first metal precursors, including a central metal M and a first ligand L1 and a second ligand L2, are formed in a first seed layer 70 on the upper surface of the lower electrode 65. However, the inventive concept is not limited to this, and the plurality of first metal precursors may be formed to be spaced apart from the upper surface of the lower electrode 65.

[0039] Figure 5 It is shown that the size of the central metal M is smaller than the size of the first ligand L1 and the second ligand L2, and the first ligand L1 and the second ligand L2 have similar sizes in the first metal precursor. However, the inventive concept is not limited to this, and the central metal M and the first ligand L1 and the second ligand L2 can have other sizes. That is, Figure 5 The structure of the invisible components is shown, and the actual size of the components may not be limited to this. "Size" refers to the physical space occupied by the ligand.

[0040] In an example embodiment, the first seed layer 70 may be formed by, for example, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process.

[0041] Reference Figure 6 The surface of the first seed layer 70 can be cleaned using a nitrogen (N2) gas cleaning process, and the second ligand L2, which is bound to the central metal M of the first metal precursor, can be replaced with a third ligand L3. The third ligand L3 may include amino groups (-NR) smaller than those included in the second ligand L2. 1 R 2 The third ligand L3 can also be an amino group (-NH2) of a size smaller than that of the second ligand L2. 1 H or -NR 2 H). R 1 and R 2 It can be an organic group, such as a methyl group or an ethyl group, as mentioned above.

[0042] Specifically, the substitution reaction can be carried out by providing ammonia (NH3) gas onto a clean first seed layer 70. The primary amine (NH2R) has a higher acidity than the secondary amine (NHR). 1 R 2 The acidity of primary amines (NH2R) is greater than that of secondary amines (NHR). 1 R 2 The reactivity of the amino group (-NH2) allows it to contain two hydrogen atoms (H) bonded to a nitrogen atom. Therefore, the amino group (-NR) bonded to the central metal M of the first metal precursor... 1 R 2 The second ligand L2 can be replaced by a third ligand L3 having an amino group (-NH2). Therefore, the first metal precursor can be converted into a product of the general formula M(L1). n (L3) l The second metal precursor is indicated, and the first seed layer 70 can be converted into the second seed layer 72.

[0043] Figure 6 It is shown that the second ligand L2, which binds to the central metal M of the first metal precursor, is completely replaced by the third ligand L3. However, the inventive concept is not limited to this. That is, the second ligand L2 may not be completely replaced by the third ligand L3, but may be partially retained, and the second ligand L2 may bind to the central metal M of the second metal precursor.

[0044] In an example embodiment, the first ligand L1 bound to the first metal precursor can also be replaced by a third ligand L3. In this case, the third ligand L3 may include an amino group (-NH2, -NR). 1 H or -NR 2 H) or a nitrogen-containing group including an amino group (-NH2), and having a size smaller than that of the first ligand L1.

[0045] Reference Figure 7 and Figure 8 The first metal precursor can be further provided onto the second seed layer 72 to form the third seed layer 74.

[0046] Since the third ligand L3, which is smaller than the second ligand L2, binds to the central metal M, an empty space for accommodating the first metal precursor can be formed in the second seed layer 72. Therefore, the first metal precursor can be provided onto the second seed layer 72 to fill the empty space, and the second seed layer 72 can be transformed into a third seed layer 74 with a density greater than that of the second seed layer 72.

[0047] In an example embodiment, the third seed layer 74 may include layers with the general formula M(L1). n (L2)m The first metallic precursor and having the general formula M(L1) n (L3) l A second metal precursor (where n and l are positive real numbers). In one embodiment, the third seed layer 74 may have a density greater than that of each of the first seed layer 70 and the second seed layer 72.

[0048] In some embodiments, a third metal precursor having a different composition from that of the first metal precursor may be provided onto the second seed layer 72 instead of the first metal precursor to form the third seed layer 74.

[0049] In an example embodiment, the third metal precursor may include a central metal different from the central metal M included in the first metal precursor, and may include ligands different from the first ligand L1 and the second ligand L2 bound to the central metal M of the first metal precursor. Optionally, the third metal precursor may include the same central metal M as the first metal precursor, but may include ligands different from the first ligand L1 and the second ligand L2 of the first metal precursor. Optionally, the third metal precursor may include a central metal different from the central metal M of the first metal precursor, but may include ligands identical to the first ligand L1 and the second ligand L2 of the first metal precursor.

[0050] In one embodiment, the central metal M included in the first metal precursor may be aluminum (Al) or zirconium (Zr), and the central metal included in the third metal precursor may be zirconium (Zr) or aluminum (Al).

[0051] For ease of explanation, the following description will only cover the case where the third seed layer 74 includes only the first metal precursor and the second metal precursor having the same central metal M, and does not include the third metal precursor having a central metal different from the central metal M of the first metal precursor and the second metal precursor.

[0052] Reference Figure 9 and Figure 10 The third seed layer 74 can be oxidized to form the dielectric layer 76.

[0053] Specifically, the oxidation process can be performed using ozone (O3) gas or ozone (O3) plasma, and each of the first to third ligands L1, L2, and L3 included in the third seed layer 74 can be replaced by oxygen (O). Therefore, the third seed layer 74, including the first and second metal precursors, can be transformed into a dielectric layer 76 comprising a metal oxide. The oxygen (O) component included in the dielectric layer 76 can be referred to as the fourth ligand L4 bound to the central metal M, and two oxygen (O) atoms can be bonded to one central metal (M) to form a metal oxide having the chemical formula MO2.

[0054] Figure 10 It is shown that the first to third ligands L1, L2, and L3 bound to the central metal M of the first and second metal precursors are completely replaced by oxygen (O). However, the inventive concept is not limited to this. That is, some of the first to third ligands L1, L2, and L3 may be retained without being replaced by oxygen (O) and may be bound to the central metal M of the first and second metal precursors.

[0055] Reference Figure 11 and Figure 12 An upper electrode 80 can be formed on the dielectric layer 76 to complete the formation of the capacitor structure 85. The capacitor structure 85 includes a lower electrode 65, a dielectric layer 76 and an upper electrode 80 stacked sequentially on the contact plug 20. A second insulating interlayer 90 can be further formed to cover the capacitor structure 85.

[0056] In an example embodiment, the upper electrode 80 may be formed to comprise a material different from that of the lower electrode 65, such as doped polycrystalline silicon and metal. Alternatively, the upper electrode 80 may be formed to comprise the same material as the lower electrode 65, such as a metal nitride. The second insulating interlayer 90 may comprise an oxide, such as silicon oxide.

[0057] The lower electrode 65 and the dielectric layer 76 may respectively comprise a metal nitride and a metal oxide. The metal nitride included in the lower electrode 65 may be of chemical formula M 1 N y (M) 1 (where y is a positive real number) indicates that the metal oxide included in dielectric layer 76 can be represented by the chemical formula M. 2 O x (M) 2 (where x is a positive real number) represents the second metal. The first metal is M. 1 Second metal M 2 They can be the same or different from each other. In one embodiment, the lower electrode 65 may include TiN, and the dielectric layer 76 may include AlO and / or ZrO.

[0058] The second ligand L2 and the third ligand L3 among the first to third ligands L1, L2 and L3 can be partially retained in the second metal M included in the dielectric layer 76. 2 The second ligand L2 and the third ligand L3 may include nitrogen (N) components, that is, amino groups (-NR) respectively. 1 R 2 The lower electrode 65 and dielectric layer 76 contain amino groups (-NH2), thus nitrogen (N) components can be detected at least in the lower portion of the dielectric layer 76. The lower electrode 65 and dielectric layer 76 can be formed to have substantially the same or similar thickness. Unlike the lower electrode 65, which can be formed by forming and nitriding a metal layer, the dielectric layer 76 can be formed by additionally providing and oxidizing a first metal precursor, such that the amount of nitrogen (N) components included in the dielectric layer 76 can be greater than the amount of nitrogen (N) components included in the lower electrode 65. In an example embodiment, the maximum detection intensity or detection quantity of the nitrogen (N) components included in the dielectric layer 76 can be greater than the maximum detection intensity or detection quantity of the nitrogen (N) components included in the lower electrode 65.

[0059] In an example embodiment, the dielectric layer 76 may include a first portion 76a and a second portion 76b sequentially stacked on the lower electrode 65, the first portion 76a and the second portion 76b may have a first thickness T1 and a second thickness T2, respectively. The second thickness T2 may be greater than the first thickness T1. Since the third seed layer 74 can be formed by further providing a first metal precursor to fill the empty spaces formed on the second seed layer 72, the amount of the second and third ligands included in the portion of the third seed layer 74 in which the empty spaces are filled by the first metal precursor may be greater than the amount in other portions of the third seed layer 74. Because the portion of the third seed layer 74 whose hollow space is filled by the first metal precursor can be oxidized to become the boundary between the first portion 76a and the second portion 76b of the dielectric layer, the detection intensity or amount of the nitrogen (N) component included in the dielectric layer 76 can have a maximum value between its bottom surface and the central portion (specifically, at the boundary between the first portion 76a and the second portion 76b), and the first portion 76a of the dielectric layer 76 can be the portion where the detection intensity or amount of the nitrogen (N) component included therein increases from its bottom to its top. Because the third seed layer 74 can be exposed to more oxygen from its bottom surface to its top surface, the second portion 76b of the dielectric layer 76 can be the portion where the detection intensity or amount of the nitrogen (N) component included therein decreases from its bottom to its top, and the detection intensity or amount of the nitrogen (N) component included in the dielectric layer 76 can have a minimum value on the top surface of the dielectric layer 76.

[0060] In the example embodiment, since a portion of the nitrogen (N) component included in the dielectric layer 76 can diffuse to the lower electrode 65, the detection intensity or detection amount of the nitrogen (N) component included in the lower electrode 65 can have a maximum value at the upper surface of the lower electrode 65, and have a value that gradually increases from the bottom surface of the lower electrode 65 toward the upper surface.

[0061] As described above, after forming the first seed layer 70 including the first metal precursor, the amino group (-NR) in the ligands bonded to the central metal M of the first metal precursor can be replaced by a third ligand L3 including an amino group (-NH2). 1 R 2 The second seed layer 72 is formed by the second ligand L2 of the first metal precursor, and the third seed layer 74 can be formed by further providing the first metal precursor onto the second seed layer 72.

[0062] Since the third ligand L3, which is smaller than the size of the second ligand L2, binds to the central metal M, an empty space for accommodating the first metal precursor can be formed in the second seed layer 72. Therefore, the first metal precursor can be further provided to fill the empty space, so that a third seed layer 74 with a density greater than that of the second seed layer 72 can be formed.

[0063] The third seed layer 74, which has an increased density, can be oxidized to form a dielectric layer 76 comprising a metal oxide, so that the dielectric layer 76 can have an increased density, which can enhance the dielectric constant of the dielectric layer 76.

[0064] Even if the density of dielectric layer 76 is increased to enhance the dielectric constant of dielectric layer 76, the thickness of dielectric layer 76 may not be increased, so the integration density of semiconductor device including dielectric layer 76 will not be degraded.

[0065] amino group (-NR) 1 R 2 Ozone (O3) can bind in the order MNCH (M is the central metal, N is nitrogen, C is carbon, H is hydrogen), thus it can attack at least three sites. However, amino groups (-NH2) can bind in the order MNH, thus ozone (O3) can attack at most two sites. Therefore, the third ligand L3, which may include amino groups (-NH2), can bind to the central metal M more effectively than the third ligand L3, which may include amino groups (-NR), which may bind to the central metal M. 1 R 2 The second ligand L2 of NH performs the oxidation process more efficiently. In addition, the binding energy of NH (about 339 kJ / mol) is lower than that of NC (about 748 kJ / mol), so the oxidation process can be further accelerated in the third ligand L3.

[0066] Figure 13 This is a flowchart illustrating a method for forming dielectric layer 76 according to an example embodiment.

[0067] Reference Figure 13 The method of forming dielectric layer 76 may include step S1, wherein a first metal precursor may be provided to form a first seed layer; step S2, wherein a dielectric layer comprising amino groups (-NH2, -NR) may be used. 1 H or -NR 2 The ligands of H) that are substituted into the ligands of the first metal precursor include amino groups (-NR). 1 R 2 The ligands of ) are used to form a second metal precursor, so that the first seed layer can be converted into a second seed layer; step S3, wherein the first metal precursor can be further provided, so that the second seed layer can be converted into a third seed layer; and step S4, wherein an oxidation process can be performed on the first metal precursor and the second metal precursor, so that the third seed layer can be converted into a dielectric layer 76.

[0068] In the example embodiment, steps S1 to S3 may be repeated before step S4 is executed.

[0069] Figures 14 to 32 These are plan views and cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to an exemplary embodiment. Specifically, Figure 14 , Figure 16 , Figure 24 and Figure 30 It is a floor plan, and Figure 15 , Figures 17-23 , Figures 25-29 and Figures 31-32 It is a sectional view. Figure 15 , Figures 17-23 , Figures 25-29 and Figures 31-32 Each of them includes a sectional view taken along lines A-A' and B-B' of the corresponding plan view.

[0070] The method includes reference Figures 1 to 13 The processes described are basically the same or similar, so repeated descriptions of them are omitted here.

[0071] Reference Figure 14 and Figure 15 An active pattern 105 can be formed on a substrate 100, and an isolation pattern 110 can be formed to cover the sidewalls of the active pattern 105.

[0072] In an example embodiment, a plurality of active patterns 105 may be formed to be spaced apart from each other in each of a first direction and a second direction, the first direction and the second direction being parallel to the upper surface of the substrate 100 and orthogonal to each other, and each of the active patterns 105 may extend upward in a third direction, the third direction being parallel to the upper surface of the substrate 100 and forming an acute angle with the first direction and the second direction.

[0073] The active pattern 105 can be formed by removing the upper portion of the substrate 100 to create a first recess, and the isolation pattern 110 can be formed by forming an isolation layer on the substrate 100 to fill the first recess and planarizing the isolation layer until the upper surface of the active pattern 105 is exposed. In an example embodiment, the planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0074] An impurity region (not shown) can be formed at the upper portion of the substrate 100 by, for example, an ion implantation process, and the active pattern 105 and the isolation pattern 110 can be partially etched to form a second recess extending in the first direction, and a gate structure 160 can be formed in the second recess.

[0075] The gate structure 160 may be formed to include a gate insulating layer 130 located on the active pattern 105 exposed by the second recess, a gate electrode 140 located on the gate insulating layer 130 that can fill the lower portion of the second recess, and a gate mask 150 located on the gate electrode 140 that can fill the upper portion of the second recess. The gate structure 160 may extend along a first direction, and a plurality of gate structures 160 may be formed to be spaced apart from each other along a second direction.

[0076] In an example embodiment, the gate insulating layer 130 can be formed by performing a thermal oxidation process on the active pattern 105 exposed by the second recess, so that the gate insulating layer 130 can be formed to include oxides, such as silicon oxide.

[0077] The gate electrode 140 can be formed by forming a gate electrode layer on the gate insulating layer 130 and the isolation pattern 110 to fill the second recess and removing the upper portion of the gate electrode layer by a CMP process and / or an etch-back process. Therefore, the gate electrode 140 can be formed in the lower portion of the second recess. The gate electrode layer can be formed of a metal such as tungsten (W), titanium (Ti), or tantalum (Ta), or a metal nitride such as tungsten nitride, titanium nitride, or tantalum nitride.

[0078] The gate mask 150 can be formed by forming a gate mask layer on the gate electrode 140, the gate insulating layer 130, and the isolation pattern 110 to fill the remainder of the second recess and planarizing the upper portion of the gate mask layer until the upper surface of the isolation pattern 110 is exposed. Therefore, the gate mask 150 can be formed in the upper portion of the second recess. The gate mask layer can be formed to include a nitride, such as silicon nitride.

[0079] Reference Figure 16 and Figure 17 An insulating layer structure 200, a first conductive layer 210, and a first etch mask 220 can be sequentially formed on the gate structure 160. The first etch mask 220 can be used to etch the first conductive layer 210 and the insulating layer structure 200 to form a second opening 230 that exposes the upper surface of the active pattern 105.

[0080] In an example embodiment, the insulating layer structure 200 may include first to third insulating layers 170, 180 and 190 stacked sequentially. The first insulating layer 170 may be formed of, for example, an oxide (such as silicon oxide), the second insulating layer 180 may be formed of, for example, a nitride (such as silicon nitride), and the third insulating layer 190 may be formed of, for example, an oxide (such as silicon oxide).

[0081] The first conductive layer 210 may be formed as, for example, polysilicon doped with impurities, and the first etch mask 220 may be formed as, for example, a nitride (such as silicon nitride).

[0082] During the etching process, the upper portion of the active pattern 105 exposed by the second opening 230, the upper portion of the isolation pattern 110 adjacent to the active pattern 105, and the upper portion of the gate mask 150 can be etched to form the third recess 230. That is, the bottom of the second opening 230 can also be referred to as the third recess 230.

[0083] In an example embodiment, the second opening 230 may be exposed on the upper surface of the central portion of each active pattern 105 extending upward from the third party, thus a plurality of second openings 230 may be formed in each of the first and second directions.

[0084] A second conductive layer 240 can be formed to fill the second opening 230.

[0085] In an example embodiment, the second conductive layer 240 can be formed by forming a preliminary second conductive layer on the active pattern 105, the isolation pattern 110, the gate mask 150, and the first etch mask 220 to fill the second opening 230, and by planarizing the upper portion of the preliminary second conductive layer. Therefore, the second conductive layer 240 can be formed to have an upper surface that is substantially coplanar with the upper surface of the first conductive layer 210.

[0086] In an example embodiment, a plurality of second conductive layers 240 may be formed to be spaced apart from each other in each of the first and second directions. The second conductive layers 240 may be formed to comprise, for example, polysilicon doped with impurities, and in some embodiments, the second conductive layers 240 may be incorporated with the first conductive layer 210.

[0087] Reference Figure 18 After removing the first etch mask 220, a third conductive layer 250, a barrier layer 270, a first metal layer 280, and a first capping layer 290 can be sequentially formed on the first conductive layer 210 and the second conductive layer 240.

[0088] In an example embodiment, the third conductive layer 250 may be formed of a material substantially the same as that of the first conductive layer 210 and the second conductive layer 240. That is, the third conductive layer 250 may be formed of polycrystalline silicon doped with impurities, and in some embodiments, the third conductive layer 250 may be integrated with the first conductive layer 210 and the second conductive layer 240.

[0089] The barrier layer 270 may be formed as a metal including, for example, titanium (Ti), tantalum (Ta), and / or a metal nitride including, for example, titanium nitride, tantalum nitride, etc. The first metal layer 280 may be formed as a metal including, for example, tungsten (W). The first capping layer 290 may be formed as a nitride including, for example, silicon nitride.

[0090] Reference Figure 19 The first capping layer 290 can be etched to form a first capping pattern 295, and the first capping pattern 295 can be used as an etching mask to sequentially etch the first metal layer 280, the barrier layer 270, the third conductive layer 250, the first conductive layer 210, and the second conductive layer 240. During the etching process, the third insulating layer 190 at the uppermost horizontal position of the insulating layer structure 200 can also be etched.

[0091] Therefore, the second conductive pattern 245, the third conductive pattern 255, the barrier pattern 275, the first metal pattern 285, and the first cover pattern 295 can be sequentially stacked on the active pattern 105, the isolation pattern 110, and the gate mask 150 in the second opening 230, and the third insulating pattern 195, the first conductive pattern 215, the third conductive pattern 255, the barrier pattern 275, the first metal pattern 285, and the first cover pattern 295 can be sequentially stacked on the second insulating layer 180 outside the second opening 230 of the insulating layer structure 200.

[0092] In some embodiments, the first to third conductive layers 210, 240, and 250 can be merged with each other, so that the sequentially stacked second conductive pattern 245 and third conductive pattern 255 can form a conductive pattern structure 265, and similarly, the sequentially stacked first conductive pattern 215 and third conductive pattern 255 can form a conductive pattern structure 265. Hereinafter, the sequentially stacked conductive pattern structure 265, the barrier pattern 275, the first metal pattern 285, and the first cover pattern 295 can be referred to as the bit line structure 305.

[0093] In the example embodiment, the bit line structure 305 may extend in the second direction, and a plurality of bit line structures 305 may be formed along the first direction.

[0094] Reference Figure 20 A first spacer layer 310 can be formed on the upper surface of the active pattern 105 exposed by the second opening 230, the upper surface of the isolation pattern 110 and the upper surface of the gate mask 150, the sidewall of the second opening 230 and the upper surface of the second insulating layer 180 to cover the bit line structure 305, and a fourth insulating layer and a fifth insulating layer can be formed sequentially on the first spacer layer 310.

[0095] The first spacer layer 310 may also cover the sidewall of the third insulating pattern 195 located beneath a portion of the second insulating layer 180 of the bit line structure 305. The first spacer layer 310 may be formed to include, for example, a nitride such as silicon nitride.

[0096] The fourth insulating layer may be formed to include, for example, an oxide such as silicon oxide. The fifth insulating layer may be formed to include, for example, a nitride such as silicon nitride. The fifth insulating layer may be formed to fill the entire portion of the second opening 230.

[0097] The fourth and fifth insulating layers can be etched using an etching process. In an example embodiment, the etching process can be performed using a wet etching process, removing all remaining portions of the fourth and fifth insulating layers except for the portion in the second opening 230. Therefore, almost the entire surface of the first spacer layer 310 (i.e., the entire portion of the first spacer layer 310 except for the portion in the second opening 230) can be exposed. The portions of the fourth and fifth insulating layers remaining in the second opening 230 can respectively form a fourth insulating pattern 320 and a fifth insulating pattern 330.

[0098] Reference Figure 21The second spacer layer can be formed on the exposed surface of the first spacer layer 310 and on the fourth insulating pattern 320 and the fifth insulating pattern 330 in the second opening 230, and the second spacer layer can be anisotropically etched to form a second spacer 340 covering the sidewall of the bit line structure 305 on the surface of the first spacer layer 310 and on the fourth insulating pattern 320 and the fifth insulating pattern 330.

[0099] The second spacer 340 may be formed as an oxide, such as silicon oxide.

[0100] The third opening 350 can be formed by a dry etching process using the first cover pattern 295 and the second spacer 340 as etching masks to expose the upper surface of the active pattern 105, and the upper surface of the isolation pattern 110 and the upper surface of the gate mask 150 can also be exposed through the third opening 350.

[0101] A portion of the first spacer layer 310 on the upper surface of the first cover pattern 295 and the upper surface of the second insulating layer 180 can be removed using a dry etching process to form a first spacer 315 covering the sidewalls of the bit line structure 305. During the dry etching process, the first insulating layer 170 and the second insulating layer 180 can also be partially removed to remain as the first insulating pattern 175 and the second insulating pattern 185, respectively. The first to third insulating patterns 175, 185, and 195 sequentially stacked under the bit line structure 305 can form an insulating pattern structure.

[0102] Reference Figure 22 A third spacer layer (not shown) may be formed on the upper surface of the first cover pattern 295, the upper surface of the first spacer 315, the outer sidewall of the second spacer 340, a portion of the upper surface of the fourth insulating pattern 320 and a portion of the upper surface of the fifth insulating pattern 330, as well as the upper surface of the active pattern 105 exposed by the third opening 350, the upper surface of the isolation pattern 110 and the upper surface of the gate mask 150. The third spacer layer may be anisotropically etched to form a third spacer 375 covering the sidewall of the bit line structure 305.

[0103] The first to third spacers 315, 340 and 375, which are sequentially stacked on the sidewall of the bit line structure 305 along a horizontal direction parallel to the upper surface of the substrate 100, can be referred to as the preliminary spacer structure.

[0104] The upper portion of the active pattern 105 can be etched by an additional etching process to form a fourth recess 390 connected to the third opening 350.

[0105] In the example embodiment, the etching process can be performed by a wet etching process. In the wet etching process, the upper portion of the isolation pattern 110 adjacent to the upper portion of the active pattern 105 can also be etched; however, the third spacer 375, the first cap pattern 295, and the gate mask 150, which include a material (e.g., nitride) that has etch selectivity relative to the active pattern 105 and the isolation pattern 110, can be hardly etched.

[0106] Reference Figure 23 The lower contact plug layer 400 can be formed to a sufficient height to fill the third opening 350 and the fourth recess 390, and the lower contact plug layer 400 can be flattened until the upper surface of the first cover pattern 295 is exposed.

[0107] In an example embodiment, the lower contact plug layer 400 may extend in a second direction, and a plurality of lower contact plug layers 400 may be formed to be spaced apart from each other along a first direction via the bit line structure 305.

[0108] Reference Figure 24 and Figure 25 A fourth mask (not shown) comprising a plurality of fourth openings spaced apart from each other in a second direction can be formed on the first cover pattern 295 and the lower contact plug layer 400, each fourth opening extending in a first direction, and the lower contact plug layer 400 can be etched by an etching process using the fourth mask as an etching mask.

[0109] In an example embodiment, each of the fourth openings may be stacked with the gate structure 160 in a vertical direction perpendicular to the upper surface of the substrate 100. As an etching process is performed, a fifth opening may be formed between the bit line structures 305, exposing the upper surface of the gate mask 150 of the gate structure 160, and after the fourth mask is removed, a second cover pattern 410 may be formed to fill the fifth opening. In an example embodiment, the second cover pattern 410 may extend between the bit line structures 305 in a first direction, and a plurality of second cover patterns 410 may be formed along a second direction.

[0110] Therefore, the lower contact plug layer 400 extending in the second direction between the bit line structures 305 can be transformed into a plurality of lower contact plugs 405 spaced apart from each other along the second direction by means of the second cover pattern 410.

[0111] Reference Figure 26 The upper portion of the lower contact plug 405 can be removed to expose the upper portion of the initial spacer structure located on the sidewall of the bit line structure 305, and the upper portions of the second spacer 340 and the third spacer 375 of the exposed initial spacer structure can be removed. The upper portion of the lower contact plug 405 can be further removed.

[0112] In an example embodiment, the upper surface of the lower contact plug 405 may be lower than the uppermost surface of the second spacer 340 and the uppermost surface of the third spacer 375.

[0113] Reference Figure 27 A fourth spacer layer can be formed on the bit line structure 305, the initial spacer structure, the first cover pattern 295 and the second cover pattern 410, and the lower contact plug 405. The fourth spacer layer can be anisotropically etched to form a fourth spacer 425 covering the first spacers to the third spacers 315, 340 and 375 on each of the opposite sidewalls of the bit line structure 305 along the first direction, thus exposing the upper surface of the lower contact plug 405.

[0114] A metal silicide pattern 435 may be formed on the exposed upper surface of the lower contact plug 405. In an example embodiment, the metal silicide pattern 435 may be formed by forming a second metal layer on the first cover pattern 295 and the second cover pattern 410, the fourth spacer 425 and the lower contact plug 405, performing heat treatment on the second metal layer and removing unreacted portions of the second metal layer.

[0115] Reference Figure 28 An upper contact plug layer 450 can be formed on the first cover pattern 295 and the second cover pattern 410, the first to fourth spacers 315, 340, 375 and 425, the metal silicide pattern 435 and the lower contact plug 405, and the upper portion of the upper contact plug layer 450 can be planarized.

[0116] In an example embodiment, the upper surface of the upper contact plug layer 450 may be higher than the upper surface of the first cover pattern 295 and the upper surface of the second cover pattern 410.

[0117] Reference Figure 29 The upper contact plug layer 450 can be patterned to form a fifth recess, and a first insulating sandwich structure comprising a sixth insulating layer 480 and a seventh insulating layer 490 stacked sequentially can be formed in the fifth recess. The first insulating sandwich structure can also be formed on the second cover pattern 410.

[0118] The fifth recess can be formed by removing the upper portion of the upper contact plug layer 450, the upper portion of the first cover pattern 295, and the upper portions of the first spacer 315, the third spacer 375, and the fourth spacer 425. This exposes the upper surface of the second spacer 340.

[0119] With the formation of the fifth recess, the upper contact plug layer 450 can be transformed into an upper contact plug 455. In an example embodiment, a plurality of upper contact plugs 455 may be formed to be spaced apart from each other in each of the first and second directions, and may be arranged in a honeycomb shape in a plan view. Each of the upper contact plugs 455 may have a circular, elliptical, or polygonal shape in a plan view.

[0120] The lower contact plug 405, the metal silicide pattern 435, and the upper contact plug 455, stacked sequentially, can form a contact plug structure.

[0121] The exposed second spacer 340 can be removed to form an air gap 345 connecting with the fifth recess. The second spacer 340 can be removed, for example, by a wet etching process.

[0122] The sixth insulating layer 480 can be formed using a material with low gap-filling properties, allowing the fifth recessed air gap 345 to remain unfilled. The air gap 345 can also be referred to as an air spacer 345, and can form a spacer structure together with the first spacer 315, the third spacer 375, and the fourth spacer 425. In other words, the air gap 345 can be a spacer that includes air.

[0123] Reference Figure 30 and Figure 31 It can be executed and referenced. Figures 1 to 12 The processes shown are essentially the same or similar to those used to manufacture the capacitor structure 540.

[0124] Specifically, after forming an etch stop layer 500 and a lower electrode 510 on the first insulating interlayer structure and the upper contact plug 455 respectively, a dielectric layer 520 can be formed on the etch stop layer 500 and the lower electrode 510, and an upper electrode 530 can be formed on the dielectric layer 520 to form a capacitor structure 540.

[0125] A first seed layer 70 comprising a first metal precursor can be formed by using an amino group having a substituted amino group (-NR) 1 R 2 Small-sized amino groups (-NH2, -NR) 1 H or -NR 2 The ligands of H) that are substituted into the ligands of the central metal of the first metal precursor include amino groups (-NR). 1 R 2 The ligands of the first metal precursor are used to form a second seed layer 72, wherein a third seed layer 74 can be formed on the second seed layer by further providing a first metal precursor, and an oxidation process can be performed on the third seed layer to form a dielectric layer 520.

[0126] A second insulating interlayer 550 can be further formed to cover the capacitor structure 540.

[0127] Reference Figure 32 After the third insulating interlayer 700 is formed on the second insulating interlayer 550, the first contact plug 712 can be formed to pass through the second insulating interlayer 550 and the third insulating interlayer 700 to contact the capacitor structure 540. The third insulating interlayer 700 may include, for example, silicon oxide, such as tetraethyl orthosilicate (TEOS).

[0128] A fourth insulating layer 720 may be formed on the third insulating layer 700 and the first contact plug 712, and the first wiring 722 may be formed to pass through the fourth insulating layer 720 to contact the first contact plug 712.

[0129] The first etch stop layer 730 and the fifth insulating layer 740 can be sequentially stacked on the fourth insulating layer 720 and the first wiring 722. The first via 751 can be formed to pass through the lower portion of the first etch stop layer 730 and the fifth insulating layer 740 to contact the first wiring 722. The second wiring 752 can be formed to pass through the upper portion of the fifth insulating layer 740 to contact the first via 751. In an example embodiment, the first via 751 and the second wiring 752 can be formed simultaneously using a dual damascene process; however, the inventive concept is not limited to this, and the first via 751 and the second wiring 752 can be formed independently using a single damascene process.

[0130] A second etch stop layer 760 and a sixth insulating layer 770 may be sequentially stacked on the fifth insulating layer 740 and the second wiring 752. A second via 781 may be formed to pass through the lower portion of the second etch stop layer 760 and the sixth insulating layer 770 to contact the second wiring 752. A third wiring 782 may be formed to pass through the upper portion of the sixth insulating layer 770 to contact the second via 781.

[0131] A third etch stop layer 790 and a seventh insulating layer 800 may be sequentially stacked on the sixth insulating layer 770 and the third wiring 782. A third via 811 may be formed to pass through the third etch stop layer 790 and the seventh insulating layer 800 to contact the third wiring 782. A fourth wiring 822 may be formed on the seventh insulating layer 800 to contact the third via 811.

[0132] In an example embodiment, each of the fourth to sixth insulating interlayers 720, 740, and 770 may include, for example, a low-dielectric material, such as fluorine- or carbon-doped silicon oxide, porous silicon oxide (SiOCH), spin-coated organic polymers, inorganic polymers (such as HSSQ and MSSQ), etc. Each of the first to third etch stop layers 730, 760, and 790 may include, for example, silicon carbonitride (SiCN). The seventh insulating interlayer 800 may include, for example, silicon oxide such as TEOS.

[0133] A first passivation layer structure can be formed on the fourth wiring 822 and the seventh insulating interlayer 800. A fourth via 860 can be formed to penetrate the first passivation layer structure to contact the fourth wiring 822. A redistribution layer 870 can be formed to contact the upper surface of the fourth via 860.

[0134] In an example embodiment, the first passivation layer structure may include a first oxide layer 830, a nitride layer 840, and a second oxide layer 850 stacked sequentially.

[0135] A semiconductor device can be completed by forming a second passivation layer 880 on the redistribution layer 870 and the second oxide layer 850.

[0136] As described above, since the dielectric layer 520 can be formed with an increased density, the dielectric constant of the dielectric layer 520 can be improved, thereby improving the electrical characteristics of the capacitor structure 540 including the dielectric layer 520. Furthermore, since the thickness of the dielectric layer 520 does not increase even with increased density and the dielectric constant of the dielectric layer 520 is improved, the integration density of the semiconductor device including the dielectric layer 520 is not degraded.

[0137] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A capacitor structure, the capacitor structure comprising: The lower electrode is located on the substrate; The dielectric layer is located on the substrate; as well as The upper electrode is located on the dielectric layer. The lower electrode includes a component with the chemical formula M 1 N y Metal nitrides, wherein M 1 It is the first metal, and y is a positive real number. The dielectric layer comprises a metal oxide and nitrogen, wherein the metal oxide has the chemical formula M. 2 O x , of which M 2 It is the second metal, x is a positive real number, and M is the second metal. 1 and M 2 Same or different, Among them, the maximum value of the detected amount of N in the dielectric layer is greater than the maximum value of the detected amount of N in the lower electrode, and The capacitor structure is formed through the following steps: A first metal precursor is provided on the lower electrode to form a first seed layer. The first metal precursor includes a central metal and a first ligand and a second ligand bound to the central metal. The second ligand is replaced with a third ligand comprising an amino group -NH2 to form a second seed layer comprising a second metal precursor, the second ligand comprising an amino group -NR. 1 R 2 , where R 1 and R 2 It is an alkyl group having 1 to 5 carbon atoms, which may be the same or different from each other, and the size of the amino group -NH2 is smaller than that of the amino group -NR. 1 R 2 Dimensions; A third metal precursor is provided onto the second seed layer to form a third seed layer, the third metal precursor comprising a fourth ligand and a fifth ligand, and the third seed layer comprising the second metal precursor and the third metal precursor; and An oxidation process is performed on the third seed layer to form a dielectric layer.

2. The capacitor structure according to claim 1, wherein, The dielectric layer also includes an amino group -NH2 or a nitrogen compound having an amino group -NH2 as a substituent.

3. The capacitor structure according to claim 1, wherein, The amount of nitrogen detected in the dielectric layer has a maximum value between the bottom surface and the central portion of the dielectric layer.

4. The capacitor structure according to claim 1, wherein, The amount of nitrogen detected in the dielectric layer is minimum at the upper surface of the dielectric layer.

5. The capacitor structure according to claim 1, wherein, The amount of nitrogen detected in the dielectric layer is greater at the bottom surface of the dielectric layer than at the top surface of the dielectric layer.

6. The capacitor structure according to claim 1, wherein, The amount of nitrogen detected in the lower electrode gradually increases from the bottom surface of the lower electrode toward the upper surface.

7. The capacitor structure according to any one of claims 1 to 6, wherein, Each of the first metal and the second metal includes at least one selected from the group consisting of Li, Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Pb, Bi, Po, Fr, Ra, and Ac.

8. The capacitor structure according to claim 7, wherein, The first metal and the second metal consist of materials that are different from each other.

9. The capacitor structure according to any one of claims 1 to 6, wherein, The lower electrode comprises TiN, and the dielectric layer comprises AlO and / or ZrO.

10. A capacitor structure, the capacitor structure comprising: The lower electrode is located on the substrate; The dielectric layer is located on the substrate; as well as The upper electrode is located on the dielectric layer. The lower electrode includes a component with the chemical formula M 1 N y Metal nitrides, wherein M 1 It is the first metal, and y is a positive real number. The dielectric layer comprises a metal oxide and nitrogen, wherein the metal oxide has the chemical formula M. 2 O x , of which M 2 It is the second metal, x is a positive real number, and M is the second metal. 1 and M 2 Same or different, The dielectric layer comprises a first portion and a second portion located on the first portion. The detection amount of nitrogen in the first portion increases from the bottom to the top of the first portion, and the detection amount of nitrogen in the second portion decreases from the bottom to the top of the second portion. The capacitor structure is formed through the following steps: A first metal precursor is provided on the lower electrode to form a first seed layer. The first metal precursor includes a central metal and a first ligand and a second ligand bound to the central metal. The second ligand is replaced with a third ligand comprising an amino group -NH2 to form a second seed layer comprising a second metal precursor, the second ligand comprising an amino group -NR. 1 R 2 , where R 1 and R 2 It is an alkyl group having 1 to 5 carbon atoms, which may be the same or different from each other, and the size of the amino group -NH2 is smaller than that of the amino group -NR. 1 R 2 Dimensions; A third metal precursor is provided onto the second seed layer to form a third seed layer, the third metal precursor comprising a fourth ligand and a fifth ligand, and the third seed layer comprising the second metal precursor and the third metal precursor; and An oxidation process is performed on the third seed layer to form a dielectric layer.

11. The capacitor structure according to claim 10, wherein, The amount of nitrogen detected in the dielectric layer has a maximum value at the boundary between the first and second parts.

12. The capacitor structure according to claim 10, wherein, The thickness of the second part of the dielectric layer is greater than the thickness of the first part of the dielectric layer.

13. The capacitor structure according to claim 10, wherein, The amount of nitrogen detected in the lower electrode has a minimum at the bottom surface of the lower electrode and a maximum at the upper surface of the lower electrode.

14. The capacitor structure according to claim 13, wherein, The amount of nitrogen detected in the lower electrode gradually increases from the bottom surface of the lower electrode toward the upper surface.

15. The capacitor structure according to any one of claims 10 to 14, wherein, The maximum detectable amount of nitrogen in the dielectric layer is greater than that in the lower electrode.

16. The capacitor structure according to any one of claims 10 to 14, wherein, The lower electrode comprises TiN, and the dielectric layer comprises AlO and / or ZrO.

17. A semiconductor device, the semiconductor device comprising: The gate structures all extend in the upper portion of the substrate along a first direction parallel to the upper surface of the substrate, and the gate structures are spaced apart from each other in a second direction parallel to the upper surface of the substrate and intersecting the first direction. Bit line structures are spaced apart from each other in a first direction, and each bit line structure extends on a gate structure in a second direction; At least one contact plug structure is adjacent to at least one bit line structure in the bit line structure; as well as The capacitor structure contacts the upper surface of at least one contact plug structure. The capacitor structure includes a lower electrode, a dielectric layer, and an upper electrode stacked sequentially. The lower electrode includes a component with the chemical formula M 1 N y Metal nitrides, wherein M 1 It is the first metal, and y is a positive real number. The dielectric layer comprises a metal oxide and nitrogen, wherein the metal oxide has the chemical formula M. 2 O x , of which M 2 It is the second metal, and x is a positive real number. Among them, the maximum detection intensity of nitrogen in the dielectric layer is greater than that of nitrogen in the lower electrode, and The capacitor structure is formed through the following steps: A first metal precursor is provided on the lower electrode to form a first seed layer. The first metal precursor includes a central metal and a first ligand and a second ligand bound to the central metal. The second ligand is replaced with a third ligand comprising an amino group -NH2 to form a second seed layer comprising a second metal precursor, the second ligand comprising an amino group -NR. 1 R 2 , where R 1 and R 2 It is an alkyl group having 1 to 5 carbon atoms, which may be the same or different from each other, and the size of the amino group -NH2 is smaller than that of the amino group -NR. 1 R 2 Dimensions; A third metal precursor is provided onto the second seed layer to form a third seed layer, the third metal precursor comprising a fourth ligand and a fifth ligand, and the third seed layer comprising the second metal precursor and the third metal precursor; and An oxidation process is performed on the third seed layer to form a dielectric layer.

18. A method for forming a capacitor structure, the method comprising the following steps: A lower electrode is formed on the substrate; A first metal precursor is provided on the lower electrode to form a first seed layer. The first metal precursor includes a first metal and a first ligand and a second ligand bound to the first metal. The first ligand and the second ligand are organic groups. The second ligand is replaced by a third ligand having an amino group -NH2 to form a second seed layer comprising a second metal precursor, wherein, The amino group -NH2 of the third ligand is smaller than the amino group -NR of the second ligand. 1 R 2 The dimensions, where R 1 and R 2 It is an alkyl group that has 1 to 5 carbon atoms, which may be the same or different from each other; A third metal precursor is provided onto the second seed layer to form a third seed layer, the third metal precursor including a fourth ligand and a fifth ligand, and the third seed layer including the second metal precursor and the third metal precursor. An oxidation process is performed on the third seed layer to form a dielectric layer; and An upper electrode is formed on the dielectric layer. Among them, the maximum value of the N detection quantity in the dielectric layer is greater than the maximum value of the N detection quantity in the lower electrode.

19. The method according to claim 18, wherein, The step of replacing the second ligand with the third ligand is performed by providing NH3 gas to the first seed layer.

20. A method of manufacturing a semiconductor device, the method comprising the following steps: Gate structures are formed in the upper portion of the substrate, extending in a first direction parallel to the upper surface of the substrate, and the gate structures are spaced apart from each other in a second direction parallel to the upper surface of the substrate and intersecting the first direction. Bit line structures spaced apart from each other in a first direction are formed on the gate structure, each of the bit line structures extending along a second direction; At least one contact plug structure is formed to be adjacent to at least one bit line structure in the bit line structure; as well as The capacitor structure is formed to contact the upper surface of the at least one contact plug structure, and the capacitor structure includes a lower electrode, a dielectric layer, and an upper electrode stacked in sequence. The steps involved in forming the capacitor structure include: A first metal precursor is provided on the lower electrode to form a first seed layer. The first metal precursor includes a central metal and a first ligand and a second ligand bound to the central metal. The second ligand is replaced with a third ligand comprising an amino group -NH2 to form a second seed layer comprising a second metal precursor, the second ligand comprising an amino group -NR. 1 R 2 , where R 1 and R 2 It is an alkyl group having 1 to 5 carbon atoms, which may be the same or different from each other, and the size of the amino group -NH2 is smaller than that of the amino group -NR. 1 R 2 Dimensions; A third metal precursor is provided onto the second seed layer to form a third seed layer, the third metal precursor comprising a fourth ligand and a fifth ligand, and the third seed layer comprising the second metal precursor and the third metal precursor; and An oxidation process is performed on the third seed layer to form a dielectric layer, and Among them, the maximum value of the N detection quantity in the dielectric layer is greater than the maximum value of the N detection quantity in the lower electrode.

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