Power clamp circuits and chips

Abstract

The present invention discloses a power clamp circuit and chip. The power clamp circuit includes: a delay unit, a discharge tube, a drive unit, and a feedback branch. The delay unit is electrically connected between a power supply and ground. The discharge tube is used to discharge static electricity. The first end of the discharge tube is electrically connected to the power supply, and the second end of the discharge tube is grounded. The input end of the drive unit is electrically connected to the common end of the delay unit, and the output end of the drive unit is electrically connected to the control end of the discharge tube. The feedback branch is connected in parallel with the drive unit and is used to generate a positive feedback voltage based on the output end voltage of the drive unit and transmit it to the input end of the drive unit to control the discharge tube to conduct before the static electricity is discharged. The main purpose of the present invention is to provide a power clamp circuit and chip that can adapt to different power-on time requirements, has a wide range of applications, and is cost-effective.

Description

Technical Field

[0001] The present invention relates to the technical field of power clamping, and in particular to a power clamping circuit and a chip. Background Art

[0002] Current power clamp control circuits typically use a simple RC delay unit and inverter structure. This structure cannot adapt to varying power-up time requirements, limiting its application range. The values of R (resistor) and C (capacitor) should not be set too small, as this reduces ESD (electrostatic discharge) protection effectiveness. Therefore, R and C are typically set to large values, which occupies a larger area and increases cost. Summary of the Invention

[0003] The main purpose of the present invention is to provide a power clamp circuit and chip that are adaptable to different power-on time requirements, have a wide application range and save costs.

[0004] To achieve the above objectives, the present invention provides a power clamp circuit, comprising:

[0005] A delay unit, the delay unit being electrically connected between a power supply and a ground;

[0006] a discharge tube for discharging static electricity; a first end of the discharge tube is electrically connected to the power supply, and a second end of the discharge tube is grounded;

[0007] a driving unit, wherein an input end of the driving unit is electrically connected to the common end of the delay unit, and an output end of the driving unit is electrically connected to the control end of the discharge pipe; and

[0008] A feedback branch is connected in parallel with the driving unit and is used to generate a positive feedback voltage according to the output terminal voltage of the driving unit and transmit it to the input terminal of the driving unit to control the discharge tube to be turned on before the static discharge is completed.

[0009] In some embodiments, the feedback branch includes a first inverter and a pull-down device, the input end of the first inverter is electrically connected to the output end of the driving unit, and the output end of the first inverter is electrically connected to the input end of the driving unit; the first end of the pull-down device is connected to the output end of the driving unit, and the second end of the pull-down device is grounded.

[0010] In some embodiments, the feedback branch includes a first three-terminal switching device and a pull-down level device, the control end of the first three-terminal switching device is electrically connected to the output end of the driving unit, the first end of the first three-terminal switching device is electrically connected to the input end of the driving unit, and the second end of the first three-terminal switching device is grounded; the first end of the pull-down level device is connected to the output end of the driving unit, and the second end of the pull-down level device is grounded.

[0011] In some embodiments, the feedback branch includes a first inverter, a second inverter, a pull-down device and a first three-terminal switch device; the first inverter and the second inverter are connected in series, and the input end of the first inverter is electrically connected to the output end of the driving unit, the output end of the second inverter is connected to the control end of the first three-terminal switch device, the first end of the first three-terminal switch device is electrically connected to the input end of the driving unit, and the second end of the first three-terminal switch device is grounded; the first end of the pull-down device is connected to the output end of the driving unit, and the second end of the pull-down device is grounded.

[0012] In some embodiments, the pull-down level device includes a pull-down resistor or an NMOS tube;

[0013] When the pull-down level device uses a pull-down resistor, a first end of the pull-down resistor is connected to the output end of the driving unit, and a second end of the pull-down resistor is grounded;

[0014] When the pull-down level device is an NMOS tube, the gate and drain of the pull-down level device are respectively connected to the output end of the driving unit, and the source of the pull-down level device is grounded.

[0015] In some embodiments, the delay unit includes a first resistor and a first capacitor connected in series, the first end of the first resistor is electrically connected to the power supply, the first end of the first capacitor is grounded, and the second end of the first resistor and the second end of the first capacitor are electrically connected to form the common end.

[0016] In some embodiments, the resistance range of the first resistor is 30-100 kΩ, and the capacitance range of the first capacitor is 0.2-1.0 pF.

[0017] In some embodiments, the discharge tube is an NMOS tube or an NPN tube;

[0018] When the discharge tube is an NMOS tube, the first end of the discharge tube is a drain, the second end is a source, and the control end is a gate;

[0019] When the discharge tube is an NPN tube, the first end of the discharge tube is the collector, the second end is the emitter, and the control end is the base.

[0020] In some embodiments, the first three-terminal switch device is an NMOS transistor or an NPN transistor;

[0021] When the first three-terminal switch device is an NMOS tube, the first terminal of the first three-terminal switch device is a drain, the second terminal is a source, and the control terminal is a gate;

[0022] When the first three-terminal switch device is an NPN tube, the first terminal of the first three-terminal switch device is a collector, the second terminal is an emitter, and the control terminal is a base.

[0023] The present application also provides a chip including the power clamping circuit.

[0024] The technical solution of the present invention forms a positive feedback voltage through a feedback branch connected in parallel to the driving unit, so that when static electricity comes, the driving unit can maintain the output high level to drive the discharge tube to conduct until the static electricity is completely discharged. Therefore, this embodiment can adapt to the power-on time requirements of different power supplies and has a wide range of applications. In addition, since the feedback branch is set to complete the static electricity discharge, this embodiment does not need to use capacitors and resistors with ultra-large time constants to ensure that the static electricity generated in the circuit is completely discharged. Therefore, the values of the resistors and capacitors in the delay unit in this embodiment are smaller than those in the delay unit in the traditional power clamp circuit, thereby reducing the time constant of the delay unit, reducing the area of the resistors and capacitors in the delay unit, and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0026] Figure 1 A circuit schematic diagram of an embodiment of a conventional power clamp circuit;

[0027] Figure 2 This is a circuit diagram of an embodiment of a power clamp circuit of the present invention;

[0028] Figure 3 is a circuit schematic diagram of another embodiment of the power clamp circuit of the present invention;

[0029] Figure 4 This is a circuit schematic diagram of another embodiment of the power clamp circuit of the present invention;

[0030] Figure 5 This is a circuit diagram of another embodiment of the power clamp circuit of the present invention;

[0031] Figure 6 This is a circuit diagram of another embodiment of the power clamp circuit of the present invention;

[0032] Figure 7 This is a circuit schematic diagram of another embodiment of the power clamp circuit of the present invention;

[0033] Figure 8 This is a circuit schematic diagram of yet another embodiment of the power clamp circuit of the present invention;

[0034] Figure 9 A comparison chart showing experimental data on current discharge speed between a conventional power clamp circuit and the present application;

[0035] Figure 10 A graph showing experimental data on leakage current generated by a traditional power clamp circuit;

[0036] Figure 11 A graph showing experimental data of leakage current generated by the power clamp circuit of the present invention;

[0037] Reference numerals:

[0038] 10-delay unit; 20-bleeder tube; 30-drive unit; 40-feedback branch; 41-first inverter; 42-first three-terminal switch device; 43-second inverter; 100-power clamp circuit; 44-pull-down level device.

[0039] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0041] In the present invention, descriptions such as "first" and "second" are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions of various embodiments may be combined with each other, but this must be based on the fact that they can be implemented by a person of ordinary skill in the art. If the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0042] Please refer to Figure 1 The existing power clamp circuit includes a delay unit consisting of a resistor R and a capacitor C, an inverter INV, and a discharge transistor MN. It is worth noting that the time constant of the RC delay unit determines the static discharge time. A larger time constant means a longer discharge time, ensuring that static electricity generated in the circuit is completely discharged.

[0043] When static electricity occurs, due to the large time constant of the delay unit composed of R and C, the input of the inverter INV cannot quickly follow the rise of the power supply voltage. Therefore, the input of the inverter INV is at a low level, and the output of the inverter INV is at a high level, causing the bleeder MN to be turned on, and the static current is discharged through the bleeder MN. At the same time, the static voltage is limited to a reasonable range to ensure that the internal circuit is not burned out. The gate voltage of the bleeder MN remains high within the time constant of the delay unit composed of R and C, ensuring that the static electricity is completely discharged. After the RC time constant, the bleeder MN will be turned off.

[0044] The aforementioned existing power clamp circuits cannot meet the power-on time requirements of various power supplies, resulting in a limited application range. Furthermore, because existing power clamp circuits typically have large R and C resistors, they occupy a large area and are costly. In certain fast-power-on applications, the large RC resistors may cause the ESD protection discharge diode MN1 to erroneously activate for a short period of time, generating significant leakage current during power-on, affecting the normal operation of modules in other circuits.

[0045] In view of this, the present application proposes a power clamp circuit and chip, which are intended to adapt to different power-on time requirements, have a wide range of applications and save costs.

[0046] Please refer to Figure 2 The present invention provides a power clamp circuit 100 , which includes a delay unit 10 , a bleeder tube 20 , a drive unit 30 and a feedback branch 40 .

[0047] The delay unit 10 is electrically connected between a power supply and ground. The delay unit 10 is used to delay a preset time to release the electrostatic current. The delay unit 10 can be an RC delay unit 10 composed of a first resistor R1 and a first capacitor C1 connected in series. The first end of the first resistor R1 is electrically connected to the power supply, the first end of the first capacitor C1 is grounded, and the second end of the first resistor R1 and the second end of the first capacitor C1 are electrically connected to form a common end.

[0048] The discharge tube 20 is used to discharge static electricity. The first end of the discharge tube 20 is electrically connected to the power supply, and the second end of the discharge tube 20 is grounded. In some embodiments, the discharge tube 20 is an NMOS transistor or an NPN transistor. When the discharge tube 20 is an NMOS transistor, the first end of the discharge tube 20 is the drain, the second end is the source, and the control end is the gate. When the discharge tube 20 is an NPN transistor, the first end of the discharge tube 20 is the collector, the second end is the emitter, and the control end is the base.

[0049] A drive unit 30 is provided. The input of the drive unit 30 is electrically connected to the common terminal of the delay unit 10, and the output of the drive unit 30 is electrically connected to the control terminal of the discharge tube 20. The drive unit 30 is configured to generate an on / off voltage for controlling the on / off state of the discharge tube 20. Specifically, the drive unit 30 may be an inverter. The input of the inverter is electrically connected to the common terminal of the delay unit 10, and the output of the inverter is electrically connected to the control terminal of the discharge tube 20.

[0050] The feedback branch 40 is connected in parallel with the driving unit 30 and is used to generate a positive feedback voltage according to the output voltage of the driving unit 30 and transmit it to the input end of the driving unit 30 to control the discharge tube 20 to be turned on before the static discharge is completed.

[0051] In this embodiment, when static electricity is generated, the delay function of the first resistor R1 and the first capacitor C1 of the delay unit 10 takes effect due to the provision of the delay unit 10. The voltage at the input of the driver unit 30 does not immediately follow the voltage increase. At this point, the output of the driver unit 30 outputs a high level, turning on the discharge tube 20 and discharging the current. The feedback branch 40 operates normally, forming a positive feedback loop that clamps the input of the driver unit 30 at a low level and maintains a high level at the output of the driver unit 30, causing the discharge tube 20 to remain on until the static electricity is completely discharged.

[0052] It is understandable that in reality, different application scenarios have different requirements for power-on time. Generally speaking, the power-on time may be between tens of nS and several S. It is difficult for existing traditional power clamp control circuits to meet the requirements. In this embodiment, a feedback branch 40 is connected in parallel to the driving unit 30, and the entire feedback branch 40 forms a positive feedback voltage, so that when static electricity comes, the driving unit 30 can maintain the output high level to drive the discharge tube 20 to be turned on until the static electricity is discharged. Therefore, this embodiment can adapt to different power-on time requirements and has a wide range of applications. In addition, since the feedback branch 40 is set to ensure that the static electricity is discharged completely, this embodiment does not need to use capacitors and resistors with ultra-large time constants to ensure that the static electricity generated in the circuit is completely discharged. Therefore, the values of the resistors and capacitors in the delay unit in this embodiment are smaller than those in the delay unit in the traditional power clamp circuit, thereby reducing the time constant of the delay unit, reducing the area of the resistors and capacitors in the delay unit, and reducing costs.

[0053] In some embodiments, the resistance of the first resistor R1 ranges from 30 kΩ to 100 kΩ, and the capacitance of the first capacitor C1 ranges from 0.2 pF to 1.0 pF.

[0054] During normal power-on, since the values of the resistors and capacitors in the delay unit are smaller than those of the traditional power clamp circuit and the time constant is smaller, the input end of the driving unit 30 tracks the input power voltage to be high, and the output after passing through the output of the driving unit 30 is low. At this time, the discharge tube 20 is closed.

[0055] Specifically, the feedback branch 40 in the present application can be implemented through various implementations, which are described below through several embodiments.

[0056] Please refer to Figure 3 or Figure 4 In some embodiments, the feedback branch 40 includes a first inverter 41 and a pull-down device 44, the input end of the first inverter 41 is electrically connected to the output end of the driving unit 30, and the output end of the first inverter 41 is electrically connected to the input end of the driving unit 30; the first end of the pull-down device 44 is connected to the output end of the driving unit 30, and the second end of the pull-down device 44 is grounded.

[0057] During normal power-up, because the resistors and capacitors in the delay unit are smaller than those in conventional power clamp circuits, resulting in a smaller time constant, the input of the driver unit 30 tracks the input power voltage, which is high. After passing through the output of the driver unit 30, the output is low, turning off the bleeder tube 20. The low level at the output of the driver unit 30 is converted to a high level after passing through the first inverter 41, and the driver unit 30 continues to drive the bleeder tube 20 to close.

[0058] The function of the pull-down level device 44 is to set the initial working level for the feedback branch 40 when the power is turned on normally, so as to ensure that the branch is disconnected, the gate level of the discharge tube 20 is low, and the discharge tube 20 is closed. The pull-down level device 44 includes a pull-down resistor R2 or an NMOS tube; please refer to Figure 3 , when the pull-down level device 44 uses the pull-down resistor R2, the first end of the pull-down resistor R2 is connected to the output end of the driving unit 30, and the second end of the pull-down resistor R2 is grounded; please refer to Figure 4 When the pull-down device 44 uses an NMOS tube, the gate and drain of the pull-down device 44 are respectively connected to the output end of the driving unit 30, and the source of the pull-down device 44 is grounded.

[0059] When static electricity is generated, due to the delay unit 10, the delay effect of the first resistor R1 and the first capacitor C1 of the delay unit 10 takes effect. The voltage at the input end of the driving unit 30 does not immediately follow the voltage increase. At this time, the output end of the driving unit 30 outputs a high level to control the discharge tube 20 to conduct, discharging current. At the same time, the high level at the output end of the driving unit 30 is converted to a low level after passing through the first inverter 41. The feedback branch 40 operates normally to form a positive feedback loop, clamping the input end of the driving unit 30 at a low level. The output end of the driving unit 30 remains at a high level, causing the discharge tube 20 to continue to conduct until the static electricity is discharged.

[0060] In this embodiment, a first inverter 41 is connected in parallel to the driving unit 30, and the entire feedback branch 40 forms a positive feedback voltage, so that when static electricity comes, the driving unit 30 can maintain the output high level to drive the discharge tube 20 to be turned on until the static electricity is discharged. Therefore, this embodiment can adapt to different power supply power-on time requirements and has a wide range of applications. In addition, since the first inverter 41 is set to ensure that the static electricity is discharged completely, this embodiment does not need to use capacitors and resistors with ultra-large time constants to ensure that the static electricity generated in the circuit is completely discharged. Therefore, the values of the resistors and capacitors in the delay unit in this embodiment are smaller than those in the delay unit in the traditional power clamp circuit 100, thereby reducing the time constant of the delay unit, reducing the area of the resistors and capacitors in the delay unit, and reducing costs.

[0061] Please refer to Figure 5 or Figure 6 In some other embodiments, the feedback branch 40 includes a first three-terminal switch device 42 and a pull-down device 44. The control terminal of the first three-terminal switch device 42 is electrically connected to the output terminal of the driving unit 30, the first terminal of the first three-terminal switch device 42 is electrically connected to the input terminal of the driving unit 30, and the second terminal of the first three-terminal switch device 42 is grounded; the first terminal of the pull-down device 44 is connected to the output terminal of the driving unit 30, and the second terminal of the pull-down device 44 is grounded.

[0062] During normal power-up, because the resistors and capacitors in the delay unit are smaller than those in conventional power clamp circuits, resulting in a shorter time constant, the input of the driver unit 30 tracks the input power voltage, which is high. After passing through the output of the driver unit 30, the output is low, turning off the bleeder tube 20. The low level at the output of the driver unit 30 is input to the control terminal of the first three-terminal switch device 42, turning off the first three-terminal switch device 42. The driver unit 30 then continues to drive the bleeder tube 20 to close.

[0063] The function of the pull-down level device 44 is to set the initial working level for the feedback branch 40 when the power is turned on normally, so as to ensure that the branch is disconnected, the gate level of the discharge tube 20 is low, and the discharge tube 20 is closed. The pull-down level device 44 includes a pull-down resistor R2 or an NMOS tube; please refer to Figure 5 , when the pull-down level device 44 uses the pull-down resistor R2, the first end of the pull-down resistor R2 is connected to the output end of the driving unit 30, and the second end of the pull-down resistor R2 is grounded; please refer to Figure 6 When the pull-down device 44 uses an NMOS tube, the gate and drain of the pull-down device 44 are respectively connected to the output end of the driving unit 30, and the source of the pull-down device 44 is grounded.

[0064] When static electricity is generated, due to the delay unit 10, the delay effect of the first resistor R1 and the first capacitor C1 of the delay unit 10 takes effect. The input voltage of the driving unit 30 will not immediately follow the voltage increase. At this time, the output end of the driving unit 30 outputs a high level to control the discharge tube 20 to turn on and discharge current. At the same time, the high level of the output end of the driving unit 30 is input to the control end of the first three-terminal switch device 42. The first three-terminal switch device 42 is turned on, the input end of the driving unit 30 is at a low level, and the feedback branch 40 works normally to form a positive feedback loop, clamping the input end of the driving unit 30 at a low level. The output end of the driving unit 30 remains at a high level, causing the discharge tube 20 to continue to turn on until the static electricity is discharged.

[0065] In this embodiment, a first three-terminal switch device 42 is connected in parallel to the drive unit 30, and the entire feedback branch 40 forms a positive feedback voltage, so that when static electricity occurs, the drive unit 30 can maintain the output high level to drive the discharge tube 20 to conduct until the static electricity is completely discharged. Therefore, this embodiment can adapt to different power supply power-on time requirements and has a wide range of applications. In addition, because the first three-terminal switch device 42 is provided to ensure that the static electricity is completely discharged, this embodiment does not need to use capacitors and resistors with very large time constants to ensure that the static electricity generated in the circuit is completely discharged. Therefore, the values of the resistors and capacitors in the delay unit in this embodiment are smaller than those in the delay unit in the traditional power clamp circuit, thereby reducing the time constant of the delay unit, reducing the area of the resistors and capacitors in the delay unit, and reducing costs.

[0066] Please refer to Figure 7 or Figure 8 In some other embodiments, the feedback branch 40 includes a branch consisting of a first inverter 41, a second inverter 43, a pull-down device 44 and a first three-terminal switch device 42; the first inverter and the second inverter 43 are connected in series, and the input end of the first inverter 41 is electrically connected to the output end of the driving unit 30, the output end of the second inverter 43 is connected to the control end of the first three-terminal switch device 42, the first end of the first three-terminal switch device 42 is electrically connected to the input end of the driving unit 30, and the second end of the first three-terminal switch device 42 is grounded; the first end of the pull-down device 44 is connected to the output end of the driving unit 30, and the second end of the pull-down device 44 is grounded.

[0067] During normal power-up, because the resistors and capacitors in the delay unit are smaller than those in conventional power clamp circuits, resulting in a shorter time constant, the input of the driver unit 30 tracks the input power voltage, which is high. After passing through the output of the driver unit 30, the output is low, turning off the bleeder tube 20. The low level at the output of the driver unit 30 is maintained at a low level by the first and second inverters 43 connected in series, and then input to the control terminal of the first three-terminal switch device 42. The first three-terminal switch device 42 is turned off, and the driver unit 30 continues to drive the bleeder tube 20 to close.

[0068] The function of the pull-down level device 44 is to set the initial working level for the feedback branch 40 when the power is turned on normally, so as to ensure that the branch is disconnected, the gate level of the discharge tube 20 is low, and the discharge tube 20 is closed. The pull-down level device 44 includes a pull-down resistor R2 or an NMOS tube; please refer to Figure 7 , when the pull-down level device 44 uses the pull-down resistor R2, the first end of the pull-down resistor R2 is connected to the output end of the driving unit 30, and the second end of the pull-down resistor R2 is grounded; please refer to Figure 8 When the pull-down device 44 uses an NMOS tube, the gate and drain of the pull-down device 44 are respectively connected to the output end of the driving unit 30, and the source of the pull-down device 44 is grounded.

[0069] When static electricity is generated, due to the delay unit 10, the delay effect of the first resistor R1 and the first capacitor C1 of the delay unit 10 takes effect. The input voltage of the driving unit 30 will not immediately follow the voltage increase. At this time, the output of the driving unit 30 outputs a high level to control the discharge tube 20 to turn on and discharge current. At the same time, the high level of the output of the driving unit 30 is maintained at a high level through the first inverter and the second inverter 43 connected in series and input to the control end of the first three-terminal switch device 42. The first three-terminal switch device 42 is turned on, the input of the driving unit 30 is at a low level, and the feedback branch 40 works normally to form a positive feedback loop, clamping the input of the driving unit 30 at a low level. The output of the driving unit 30 remains at a high level, causing the discharge tube 20 to continue to turn on until the static electricity is discharged.

[0070] In this embodiment, a feedback branch 40 consisting of a first inverter 41, a second inverter 43, and a first three-terminal switch device 42 is connected in parallel to the drive unit 30. The entire feedback branch 40 forms a positive feedback voltage, so that when static electricity comes, the drive unit 30 can maintain the output high level to drive the discharge tube 20 to be turned on until the static electricity is discharged. Therefore, this embodiment can adapt to different power supply power-on time requirements and has a wide range of applications. In addition, since the first three-terminal switch device 42 is provided to ensure that the static electricity is discharged completely, this embodiment does not need to use capacitors and resistors with ultra-large time constants to ensure that the static electricity generated in the circuit is completely discharged. Therefore, the values of the resistors and capacitors in the delay unit in this embodiment are smaller than those in the delay unit in the traditional power clamp circuit, thereby reducing the time constant of the delay unit, reducing the area of the resistors and capacitors in the delay unit, and reducing costs.

[0071] It should be noted that providing the first inverter 41 and the second inverter 43 in series in the feedback branch 40 can better shape the signal input to the control terminal of the first three-terminal switch device 42 and enhance the signal driving capability.

[0072] It should be noted that the first three-terminal switch device 42 is an NMOS tube or an NPN tube; when the first three-terminal switch device 42 is an NMOS tube, the first end of the first three-terminal switch device 42 is a drain, the second end is a source, and the control end is a gate; when the first three-terminal switch device 42 is an NPN tube, the first end of the first three-terminal switch device 42 is a collector, the second end is an emitter, and the control end is a base.

[0073] The feedback branch 40 is composed of the first inverter 41, the second inverter 43 and the first three-terminal switch device 42 as an example. Figure 1 Experimental data on current discharge speed and leakage current of the traditional power clamp circuit (hereinafter referred to as the original circuit) and the present application.

[0074] Please refer to Figure 9 ,set up Figure 1 The conventional power clamp circuit and the discharge tube 20 of the present application circuit have the same size. Figure 9 The simulation results are compared: the peak value of the power supply voltage of the circuit of this application is about 3V, and the discharge is faster; the effect of the original circuit is not good, the peak value reaches about 9V, and the charge discharge speed is slow. Figure 1 The traditional power clamp circuit in the circuit has a faster current discharge speed and is more conducive to protecting other circuits.

[0075] In addition, please refer to Figure 10 and Figure 11 This embodiment also compares the leakage current of the original circuit and the circuit of the present application when the power rise time is 0.5uS. The maximum leakage current of the original circuit is about 300mA, while the leakage current of the circuit of the present application is much lower, about 10uA. Figure 1 The traditional power clamp circuit in the circuit has smaller leakage current and is suitable for occasions requiring fast power-on.

[0076] In summary, the above analysis shows that, given the same discharge tube 20 dimensions, the circuit of the present application offers faster charge discharge, better protection, and extremely low leakage current. The existing circuit, on the other hand, suffers from poor protection and high leakage current, and both characteristics cannot be balanced. Optimizing one characteristic degrades the other. Furthermore, the present application can adapt to varying power-on time requirements, has a wide range of applications, reduces the area of the resistors and capacitors in the delay unit, and reduces costs.

[0077] The present application also provides a chip including a power clamp circuit 100 .

[0078] The specific structure of the power clamp circuit 100 refers to the above embodiments. Since this chip adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0079] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the inventive concept of the present invention, or direct / indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A power clamp circuit, characterized in that: include: A delay unit, the delay unit being electrically connected between a power supply and a ground; a discharge tube for discharging static electricity; a first end of the discharge tube is electrically connected to the power supply, and a second end of the discharge tube is grounded; a driving unit, wherein an input end of the driving unit is electrically connected to the common end of the delay unit, and an output end of the driving unit is electrically connected to the control end of the discharge pipe; as well as A feedback branch, connected in parallel with the driving unit, for generating a positive feedback voltage according to the output terminal voltage of the driving unit and transmitting the positive feedback voltage to the input terminal of the driving unit, so as to control the discharge tube to be turned on before the static discharge is completed; The feedback branch includes a first three-terminal switch device and a pull-down device, wherein the control terminal of the first three-terminal switch device is electrically connected to the output terminal of the driving unit, the first terminal of the first three-terminal switch device is electrically connected to the input terminal of the driving unit, and the second terminal of the first three-terminal switch device is grounded; the first terminal of the pull-down device is connected to the output terminal of the driving unit, and the second terminal of the pull-down device is grounded; The pull-down level device includes a pull-down resistor or an NMOS tube; when the pull-down level device uses a pull-down resistor, the first end of the pull-down resistor is connected to the output end of the driving unit, and the second end of the pull-down resistor is grounded; when the pull-down level device uses an NMOS tube, the gate and drain of the pull-down level device are respectively connected to the output end of the driving unit, and the source of the pull-down level device is grounded.

2. The power clamp circuit according to claim 1, wherein: The feedback branch includes a first inverter and a pull-down device, the input end of the first inverter is electrically connected to the output end of the driving unit, and the output end of the first inverter is electrically connected to the input end of the driving unit; A first end of the pull-down level device is connected to the output end of the driving unit, and a second end of the pull-down level device is grounded.

3. The power clamp circuit according to claim 1, wherein: The feedback branch includes a first inverter, a second inverter, a pull-down device and a first three-terminal switch device; the first inverter and the second inverter are connected in series, and the input end of the first inverter is electrically connected to the output end of the driving unit, the output end of the second inverter is connected to the control end of the first three-terminal switch device, the first end of the first three-terminal switch device is electrically connected to the input end of the driving unit, and the second end of the first three-terminal switch device is grounded; the first end of the pull-down device is connected to the output end of the driving unit, and the second end of the pull-down device is grounded.

4. The power clamp circuit according to claim 1, wherein: The delay unit includes a first resistor and a first capacitor connected in series, a first end of the first resistor is electrically connected to the power supply, a first end of the first capacitor is grounded, and a second end of the first resistor and a second end of the first capacitor are electrically connected to form the common end.

5. The power clamp circuit according to claim 4, wherein: The resistance range of the first resistor is 30-100 kΩ, and the capacitance range of the first capacitor is 0.2-1.0 pF.

6. The power clamp circuit according to any one of claims 2 to 3, wherein: The discharge tube is an NMOS tube or an NPN tube; When the discharge tube is an NMOS tube, the first end of the discharge tube is a drain, the second end is a source, and the control end is a gate; When the discharge tube is an NPN tube, the first end of the discharge tube is the collector, the second end is the emitter, and the control end is the base.

7. The power clamp circuit according to claim 2 or 3, wherein: The first three-terminal switch device is an NMOS tube or an NPN tube; When the first three-terminal switch device is an NMOS tube, the first terminal of the first three-terminal switch device is a drain, the second terminal is a source, and the control terminal is a gate; When the first three-terminal switch device is an NPN tube, the first terminal of the first three-terminal switch device is a collector, the second terminal is an emitter, and the control terminal is a base.

8. A chip, characterized in that: A power clamp circuit comprising the power clamp circuit according to any one of claims 1 to 7.

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