Wafer-Level Packaging Using Molded Interposer

Abstract

The present invention relates to wafer-level packaging using a molded interposer. A molded interposer comprises: a first molding material layer having a first surface and a second surface opposite to the first surface; a first redistribution layer (RDL) structure disposed on the first surface; a second redistribution layer (RDL) structure disposed on the second surface; a plurality of metal plugs buried in the first molding material layer to electrically connect the first redistribution layer structure with the second redistribution layer structure; and a passive device buried in the first molding material layer.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of the invention patent application with the application date of January 3, 2017, application number 201710002754.4, and invention name “Wafer-level packaging using molded interposer”. Technical Field

[0003] The present invention relates to the technical field of semiconductor packaging, and in particular to a wafer level package (WLP) using a molded interposer, wherein an integrated passive device is buried in the molded interposer. Background Art

[0004] 2.5D semiconductor packaging, such as CoWoS (Chip-On-Wafer-On-Substrate) technology, is known in the art. CoWoS technology generally uses through-silicon via (TSV) technology to combine multiple chips into a single device.

[0005] This architecture provides higher density interconnects, reduces overall interconnect length, and reduces associated resistive and capacitive loading, resulting in improved performance and reduced power consumption in a smaller form factor.

[0006] Since the process of the interposer substrate with TSV is relatively complicated, the TSV silicon interposer is generally expensive, and therefore, it may not be suitable for forming a WLP product including a TSV interposer for certain applications.

[0007] In addition, 2.5D semiconductor packaging places multiple chips side by side on a TSV silicon interposer. Passive devices such as capacitors or resistors can be placed on the same surface where the chips are mounted. This arrangement results in a TSV interposer with a large surface area. However, in practical applications, it is usually desirable to reduce the size of the interposer. Summary of the invention

[0008] The present invention provides a molded interposer having a smaller size and a semiconductor package using the molded interposer.

[0009] In one aspect of the present invention, a molded interposer is provided, comprising: a first molding compound layer having a first surface and a second surface opposite to the first surface; a first redistribution layer structure disposed on the first surface; a second redistribution layer structure disposed on the second surface; a plurality of metal plugs buried in the first molding compound layer to electrically connect the first redistribution layer structure and the second redistribution layer structure; and a passive device buried in the first molding compound layer, wherein the passive device is electrically connected to the first redistribution layer structure via a plurality of connectors.

[0010] In another aspect, the present invention provides a semiconductor package, comprising the above-mentioned molded interposer and at least one semiconductor chip disposed on the first redistribution layer structure of the molded interposer. The semiconductor chip is molded and encapsulated by a second molding compound layer. The first molding compound layer and the second molding compound layer have different compositions.

[0011] In another aspect, the present invention provides a method for manufacturing a semiconductor package. First, a first carrier is provided; then, a first redistribution layer structure is formed on the first carrier; then, a template layer is formed on the first redistribution layer structure, and then, a plurality of guide holes are formed in the template layer; then, metal plugs are formed in the plurality of guide holes respectively; then, the template layer is removed; then, a passive device is arranged on the first redistribution layer structure; then, the passive device and the metal plug are mold-encapsulated and coated in a first molding material layer; then, the first molding material layer is polished to expose the metal plug; then, a second redistribution layer structure is formed on the first molding material layer; then, a plurality of solder balls are formed on the second redistribution layer structure; finally, a semiconductor chip is arranged on the first redistribution layer structure.

[0012] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate some embodiments of the invention and together with the description serve to explain the principles thereof.

[0014] Figures 1 to 13 FIG. 4 is an exemplary method of manufacturing a wafer-level package with a molded interposer according to an embodiment of the present invention.

[0015] Figures 14 to 20 FIG. 4 is an exemplary method for manufacturing a wafer-level package with a molded interposer according to another embodiment of the present invention.

[0016] Fig.21 The metal plugs including dummy metal plugs are shown having a larger via diameter than non-dummy metal plugs. DETAILED DESCRIPTION

[0017] In the following, specific embodiments of the present invention are described, and the specific embodiments may refer to the corresponding drawings, so that the drawings constitute a part of the embodiments. At the same time, by way of description, the manner in which the present invention can be implemented is disclosed. The embodiments have been clearly described in sufficient detail so that those skilled in the art can implement the invention. Other embodiments may also be implemented, and changes made to their structures are still within the scope of the present invention.

[0018] Therefore, the following detailed description shall not be considered as a limitation, and the scope of the present invention is only covered by the claims and their equivalents. One or more embodiments of the present invention will be described with reference to the accompanying drawings, in which the same element numbers are used to represent the same elements throughout, and the structures described therein are not necessarily drawn to scale.

[0019] The terms "chip," "semiconductor chip," and "semiconductor die" are used interchangeably throughout the specification.

[0020] As used herein, the terms "wafer" and "substrate" include any structure having an exposed surface on which a layer is deposited according to the present invention, for example, to form a circuit structure such as a redistribution layer. The term "substrate" is understood to include semiconductor wafers, but is not limited thereto. The term "substrate" may also be used to refer to a semiconductor structure in process, and may include other layers that have been fabricated thereon.

[0021] Please refer to Figures 1 to 13 . Figures 1 to 13 FIG. 4 is an exemplary method of manufacturing a wafer-level package with a molded interposer according to an embodiment of the present invention.

[0022] like Figure 1 As shown, first, a carrier 300 is provided. The carrier 300 may be a substrate that can be torn off. The carrier 300 may include glass, silicon, ceramic, metal or any suitable supporting material. At least one dielectric layer or passivation layer 310 is provided on the upper surface of the carrier 300. The passivation layer 310 may include an organic material such as polyimide or an inorganic material such as silicon nitride, silicon oxide, or the like, but is not limited thereto.

[0023] Then, if Figure 2 As shown, a redistribution layer (RDL) structure 410 is formed on the passivation layer 310. The RDL structure 410 is used as a front-side (or chip-side) RDL interposer that can fan out the output / input pads on the semiconductor chip. The RDL structure 410 may include at least one dielectric layer 412 and at least one metal layer 414.

[0024] According to an embodiment of the present invention, the dielectric layer 412 may include an organic material such as polyimide, or an inorganic material such as silicon nitride, silicon oxide, or the like, but is not limited thereto.

[0025] Metal layer 414 may include aluminum, copper, tungsten, titanium, titanium nitride, or the like. According to the illustrated embodiment, metal layer 414 may include a plurality of fine pitch wirings, contact pads 418 emerging from the upper surface of dielectric layer 412 , and contact pads 419 directly contacting passivation layer 310 .

[0026] It should be understood that the layers and layout of the metal layer 414 and the contact pads 418 and 419 are for illustration purposes only. In other embodiments, more layers of metal wiring may be formed in the RDL structure 410 according to design requirements.

[0027] like Figure 3 As shown, a template layer 500 is coated on the RDL structure 410. For example, the template layer 500 may be a photoresist, such as an I-line photoresist or a directed self-assembly (DSA) material, but is not limited thereto.

[0028] like Figure 4 As shown, guide holes 501 are formed in the template layer 500. Each guide hole 501 extends through the entire thickness of the template layer 500. According to an embodiment of the present invention, the guide hole 501 may expose the corresponding contact pad 418 for further connection. According to an embodiment of the present invention, the guide hole 501 may include at least one dummy guide hole 501a.

[0029] In order to form the guide hole 501 , a photolithography process may be performed on the template layer 500 including, for example, photoresist, including but not limited to an exposure process and a development process.

[0030] According to one embodiment of the present invention, the guide holes 501 may have the same through hole diameter or size. According to other embodiments of the present invention, the guide holes 501 may have different through hole diameters. For example, the dummy guide hole 501a may have a larger through hole diameter than other non-dummy guide holes.

[0031] like Figure 5 As shown, after forming the guide holes 501, metal plugs 510 are formed in the guide holes 501. According to an embodiment of the present invention, the guide holes 501 are completely filled with metal, such as copper, tungsten, aluminum, titanium, titanium nitride or the like, to form metal plugs 510. The metal plugs 510 can be formed by deposition, screen printing or any other suitable method.

[0032] According to an embodiment of the present invention, the metal plug 510 may include at least one dummy metal plug 510a formed in the dummy via 501a for the purpose of eliminating stress or controlling warpage. At least one dummy via 501a may be directly disposed on the dummy pad 418a. The dummy pad 418a is an electrically isolated pad. When the integrated circuit package is in operation, no signal passes through the dummy pad 418a and the dummy metal plug 510a.

[0033] A chemical mechanical polishing (CMP) process may be optionally performed to remove excess metal outside the via 501. According to an embodiment of the present invention, the metal plug 510 may have a height that is the same as the thickness t of the template layer 500.

[0034] According to one embodiment of the present invention, the metal plugs 510 may have the same diameter or size. According to other embodiments of the present invention, the metal plugs 510 may have different diameters. For example, the dummy metal plug 510a may have a larger diameter than other non-dummy metal plugs.

[0035] According to an embodiment of the present invention, the metal plug 510 may be used as an interconnection between the front-side RDL structure and the back-side RDL structure, a heat sink, or a stress adjuster (dummy metal plug).

[0036] like Figure 6 As shown, after forming the metal plug 510, the template layer 500 is completely removed, leaving the complete metal plug 510, which includes the dummy metal plug 510a. For example, if the template layer 500 contains a photoresist, the template layer 500 can be removed by plasma etching or ashing process. The contact pad 418 is exposed, and the passive device setting areas 602 and 603 are defined between the metal plugs 510.

[0037] like Figure 7 As shown, passive device 612 and passive device 613 are respectively disposed on contact pad 418 exposed in passive device disposition regions 602 and 603. Passive device 612 can be electrically connected to contact pad 418 via connector 614, and passive device 613 can be electrically connected to contact pad 418 via connector 615.

[0038] According to an embodiment of the present invention, the connectors 614 and 615 may include tin bumps, copper bumps, micro bumps or copper pillars, but are not limited thereto. According to an embodiment of the present invention, the passive components 612 and 613 may include capacitors, resistors or inductors, but are not limited thereto. According to an embodiment of the present invention, the passive components 612 and 613 may be disposed on the contact pad 418 by using surface mount technology (SMT).

[0039] like Figure 8As shown, a molding compound 550 is formed to encapsulate the metal plug 510, the passive devices 612 and 613, and the RDL structure 410. The molding compound 550 may be subjected to a curing process. The molding compound 550 may include a mixture of epoxy resin and silicon filler, but is not limited thereto. The thickness of the molding compound 550 is thicker than the thickness of the passive devices 612 and 613.

[0040] like Fig. 9 As shown, a polishing process is performed to remove the upper portion of the molding material 550 to expose the upper surface of the metal plug 510 .

[0041] like Fig.10 As shown, a redistribution layer (RDL) structure 710 is formed on the molding compound 550 and the metal plug 510. The RDL structure 710 is used as a backside (or PCB side) RDL interposer. The RDL structure 710 may include at least one dielectric layer 712 and at least one metal layer 714.

[0042] According to an embodiment of the present invention, the dielectric layer 712 may include an organic material such as polyimide, or an inorganic material such as silicon nitride, silicon oxide, or the like, but is not limited thereto.

[0043] The metal layer 714 may include aluminum, copper, tungsten, titanium, titanium nitride, or the like. According to the illustrated embodiment, the metal layer 714 may include a plurality of wirings, and the contact pad 718 is exposed from the upper surface of the dielectric layer 712. A dummy metal layer 714a may be selectively formed on the dummy metal plug 510a. The dummy metal layer 714a is electrically isolated and is not connected to other wirings of the metal layer 714.

[0044] It should be understood that the layers and layout of the metal layer 714 and the contact pad 718 are for illustration purposes only. In other embodiments, more layers of metal wiring may be formed in the RDL structure 710 according to design requirements.

[0045] Subsequently, solder balls 810, such as ball grid array (BGA) solder balls, are formed on the contact pads 718. It should be understood that the solder resist 802 may be formed on the RDL structure 710. Before forming the solder balls 810, an under bump metal (UBM) layer (not explicitly shown in the figure) may be formed on the contact pads 718.

[0046] like Fig.11As shown, after forming the solder balls 810, the passivation layer 310 and the carrier 300 are removed, thereby exposing the contact pads 419 of the RDL structure 410, and completing the wafer-level molded interposer 100. Subsequently, the wafer-level molded interposer 100 is bonded to the carrier 320, wherein the solder balls 810 are in direct contact with the carrier 320. An adhesive layer (not explicitly shown in the figure) may be provided on the carrier 320. The carrier 320 may include glass, silicon, ceramic, metal, or any suitable support material.

[0047] like Fig.12 As shown, the semiconductor chip 11 and the semiconductor chip 12 are disposed on the RDL structure 410. The semiconductor chip 11 and the semiconductor chip 12 may be flip chips. The semiconductor chip 11 and the semiconductor chip 12 are electrically connected to the RDL structure 410 through the contact pad 419. The semiconductor chip 11 and the semiconductor chip 12 are electrically connected to the RDL structure 710 through the RDL structure 410 and the metal plug 510.

[0048] Subsequently, a molding compound 560 is formed to encapsulate the RDL structure 410 and the semiconductor chips 11 and 12, thereby forming a wafer-level package 101. In order not to affect the properties of the molding compound 550, the glass transition temperature of the molding compound 560 can be lower than the glass transition temperature of the molding compound 550.

[0049] According to an embodiment of the present invention, the molding compound 560 may be cured at a lower temperature, for example, a temperature below the glass transition temperature of the molding compound 550. According to an embodiment of the present invention, the molding compound 550 and the molding compound 560 may have different compositions. In other embodiments, the molding compound 560 may be omitted.

[0050] like Fig.13 As shown, a dicing process may be performed to diced the wafer level package 101 into individual chip packages 10. It should be understood that in other embodiments, each chip package 10 may include only one chip.

[0051] The technical feature of the present invention is that the passive components 612 and 613 are embedded in the molded interposer 100 and are molded by the molding compound 550. The overall size of the molded interposer in each chip package 10 can be reduced.

[0052] Please refer to Figures 14 to 20 . Figures 14 to 20 FIG. 4 is an exemplary method for manufacturing a wafer-level package with a molded interposer according to another embodiment of the present invention, wherein the same reference numerals are used to represent the same layers, regions or components.

[0053] like Fig.14As shown, a carrier 300 is provided first. Then, a redistribution layer (RDL) structure 410 is formed on the passivation layer 310. The RDL structure 410 is used as a front-side (or chip-side) RDL interposer, which can fan out the output / input pads on the semiconductor chip. The RDL structure 410 may include at least one dielectric layer 412 and at least one metal layer 414.

[0054] A template layer 500 is coated on the RDL structure 410. For example, the template layer 500 may be a photoresist, such as an I-line photoresist or a directed self-assembly (DSA) material, but is not limited thereto. Subsequently, guide holes 501 are formed in the template layer 500. Each guide hole 501 extends through the entire thickness of the template layer 500.

[0055] According to one embodiment of the present invention, the guide holes 501 may have the same through hole diameter or size. According to other embodiments of the present invention, the guide holes 501 may have different through hole diameters. According to other embodiments of the present invention, some of the guide holes 501 are dummy guide holes.

[0056] like Fig.15 As shown, after forming the guide holes 501, metal plugs 510 are formed in the guide holes 501. According to one embodiment of the present invention, the guide holes 501 are completely filled with metal, such as copper, tungsten, aluminum, titanium, titanium nitride or the like, to form metal plugs 510. The metal plugs 510 can be formed by deposition, screen printing or any suitable method. According to other embodiments of the present invention, some of the metal plugs 510 are dummy metal plugs.

[0057] A chemical mechanical polishing (CMP) process may be optionally performed to remove excess metal outside the via 501. According to an embodiment of the present invention, the metal plug 510 may have a height that is the same as the thickness t of the template layer 500.

[0058] According to other embodiments of the present invention, the metal plug 510 may have different through-hole diameters, for example, Fig.21 As shown, the metal plug 510 may include a dummy metal plug 510 ′ having a larger via diameter than other non-dummy metal plugs.

[0059] According to an embodiment of the present invention, the metal plug 510 may be used as an interconnection between the front-side RDL structure and the back-side RDL structure, a heat sink, or a stress adjuster (dummy metal plug).

[0060] like Fig.16 As shown, after the metal plug 510 is formed, the template layer 500 is completely removed, leaving the complete metal plug 510. For example, when the template layer 500 contains photoresist, the template layer 500 can be removed by plasma etching or ashing process.

[0061] like Fig.17 As shown, a molding compound 550 is formed to cover the metal plug 510 and the RDL structure 410. A curing process may be performed on the molding compound 550. The molding compound 550 may include a mixture of epoxy resin and silicon filler, but is not limited thereto. Then, a polishing process is performed to remove the upper portion of the molding compound 550 to expose the upper surface of the metal plug 510.

[0062] like Fig.18 As shown, a redistribution layer (RDL) structure 710 is formed on the molding compound 550 and the metal plug 510. The RDL structure 710 is used as a backside (or PCB side) RDL interposer. The RDL structure 710 may include at least one dielectric layer 712 and at least one metal layer 714.

[0063] According to an embodiment of the present invention, the dielectric layer 712 may include an organic material such as polyimide, or an inorganic material such as silicon nitride, silicon oxide, or the like, but is not limited thereto.

[0064] Metal layer 714 may include aluminum, copper, tungsten, titanium, titanium nitride, or the like. According to the illustrated embodiment, metal layer 714 may include a plurality of wirings, and contact pads 718 may be exposed from the upper surface of dielectric layer 712 .

[0065] It should be understood that the layers and layout of the metal layer 714 and the contact pad 718 are for illustration purposes only. In other embodiments, more layers of metal wiring may be formed in the RDL structure 710 according to design requirements.

[0066] Subsequently, solder balls 810, such as ball grid array (BGA) solder balls, are formed on the contact pads 718. It should be understood that the solder resist 802 may be formed on the RDL structure 710. Before forming the solder balls 810, an under bump metal (UBM) layer (not explicitly shown in the figure) may be formed on the contact pads 718.

[0067] like Fig.19 As shown, after forming the solder balls 810, the passivation layer 310 and the carrier 300 are removed, thereby exposing the contact pads 419 of the RDL structure 410, and completing the wafer-level molding interposer 100. Subsequently, the wafer-level molding interposer 100 is bonded to the carrier 320, wherein the solder balls 810 are in direct contact with the carrier 320. An adhesive layer (not explicitly shown in the figure) may be provided on the carrier 320 to adhere the solder balls 810 to the carrier 320. The carrier 320 may include glass, silicon, ceramic, metal, or any suitable support material.

[0068] like Fig. 20As shown, the semiconductor chip 11 and the semiconductor chip 12 are disposed on the RDL structure 410. The semiconductor chip 11 and the semiconductor chip 12 may be flip chips. The semiconductor chip 11 and the semiconductor chip 12 are electrically connected to the RDL structure 410 through the contact pad 419. The semiconductor chip 11 and the semiconductor chip 12 are electrically connected to the RDL structure 710 through the RDL structure 410 and the metal plug 510.

[0069] Subsequently, a molding compound 560 is formed to encapsulate the RDL structure 410 and the semiconductor chips 11 and 12 to form a wafer-level package. In order not to affect the properties of the molding compound 550 , the glass transition temperature of the molding compound 560 may be lower than the glass transition temperature of the molding compound 550 .

[0070] According to an embodiment of the present invention, the molding compound 560 may be cured at a lower temperature, for example, a temperature lower than the glass transition temperature of the molding compound 550. According to an embodiment of the present invention, the molding compound 550 and the molding compound 560 may have different compositions. In other embodiments, the molding compound 560 may be omitted. Then, a dicing process may be performed to dicing the wafer-level package into individual chip packages 10. It should be understood that in other embodiments, each chip package 10 may only include one chip.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor package, comprising: A molded interposer comprising: A first molding compound having a first surface and a second surface opposite to the first surface; A first redistribution layer (RDL) structure disposed on the first surface; A second redistribution layer (RDL) structure disposed on the second surface; a metal plug, which is buried in the first molding compound and electrically connects the first redistribution layer RDL structure with the second redistribution layer RDL structure; and Passive devices, each of which is provided by surface mount technology (SMT) and electrically connected to the first redistribution layer (RDL) structure, each of which is completely buried and completely surrounded by the first molding material, and the thickness of the first molding material is greater than the thickness of each of the passive devices; a semiconductor chip disposed on the first redistribution layer (RDL) structure and electrically connected to the first redistribution layer (RDL) structure at a side opposite to the passive device in a flip-chip manner, each of the semiconductor chips being electrically connected to a corresponding one of the passive devices by direct connection using a connector and having a package covering the corresponding one, so as to form a face-to-face connection between each of the semiconductor chips and the corresponding one of the passive devices using the first redistribution layer (RDL) structure; a second molding material located on the side of the first redistribution layer (RDL) structure opposite to the passive device, the second molding material encapsulating at least one of the semiconductor chips, the first molding material and the second molding material having different compositions from each other, and a glass transition temperature of the second molding material being lower than a glass transition temperature of the first molding material; and The solder balls are arranged on the second redistribution layer RDL structure.

2. The semiconductor package according to claim 1, further comprising: A dummy metal plug is buried in the first molding compound and extends between the first redistribution layer (RDL) structure and the second redistribution layer (RDL) structure, the dummy metal plug being electrically isolated from a signal and positioned for at least one of stress relief or warpage control of the semiconductor package. 3 . The semiconductor package of claim 2 , wherein a diameter of each corresponding dummy metal plug is larger than a diameter of each corresponding non-dummy metal plug. 4 . The semiconductor package according to claim 2 , wherein the second redistribution layer (RDL) structure comprises a dummy metal material layer formed on the dummy metal plug, the dummy metal material being electrically isolated from a signal. 5 . The semiconductor package according to claim 1 , wherein each of the passive devices comprises a capacitor, a resistor, or an inductor. 6 . The semiconductor package according to claim 1 , wherein a height of each of the metal plugs is equal to a thickness of the first molding compound. 7 . The semiconductor package according to claim 1 , wherein each of the passive devices is off-center relative to each of the semiconductor chips. 8 . The semiconductor package according to claim 1 , wherein the first redistribution layer (RDL) structure is configured as a chip-side redistribution layer (RDL) interposer to fan out input / output pads on each of the semiconductor chips. 9 . The semiconductor package according to claim 1 , wherein the second redistribution layer (RDL) structure is configured as a PCB-side interposer.

10. The semiconductor package according to any one of claims 1 to 4, wherein the solder balls comprise ball grid arrays (BGA).

11. A method for manufacturing a semiconductor package, comprising: providing a first carrier board; forming a first redistribution layer (RDL) structure on the first carrier; forming a template structure layer on the first redistribution layer RDL structure; forming a plug in the template structure; forming a metal structure in the plug electrically connected to the first redistribution layer (RDL) structure; removing the template structure; Disposing passive devices on the first redistribution layer (RDL) structure, each of the passive devices being electrically connected to the first redistribution layer (RDL) structure through surface mount technology (SMT); Molding each of the passive devices and each of the metal structures with a first molding compound, so that each of the passive devices is completely buried in the first molding compound layer, and each of the passive devices is completely surrounded by the first molding compound; polishing the first molding compound material to expose the end surface of the metal structure, so that the thickness of the remaining first molding compound material is greater than the thickness of each of the passive components; forming a second redistribution layer (RDL) structure on the first molding compound material to electrically connect the second redistribution layer (RDL) structure to the first redistribution layer (RDL) structure through the metal structure; forming solder balls on the second redistribution layer RDL structure; Disposing semiconductor chips on the first redistribution layer (RDL) structure, and electrically connecting each of the semiconductor chips to a surface of the first redistribution layer (RDL) structure opposite to one of the passive devices using surface mount technology (SMT); Molding each of the semiconductor chips with a second molding compound on the side of the first redistribution layer (RDL) structure facing the passive device, wherein the first molding compound and the second molding compound have different compositions from each other, and curing the second molding compound at a temperature lower than a glass transition temperature of the first molding compound; as well as Each of the semiconductor chips is electrically connected to a corresponding one of the passive devices and a package of each of the semiconductor chips is positioned to cover the corresponding one.

12. The method according to claim 11, further comprising: Before disposing each of the semiconductor chips on the first redistribution layer RDL structure and after forming the solder balls on the second redistribution layer RDL structure: removing the first carrier to form a wafer-level molded interposer; as well as The wafer-level molded interposer is bonded to a second carrier, and the solder balls directly contact the second carrier when the wafer-level molded interposer is bonded to the second carrier.

13. The method of claim 11 or 12, wherein forming the template structure comprises forming a photoresist structure. 14 . The method according to claim 11 , wherein disposing the passive device on the first redistribution layer (RDL) structure comprises selecting the passive device from among a capacitor, a resistor and an inductor.

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