Composite circuit protection device

Abstract

A composite circuit protection device includes a positive temperature coefficient (PTC) element, a varistor, a first conductive lead and a second conductive lead. The PTC element includes a PTC layer, a first electrode layer and a second electrode layer, the PTC layer has two opposite surfaces, and the first electrode layer and the second electrode layer are respectively arranged on the two opposite surfaces of the PTC layer. The varistor is connected to the second electrode layer. The first conductive lead is connected to the first electrode layer. The second conductive lead is connected to the varistor. The PTC element has a rated voltage, and the rated voltage is between 40% and 200% of the varistor voltage measured at 1 mA. The composite circuit protection device of the present invention has excellent tolerance. In the presence of overcurrent and overvoltage, the PTC element can protect the varistor from burning.

Description

Technical Field

[0001] The present invention relates to a composite circuit protection device, and more particularly to a composite circuit protection device comprising a positive temperature coefficient (PTC) element whose rated voltage is between 40% and 200% of a varistor (VDR, or varistor) measuring a varistor voltage at 1 mA. Background Art

[0002] US Patent No. 8,508,328B1 describes a plug-in polymer positive temperature coefficient (PPTC) over-current protection device. Figure 1 The PPTC overcurrent protection device comprises two electrodes 30, solder material, conductive leads 50, 60 respectively connected to the electrodes 30, and a PTC polymer substrate 20 laminated between the electrodes 30. A hole 40 is formed on the PTC polymer substrate 20, and the hole 40 has an effective volume capable of accommodating the thermal expansion of the PTC polymer substrate 20 when the temperature rises.

[0003] Electrical properties, such as operating current and high-voltage surge endurance, are important factors that affect the occurrence of power surges in PPTC overcurrent protection devices. When the operating current of the PPTC overcurrent protection device is increased by increasing the thickness or area of ​​the PTC polymer substrate 20, it is more susceptible to damage by power surges. On the other hand, when the high-voltage endurance of the PPTC overcurrent protection device is increased by reducing the thickness or area of ​​the PTC polymer substrate 20, the PPTC overcurrent protection device may not be less susceptible to damage by power surges.

[0004] Although a voltage-dependent resistor (VDR) can be combined with the PPTC overcurrent protection device to provide overcurrent and overvoltage protection for the combined composite circuit protection device, the VDR can only withstand power surges for a short period of time (e.g., 0.001 seconds). In other words, if the surge time exceeds the cut-off time interval, the VDR will burn out or be damaged due to overcurrent or overvoltage, causing the composite circuit protection device to permanently lose its function. Summary of the invention

[0005] An object of the present invention is to provide a composite circuit protection device that can overcome at least one disadvantage of the above-mentioned background technology.

[0006] The composite circuit protection device of the present invention comprises a positive temperature coefficient (PTC) element, a varistor, a first conductive lead and a second conductive lead. The PTC element comprises a PTC layer, a first electrode layer and a second electrode layer, the PTC layer has two opposite surfaces, and the first electrode layer and the second electrode layer are respectively arranged on two opposite surfaces of the PTC layer. The varistor is connected to the second electrode layer. The first conductive lead is connected to the first electrode layer. The second conductive lead is connected to the varistor. The PTC element has a rated voltage, and the rated voltage is between 40% and 200% of the varistor voltage measured at 1 mA of the varistor.

[0007] In the composite circuit protection device of the present invention, the PTC element has a rated voltage between 45% and 100% of the varistor's varistor voltage measured at 1 mA.

[0008] In the composite circuit protection device of the present invention, the PTC element has a rated voltage between 45% and 70% of the varistor voltage measured at 1 mA.

[0009] The composite circuit protection device of the present invention is that the PTC element is tripped before the varistor is burned when the PTC element is under overcurrent and a voltage greater than the varistor voltage.

[0010] The composite circuit protection device of the present invention is designed such that the PTC element trips within 1 μs to 100s when it is exposed to an overcurrent greater than 0.1A and a voltage greater than the varistor voltage.

[0011] The composite circuit protection device of the present invention is designed such that the PTC element trips within 1ms to 10s when it is exposed to an overcurrent greater than 0.5A and a voltage greater than the varistor voltage.

[0012] The composite circuit protection device of the present invention is designed such that the PTC element trips within 1ms to 1s when it is subjected to an overcurrent greater than 10A and a voltage greater than the varistor voltage.

[0013] In the composite circuit protection device of the present invention, the PTC element has a first hole formed in the PTC layer.

[0014] In the composite circuit protection device of the present invention, the PTC layer of the PTC element has a periphery, which defines the boundary of the PTC layer and is interconnected with two opposite surfaces of the PTC layer, and the first hole is spaced apart from the periphery of the PTC layer.

[0015] In the composite circuit protection device of the present invention, the first hole penetrates at least one of the two opposite surfaces of the PTC layer.

[0016] In the composite circuit protection device of the present invention, the first hole also penetrates at least one of the first electrode layer and the second electrode layer.

[0017] The composite circuit protection device of the present invention has a second hole formed on the varistor.

[0018] The composite circuit protection device of the present invention comprises a varistor including a varistor layer, a third electrode layer and a fourth electrode layer. The varistor layer has two opposite surfaces. The third electrode layer is arranged on one of the two opposite surfaces of the varistor layer and connected to the second electrode layer of the PTC element. The fourth electrode layer is arranged on the other of the two opposite surfaces of the varistor layer. The second conductive lead is connected to one of the third electrode layer and the fourth electrode layer of the varistor.

[0019] The composite circuit protection device of the present invention further comprises a third conductive lead. The second conductive lead is connected to the fourth electrode layer. The third conductive lead is connected to and disposed between the second electrode layer and the third electrode layer.

[0020] In the composite circuit protection device of the present invention, the varistor has a second hole formed in the varistor layer.

[0021] The composite circuit protection device of the present invention has a varistor layer with a periphery, which defines the boundary of the varistor layer and is interconnected with two opposite surfaces of the varistor layer, and the second hole is spaced apart from the periphery of the varistor layer.

[0022] In the composite circuit protection device of the present invention, the second hole penetrates at least one of the two opposite surfaces of the varistor layer.

[0023] In the composite circuit protection device of the present invention, the second hole also penetrates at least one of the third electrode layer and the fourth electrode layer.

[0024] In the composite circuit protection device of the present invention, the PTC element is a polymer PTC element, and the PTC layer is a PTC polymer layer.

[0025] The composite circuit protection device of the present invention further comprises a packaging material, wherein the packaging material packages the PTC element, the varistor, a portion of the first conductive lead and a portion of the second conductive lead.

[0026] The beneficial effects of the present invention are as follows: the composite circuit protection device of the present invention has excellent tolerance and reliability, and the PTC element can protect the varistor from burning out in the presence of overcurrent and overvoltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, in which:

[0028] Figure 1 It is a schematic diagram of an existing plug-in PPTC overcurrent protection device;

[0029] Figure 2 is a schematic diagram of a first specific embodiment of a composite circuit protection device of the present invention;

[0030] Figure 3 is a cross-sectional schematic diagram of the first specific embodiment;

[0031] Figure 4 is a schematic diagram of a second specific embodiment of the composite circuit protection device of the present invention;

[0032] Figure 5 is a cross-sectional schematic diagram of the second specific embodiment;

[0033] Figure 6 is a schematic diagram of a third specific embodiment of the composite circuit protection device of the present invention;

[0034] Figure 7 It is a cross-sectional schematic diagram of the third specific embodiment. DETAILED DESCRIPTION

[0035] Before the present invention is described in detail, it should be noted that similar elements are denoted by the same reference numerals in the following description.

[0036] See also Figure 2 and Figure 3 The first embodiment of the composite circuit protection device of the present invention comprises a positive temperature coefficient (PTC) element 2 , a varistor 3 , a first conductive lead 4 and a second conductive lead 5 .

[0037] The PTC element 2 includes a PTC layer 21 , a first electrode layer 22 and a second electrode layer 23 . The PTC layer 21 has two opposite surfaces 211 . The first electrode layer 22 and the second electrode layer 23 are respectively disposed on the two opposite surfaces 211 of the PTC layer 21 .

[0038] The varistor 3 is connected to the second electrode layer 23 via solder.

[0039] The first conductive lead 4 is connected to the first electrode layer 22 . The second conductive lead 5 is connected to the varistor 3 .

[0040] The PTC element 2 has a rated voltage, which is between 40% and 200% of the varistor voltage of the varistor 3 measured at 1 mA. In some embodiments of the present invention, the PTC element 2 has a rated voltage between 45% and 100% of the varistor voltage of the varistor 3 measured at 1 mA. In some embodiments of the present invention, the PTC element 2 has a rated voltage between 45% and 70% of the varistor voltage of the varistor 3 measured at 1 mA.

[0041] According to the present invention, the PTC element 2 is tripped before the varistor 3 burns out under the overcurrent and the voltage greater than the varistor voltage of the varistor 3. In other words, under the overcurrent and the voltage greater than the varistor voltage of the varistor 3, the PTC element 2 quickly trips to a high resistance state so that the overcurrent is limited from flowing through the varistor 3, thereby protecting the varistor 3 from burning out, and the composite circuit protection device can be reused.

[0042] In this document, the terms "burn", "spark" and "fire" are used interchangeably and refer to the varistor losing its function, usually at temperatures above 180°C.

[0043] In some specific embodiments of the present invention, the PTC element 2 is tripped within 1μs to 100s when it is in an overcurrent greater than 0.1A and a voltage greater than the varistor voltage of the varistor 3. In some specific embodiments of the present invention, the PTC element 2 is tripped within 10μs to 10s when it is in an overcurrent greater than 0.1A and a voltage greater than the varistor voltage of the varistor 3. In some specific embodiments of the present invention, the PTC element 2 is tripped within 0.1ms to 1s when it is in an overcurrent greater than 0.1A and a voltage greater than the varistor voltage of the varistor 3.

[0044] In some specific embodiments of the present invention, the PTC element 2 is tripped within 1ms to 10s when it is subjected to an overcurrent greater than 0.5A and a voltage greater than the varistor voltage of the varistor 3. In some specific embodiments of the present invention, the PTC element 2 is tripped within 1ms to 1s when it is subjected to an overcurrent greater than 0.5A and a voltage greater than the varistor voltage of the varistor 3.

[0045] In some specific embodiments of the present invention, the PTC element 2 is tripped within 1ms to 1s when it is subjected to an overcurrent greater than 10A and a voltage greater than the varistor voltage of the varistor 3. In some specific embodiments of the present invention, the PTC element 2 is tripped within 1ms to 0.1s when it is subjected to an overcurrent greater than 10A and a voltage greater than the varistor voltage of the varistor 3.

[0046] The PTC element 2 may be formed with a first hole 210. In the present embodiment, the first hole 210 is formed in the PTC layer 21. The PTC layer 21 of the PTC element 2 has a periphery 212, which defines the boundary of the PTC layer 21 and is interconnected with two opposite surfaces 211 of the PTC layer 21. The first hole 210 is spaced from the periphery 212 of the PTC layer 21 and has an effective volume that can accommodate the thermal expansion of the PTC layer 21 when the temperature rises, so as to avoid the PTC layer 21 from having an undesirable structural deformation.

[0047] In some specific embodiments of the present invention, the first hole 210 penetrates at least one of the two opposite surfaces 211 of the PTC layer 21. In some specific embodiments of the present invention, the first hole 210 also penetrates at least one of the first electrode layer 22 and the second electrode layer 23. In this embodiment, the first hole 210 penetrates the two opposite surfaces 211 of the PTC layer 21 and the first electrode layer 22 and the second electrode layer 23 to form a through hole. In some specific embodiments of the present invention, the first hole 210 extends along a line passing through the geometric center of the PTC layer 21 and crossing the two opposite surfaces 211. The first hole 210 is defined by a hole definition wall, and the hole definition wall has a cross section parallel to the surface 211 of the PTC layer 21. The cross section of the hole definition wall can be circular, square, elliptical, triangular, cross-shaped, etc.

[0048] According to the present invention, the PTC element 2 may be a polymer PTC (PPTC) element, and the PTC layer 21 may be a PTC polymer layer. The PTC polymer layer includes a polymer substrate and a conductive filler dispersed in the polymer substrate. The polymer substrate may be made from a polymer composition containing a non-grafted olefin-based polymer. In certain specific embodiments of the present invention, the non-grafted olefin-based polymer is a high-density polyethylene (HDPE). In certain specific embodiments of the present invention, the polymer composition also includes a grafted olefin-based polymer. In certain specific embodiments of the present invention, the grafted olefin-based polymer is an olefin-based polymer grafted with carboxylic anhydride. The conductive filler applicable to the present invention is selected from carbon black powder, metal powder, conductive ceramic powder or a combination of the foregoing, but is not limited thereto.

[0049] According to the present invention, the varistor 3 may include a varistor layer 31, a third electrode layer 32 and a fourth electrode layer 33. The varistor layer 31 has two opposite surfaces 311. The second conductive lead 5 is connected to one of the third electrode layer 32 and the fourth electrode layer 33 of the varistor 3. In some specific embodiments of the present invention, the varistor layer 31 is made of a metal oxide material.

[0050] In this embodiment, the third electrode layer 32 is disposed on one of the two opposite surfaces 311 of the varistor layer 31 and connected to the second electrode layer 23 of the PTC element 2; the fourth electrode layer 33 is disposed on the other of the two opposite surfaces 311 of the varistor layer 31. The second conductive lead 5 is connected and disposed between the second electrode layer 23 and the third electrode layer 32.

[0051] The varistor 3 may have a second hole 310 formed in the varistor layer 31. In the present embodiment, the varistor layer 31 of the varistor 3 has a periphery 312, which defines the boundary of the varistor layer 31 and interconnects two opposite surfaces 311 of the varistor layer 31. The second hole 310 is spaced apart from the periphery 312 of the varistor layer 31.

[0052] In some embodiments of the present invention, the second hole 310 penetrates at least one of the two opposite surfaces 311 of the varistor layer 31. In some embodiments of the present invention, the second hole 310 also penetrates at least one of the third electrode layer 32 and the fourth electrode layer 33. In this embodiment, the second hole 310 penetrates the two opposite surfaces 311 of the varistor layer 31 and the third electrode layer 32 and the fourth electrode layer 33 to form a through hole.

[0053] According to the present invention, the first conductive lead 4 has a connection portion 41 and a free portion 42, and the second conductive lead 5 has a connection portion 51 and a free portion 52. The connection portion 41 of the first conductive lead 4 is connected to the outer surface of the first electrode layer 22 by solder, and the free portion 42 of the first conductive lead 4 extends from the connection portion 41 out of the first electrode layer 22 for insertion into a pin hole of a circuit board or a circuit device (not shown). In the present embodiment, the connection portion 51 of the second conductive lead 5 is connected by solder and disposed between the second electrode layer 23 and the third electrode layer 32, and the free portion 52 of the second conductive lead 5 extends from the connection portion 51 out of the second electrode layer 23 and the third electrode layer 32 for insertion into a pin hole of a circuit board or a circuit device (not shown).

[0054] See also Figure 4 and Figure 5 The second embodiment of the composite circuit protection device of the present invention is similar to the first embodiment, except that in the second embodiment, the connection portion 51 of the second conductive lead 5 is connected to the outer surface of the fourth electrode layer 33 by solder, and the free portion 52 of the second conductive lead 5 extends from the connection portion 51 out of the fourth electrode layer 33 for insertion into the pin hole of a circuit board or circuit device (not shown). In addition, the second embodiment further includes a packaging material 7, which packages the PTC element 2, the varistor 3, a portion of the first conductive lead 4 and a portion of the second conductive lead 5. The free portion 42 of the first conductive lead 4 and the free portion 52 of the second conductive lead 5 are exposed outside the packaging material 7. In some specific embodiments of the present invention, the packaging material 7 is made of epoxy resin.

[0055] See also Figure 6 and Figure 7The third embodiment of the composite circuit protection device of the present invention is similar to the second embodiment, except that the third embodiment further comprises a third conductive lead 6, which is connected and disposed between the second electrode layer 23 and the third electrode layer 32. The third conductive lead 6 has a connecting portion 61 and a free portion 62. The connecting portion 61 of the third conductive lead 6 is connected to the second electrode layer 23 and the third electrode layer 32, and the free portion 62 of the third conductive lead 6 extends from the connecting portion 61 out of the second electrode layer 23 and the third electrode layer 32 for insertion into a pin hole of a circuit board or a circuit device (not shown).

[0056] In this embodiment, the packaging material 7 packages the PTC element 2, the varistor 3, a portion of the first conductive lead 4, a portion of the second conductive lead 5, and a portion of the third conductive lead 6. The free portion 42 of the first conductive lead 4, the free portion 52 of the second conductive lead 5, and a portion of the free portion 62 of the third conductive lead 6 are exposed outside the packaging material 7.

[0057] The present invention will be further described with reference to the following examples, but it should be understood that the examples are only for illustration and should not be construed as limitations of the present invention.

[0058] Example

[0059] <Example 1 (E1)>

[0060] 21g HDPE (purchased from Taiwan Plastics Industry Co., Ltd., product model: HDPE9002) is used as the non-grafted olefin polymer, 21g HDPE grafted with maleic anhydride (purchased from DuPont, product model: MB100D) is used as the olefin polymer grafted with carboxylic anhydride, and 58g carbon black powder (purchased from Columbian Chemicals, product model: Raven430UB) is used as the conductive filler.

[0061] The above three ingredients were mixed in a mixer (Brabender) at a temperature of 200° C. and a stirring speed of 30 rpm for 10 minutes.

[0062] The above-obtained mixture was placed in a mold and hot-pressed at a temperature of 200°C and a pressure of 80 kg / cm 2 The PTC polymer layer sheet was formed by hot pressing for 4 minutes under the conditions of 200°C and 80kg / cm 2The PPTC element is hot pressed for 4 minutes to form a PPTC element with a thickness of 0.42 mm. The PPTC element is then cut into a plurality of 9.5 mm × 11 mm chips (hereinafter referred to as PPTC-1), and each chip is irradiated with Co-60 gamma rays with a total radiation dose of 150 kGy. The first conductive lead and the second conductive lead are respectively welded to the two copper foils of each chip, and then a metal oxide varistor (MOV, purchased from Ceramate Technical Company, product model: 07D270K, hereinafter referred to as MOV-1) is welded to one of the two copper foils to form an E1 composite circuit protection device.

[0063] According to Underwriter Laboratories' safety standard UL 1434 for thermistor-type devices, the hold current (i.e., the maximum current value during normal operation), trip current (i.e., the minimum current value required for the PPTC element to reach a high resistance state), rated voltage (i.e., the voltage applicable to the PPTC element when it is working), and withstand voltage (i.e., the maximum voltage that will not cause PPTC element failure or damage) of the PPTC chip were measured. In addition, according to Underwriter Laboratories' safety standard UL 1449 for transient voltage surge suppressors, the varistor voltage (i.e., the voltage at which the MOV triggers its operation) and clamping voltage (i.e., the maximum voltage that the MOV can provide for limitation) of the MOV element were measured. The property measurement results of PPTC-1 and MOV-1 are shown in Table 1.

[0064] Table 1

[0065]

[0066] a: Measured at 1mA.

[0067] b: In the pulse waveform (t p )8 / 20μs and pulse current (I p )Measured at 2.5A.

[0068] <Examples 2 to 4 (E2-E4)>

[0069] The process conditions of the composite circuit protection devices E2-E4 are similar to those of E1. The difference is that the PPTC chip is formed with a first through hole and / or the MOV is formed with a second through hole (as shown in Table 3). Each first through hole and each second through hole is formed with a circular cross section (diameter is 1.5 mm, circle area is 1.77 mm 2 ) is defined by the hole definition wall.

[0070] In E2, after γ-ray irradiation, a first through hole is bored in the center of the PPTC chip. In E3, before copper foil is soldered, a second through hole is bored in the center of the MOV. In E4, a first through hole is bored in the center of the PPTC chip and a second through hole is bored in the center of the MOV (e.g., Figure 3 shown).

[0071] <Comparative Examples 1 to 4 (CE1-CE4)>

[0072] The process conditions of the composite circuit protection devices of CE1-CE4 are similar to those of E1-E4, respectively, with the difference being that CE1 and CE2 do not contain PPTC chips, and CE3 and CE4 do not contain MOVs.

[0073] <Examples 5 to 8 (E5-E8)>

[0074] The process conditions of the composite circuit protection device of E5-E8 are similar to those of E1-E4, respectively. The difference is that the ingredients for forming the PTC polymer layer sheet of E5-E8 are 10g HDPE, 10g HDPE grafted with maleic anhydride, 15g carbon black powder and 15g magnesium hydroxide (purchased from MagChem, product model: MH 10), and the PPTC small piece of E5-E8 (hereinafter referred to as PPTC-2) is cut into a circle with a thickness of 2.2mm (diameter of 3.1mm). In addition, the MOV of E5-E8 is purchased from Ceramate Technical, product model: 20D361K (hereinafter referred to as MOV-2). The property measurement results of PPTC-2 and MOV-2 ​​are shown in Table 2.

[0075] Table 2

[0076]

[0077] a: Measured at 1mA.

[0078] b: In the pulse waveform (t p )8 / 20μs and pulse current (I p )Measured at 2.5A.

[0079] <Comparative Examples 5 to 8 (CE5-CE8)>

[0080] The process conditions of the composite circuit protection devices of CE5-CE8 are similar to those of E5-E8, respectively. The difference is that CE5 and CE6 do not contain PPTC chips, and CE7 and CE8 do not contain MOV.

[0081] <Examples 9 to 12 (E9-E12)>

[0082] The process conditions of the composite circuit protection device of E9-E12 are similar to those of E5-E8. The difference is that the MOV used to form E9-E12 is purchased from Ceramate Technical Company, product model: 20D511K (hereinafter referred to as MOV-3). The varistor voltage of MOV-3 is 510V (measured at 1mA), and its clamping voltage is 845V [in the pulse waveform (t p )8 / 20μs and pulse current (I p )Measured at 2.5A].

[0083] <Comparative Examples 9 to 12 (CE9-CE12)>

[0084] The process conditions of the composite circuit protection devices of CE9-CE12 are similar to those of E9-E12, respectively, with the difference being that CE9 and CE10 do not contain PPTC chips, and CE11 and CE12 do not contain MOVs.

[0085] Table 3

[0086]

[0087]

[0088] “--” means there is no such component.

[0089] Performance Testing

[0090] [Surge immunity test]

[0091] Ten composite circuit protection devices of E1-E12 and CE1-CE12 were taken as test samples for surge immunity test.

[0092] For E1-E4 and CE1-CE4 composite circuit protection devices, the surge immunity test of each test sample is conducted at a voltage greater than the varistor voltage of MOV-1 (including 38V and 44V) and a current of 0.5A and PPTC-1 overcurrent (i.e. 10A) by first turning on for 60 seconds and then turning off. If neither the PPTC chip nor the MOV is burned or damaged, the test sample passes the surge immunity test, and the average time of the PPTC chip tripping is recorded (if there is a trip). If one of the PPTC chip and the MOV is burned, the test sample is burned, and the average time of its burning is recorded. The results are shown in Table 4.

[0093] Table 4

[0094]

[0095] The results in Table 4 show that the test samples of CE1 and CE2 containing only MOV-1 burned within 5 seconds under a current of 0.5A and a voltage of at least 1.4 times the varistor voltage of MOV-1 (generally MOV can withstand a voltage of 1.2 times its varistor voltage), or burned within 2.5 seconds under an overcurrent and overvoltage of 10A, and the damage cannot be repaired. The test samples of CE3 and CE4 containing only PPTC-1 burned under an overcurrent of 10A. On the contrary, all the test samples of E1-E4 containing a combination of PPTC-1 and MOV-1 (where the rated voltage of PPTC-1 is about 59% of the varistor voltage of MOV-1) passed the surge immunity test without burning. In addition, compared to E1, the test samples of E2-E4 with PPTC-1 and / or MOV-1 formed with perforations improve heat transfer, further shorten the time for PPTC-1 to trip, and prevent overcurrent from flowing through MOV-1, thereby protecting its MOV-1 from burning. In other words, in the test samples of E1-E4, PPTC-1 is tripped before MOV-1 burns under overcurrent and voltage greater than the varistor voltage of MOV-1.

[0096] For E5-E8 and CE5-CE8 composite circuit protection devices, the surge immunity test of each test sample is similar to the above, the difference is that the applied voltage is greater than the varistor voltage of MOV-2 ​​(including 400V and 500V) and the applied current is the overcurrent of PPTC-2 (i.e. 0.5A or 10A). The results are shown in Table 5.

[0097] Table 5

[0098]

[0099] The results in Table 5 show that the test samples of CE5 and CE6 containing only MOV-2 ​​burned within 20s under an overcurrent of 0.5A and an overvoltage greater than the varistor voltage of MOV-2, or burned within 1.5s under an overcurrent and overvoltage of 10A, and the damage was irreparable. The test samples of CE7 and CE8 containing only PPTC-2 burned under overcurrents of 0.5A and 10A. On the contrary, all the test samples of E5-E8 containing a combination of PPTC-2 and MOV-2 ​​(where the rated voltage of PPTC-2 is approximately 69% of the varistor voltage of MOV-2) passed the surge immunity test without burning. In addition, compared with E5, the test samples of E6-E8 with perforations formed on PPTC-2 and / or MOV-2 ​​improve heat transfer, which can further shorten the time for PPTC-2 to trip and prevent overcurrent from flowing through MOV-2, thereby protecting its MOV-2 ​​from burning. In other words, in the test samples E5-E8, PPTC-2 was tripped before MOV-2 ​​was burned out under the overcurrent and the voltage greater than the varistor voltage of MOV-2.

[0100] For E9-E12 and CE9-CE12 composite circuit protection devices, the surge immunity test of each test sample is similar to the above, the difference is that the applied voltage is greater than the varistor voltage of MOV-3 (including 600V and 700V). The results are shown in Table 6.

[0101] Table 6

[0102]

[0103]

[0104] The results in Table 6 show that the test samples of CE9 and CE10 containing only MOV-3 burned within 18 seconds under an overcurrent of 0.5A and an overvoltage greater than the varistor voltage of MOV-3, or burned within 1 second under an overcurrent and overvoltage of 10A, and the damage was irreparable. The test samples of CE11 and CE12 containing only PPTC-2 burned under overcurrents of 0.5A and 10A. On the contrary, all the test samples of E9-E12 containing a combination of PPTC-2 and MOV-3 (where the rated voltage of PPTC-2 is approximately 49% of the varistor voltage of MOV-3) passed the surge immunity test without burning. In addition, compared with E9, the test samples of E10-E12 with perforations formed in PPTC-2 and / or MOV-3 improve heat transfer, which can further shorten the time for PPTC-2 to trip and prevent overcurrent from flowing through MOV-3, thereby protecting its MOV-3 from burning. In other words, in the test samples E9-E12, PPTC-2 was tripped before MOV-3 was burned out under the overcurrent and voltage greater than the varistor voltage of MOV-3.

[0105] In summary, by including a PTC element having a desired rated voltage (e.g., 40% to 200% of the varistor's varistor voltage measured at 1 mA), in the presence of the overcurrent and the overvoltage, the PTC element quickly trips to a high resistance state to protect the varistor from burning due to the overcurrent. The composite circuit protection device of the present invention can thus be repeatedly used, demonstrating its excellent tolerance and reliability, and thus can truly achieve the purpose of the present invention.

[0106] The above descriptions are merely embodiments of the present invention and should not be used to limit the scope of the present invention. That is, any simple equivalent changes and modifications made according to the claims and description of the present invention still fall within the scope of the present invention.

Claims

1. A composite circuit protection device, characterized in that It contains: PTC components, including: A PTC layer having two opposite surfaces, and A first electrode layer and a second electrode layer are respectively disposed on two opposite surfaces of the PTC layer; A varistor connected to the second electrode layer; A first conductive lead connected to the first electrode layer; and A second conductive lead is connected to the varistor, The PTC element has a rated voltage between 45% and 70% of the varistor voltage measured at 1 mA, and the PTC element is tripped before the varistor burns out when it is under an overcurrent and a voltage of 700V.

2. The composite circuit protection device according to claim 1, characterized in that: The PTC element trips within 1 μs to 100s under an overcurrent greater than 0.1A and a voltage of 700V.

3. The composite circuit protection device according to claim 1, characterized in that: The PTC element trips within 1 ms to 10 s when exposed to an overcurrent greater than 0.5 A and a voltage of 700 V.

4. The composite circuit protection device according to claim 1, characterized in that: The PTC element trips within 1ms to 1s when exposed to an overcurrent greater than 10A and a voltage of 700V.

5. The composite circuit protection device according to claim 1, characterized in that: The PTC element has a first hole formed in the PTC layer.

6. The composite circuit protection device according to claim 5, characterized in that: The PTC layer of the PTC element has a periphery defining a boundary of the PTC layer and interconnecting two opposite surfaces of the PTC layer, and the first hole is spaced apart from the periphery of the PTC layer.

7. The composite circuit protection device according to claim 5, characterized in that: The first hole penetrates at least one of the two opposite surfaces of the PTC layer.

8. The composite circuit protection device according to claim 7, characterized in that: The first hole also penetrates at least one of the first electrode layer and the second electrode layer.

9. The composite circuit protection device according to claim 1, characterized in that: The varistor is formed with a second hole.

10. The composite circuit protection device according to claim 1, characterized in that: The varistor includes: a varistor layer having two opposing surfaces; a third electrode layer, disposed on one of two opposite surfaces of the varistor layer and connected to the second electrode layer of the PTC element; and a fourth electrode layer disposed on the other of the two opposite surfaces of the varistor layer, The second conductive lead is connected to one of the third electrode layer and the fourth electrode layer of the varistor.

11. The composite circuit protection device according to claim 10, characterized in that: The device also comprises a third conductive lead. The second conductive lead is connected to the fourth electrode layer. The third conductive lead is connected to and arranged between the second electrode layer and the third electrode layer.

12. The composite circuit protection device according to claim 10, characterized in that: The varistor has a second hole formed in the varistor layer.

13. The composite circuit protection device according to claim 12, characterized in that: The varistor layer of the varistor has a periphery defining a boundary of the varistor layer and interconnecting two opposite surfaces of the varistor layer, and the second hole is spaced apart from the periphery of the varistor layer.

14. The composite circuit protection device according to claim 12, characterized in that: The second hole penetrates at least one of the two opposite surfaces of the varistor layer.

15. The composite circuit protection device according to claim 14, characterized in that: The second hole also penetrates at least one of the third electrode layer and the fourth electrode layer.

16. The composite circuit protection device according to claim 1, characterized in that: The PTC element is a polymer PTC element, and the PTC layer is a PTC polymer layer.

17. The composite circuit protection device according to claim 1, characterized in that: The invention also comprises a packaging material, wherein the packaging material packages the PTC element, the varistor, a part of the first conductive lead and a part of the second conductive lead.

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