Data processing device and data processing system

Abstract

The present invention relates to a data processing device and a data processing system. The data processing device includes: a data selector circuit that divides a plurality of data into divided data according to the classification of the data; a plurality of compression circuits that respectively compress the divided data into compressed data with different formats in parallel according to each of the plurality of data; and a data transmission circuit that transmits the compressed data to a terminal. Wherein, when a data control signal is received from a circuit that has transmitted a set of a plurality of data, the data selector circuit divides the set of a plurality of data; wherein the data control signal is received separately from the plurality of data, and the data control signal includes information specifying the structure of each of the plurality of data in the set of a plurality of data; and wherein the data selector circuit divides the set of a plurality of data based on the data control signal.

Description

[0001] This application is a divisional application of an application with national application number 201580001866.7 (international application number PCT / JP2015 / 001374, international filing date March 12, 2015, invention title "Data processing device, data processing system, and method"). Technical Field

[0002] The present invention relates to a data processing device, a data processing system, and a method, and for example, relates to a data processing device, a data processing system, and a method for compressing and transmitting data. Background Art

[0003] In order to increase data transmission efficiency when acquiring data and transmitting the acquired data to a terminal, a technique of using compressed data to reduce the amount of data and transmitting the compressed data is used. For example, image data is acquired from a device such as a camera, and the image data is compressed and transmitted to a terminal. An application example of this technique is to display an image captured by an in-vehicle camera such as a rear monitor or a top view monitor of a vehicle such as a car on a display or the like. In this technique, it is necessary to reduce the time lag between the timing when the camera captures an image and the timing when the image is displayed on the display (to reduce the time delay). In this case, by compressing and transmitting the image data from the camera, the transmission speed from the camera to the display can be increased.

[0004] Regarding the above technique, Patent Document 1 discloses an image transmission device that can simultaneously transmit image data to a network and store the image data in an HDD through an encoding circuit and a compression device in a single system. Since the technique disclosed in Patent Document 1 classifies the compressed data in the order of compression, stores it in a compressed data storage device, and then reads the compressed data from the compressed data storage device in response to a request from a terminal, each compressed data can be transmitted to each terminal.

[0005] Citation List

[0006] Patent Documents

[0007] PTL 1: Japanese Unexamined Patent Publication No. 2003 - 299076 Summary of the Invention

[0008] Technical Problem

[0009] Recently, it has become possible to transmit various types of data, such as image data and other data (e.g., distance data), from a device such as a camera. Therefore, there is a need to transmit various types of data to a terminal with low latency.

[0010] However, according to the technology disclosed in Patent Document 1, since there is only one path for compression, only one data can be compressed at a time. Therefore, in the technology disclosed in Patent Document 1, when transmitting multiple types of data, the delay may be deteriorated.

[0011] Other problems and novel features of the present invention will become apparent from the description of the specification and the drawings.

[0012] Solution to the problem

[0013] According to one embodiment, a data processing device includes: a data selector circuit that divides a data group including multiple types of data into multiple types of data; a plurality of compression circuits that compress the multiple types of data in parallel with each other according to each of the multiple types of data; and a data transmission circuit that transmits the compressed data of the multiple types to a terminal.

[0014] Advantageous effects of the present invention

[0015] According to the above embodiment, it is possible to transmit multiple types of data with low delay. Brief description of the drawings

[0016] Figure 1 is a view showing an overview of a data processing device according to an embodiment;

[0017] Figure 2 is a view showing a data processing system according to a first embodiment;

[0018] Figure 3 is a flowchart showing a data processing method in the data processing system according to the first embodiment;

[0019] Figure 4 is a view showing a data processing system according to a first alternative example of the first embodiment;

[0020] Figure 5 is a view showing a data processing system according to a second alternative example of the first embodiment;

[0021] Figure 6 is a view showing a data processing system according to a third alternative example of the first embodiment;

[0022] Figure 7 is a view showing a data processing system according to a second embodiment;

[0023] Figure 8 is a flowchart showing a data processing method in the data processing device according to the second embodiment;

[0024] Figure 9is a view showing a data processing system according to a first alternative example of the second embodiment;

[0025] Figure 10 is a view showing a data processing system according to the third embodiment; and

[0026] Figure 11 is a view showing an example in which the data processing system according to the third embodiment is installed in an automobile. Detailed Description

[0027] Hereinafter, embodiments of the present invention will be described. The following description and drawings are appropriately shortened and simplified to make the description clear. In the drawings, the same reference numerals refer to the same structural elements, and redundant descriptions thereof are omitted.

[0028] In the following embodiments, for convenience, the description is divided into multiple parts or embodiments when necessary. However, unless otherwise explicitly specified, these parts or embodiments are by no means unrelated to each other, but are in a relationship such as a modification, detailed or supplementary description of one representing part or all of the other. Additionally, in the following embodiments, when referring to the number of elements, etc. (including digital-to-analog, numerical values, quantities, ranges, etc.), unless otherwise explicitly specified or in a case where the quantity is obviously limited to a specific number in principle, the number is not limited to a specific number, but can be greater than or less than the specific number.

[0029] Needless to say, in the following embodiments, its constituent elements (including operation steps) are not necessarily essential, except in cases where it is otherwise explicitly specified or where they are obviously considered essential in principle. Similarly, in the following embodiments, when referring to the shape, relative position, etc. of constituent elements, etc., it includes those shapes, etc. that are substantially similar or approximate to the shape, etc., except in cases where it is otherwise explicitly specified or where it is obviously considered not to be the case in principle. This also applies to the above-mentioned numbers, etc. (including numbers, numerical values, quantities, ranges, etc.).

[0030] Furthermore, elements shown as functional blocks for performing various processes in the drawings can be configured as hardware by a CPU (Central Processing Unit), a memory, or other circuits, or can be implemented as software by a program loaded in the memory, etc. Therefore, it will be obvious to those skilled in the art that these functional block diagrams can be implemented in various forms such as only hardware, only software, or a combination of these, and are not limited to any one.

[0031] In addition, any type of non-transitory computer-readable medium can be used to store the above program in a computer and provide the above program to the computer. The non-transitory computer-readable medium includes any type of tangible storage medium. Examples of the non-transitory computer-readable medium include magnetic storage media (such as floppy disks, magnetic tapes, hard disk drives, etc.), magneto-optical storage media (e.g., magneto-optical disks), CD-ROM (read-only memory), CD-R, CD-R / W, and semiconductor memories (such as mask ROM, PROM (programmable ROM), EPROM (erasable PROM), flash ROM, RAM (random access memory), etc.). Any type of transitory computer-readable medium can be used to provide the program to the computer. Examples of the transitory computer-readable medium include electrical signals, optical signals, and electromagnetic waves. The transitory computer-readable medium can provide the program to the computer via a wired communication line such as a wire or an optical fiber or a wireless communication line.

[0032] (Overview of the Embodiment)

[0033] Before describing the embodiment, an overview of the embodiment is provided below. Figure 1 is a view showing an overview of the data processing device 1 according to the embodiment. As Figure 1 shown, the data processing device 1 includes a data selector circuit 2, a first compression circuit 4a, a second compression circuit 4b, and a data transmission circuit 6. Note that although two compression circuits (the first compression circuit 4a and the second compression circuit 4b) are shown in Figure 1 , the number of compression circuits may be three or more. In addition, although the first compression circuit 4a performs irreversible compression and the second compression circuit 4b performs reversible compression, this is not limiting. The first compression circuit 4a may perform reversible compression, and the second compression circuit 4b may perform irreversible compression. In addition, both the first compression circuit 4a and the second compression circuit 4b may perform irreversible compression, or both may perform reversible compression.

[0034] The data selector circuit 2 divides a data group including various types of data into various types of data b1 and c1. The first compression circuit 4a and the second compression circuit 4b compress the various types of data b1 and c1 in parallel with each other according to each type of the various types of data b1 and c1. Specifically, the first compression circuit 4a compresses the data b1 and obtains compressed data b2. The second compression circuit 4b compresses the data c1 and obtains compressed data c2.

[0035] The data transmission circuit 6 transmits the various types of compressed data to the terminal. Specifically, the data transmission circuit 6 transmits the compressed data b2 and the compressed data c2 to the terminal. The data transmission circuit 6 may transmit the compressed data b2 and the compressed data c2 at the same timing or at different timings.

[0036] Since the data processing device 1 according to this embodiment divides a data group including various types of data according to the type of data and compresses the divided data in parallel with each other, the delay when sending it to the terminal is improved. Therefore, the data processing device 1 according to this embodiment can transmit various types of data with low latency.

[0037] For example, in a driving support system such as a rear monitor or a top view monitor of a vehicle such as a car, it is necessary to transmit data from a camera to a display with low latency (the difference between the actual movement and the movement when displaying the camera image on the display or the like is small). In addition, there is an increasing need, such as in an automotive braking system or a cruise control system, to acquire not only surrounding images but also data on the distance to an object or a person near the vehicle, for example. As described above, since the data processing device 1 according to this embodiment can transmit various types of data with low latency, it can be effectively applied to the above systems.

[0038] (First Embodiment)

[0039] Figure 2 FIG. is a view showing a data processing system 10 according to the first embodiment. The data processing system 10 includes a camera 100, a data processing device 110, and receiving terminals 120 (receiving terminals 120a, 120b, and 120c). The data processing device 110 is connected to be able to communicate with the receiving terminal 120 through a communication line 50 such as a bus, for example. The data processing device 110 includes a data selector circuit 111, a reversible compression circuit 112, an irreversible compression circuit 113, a memory 114, and a data transmission circuit 115.

[0040] The camera 100 can output various different types of data at the same timing. Specifically, the camera 100 outputs a data group including various different types of data. In this embodiment, the camera 100 outputs camera data A1 as a data group to the data processing device 110. The camera data A1 is, for example, image data such as YUV color image data, IR (infrared) image data, distance data, etc. Although in this example, the camera data A1 is sent through one data bus, the number of data buses is not limited. The camera 100 also outputs a data control signal A2 related to the camera data A1 to the data processing device 110. The data control signal A2 will be described later.

[0041] The data selector circuit 111 divides the data output from the camera 100 that transmits data based on the data control signal A2. Specifically, the data selector circuit 111 analyzes the camera data A1 through a predetermined setting. And it divides it into data B1 effective for reversible compression and data C1 effective for irreversible compression. The data effective for reversible compression is the data that does not need to change before and after compression. On the other hand, the data effective for irreversible compression is the data that allows changes before and after compression, and the compressibility of this data can be improved through irreversible compression.

[0042] The reversible compression circuit 112 and the irreversible compression circuit 113 are circuits for performing reversible compression and irreversible compression respectively on each of the divided data. The reversible compression circuit 112 and the irreversible compression circuit 113 perform compression on various types of divided data in parallel with each other. Note that although in this embodiment, the data processing device 110 includes the reversible compression circuit 112 and the irreversible compression circuit 113, it is not limited thereto. Both compression circuits can perform reversible compression, or both of them can perform irreversible compression.

[0043] The reversible compression circuit 112 compresses the data B1 in a reversible compression format (e.g., Zip, gzip, etc.). Then, the reversible compression circuit 112 stores the obtained compressed data B2 in the memory 114. At this time, the reversible compression circuit 112 outputs a data transmission request signal R1 reporting the completion of compression to the data transmission circuit 115. The data transmission request signal R1 contains information specifying the area where the compressed data B2 is stored in the memory 114.

[0044] The irreversible compression circuit 113 compresses the data C1 in an irreversible compression format (e.g., JPEG, MPEG-2, etc.). Then, the irreversible compression circuit 113 stores the obtained compressed data C2 in the memory 114. At this time, the irreversible compression circuit 113 outputs a data transmission request signal R2 reporting the completion of compression to the data transmission circuit 115. The data transmission request signal R2 contains information specifying the area where the compressed data C2 is stored in the memory 114.

[0045] The data transmission circuit 115 receives the data transmission request signal R1 from the reversible compression circuit 112, and then reads the compressed data B2 from the memory 114. Specifically, the data transmission circuit 115 reads the compressed data B2 from the area in the memory 114 specified by the data transmission request signal R1. Then, the data transmission circuit 115 transmits the read compressed data B2 to the receiving terminal 120 via the communication line 50. Similarly, the data transmission circuit 115 receives the data transmission request signal R2 from the irreversible compression circuit 113, and then reads the compressed data C2 from the memory 114. Specifically, the data transmission circuit 115 reads the compressed data C2 from the area in the memory 114 specified by the data transmission request signal R2. Then, the data transmission circuit 115 transmits the read compressed data C2 to the receiving terminal 120 via the communication line 50.

[0046] The data transmission circuit 115 can transmit the compressed data B2 and the compressed data C2 separately from each other. Specifically, for example, the data transmission circuit 115 can transmit the compressed data B2 when it receives the data transmission request signal R1, and then transmit the compressed data C2 when it receives the data transmission request signal R2 thereafter. In this way, the data transmission circuit 115 can sequentially transmit the compressed data to the receiving terminal 120. In addition, the data transmission circuit 115 can transmit multiple frames simultaneously. Note that the data transmission circuit 115 can transmit the compressed data B2 and the compressed data C2 simultaneously. Specifically, the data transmission circuit 115 can store the compressed data B2 and the compressed data C2 in one or more communication frames and transmit these communication frames simultaneously. In this case, the data transmission circuit 115 can include a buffer for storing the data that has been compressed previously.

[0047] The receiving terminal 120 is, for example, a control chip or a computer (PC) connected to a display. The receiving terminal 120 receives the compressed data B2 and the compressed data C2 transmitted from the data processing device 110. Then, the receiving terminal 120 decompresses the compressed data B2 and C2 into the original data B1 and C1, and performs necessary processing such as displaying image data on the display.

[0048] Hereinafter, the processing flow of the data processing device 110 is described.

[0049] Figure 3 is a flowchart showing the data processing method in the data processing system 110 according to the first embodiment. First, the data selector circuit 111 divides the camera data A1 including various different types of data by each data type based on the data control signal A2 (S100).

[0050] Next, when the divided data is data that needs to be reversibly compressed (yes in S101), the data processing device 110 performs reversible compression on the data (S102a). On the other hand, when the divided data is data that does not need to be reversibly compressed (no in S101), the data processing device 110 performs irreversible compression on the data (S102b). Specifically, the data selector circuit 111 divides the camera data A1 into data B1 that is effective for reversible compression and data C1 that is effective for irreversible compression. Then, the data selector circuit 111 outputs the data B1 to the reversible compression circuit 112 and outputs the data C1 to the irreversible compression circuit 113. The reversible compression circuit 112 performs reversible compression on the data B1. In addition, the irreversible compression circuit 113 performs irreversible compression on the data C1.

[0051] The data control signal A2 output from the camera 100 includes a valid signal that indicates, for example, that the camera data A1 output at the same timing as the output of the data control signal A2 is valid data. Therefore, when the data selector circuit 111 receives the data control signal A2 including the valid signal, it performs processing on the camera data A1 output at the same timing as the output of the data control signal A2. The data selector circuit 111 can thus perform processing at an appropriate timing. In other words, when the data selector circuit 111 receives invalid data, such as data output when the camera 100 is in the idle mode, it can prevent processing from being performed on the data.

[0052] In addition, the camera data A1 includes, for example, the above-mentioned YUV color image data, distance data, etc. The YUV color image data is image data indicating a color image to be viewed by the user in the receiving terminal 120. When a person views an image, even if the image data changes slightly before and after compression, the person can hardly recognize the change. Therefore, since the data change caused by compression has little effect on the YUV color image data, it is effective to perform irreversible compression to increase compressibility. Therefore, the data selector circuit 111 classifies the YUV color image data as data C1 that is effective for irreversible compression.

[0053] On the other hand, the distance data (numerical data indicating the distance from the camera 100 to an object) is used to cause a calculation circuit such as a CPU to perform calculations in the receiving terminal 120. Therefore, for the distance data, it is necessary for the data to remain unchanged before and after compression. Therefore, it is effective to perform reversible compression on the distance data. Therefore, the data selector circuit 111 classifies the distance data as data B1 that is effective for reversible compression.

[0054] Note that the IR image data is used for viewing by a user in the receiving terminal 120 in some cases, and for being calculated in the receiving terminal 120 in other cases. Therefore, the data selector circuit 111 can classify the IR image data into data B1 or data C1 according to the use in the data selector circuit 111.

[0055] Note that the data control signal A2 can include information specifying the data structure of the camera data A1. This applies to the case where the camera 100 can output the data control signal A2 including such information. Specifically, when, for example, the camera data A1 is 24 bits, the high 8 bits of the camera data A1 are data B1 (e.g., distance data) and the low 16 bits of the camera data A1 are data C1 (e.g., image data), the data control signal A2 can include information indicating this. Then, the data selector circuit 111 divides the camera data A1 into data B1 effective for reversible compression and data C1 effective for irreversible compression by using the information specifying the data structure. In this configuration, the data selector circuit 111 can easily divide the camera data A1.

[0056] In addition, the information specifying the data structure of the camera data A1 can be preset to the data selector circuit 111. Specifically, when the specifications of the camera 100 are known, the information specifying the structure of the camera data A1 can be set to the data selector circuit 111 according to the specifications. In this configuration, it is not necessary to specify the data structure in the data control signal A2. On the other hand, by specifying the data structure in the data control signal A2, it is not necessary to preset this information to the data selector circuit 111.

[0057] The data B1 and data C1 classified in the data selector circuit 111 are respectively input to the reversible compression circuit 112 and the irreversible compression circuit 113. The reversible compression circuit 112 and the irreversible compression circuit 113 that respectively receive the data B1 and data C1 perform data compression according to a predetermined setting. Note that the timings at which the data B1 and data C1 are respectively input to the reversible compression circuit 112 and the irreversible compression circuit 113 can be the same. Then, the reversible compression circuit 112 and the irreversible compression circuit 113 perform data compression in parallel. Specifically, the processing steps S102a and S102b are performed in parallel with each other.

[0058] The reversible compression circuit 112 continues the compression process until the compression is completed (No in S103a). When the compression is completed (Yes in S103a), the reversible compression circuit 112 outputs the obtained compressed data B2 to the memory 114, and writes the compressed data B2 into a specific area in the memory 114. At this time, the reversible compression circuit 112 outputs a data transmission request signal R1 to the data transmission circuit 115, and thereby requests the data transmission circuit 115 to transmit the data (S104a).

[0059] Similarly, the irreversible compression circuit 113 continues the compression process until the compression is completed (No in S103b). When the compression is completed (Yes in S103b), the irreversible compression circuit 113 outputs the obtained compressed data C2 to the memory 114 and writes the compressed data C2 into a specific area in the memory 114. At this time, the irreversible compression circuit 113 outputs a data transmission request signal R1 to the data transmission circuit 115 and thus requests the data transmission circuit 115 to transmit the data (S104b). Note that the processing steps S102a, S103a, and S104a are executed in parallel with the processing steps S102b, S103b, and S104b.

[0060] The data transmission circuit 115 starts the transmission of the compressed data input from the memory 114 (S105). Specifically, when the data transmission circuit 115 receives the data transmission request signal R1, it extracts the compressed data B2 from the memory 114 and transmits it to the receiving terminal 120. On the other hand, when the data transmission circuit 115 receives the data transmission request signal R2, it extracts the compressed data C2 from the memory 114 and transmits it to the receiving terminal 120. Note that the data transmission circuit 115 can transmit a plurality of data frames to a plurality of receiving terminals 120 simultaneously.

[0061] The time taken to output both the compressed data B2 and C2 from the memory 114 to the data transmission circuit 115 is generally shorter than the time required for one compression. Therefore, the data transmission circuit 115 can receive the compressed data B2 and C2 before the next compressed data is output from the reversible compression circuit 112 and the irreversible compression circuit 113. Thereby, data loss of the compressed data can be prevented. Note that even if the time taken to output the two compressed data B2 and C2 from the memory 114 to the data transmission circuit 115 is equal to or longer than the time required for one compression, since the memory 114 temporarily stores the compressed data, data loss can be prevented regardless of the timing for transmitting the compressed data. In addition, since the memory 114 temporarily stores the compressed data, the data transmission circuit 115 can transmit the compressed data B2 and the compressed data C2 to the receiving terminal 120 at an arbitrary timing. For example, the data transmission circuit 115 can transmit the compressed data B2 and the compressed data C2 to the receiving terminal 120 simultaneously. Alternatively, the data transmission circuit 115 can transmit the compressed data B2 and the compressed data C2 to the receiving terminal 120 at the timing when the receiving terminal 120 needs the compressed data B2 and the compressed data C2.

[0062] In the above patent document, when processing multiple types of data, the next data cannot be processed until the processing of one data ends and the selector is switched. Additionally, since another data cannot be compressed during the time period when one data is being compressed, it takes a long time to transmit all the data.

[0063] On the other hand, the data processing device 110 according to this embodiment includes a data selector circuit 111 that divides multiple types of data, and includes two compression circuits arranged in parallel with each other. In other words, there are multiple compression paths in this embodiment. Therefore, each of the multiple types of divided data can be compressed in parallel with each other. Thus, compared with the case of sequentially compressing multiple data, the delay when transmitting multiple types of data can be reduced.

[0064] Additionally, the data processing device 110 according to this embodiment includes two compression circuits that perform compression in different compression formats. Specifically, in this embodiment, the first compression circuit (in this embodiment, the irreversible compression circuit 113) compresses the first type of data (in this embodiment, image data) in the first format (in this embodiment, the irreversible compression format). On the other hand, the second compression circuit (in this embodiment, the reversible compression circuit 112) compresses the second type of data (in this embodiment, distance data) in the second format (in this embodiment, the reversible compression format), and the second format is different from the first format. In this configuration, even if multiple different types of data are input, these data can be compressed according to the type of data by a compression method suitable for the use of each data.

[0065] Furthermore, the data processing device 110 according to this embodiment includes a reversible compression circuit 112 and an irreversible compression circuit 113 arranged in parallel with each other. In this configuration, compression in the irreversible compression format and compression in the reversible compression format can be performed in parallel with each other.

[0066] In addition, since only one compression circuit is arranged in the above patent document, any one of irreversible compression and reversible compression formats can be selected even when multiple types of data are input. On the other hand, the data processing device 110 according to this embodiment can separately process data (first type of data) such as image data to be viewed by the user in the receiving terminal 120 and data (second type of data) such as distance data to be calculated in the receiving terminal 120. As described above, for image data such as YUV color image data, even if the image data changes slightly before and after compression, the change is hardly recognizable to humans. On the other hand, for distance data, since it is used for operations such as calculations in the receiving terminal 120, it is necessary for the data to remain unchanged before and after compression. Therefore, the data processing device 110 according to this embodiment can perform irreversible compression on the image data to increase compressibility, and perform reversible compression on the distance data so as not to cause changes in the data.

[0067] In addition, in the above embodiment, the reversible compression circuit 112 and the irreversible compression circuit 113 respectively output data transmission request signals R1 and R2 to the data transmission circuit 115, and the data transmission circuit 115 transmits the compressed data based on the data transmission request signals R1 and R2. In other words, without using CPU processing, a series of data processing operations from the compression of the data A1 input from the camera 100 to the transmission of the compressed data to the receiving terminal 120 are performed. In this configuration, the compression of data and the transmission of data can be performed by using hardware without any software processing (such as processing by the CPU) that can perform high-speed processing.

[0068] In the case of performing software processing by the CPU, it is necessary to perform interrupt processing on the CPU when compression is completed. At this time, the CPU needs to perform interrupt processing and bus access processing, and access the data transmission circuit. On the other hand, in the configuration of this embodiment, the data transmission request signals R1 and R2 (completion flags) are directly input from the reversible compression circuit 112 and the irreversible compression circuit 113 to the data transmission circuit 115. This eliminates the need for interrupt processing and bus access processing in the CPU, and thus high-speed processing can be achieved.

[0069] (Alternative Example of the First Embodiment)

[0070] Figure 4 is a view showing a data processing system 10 according to a first alternative example of the first embodiment. Figure 4 shows a case where three or more types of data are input to the data processing device 110. Specifically, in Figure 4 it, the data processing system 10 includes two cameras 100a and 100b. In addition, in Figure 4In addition to the reversible compression circuit 112 and the irreversible compression circuit 113, the data processing device 110 includes a reversible compression circuit 134.

[0071] As Figure 2 In the camera 100 as in Figure 2 , the camera 100a outputs camera data A1 including YUV color image data and distance data, and a data control signal A2 related to the camera data A1. On the other hand, the camera 100b outputs camera data A3 including, for example, IR image data, and a data control signal A4 related to the camera data A3. The data control signal A4 has the same structure as the data control signal A2.

[0072] As described above, the data selector circuit 111 divides the camera data A1 into YUV color image data and distance data based on the data control signal A2. Then, the data selector circuit 111 outputs the distance data as data B1 to the reversible compression circuit 112, and outputs the YUV color image data as data C1 to the irreversible compression circuit 113. In addition, the data selector circuit 111 outputs the IR image data included in the camera data A3 as data D1 to the reversible compression circuit 134 based on the data control signal A4. Therefore, in this example, the IR image data is data for which reversible compression is effective, that is, this data is data to be calculated in the receiving terminal 120.

[0073] The processing operations of the reversible compression circuit 112 and the irreversible compression circuit 113 are the same as those described with reference to Figure 2 and are not redundantly described. The reversible compression circuit 134 performs reversible compression on the data D1 in the same manner as the reversible compression circuit 112, and stores the resulting compressed data D2 in the memory 114. In addition, the reversible compression circuit 134 outputs a data transmission request signal R3 reporting the completion of compression to the data transmission circuit 115. The data transmission circuit 115 thereby transmits the compressed data D2 to the receiving terminal 120.

[0074] As described above, this embodiment is also applicable to the case where there are three types of data. In addition, in the case where there are four or more types of data, compression circuits can be added in parallel according to the number of types. Note that by arranging the memory in the data selector circuit 111, compression can be performed on each of multiple types of data without increasing the number of compression circuits. Note that in the Figure 4 example of Figure 4 , when the IR image data is data for which irreversible compression is effective, that is, this data is data to be viewed by the user in the receiving terminal 120, an irreversible compression circuit can be arranged to replace the reversible compression circuit 134. In addition, although in Figure 4There are multiple cases where you are missed by 100 shown, but camera data A1 including three or more types of data can be output from one camera 100.

[0075] Figure 5 It is a view showing the data processing system 10 according to the second alternative example of the first embodiment. In Figure 5 In the example, a plurality of data transmission circuits are arranged respectively for the compressed data B2 from the reversible compression circuit 112 and the compressed data C2 from the reversible compression circuit 113. Specifically, in Figure 5 In the example, the data processing system 10 includes a data transmission circuit 141 for transmitting the compressed data B2 and a data transmission circuit 142 for transmitting the compressed data C2. In Figure 5 In the example, the data processing system 10 does not need to include the memory 114.

[0076] The reversible compression circuit 112 outputs the compressed data B2 to the data transmission circuit 141. At this time, the reversible compression circuit 112 outputs a data transmission request signal R1 reporting the completion of compression to the data transmission circuit 141. The data transmission circuit 141 receives the data transmission request signal R1, and thereby transmits the compressed data B2 output from the reversible compression circuit 112 to the receiving terminal 120.

[0077] The irreversible compression circuit 113 outputs the compressed data C2 to the data transmission circuit 142. At this time, the irreversible compression circuit 113 outputs a data transmission request signal R2 reporting the completion of compression to the data transmission circuit 142. The data transmission circuit 142 receives the data transmission request signal R2, and thus transmits the compressed data C2 output from the irreversible compression circuit 113 to the receiving terminal 120.

[0078] In Figure 5 In the example, the data transmission circuit 141 for transmitting the compressed data B2 and the data transmission circuit 142 for transmitting the compressed data C2 are arranged separately. Therefore, even in the case where there is no memory for temporarily storing the compressed data, the data processing device 110 can separately transmit the compressed data B2 from the reversible compression circuit 112 and the compressed data C2 from the irreversible compression circuit 113 without data loss.

[0079] Figure 6 It is a view showing the data processing system 10 according to the third alternative example of the first embodiment. In Figure 6 In the example, channels Ch1 and Ch2 for separately transmitting the compressed data B2 from the reversible compression circuit 112 and the compressed data C2 from the irreversible compression circuit 113 are arranged separately. Specifically, in Figure 6In the example, the data processing device 110 includes a data transmission circuit 150 compatible with channels Ch1 and Ch2. In Figure 6 the example, the data processing device 110 does not need to include the memory 114.

[0080] The reversible compression circuit 112 outputs the compressed data B2 to the data transmission circuit 150. At this time, the reversible compression circuit 112 outputs a data transmission request signal R1 reporting the completion of compression to the data transmission circuit 150. The data transmission circuit 150 receives the data transmission request signal R1, and thereby transmits the compressed data B2 to the receiving terminal 120 through channel Ch1.

[0081] The irreversible compression circuit 113 outputs the compressed data C2 to the data transmission circuit 150. At this time, the irreversible compression circuit 113 outputs a data transmission request signal R2 reporting the completion of compression to the data transmission circuit 150. The data transmission circuit 150 receives the data transmission request signal R2, and thereby transmits the compressed data C2 to the receiving terminal 120 through channel Ch2.

[0082] In Figure 6 the example, channels Ch1 and Ch2 for separately transmitting the compressed data B2 and the compressed data C2 are arranged separately. Therefore, even in the case where there is no memory for temporarily storing the compressed data, the data processing device 110 can separately transmit the compressed data B2 from the reversible compression circuit 112 and the compressed data C2 from the irreversible compression circuit 113 without data loss.

[0083] (Second Embodiment)

[0084] Figure 7 is a view showing a data processing system 20 according to the second embodiment. In the second embodiment, the data processing system communicates with the receiving terminal in a format compatible with Ethernet (registered trademark).

[0085] The data processing system 20 includes a camera 100, a data processing device 210, and receiving terminals 120 (receiving terminals 120a, 120b, and 120c). The data processing device 210 is connected so as to be able to communicate with the receiving terminal 120 through a communication line 52 compatible with, for example, Ethernet. The data processing device 210 includes a data selector circuit 111, a reversible compression circuit 112, an irreversible compression circuit 113, an Ethernet header addition circuit 212, an Ethernet header addition circuit 213, a memory 114, and an Ethernet communication circuit 215. Therefore, in the second embodiment, the Ethernet header addition circuit 212 and the Ethernet header addition circuit 213 are added, and the Ethernet communication circuit 215 replaces the data transmission circuit 115. Other elements are the same as those in the first embodiment and will not be redundantly described.

[0086] Figure 8 is a flowchart showing a data processing method in the data processing apparatus 210 according to the second embodiment. In Figure 8 it, descriptions of the same processing steps (S100 to S103) as in the first embodiment are omitted. Hereinafter, with reference to Figure 8 the operations of each circuit of the data processing apparatus 210 are described.

[0087] The reversible compression circuit 112 performs compression and outputs the compressed data B2 to the Ethernet header addition circuit 212. The Ethernet header addition circuit 212 adds an Ethernet header related to the compressed data B2 to the compressed data B2 (S202a). Then, the Ethernet header addition circuit 212 writes the compressed data B3 with the added Ethernet header into a predetermined area in the memory 114. In the second embodiment, when the Ethernet header addition circuit 212 adds an Ethernet header, the Ethernet header addition circuit 212 outputs a data transmission request signal R1 to the Ethernet communication circuit 215. The Ethernet header addition circuit 212 thereby requests the Ethernet communication circuit 215 to transmit data (S204a).

[0088] The irreversible compression circuit 113 performs compression and outputs the compressed data C2 to the Ethernet header addition circuit 213. The Ethernet header addition circuit 213 adds an Ethernet header related to the compressed data C2 to the compressed data C2 (S202b). Then, the Ethernet header addition circuit 213 writes the compressed data C3 with the added Ethernet header into a predetermined area in the memory 114. In the second embodiment, when the Ethernet header addition circuit 213 adds an Ethernet header, the Ethernet header addition circuit 212 outputs a data transmission request signal R2 to the Ethernet communication circuit 215. The Ethernet header addition circuit 213 thereby requests the Ethernet communication circuit 215 to transmit data (S204b).

[0089] The Ethernet communication circuit 215 starts transmission of the compressed data input from the memory 114 (S205). Specifically, when the Ethernet communication circuit 215 receives the data transmission request signal R1, it extracts the compressed data B3 with a header from the memory 114. Then, the Ethernet communication circuit 215 transmits the compressed data B3 with a header to the receiving terminal 120 in an Ethernet-compatible format. On the other hand, when the Ethernet communication circuit 215 receives the data transmission request signal R2, it extracts the compressed data C3 with a header from the memory 114. Then, the Ethernet communication circuit 215 transmits the compressed data C3 with a header to the receiving terminal 120 in an Ethernet-compatible format.

[0090] In the second embodiment, the data processing device 210 can send the compressed data to the receiving terminal 120 in a format compatible with Ethernet. Thus, for a plurality of data processing devices 210 and a plurality of receiving terminals 120 (receiving terminals 120a, 120b, and 120c), a network configuration such as a bus type or a star type can be constructed. Additionally, compared with cables in analog format and LVDS (Low Voltage Differential Signaling) format cables, the cables used in Ethernet communication may have a high tolerance for noise. Therefore, the cables used in Ethernet communication may not require a shielding film. Thus, by sending the compressed data in a format compatible with Ethernet, the cables can be thinner, which makes wiring easier. This also allows the use of inexpensive cables. This is particularly effective when a digital camera is connected to a device inside a vehicle or the like.

[0091] Additionally, in the second embodiment, an Ethernet header is added to the compressed data. The Ethernet header contains information such as a timestamp defined by Ethernet (registered trademark), etc. By using this information, when the data processing device 210 receives a plurality of different camera data from a plurality of cameras 100, etc., a plurality of image data, etc. respectively included in the plurality of camera data can be synchronized. This is particularly effective in the case of a top view monitor technique that combines a plurality of image data obtained by using a plurality of cameras.

[0092] Note that in the second embodiment as well, the reversible compression circuit 112 and the irreversible compression circuit 113 are arranged in parallel. Thus, in the second embodiment as well, substantially the same beneficial effects as in the first embodiment are obtained.

[0093] (Alternative Example of the Second Embodiment)

[0094] Figure 9 is a view showing a data processing system 20 according to a first alternative example of the second embodiment. In Figure 9 compared with Figure 7 the positions of the replacement memory and the Ethernet header addition circuit are swapped.

[0095] Specifically, in the example of Figure 9 the data processing device 210 includes a memory 220 instead of the memory 114, and includes an Ethernet header addition circuit 222 instead of the Ethernet header addition circuits 212 and 213. In Figure 9 the reversible compression circuit 112 is in the same way as Figure 2In the same manner as in the example, the compressed data B2 is stored in the memory 220. At this time, the reversible compression circuit 112 outputs a data transmission request signal R1 to the Ethernet communication circuit 215. Further, after the compressed data B2 is stored in the memory 220, the Ethernet header addition circuit 222 adds an Ethernet header to the stored compressed data B2. Thus, the compressed data B3 with the Ethernet header added is stored in the memory 220.

[0096] Further, the irreversible compression circuit 113 stores the compressed data C2 in the memory 220 in the same manner as in the Figure 2 example. At this time, the irreversible compression circuit 113 outputs a data transmission request signal R2 to the Ethernet communication circuit 215. Further, after the compressed data C2 is stored in the memory 220, the Ethernet header addition circuit 222 adds an Ethernet header to the stored compressed data C2. Thus, the compressed data C3 with the Ethernet header added is stored in the memory 220.

[0097] When the Ethernet communication circuit 215 receives the data transmission request signal R1, it extracts the compressed data B3 with the header from the memory 220 in the same manner as in the Figure 7 example and sends it to the receiving terminal 120. On the other hand, when the Ethernet communication circuit 215 receives the data transmission request signal R2, it extracts the compressed data C3 with the header from the memory 220 in the same manner as in the Figure 7 example and sends it to the receiving terminal 120.

[0098] In the Figure 9 example, only one Ethernet header addition circuit is arranged. Therefore, compared with the Figure 7 one, the circuit scale is reduced by an amount corresponding to the size of the Ethernet header addition circuit.

[0099] (Third Embodiment)

[0100] Figure 10 is a view showing the data processing system 30 according to the third embodiment. The third embodiment is different from other embodiments in that more than one data processing device 110 according to the first embodiment is arranged. In the third embodiment, more than one data processing device 210 according to the second embodiment may be arranged. In the third embodiment, a network is constructed using a plurality of data processing devices according to the first or second embodiment.

[0101] The data processing system 30 includes camera data processing units 301, 302, 303, and 304, a relay device 300, and a receiving terminal 120. The camera data processing unit 301 includes a camera 100a and a data processing device 110a. Similarly, the camera data processing unit 302 includes a camera 100b and a data processing device 110b. The camera data processing unit 303 includes a camera 100c and a data processing device 110c. The camera data processing unit 304 includes a camera 100d and a data processing device 110d. The cameras 100a, 100b, 100c, and 100d have substantially the same functions as Figure 2 the camera 100 shown in. Similarly, the data processing devices 110a, 110b, 110c, and 110d have substantially the same configurations as Figure 2 the data processing device 110 shown in. Each of the data processing devices 110a, 110b, 110c, and 110d sends compressed data (compressed data B2 and C2) to the relay device 300.

[0102] The relay device 300 is, for example, a hub, a router, or a switch in Ethernet or the like. The relay device 300 has a function of relaying the compressed data output from the data processing devices 110a, 110b, 110c, and 110d to the receiving terminal 120. The relay device 300 can send the compressed data output from the data processing devices 110a, 110b, 110c, and 110d to the receiving terminal 120 as a bundle. At this time, the compressed data of the camera data simultaneously obtained by the cameras 100a, 100b, 100c, and 100d respectively can be synchronized by using the Ethernet header according to the second embodiment.

[0103] In the third embodiment, a network is constructed using multiple data processing devices. Therefore, various processes can be performed in the receiving terminal 120 by using the camera data acquired by the multiple cameras 100. Hereinafter, application examples of the third embodiment will be described.

[0104] Figure 11 is a view showing an example in which the data processing system 30 according to the third embodiment is installed on a vehicle 900. Although Figure 11 an example in which the system is used for an in-vehicle top view system is shown, it is not limited thereto.

[0105] The vehicle 900 includes camera data processing units 301, 302, 303, and 304 and a top view receiving terminal 310. The top view receiving terminal 310 has Figure 10Functions of the relay device 300 and the receiving terminal 120 shown in the figure. The camera 100a of the camera data processing unit 301 captures an image in front of the vehicle 900 and obtains image data related to the front. In addition, the camera 100a of the camera data processing unit 301 measures the distance to an object in front of the vehicle 900 and obtains distance data indicating the measured value. The data processing device 110a of the camera data processing unit 301 obtains camera data including the image data and the distance data and performs compression as described above. Then, the data processing device 110a sends the compressed data related to the front to the top view receiving terminal 310.

[0106] Similarly, the camera data processing unit 302 obtains and compresses the image data and the distance data related to the right side of the vehicle 900 and sends the compressed data related to the right side to the top view receiving terminal 310. The camera data processing unit 303 obtains and compresses the image data and the distance data related to the rear of the vehicle 900 and sends the compressed data related to the rear to the top view receiving terminal 310. The camera data processing unit 304 obtains and compresses the image data and the distance data related to the left side of the vehicle 900 and sends the compressed data related to the left side to the top view receiving terminal 310.

[0107] The top view receiving terminal 310 decompresses the compressed data related to the above four directions (front, rear, right, and left) and performs various processes. For example, the top view receiving terminal 310 combines the image data related to these four directions to generate an image related to the top view and displays it on the display.

[0108] In addition, when there is an object (obstacle) within a specific distance from the vehicle 900 (camera 100) in a specific direction (for example, the left side), the top view receiving terminal 310 performs a specific process to warn the user of this fact. For example, in this case, the top view receiving terminal 310 may output a warning or change the color of the image data related to the corresponding direction (for example, the left side). As described above, by constructing the system according to the third embodiment, various processes can be performed in the receiving terminal 120.

[0109] (Alternative example)

[0110] This embodiment is not limited to the above-described embodiments and can be varied in many ways within the scope of the present invention. For example, although the data processing device includes a memory in the above-described embodiments, it may include a data selection logic circuit instead of the memory. The data selection logic circuit is a circuit that receives compressed data sent from a plurality of circuits and sends it to the data transmission circuit. The time it takes for the data selection logic circuit to output data to the data transmission circuit 115 is shorter than the time required for one compression, and thus the compressed data can be sent to the data transmission circuit before the next data is output from the compression circuit. In addition, the data selection logic circuit can send the compressed data to the data transmission circuit in a different order according to settings made by inputting an external signal or the like. For example, when it is desired to first process the distance data among the data included in the camera data, the distance data can be sent first even when the distance data and the YUV image data are received simultaneously.

[0111] In addition, although the data processing device includes a reversible compression circuit and an irreversible compression circuit in the above-described embodiments, it is not limited thereto. All of the plurality of compression circuits included in the data processing device can be reversible compression circuits, or they can all be irreversible compression circuits.

[0112] In addition, although the camera output includes a data group of a plurality of different types of data in the above-described embodiments, the device that outputs the data group is not limited to a camera. This embodiment can be applied to any device capable of outputting a data group. For example, a scanner can output a data group, or a recording device can output a data group. In the case of a scanner, the data group can include, for example, image data obtained by scanning and data indicating the characteristics of the image data. In addition, in the case of a recording device, the data group can include data representing the recorded video and data related to the video (recording time, position data indicating the recording location, etc.).

[0113] Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments and can be variously changed and modified without departing from the scope of the present invention.

[0114] List of Reference Numerals

[0115] 1 Data processing device

[0116] 2 Data selector circuit

[0117] 4A First compression circuit

[0118] 4B Second compression circuit

[0119] 6 Data transmission circuit

[0120] 10 Data processing system

[0121] 20 Data processing system

[0122] 30 Data processing system

[0123] 100 Camera

[0124] 110 Data processing device

[0125] 111 Data selector circuit

[0126] 112 Reversible compression circuit

[0127] 113 Irreversible compression circuit

[0128] 114 Memory

[0129] 115 Data transmission circuit

[0130] 120 Receiving terminal

[0131] 134 Reversible compression circuit

[0132] 141 Data transmission circuit

[0133] 142 Data transmission circuit

[0134] 150 Data transmission circuit

[0135] 210 Data processing device

[0136] 212 Ethernet header addition circuit

[0137] 213 Ethernet header addition circuit

[0138] 215 Ethernet communication circuit

[0139] 220 Memory

[0140] 222 Ethernet header addition circuit

[0141] 300 Relay device

[0142] 301 Camera data processing unit

[0143] 302 Camera data processing unit

[0144] 303 Camera data processing unit

[0145] 304 Camera data processing unit

[0146] 310 Top view receiving terminal

Claims

1. A data processing device, comprising: a data selector circuit that divides each of a plurality of data into divided data according to the classification of the data, each of the plurality of data including multiple types of data, and the classification of the data refers to data for which reversible compression is effective and data for which irreversible compression is effective; a plurality of compression circuits that respectively compress the divided data into compressed data having different formats in parallel with each other according to each of the plurality of data, the different formats being a reversible compression format and an irreversible compression format; and a data transmission circuit that transmits the compressed data to a terminal, wherein, when a data control signal is received from a circuit that has transmitted a set of the plurality of data, the data selector circuit divides the set of the plurality of data, wherein the data control signal is received separately from the plurality of data, and the data control signal includes information specifying the structure of each of the plurality of data in the set of the plurality of data, and wherein the data selector circuit divides each of the set of the plurality of data into the divided data for which reversible compression is effective and the divided data for which irreversible compression is effective based on the information specifying the structure of each of the plurality of data included in the data control signal.

2. The data processing device according to claim 1, wherein, when compression ends, each of the plurality of compression circuits outputs a data transmission request signal to the data transmission circuit, and wherein, based on the data transmission request signal, the data transmission circuit transmits each of the compressed data to the terminal.

3. The data processing device according to claim 1, further comprising: a memory that stores the compressed data respectively compressed by the plurality of compression circuits.

4. The data processing device according to claim 1, wherein, the data transmission circuit transmits the compressed data to the terminal in a format compatible with Ethernet.

5. The data processing device according to claim 4, further comprising: a header addition circuit that adds an Ethernet header to the compressed data respectively compressed by the plurality of compression circuits, wherein the data transmission circuit transmits the compressed data having the Ethernet header to the terminal.

6. The data processing device according to claim 1, wherein, the data transmission circuits transmit the compressed data separately from each other.

7. The data processing device according to claim 1, wherein, the information specifying the structure of each of the plurality of data in the set of the plurality of data is preset in the data selector circuit.

8. The data processing device according to claim 1, wherein, the data selector circuit divides the plurality of data into a first type of data of the divided data and a second type of data of the divided data, and the second type of data has a different compression reversibility from the first type of data of the divided data.

9. The data processing apparatus according to claim 8, wherein, the plurality of compression circuits compress the first type of data of the divided data in the first format of the different formats, and also compress the second type of data of the divided data in the second format of the different formats.

10. A data processing system, comprising: a plurality of data processing apparatuses, each of the plurality of data processing apparatuses comprising: a data selector circuit that divides each of a plurality of data into divided data according to a classification of the data, each of the plurality of data including multiple types of data, and the classification of the data refers to data for which reversible compression is effective and data for which irreversible compression is effective; a plurality of compression circuits that respectively compress the divided data into compressed data having different formats according to each of the plurality of data, the different formats being a reversible compression format and an irreversible compression format; and a data transmission circuit that transmits the compressed data to a terminal; and a repeater that transmits the compressed data transmitted from the plurality of data processing apparatuses to the terminal, wherein, when a data control signal is received from a circuit that has transmitted a set of the plurality of data, the data selector circuit divides the set of the plurality of data, wherein the data control signal is received separately from the plurality of data, and the data control signal includes information specifying the structure of each of the plurality of data in the set of the plurality of data, and wherein the data selector circuit divides each of the set of the plurality of data into the divided data for which reversible compression is effective and the divided data for which irreversible compression is effective based on the information specifying the structure of each of the plurality of data included in the data control signal.

11. The data processing system according to claim 10, wherein, the data selector circuit divides the plurality of data into a first type of data of the divided data and a second type of data of the divided data, and the second type of data has a different compression reversibility from the first type of data of the divided data.

12. The data processing system according to claim 11, wherein the plurality of compression circuits compress the first type of data of the divided data in the first format of the different formats, and compress the second type of data of the divided data in the second format of the different formats.

13. The data processing system according to claim 10, wherein, when compression ends, each of the plurality of compression circuits outputs a data transmission request signal to the data transmission circuit.

14. The data processing system according to claim 13, wherein, based on the data transmission request signal, the data transmission circuit transmits each of the compressed data to the terminal.

15. The data processing system according to claim 10, wherein, the data transmission circuit transmits the compressed data to the terminal in a format compatible with Ethernet.

16. The data processing system according to claim 15, further comprising: a header addition circuit that adds an Ethernet header to the compressed data respectively compressed by the plurality of compression circuits.

17. The data processing system according to claim 16, wherein, the data transmission circuit transmits the compressed data with the Ethernet header to the terminal.

18. The data processing system according to claim 10, wherein, the data transmission circuits transmit the compressed data separately from each other.

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