SOT MRAM cells and arrays including multiple SOT MRAM cells

Abstract

An SOT-MRAM cell (100) comprising at least one magnetic tunnel junction (MTJ) (20) comprising a tunnel barrier layer (22) between a pinned ferromagnetic layer (21) and a free ferromagnetic layer (23); an SOT wire (30) extending substantially parallel to the plane of the layers (21-23) and contacting a first end of the at least one MTJ (20); at least a first source line (SL1) connected to one end of the SOT wire (30); at least a first bit line (BL1) and a second bit line (BL2), wherein the SOT-MRAM cell comprises one MTJ (20), each bit line connected to the other end of the MTJ (20); or wherein the SOT-MRAM cell comprises two MTJs (20), each MTJ connected to one of the first bit line (BL1) and the second bit line (BL2).

Description

Technical Field

[0001] The present invention relates to spin-orbit torque (SOT)-magnetic random access memory (MRAM) cells and arrays comprising multiple SOT-MRAM cells. Background Technology

[0002] Spin-orbit torque (SOT)-magnetic random access memory (MRAM) elements have been identified as promising candidates. Figure 1 A conventional SOT-MRAM element 10 is shown. The SOT-MRAM element 10 includes a magnetic tunnel junction (MTJ) 20 comprising a tunnel barrier layer 22 sandwiched between a pinned ferromagnetic layer 21 having pinned magnetization 210 and a free ferromagnetic layer 23 having free magnetization 230. The SOT-MRAM element 10 further includes a heavy metal SOT line 30 extending generally parallel to the plane of layers 21-23 and contacting the MTJ 20 at its first end (on one side of the free layer 23). The SOT line 30 is configured to carry an SOT current 31 adapted to switch a second magnetization 230. Specifically, through the spin Hall effect and / or the Lashba-Edstein effect, the SOT current 31 applies a torque on the initial orientation of the free magnetization 230, causing the orientation of the free magnetization 230 to change, for example, from parallel to the pinned magnetization 210 to antiparallel to the pinned magnetization 210.

[0003] SOT-based switching allows for lower current densities and independent read and write paths. Pinned magnetization 210 and free magnetization 230 can be perpendicular to the plane of layers 21 and 23 (e.g., Figure 1 (as shown in the diagram), or a plane parallel to layers 21 and 23.

[0004] Figure 2a and 2b A conventional SOT-MRAM cell 100 is shown, comprising an SOT-MRAM element 10, a bit line BL connected to one end of an SOT line 30, and a source line SL connected to an MTJ 20 via a first transistor 40. The first transistor 40 is connected to a second end of the MTJ 20 opposite to the first end (on one side of the pinned layer 21). The source line SL is further connected to the other end of the SOT line 30 via a second transistor 41. The gate of the first transistor 40 is controlled by a read word line WLR, and the gate of the second transistor 41 is controlled by a write word line WLW. The SOT-MRAM cell 100 forms a three-terminal, two-transistor, and one-resistor (2T1R) single-level cell (SLC) circuit.

[0005] During write operations ( Figure 2a Apply an appropriate positive or negative write voltage V to the bit line BL. 写入The source line SL is set to "0". The write word line WLW is biased to "1" to control the second transistor 41 in pass mode, allowing the SOT current 31 to flow through the SOT line 30. The first transistor 40 is in close mode "0", and no current flows in the MTJ 20.

[0006] Alternatively, instead of applying a negative voltage to BL, a positive write voltage V can be applied to SL. 写入 And set BL to "0".

[0007] During the read operation ( Figure 2b Apply an appropriate read voltage V to the bit line BL. 读取 The source line SL is set to "0". The read word line WLR is biased to "1" to control the first transistor 40 in pass mode, allowing the read current 32 to flow through the MTJ20. The second transistor 41 is in close mode, and no current flows in the SOT line 30.

[0008] Figure 2a and 2b The 2T1R SOT-MRAM cell 100 shown can be used in a single-port circuit, thereby allowing write voltage V to be applied separately. 写入 and read voltage V 读取 The same bit line BL is used for input SOT current 31 and read current 32. During the read operation, the leakage current I... 漏 The current can flow through the second transistor 41 connected to the SOT line 30 because the read current 32 may preferably flow through the low-resistance path transistor 40 rather than the high-resistance path transistor 41.

[0009] Figure 3a It shows Figure 2a , 2b A variation of the 2T1R SOT-MRAM cell 100 shown is described in the reference: Yeongkyo Seo et al., "High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R / 1W) Spin-Orbit Torque MRAM", IEEE Journal of Emerging and Selected Topics in Circuits and Systems, Vol. 6, No. 3, September 2016. Here, the SOT-MRAM cell 100 includes a source line SL connected to one end of the SOT line 30, a read bit line BLR connected to the second end of the MTJ 20 via a first transistor 40, and a write bit line BLW connected to the other end of the SOT line 30 via a second transistor 41. The gate of the first transistor 40 is controlled by the read word line WLR, and the gate of the second transistor 41 is controlled by the write word line WLW.

[0010] Figure 3b It indicates that it includes two Figure 3a An array 200 of SOT-MRAM cells 100. Read bit line BLR and write bit line BLW are connected to MTJ 20 in a column. The read array 200 can be accessed by applying a read voltage V to the read bit line BLR. 读取 This is implemented by setting the source line SL to "0". When the first transistor 40 is in pass mode, the read current 32 flows through MTJ 20. The first transistor 40 of the top MTJ 20 is in pass mode, causing the top MTJ 20 to be read. The write array can be written by applying a write voltage V to the write bit line BLW. 写入 And the source line SL is set to "0" to perform this. When the second transistor 41 is in pass mode, the SOT current 31 flows through the SOT line 30 ( Figure 3b (The bottom of MTJ 20). By applying a read voltage V between the read bit line BLR and the source line SL. 读取 And by setting the first transistor 40 to pass mode, an MTJ 20 can be read by applying a write voltage V on the write bit line BLW. 写入 The source line SL is set to "0" and the second transistor 42 is set to pass mode while another MTJ 20 is written. Since the MTJ 20s in the same column share the same read bit line BLR, simultaneous read operations on the same column are not possible. Similarly, write operations on the same column are not possible.

[0011] At the memory level, read and write operations can be performed on a single read / write port by using the read bit line BLR and the write bit line BLW separately and sequentially, or by simultaneously performing read and write operations on one port and one port in a two-port register file. Simultaneous read and write operations on the MTJ 20 on the same SOT-MRAM cell 100 are not possible. Furthermore, during write operations, the source line SL is set to 0V, requiring the write bit line BLW to be set to a negative voltage depending on the polarity of the SOT current 31. Summary of the Invention

[0012] This disclosure relates to an SOT-MRAM cell comprising: at least one magnetic tunnel junction (MTJ) including a tunnel barrier layer between a pinned ferromagnetic layer and a free ferromagnetic layer; an SOT line extending generally parallel to a plane of the layer and contacting a first end of the at least one MTJ; at least a first source line connected to one end of the SOT line; and at least a first bit line and a second bit line, wherein the SOT-MRAM cell comprises one MTJ and each bit line is connected to the other end of the MTJ; or wherein the SOT-MRAM cell comprises two MTJs, each MTJ being connected to one of the first bit line and the second bit line.

[0013] This disclosure further relates to an array comprising multiple SOT MRAM cells.

[0014] The SOT MRAM cells disclosed in this paper provide dual-port functionality (simultaneous read, simultaneous write, or simultaneous read and write) or differential read / write in a single-port architecture. Attached Figure Description

[0015] The invention will be better understood through the description of embodiments given by way of example and illustrated in the accompanying drawings, wherein:

[0016] Figure 1 A conventional SOT-MRAM element is shown;

[0017] Figure 2a and 2b This shows the write operation ( Figure 2a ) and read operations ( Figure 2b During the period, including Figure 1 The conventional SOT-MRAM cell of the SOT-MRAM element;

[0018] Figure 3a It shows Figure 2a , 2b Variations of the SOT-MRAM cell;

[0019] Figure 3b It indicates that it includes two Figure 3a An array of SOT-MRAM cells,

[0020] Figure 4a An SOT-MRAM cell according to an embodiment is shown;

[0021] Figure 4b This indicates that, according to the embodiment, two are arranged in columns. Figure 4a An array of SOT-MRAM cells;

[0022] Figure 4c This indicates two items arranged in rows. Figure 4aAn array of SOT-MRAM cells;

[0023] Figure 5a An SOT-MRAM cell according to another embodiment is shown;

[0024] Figure 5b The illustration shows two columns arranged in columns according to an embodiment. Figure 5a An array of SOT-MRAM cells;

[0025] Figure 6 It shows Figure 5a Variations of the SOT-MRAM cell;

[0026] Figure 7 It shows Figure 5a Another variation of the SOT-MRAM cell;

[0027] Figure 8 It shows Figure 6 Variations of the SOT-MRAM cell;

[0028] Figures 9a-9c The illustration depicts a write operation according to another embodiment. Figure 9b ) and read operations ( Figure 9c SOT-MRAM cells during the period ( Figure 9a );

[0029] Figure 9d It shows Figures 9a-9c A top view of the SOT-MRAM cell 100; and

[0030] Figures 10a-10c The diagram illustrates the write operation ( Figure 10b ) and read operations ( Figure 10c During another configuration () Figure 10a The SOT-MRAM cell in ). Detailed Implementation

[0031] Figure 4a An SOT-MRAM cell 100 according to an embodiment is shown. The SOT-MRAM cell 100 includes an SOT-MRAM element 10, a first source line SL1 connected to one end of an SOT line 30, and a first bit line BL1 connected to a second end of an MTJ 20 via a first transistor 40. The SOT-MRAM cell 100 further includes a second bit line BL2 connected to the other end of the SOT line 30 via a third transistor 42 and connected to the second end of the MTJ 20 via a second transistor 41. A first read word line WLR1 and a second read word line WLR2 are connected to the gates of the first transistor 40 and the second transistor 41, respectively. A first write word line WLW1 is connected to the gate of the third transistor 42. Figure 4aThe SOT-MRAM cell 100 forms a 3T1R circuit.

[0032] Figure 4b The illustration shows two columns arranged in a column, according to an embodiment. Figure 4a An array 200 of SOT-MRAM cells 100. Each of the first and second bit lines BL1, BL2 and the first source line SL1 is connected to an SOT-MRAM element 10 in a column. It should be understood that the array 200 may include more than two SOT-MRAM cells 100.

[0033] An array comprising multiple SOT-MRAM cells 100 can be arranged such that each of the first and second bit lines BL1, BL2 connecting a row of SOT-MRAM cells 100 is at least orthogonal to a first source line SL1 connecting a row of SOT-MRAM cells 100. Figure 4c It shows two Figure 4a An array 200 of SOT-MRAM cells 100. Specifically, the first and second bit lines BL1... n BL2 n BL1 n+1 BL2 n+1 Each of them is orthogonal to the first source line SL1 of the SOT-MRAM element 10 connected in a row.

[0034] During a write operation, a positive or negative write voltage V is applied to the second bit line BL2. 写入 And set the first source line SL1 to "0". First write word line WLW n (or WLW) n+1 The third transistor 42 is controlled to be in pass mode, so that the SOT current 31 passes through the SOT line 30 and is written into MTJ 20. The first and second transistors 40 and 41 are in close mode.

[0035] Alternatively, instead of applying a negative voltage to BL2, a positive write voltage V can be applied to SL1. 写入 And set BL2 to "0".

[0036] During a read operation, when the first source line SL1 is set to "0", a read voltage V can be applied to the first source line BL1. 读取 First read word line WLR1 n+1 (or WLR1) n The first transistor 40 is controlled to be in pass mode, such as allowing the read current 32 to flow through MTJ 20. The second and third transistors 41 and 42 are in close mode. Alternatively, when the first source line SL1 is set to "0", a read voltage V can be applied to the second bit line BL2. 读取The second read word line, WLR2. n (or WLR2) n+1 The second transistor 41 is controlled to be in pass mode, such as allowing the read current 32 to pass through MTJ 20. The first and third transistors 40 and 42 are in close mode. This is achieved by simultaneously applying the read voltage V to the first and second bit lines BL1 and BL2. 读取 Setting the first source line SL1 to "0" may also enable simultaneous reading on both ports. The first and second read word lines WLR1 n (or WLR1) n+1 WLR2 n (or WLR2) n+1 The first and second transistors 40 and 41 are respectively controlled to be in the off mode. Then, the read current 32 passes through the two transistors 20.

[0037] Therefore, SOT-MRAM cell 100 and array 200 can be written to on one port and read from on two ports simultaneously.

[0038] Figure 5a A SOT-MRAM cell 100 according to another embodiment is shown. The SOT-MRAM cell 100 includes two SOT-MRAM elements 10 connected by their SOT lines 30, and a first source line SL1 connected to one end of the SOT lines 30. A first bit line BL1 is connected to a second end of an MTJ 20 via a first transistor 40. A second bit line BL2 is connected to the second end of another MTJ 20 via a second transistor 41, and to the other end of the SOT lines 30 via a third transistor 42. A first read word line WLR1 and a second read word line WLR2 are connected to the gates of the first transistor 40 and the second transistor 41, respectively. A first write word line WLW1 is connected to the gate of the third transistor 42. Figure 5a The SOT-MRAM cell 100 forms a 3T2R circuit.

[0039] Figure 5b The illustration shows two columns arranged in columns according to an embodiment. Figure 5a An array 200 of SOT-MRAM cells 100. Each of the first and second bit lines BL1, BL2 and the first source line SL1 is connected to a pair of SOT-MRAM elements 10 in a column. It should be understood that the array 200 may include more than two SOT-MRAM cells 100. As described above, the source line SL1 may be connected to a row of SOT-MRAM cells 100, while the bit lines BL1, BL2 are connected to a column of SOT-MRAM cells 100. For example, each of the first and second bit lines BL1, BL2 may be orthogonal to the first source line SL1 connected to a row of SOT-MRAM elements 10.

[0040] During a write operation, a positive or negative write voltage V is applied to the first bit line BL2. 写入 The first source line SL1 is set to "0". The first write word line WLW1 controls the third transistor 42 to be in pass mode, allowing the SOT current 31 to pass through the SOT line 30 and write to the two MTJ 20. The first and second transistors 40 and 41 are in closed mode.

[0041] Alternatively, instead of applying a negative voltage to BL2, a positive write voltage V can be applied to SL. 写入 And set BL2 to "0".

[0042] During a read operation, when the first source line SL1 is set to "0", a read voltage V can be applied to the first source line BL1. 读取 The first read word line WLR1 controls the first transistor 40 to be in pass mode, such as allowing the read current 32 to flow through MTJ 20 connected to the first transistor 40. The second and third transistors 41 and 42 are in close mode. Alternatively, when the first source line SL1 is set to "0", a read voltage V can be applied to the second bit line BL2. 读取 The second read word line WLR2 controls the second transistor 41 to be in pass mode, such as allowing the read current 32 to pass through MTJ 20 connected to the second transistor 41. The first and third transistors 40, 42 are in close mode. Preferably, this is achieved by applying a read voltage V to the first and second bit lines BL1, BL2. 读取 The first source line SL1 is set to "0", and the first and second read word lines WLR1 and WLR2 control the first and second transistors 40 and 41 to be in pass mode, such as allowing the read current 32 to pass through the two MTJ 20, to perform simultaneous reading on both ports. The third transistor 42 is in closed mode.

[0043] Figure 5a SOT-MRAM cell 100 and Figure 5b The array 200 is capable of simultaneous reading on two ports and writing on one port. Furthermore, differential read operations can be performed on one port using BL1 and BL2. A differential read operation involves writing two opposite values ​​to the two MTJ 20s and applying a voltage V to BL1 and BL2. 读取 Such as generating a difference in read current 32 between two MTJ 20s.

[0044] Figure 6 It shows Figure 5a A variation of the SOT-MRAM cell 100. Here, the SOT-MRAM cell 100 further includes a fourth transistor 43 that connects the second bit line BL2 to the other end of the SOT line 30. Figure 6 The SOT-MRAM cell 100 forms a 4T2R circuit. The second write word line WLW2 is connected to the gate of the fourth transistor 43.

[0045] Figure 6 The SOT-MRAM cell 100 allows for dual-port writing. During a write operation, a positive or negative write voltage V can be applied to one of the first or second bit lines BL1, BL2. 写入 Meanwhile, the first source line SL1 is set to "0", and the third or fourth transistors 42 and 43 are respectively controlled to be in pass mode, such as allowing the SOT current 31 to pass through the SOT line 30.

[0046] By applying a read voltage V to the first and second bit lines BL1 and BL2 读取 Set the first source line SL1 to "0" and control the first and second transistors 40 and 41 to be in pass mode, such as allowing the read current 32 to pass through both MTJ 20. Figure 6 The SOT-MRAM cell 100 further allows simultaneous reading on both ports.

[0047] therefore, Figure 6 The SOT-MRAM cells 100 provide read and write access on the same column rather than on the same SOT-MRAM cell 100. The SOT-MRAM cells 100 are also adapted to perform differential read operations on a single-port architecture.

[0048] During a write operation, a negative voltage V may need to be applied to the first or second bit lines BL1, BL2. 写入 .

[0049] Figure 7 It shows Figure 5a Another variation of the SOT-MRAM cell 100, wherein the third transistor 42 is not connected to the second bit line BL2, but is connected to the third bit line BL3. Figure 7 The SOT-MRAM cell 100 forms a 3T2R circuit.

[0050] During a write operation, a positive or negative write voltage V is applied to the third line BL3. 写入 Simultaneously, the first source line SL1 is set to "0", and the third transistor 42 is controlled to be in pass mode. Then, the SOT current 31 flows through the SOT line 30, thereby writing to the two MTJ 20.

[0051] Alternatively, instead of applying a negative voltage to BL2, a positive write voltage V can be applied to SL1. 写入 And set BL3 to "0".

[0052] By applying a read voltage V to the first and second bit lines BL1 and BL2 读取 By setting the first source line SL1 to "0" and controlling the first and second transistors 40 and 41 to be in pass mode, such as allowing the read current 32 to pass through both MTJ 20, simultaneous reading can be achieved on both ports. Figure 7 SOT-MRAM cell 100.

[0053] Figure 7 The SOT-MRAM cell 100 allows for read and write access on the same column and is suitable for performing differential read operations (single-port). However, in the case of two ports, during write operations, Figure 7 The SOT-MRAM cell 100 requires a negative voltage on the third bit line BL3.

[0054] exist Figure 7 In a variant of the SOT-MRAM cell 100 (not shown), the first, second, and third transistors 40, 41, and 42 are controlled by the same word line. This configuration has a smaller area. Figure 7 The SOT-MRAM cell 100 can be used as a single-port or two-port cell.

[0055] Figure 8 It shows Figure 6 A variation of the SOT-MRAM cell 100 further includes a fifth transistor 44 connected between the first source line SL1 and the SOT line 30. The SOT-MRAM cell 100 further includes a second source line SL2 connected to one end of the SOT line 30 via a sixth transistor 45. The fifth and sixth transistors 44 and 45 are controlled by the first and second word lines WLW1 and WLW2, respectively. Figure 8 The SOT-MRAM cell 100 forms a 6T2R circuit.

[0056] Figure 8 The SOT-MRAM cell 100 allows for dual-port write and read operations on both bit lines BL1, BL2 and source lines SL1, SL2. During a write operation, a write voltage V is applied to the first and / or second bit lines BL1, BL2. 写入 Simultaneously, the first and / or second source lines SL1, SL2 are set to "0". Alternatively, a write voltage V can be applied to the first and / or second source lines SL1, SL2. 写入The first and / or second bit lines BL1, BL2 are set to "0" to perform a write operation. The first or second word lines WLW1, WLW2 are controlled to set the third and fourth transistors 42, 43 to pass mode, respectively. The first or second read / write word lines WLRW1, WLRW2 are controlled to set the sixth and seventh transistors 44, 45 to pass mode, respectively. The first and second transistors 40, 41 are in closed mode.

[0057] By applying a read voltage V to the first and second bit lines BL1 and BL2 读取 Then set the first and second source lines SL1 and SL2 to "0". Figure 8 The SOT-MRAM cell 100 allows simultaneous reading on two ports. Reading can also be achieved by applying a read voltage V to the first and second source lines SL1, SL2. 读取 The first and second bit lines BL1 and BL2 are set to "0" to achieve simultaneous reading on both ports. During the read operation, the first and second transistors 40 and 41, as well as transistor 44 or 45, are set to pass mode, such as allowing the read current 32 to pass through MTJ 20. The third or fourth transistor 42 and 43 are in closed mode.

[0058] Figure 8 The SOT-MRAM cell 100 allows a positive voltage V to be applied to ports BL1, BL2, SL1, and SL2. 写入 and V 读取 Regardless of the cell type, simultaneous read access on both ports is possible, as is simultaneous write access on the same column in the array rather than on the same SOT-MRAM element 10. In a single-port architecture, the SOT-MRAM cell 100 is adapted to perform differential read operations.

[0059] Figures 9a-9c The illustration shows a SOT-MRAM cell 100 according to another embodiment. The SOT-MRAM cell 100 includes first and second bit lines BL1, BL2, each bit line being directly connected to a second terminal of one of the transistors 20. First and second source lines SL1, SL2 are individually connected to an SOT line 30 via first and second transistors 40, 41, respectively. A third transistor 42 is included on the SOT line 30 between the two SOT-MRAM cells 10. A word line WL can be controlled to set transistors 40, 41, and 42 to either closed or open mode. Figure 9a The SOT-MRAM cell 100 forms a 3T2R circuit.

[0060] Figure 9b The diagram illustrates the process during a write operation. Figure 9aThe SOT-MRAM cell 100, wherein a write voltage V is applied to one of the first or second source lines SL1, SL2. 写入 Meanwhile, another source line is set to "0". When the three transistors 40-42 are set to pass mode "1" by word line WL, SOT current 31 flows through SOT line 30.

[0061] Figure 9c The diagram illustrates the process during a read operation. Figure 9a The SOT-MRAM cell 100, wherein a read voltage V is applied to the first bit line BL1 and the second bit line BL2. 读取 Simultaneously, source lines SL1 and SL2 are set to "0". Word line WL sets the three transistors 40-42 to pass mode "1". In this way, read current 32 flows between the first bit line BL1 and the first source line SL1, passing through one of the MTJ 20, and read current 32 flows between the second bit line BL2 and the second source line SL2, passing through the other MTJ 20. Because the third transistor 42 is in off mode, read current can also flow in the SOT line 30 between the two SOT-MRAM cells 10.

[0062] The read current 32 passing through the SOT line 30 may cause undesirable reorientation of the free magnetization. Because... Figures 9a-9c With the symmetrical configuration of the SOT-MRAM cells 10, the read current 32 can flow between the two SOT-MRAM cells 100 via the third transistor 42. Therefore, the read current 32 will be split into two current portions in opposite directions in the SOT line 30 under each MTJ 20. Any parasitic writes to the MTJ 20 by the read current 32 are then canceled.

[0063] Figure 9d A top view of an SOT-MRAM cell 100 is shown, in which the SOT-MRAM elements 10 are arranged in a U-shaped configuration. During a write operation, the U-shaped configuration of the SOT lines 30 allows the SOT current 31 to flow under one of the MTJ 20 in the opposite direction to the direction in which one of the SOT currents 31 flows under the other MTJ 20. Therefore, the SOT current 31 can write two opposite logic states in the MTJ 20, such as state "0" (parallel) in one MTJ 20 and state "1" (antiparallel) in the other MTJ 20. Differential read operations can thus be performed. This U-shaped configuration can be applied to... Figures 9a-9c and Figures 10a-10c Any of the SOT-MRAM cells 100, and in the case where there is no third transistor 42 on the SOT line 30 between the two SOT-MRAM cells 10, can be applied to Figures 4a-4cSOT-MRAM cells 100 configuration of 5a-5b and 6 to 8.

[0064] Figures 10a-10c The illustration shows an SOT-MRAM cell 100 in another configuration. The SOT-MRAM cell 100 includes a first bit line BL1 directly connected to one end of the SOT line 30 and a second bit line BL2 also directly connected to the other end of the SOT line 30. Source lines SL are connected to the second ends of each of the two MTJ 20 via first transistor 40 and second transistor 41, respectively. A third transistor 42 is included on the SOT line 30 between the two MRAM cells 10. A first read word line WLR1 and a second read word line WLR2 set the first and second transistors 40 and 41 to either closed or open mode, respectively. The third transistor 42 is controlled by a first write word line WLW1. Figures 10a-10c The SOT-MRAM cell 100 forms a 3T2R circuit.

[0065] Figure 10b The diagram illustrates an SOT-MRAM cell 100 during a write operation, thereby applying a write voltage V to one of the first or second bit lines BL1, BL2. 写入 Meanwhile, set the other line to "0". Set the third transistor 42 to pass mode, allowing the SOT current 31 to flow through the SOT line 30. Set transistors 40 and 41 to close mode.

[0066] Figure 10c The diagram illustrates an SOT-MRAM cell 100 during a read operation, thereby applying a read voltage V to the first bit line BL1 and the second bit line BL2. 读取 Simultaneously, the source line SL is set to "0". The first and second transistors 40 and 41 are set to pass mode, causing the read current 32 to flow between the first bit line BL1 and the source line SL, and between the second bit line BL2 and the source line SL, passing through each of the MTJ 20. The third transistor 42 is set to close mode, and no current flows between the two MTJ 20. The SOT-MRAM cell 100 is adapted to perform differential read operations (single-port).

[0067] Reference marks and symbols

[0068] 10 SOT-MRAM components

[0069] 100 SOT-MRAM cells

[0070] 20 MTJ

[0071] 200 array

[0072] 21. Pinning ferromagnetic layers

[0073] 210 Pinning magnetization

[0074] 22 Tunnel Barrier Layer

[0075] 23 Free ferromagnetic layer

[0076] 230 Free magnetization

[0077] 24 First antiferromagnetic layer

[0078] 30 SOT layers

[0079] 31 SOT current

[0080] 40 First transistor

[0081] 41 Second transistor

[0082] 42 Third transistor

[0083] 43 Fourth transistor

[0084] 44. Fifth transistor

[0085] 45. Sixth transistor

[0086] BL bitline

[0087] BL1 First Line

[0088] BL2 Second Line

[0089] BL3 Third Line

[0090] i 漏 Leakage current

[0091] SL source line

[0092] SL1 First Source Line

[0093] SL2 Second Source Line

[0094] V 读取 Read voltage

[0095] V 写入 Write voltage

[0096] WL lettering

[0097] WLR read word line

[0098] WLW write word lines

[0099] WLW1 First Write Word Line

[0100] WLW2 Second Write Word Line

[0101] WLR1 First Read Word Line

[0102] WLR2 Second Read Word Line

[0103] WLRW1 First Read / Write Word Line

[0104] WLRW2 Second Read / Write Word Line

Claims

1. A spin-orbit torque (SOT) -magnetic random access memory (MRAM) cell (100), comprising: at least one magnetic tunnel junction (MTJ) (20) comprising a tunnel barrier layer (22) between a pinned ferromagnetic layer (21) and a free ferromagnetic layer (23); a SOT wire (30) extending parallel to the plane of layers 21-23 and contacting a first end of the at least one MTJ (20); at least a first source line (SL1) connected to one end of the SOT wire (30); at least a first bit line (BL1) and a second bit line (BL2), characterized in that the SOT-MRAM cell (100) comprises at least one MTJ (20), each bit line (BL1, BL2) is connected to a second end of the at least one MTJ (20); wherein the first bit line (BL1) connects the at least one MTJ (20) via a first transistor (40), and the second bit line (BL2) connects the at least one MTJ (20) via a second transistor (41), and wherein the second bit line (BL2) further connects the other end of the SOT wire (30) via a third transistor (42), or in that the SOT-MRAM cell (100) comprises two MTJs (20), which are connected to each other and each MTJ (20) is connected to one of the first bit line (BL1) and the second bit line (BL2), and wherein the first bit line (BL1) is further connected to the other end of the SOT wire (30) via a fourth transistor (43).

2. The SOT-MRAM cell (100) according to claim 1, wherein the SOT-MRAM cell (100) comprises a third bit line (BL3) connected to the other end of the SOT wire (30) via a third transistor (42).

3. The SOT-MRAM cell (100) according to claim 1, wherein the first source line (SL1) is connected to one end of the SOT wire (30) via a fifth transistor (44), and a second source line (SL2) is connected to one end of the SOT wire (30) via a sixth transistor (45).

4. The SOT-MRAM cell (100) according to claim 1, comprising two MTJs (20), a first bit line (BL1) and a second bit line (BL2), each directly connected to a second end of one of the MTJs (20); a first and a second source line (SL1, SL2), each connected to the SOT wire (30) via a first and a second transistor (40, 41), respectively; and a third transistor (42) included in the path of the SOT wire (30) between the two MTJs (20).

5. An array (200) comprising a plurality of SOT-MRAM cells (100) according to claim 1, wherein each of the first and second bit lines (BL1, BL2) and the at least first source line (SL1) is connected to SOT-MRAM elements (10) in one column or one row.

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