Non-volatile memory and operation method thereof

Abstract

The present invention discloses a non-volatile memory and an operation method thereof. The non-volatile memory comprises a plurality of memory cell strings, a plurality of bit switches, a memory operation circuit and a plurality of source switches. The bit switches are electrically connected to the memory cell strings. The memory operation circuit is electrically connected to the bit switches for transmitting a write signal to the memory cell strings. The source switches are electrically connected to the memory cell strings so that the memory cell strings receive a bias signal via the source switches. In a write phase, when the first bit switch in the bit switches is turned on so that the first memory cell string receives a write signal via the first bit switch, the source switches electrically connected to other memory cell strings will be turned on.

Description

Technical Field

[0001] The invention relates to a non-volatile memory and an operating method. Background Art

[0002] As the manufacturing process of planar non-volatile memory is gradually approaching the limit of miniaturization, in order to more efficiently increase the capacity per unit area of ​​non-volatile memory, three-dimensional non-volatile memory is gradually gaining attention in the industry. Three-dimensional non-volatile memory has a multi-layer stacked structure, which can achieve higher storage capacity and has excellent electronic properties, such as good data storage reliability and operation speed. Summary of the invention

[0003] One embodiment of the present invention is a non-volatile memory, comprising a memory cell array, a plurality of bit switches, a memory operation circuit, and a plurality of source switches. The memory cell array comprises a plurality of memory cell strings. The bit switches are electrically connected to the memory cell strings. The memory operation circuit is electrically connected to the bit switches and is used to transmit a write signal to the memory cell array via the bit switches during a write phase. The source switch is electrically connected to the memory cell strings. At least one of the memory cell strings is used to receive a bias signal via at least one of the source switches. During the write phase, when a first bit switch in the bit switches is turned on, so that a first memory cell string in the memory cell string receives a write signal via the first bit switch, the source switches electrically connected to other memory cell strings will be turned on.

[0004] Another embodiment of the present invention is an operation method of a non-volatile memory, comprising the following steps: in a write phase, turning on a first switch so that a write signal is input to a first memory cell in a first memory cell series via the first switch and a first line. Turning off a first source switch so that a circuit is formed between the first memory cell series and a bias circuit, and the first line and the first source line in the first memory cell series are maintained at the same potential through the first memory cell.

[0005] Another embodiment of the present invention is a non-volatile memory, comprising a memory cell array, a plurality of bit switches, a memory operation circuit, and a plurality of source switches. The memory cell array comprises a plurality of memory cell strings. The bit switches are electrically connected to the memory cell strings. The memory operation circuit is electrically connected to the bit switches and is used to transmit a write signal to the memory cell array via the bit switches during a write phase. The source switches are electrically connected to the memory cell strings. At least one of the memory cell strings is used to receive a bias signal via at least one of the source switches. During the write phase, when the first bit switch in the bit switches is turned on so that the first memory cell string in the memory cell string receives the write signal, the first source switch in the source switches electrically connected to the first memory cell string will be turned off.

[0006] Accordingly, since the nonvolatile memory transmits the write signal and the bias signal through different paths and switches, the bit line and the source line in each memory cell string can be maintained at the same potential to ensure the correct reading and writing of the nonvolatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A Schematic diagram of a non-volatile memory according to some embodiments of the present invention.

[0008] Figure 1B Schematic diagram of equivalent circuit of a non-volatile memory according to some embodiments of the present invention.

[0009] Figure 2 Schematic diagram of a non-volatile memory according to some embodiments of the present invention.

[0010] Figure 3A to Figure 3E FIG. 1 is a schematic diagram of the operating state of a non-volatile memory according to some embodiments of the present invention.

[0011] Figure 4 FIG. 4 is a schematic diagram of an operation method of a non-volatile memory according to some embodiments of the present invention.

[0012] Figure 5A FIG. 4 is a potential detection diagram in a memory cell string corresponding to a write target.

[0013] Figure 5B FIG. 4 is a diagram showing potential detection in a memory cell string that does not correspond to a write target.

[0014]

Explanation of symbols

[0015] X...Channel Unit

[0016] X1...Doping Department

[0017] X2...Doping Department

[0018] Y...Storage Layer

[0019] Y1...Oxide layer

[0020] Y2...conductive layer

[0021] CH...Channel

[0022] 100...Non-volatile memory

[0023] 200...Non-volatile memory

[0024] A...Memory Cell Array

[0025] A1~An...Memory cell series

[0026] M21~M2n...Memory unit

[0027] M31~M3n...Memory unit

[0028] Mn1~Mnn...Memory unit

[0029] BT1~BTn...position switch

[0030] ST1~STn...Source switch

[0031] BL1~BLn...bit lines

[0032] SL1~SLn...Source line

[0033] WL1~WLn...word line

[0034] GBL...Common Bit Line

[0035] CSL...Common Source Line

[0036] 110...Memory operation circuit

[0037] 111...Cache circuit

[0038] 112...Buffer circuit

[0039] 113...Amplifier circuit

[0040] 120...Bias circuit

[0041] V CSL ...bias signal

[0042] Sr...Write signal

[0043] Vbl...bit line voltage

[0044] Vwl...word line voltage

[0045] Vsl...Source line voltage

[0046] S401~S408...Steps DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0048] The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be depicted in a simple schematic manner in the drawings.

[0049] In this document, when an element is referred to as "connected" or "electrically connected", it may refer to "electrically connected" or "electrically electrically connected". "Connected" or "electrically connected" may also be used to indicate that two or more elements cooperate with each other or interact with each other. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish between elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present invention.

[0050] The present invention relates to a non-volatile memory and an operation method thereof. In some embodiments, the present invention is to apply a 3D AND flash memory structure. Figure 1A and Figure 1B As shown, Figure 1A It is a schematic diagram of the structure of a three-dimensional AND gate flash memory. Figure 1B The memory cell array A in Figure 1A The equivalent circuit diagram of Figure 1A As shown, the non-volatile memory 100 includes multiple storage layers X and multiple channel units Y (Channel poly-Si Unit). The storage layer X includes an oxide layer X1 (such as: Oxide-Nitride-Oxide, oxide-nitride-oxide) and a conductive layer X2. The channel unit Y has doped parts Y1 and Y2. In the manufacturing process, the columnar semiconductor is vertically etched (vertical holeetching), and then pentavalent atoms are doped into the polysilicon through vertical buried diffusion technology (vertical Buried Diffusion) to form doped parts Y1 and Y2, and the channel CH is located between the doped parts Y1 and Y2. Under this structure, the non-volatile memory 100 will include multiple transistors as memory cells. The memory cells will form a multi-layer memory cell array connected in parallel. As Figure 1A As shown, the memory layer X2 is used as the gate of the memory cell, and the doped portions Y1 and Y2 are used as the source and drain of the memory cell respectively.

[0051] In the non-volatile memory 100, the gate of the memory cell and the oxide layer X1 have a floating gate or a charge trapping layer. Through the tunneling effect (F-N tunneling) of the semiconductor, when a high voltage is applied to the memory cell, electrons are attracted by the voltage and pass through the oxide layer to the floating gate (or charge storage layer), so that the transistor stores corresponding charge information. Since those skilled in the art can understand the technical principle of the non-volatile memory 100 using the tunneling effect to store charges, it will not be repeated here.

[0052] like Figure 1B The equivalent circuit shown in FIG. 1 shows a nonvolatile memory 100 including a memory cell array A, a plurality of bit switches BT1-BTn, a memory operation circuit 110, and a plurality of source switches ST1-STn. In some embodiments, the memory cell array A includes a plurality of memory cell strings A1-An. The memory cell strings A1-An each include a plurality of memory cells (e.g., Figure 1A , Figure 1B As shown in FIG. 1 , there are multiple bit lines BL1 to BLn and multiple source lines SL1 to SLn ( M11 to M1n, M21 to M2n, M31 to M3n, Mn1 to Mnn).

[0053] The bit switches BT1-BTn are electrically connected to the memory cell series A1-An through the bit lines BL1-BLn, respectively. In some embodiments, the bit switches BT1-BTn are electrically connected to the first end of the memory cell. The memory operation circuit 110 is electrically connected to the bit switches BT1-BTn. In some embodiments, the memory operation circuit 110 is used to receive the read / write instructions from the processor, and then apply a corresponding voltage signal (e.g., write signal Sr) to the memory cell array A according to the read / write instructions, or receive a current signal.

[0054] The source switches ST1 ˜STn are electrically connected to the memory cell strings A1 ˜An through the source lines SL1 ˜SLn. In some embodiments, the source switches ST1 ˜STn are electrically connected to the second terminals of the memory cells.

[0055] In the "write phase (Program mode, Write mode)" in which the memory operation circuit 110 writes data into the memory cell array A, at least one source switch is turned on, so that at least one memory cell string receives the bias signal V from the bias circuit 120 through the turned-on source switch. CSL. At the same time, at least one bit switch will be turned on so that the write signal Sr can be written to the corresponding memory cell. For example, during the write phase, if the "write target" is the first memory cell M13 in the first memory cell array A1. At this time, the first bit switch BT1 corresponding to the first memory cell string A1 will be turned on and the first source switch ST1 will be turned off, so that the first memory string A1 receives the write signal Sr through the first bit switch BT1. At the same time, the other source switches ST2~STn (such as the second source switch ST2) corresponding to other memory cell strings A2~An will be turned on, and the other bit switches BT2~BTn (such as the second bit switch BT2) corresponding to other memory cell strings A2~An will be turned off.

[0056] See also Figure 1B As shown, in addition to the multiple source lines SL1-SLn and bit lines BL1-BLn in the vertical direction, the memory cell array A also includes multiple word lines WL1-WLn in the horizontal direction. These word lines WL1-WLn are electrically connected to the control terminals of multiple memory cells in the memory cell array A. During the writing phase, the word lines WL1-WLn transmit an enable signal (e.g., a high voltage signal of 15-25 volts) to the memory cell corresponding to the writing target to turn on the memory cell so that the writing signal Sr transmitted by the memory operation circuit 110 can be written into the memory cell.

[0057] The present invention uses these bit switches BT1-BTn to control the conduction relationship between the memory cell series A1-An and the memory operation circuit 110, so as to selectively transmit the write signal Sr to the corresponding memory cell. In addition, the conduction relationship between the memory cell series A1-An and the bias circuit 120 is controlled by these source switches ST1-STn, so that other memory cells that are not the write target can be biased by the bias signal V CSL (e.g. 8 volts) to prevent receiving erroneous write data. Figure 1B As shown, since the word lines WL1-WLn will turn on multiple memory cells in the same row, the first memory cell string A1, which is the write target, will be able to keep the first bit line BL1 and the first source line SL1 at the same potential through the first memory cell M13, thereby preventing the potentials of the first bit line BL1 and the first source line SL1 from floating. In addition, for the bit lines and source lines (such as the second bit line BL2 and the second source line SL2) in other memory cell strings (such as the second memory cell string A2) that are not the write targets, they can also be kept at the same potential through the turned-on memory cells (such as the second memory cell). For example, the potentials of the second bit line BL2 and the second source line SL2 will both be inhibited by the bias signal V CSL voltage.

[0058] In some embodiments, the memory operation circuit 110 transmits a write signal Sr through a common bit line GBL, and the bias circuit 120 includes a common source line CSL (eg, Figure 2 As shown, the details will be described in the following paragraphs), used to bias the bias signal V CSL Passed to memory cell array A.

[0059] like Figure 1A In the three-dimensional structure shown, in some embodiments, since the bit line and the source line have large internal capacitance, when the word line transmits the enable signal, the memory cells in different horizontal rows cannot be coupled to each other through the self-boosting programming method. In this case, if the potential of the bit line or the source line is not controlled, the potential of the bit line or the source line will float to the ground potential. However, in this embodiment, the non-volatile memory 100 belongs to the "AND" memory structure, and the storage function is realized between the memory cells through the tunneling effect (FN tunneling) of the semiconductor. That is, when writing data, there should be no voltage difference between the bit line and the source line. Therefore, the present invention transmits the write signal to the memory cell string corresponding to the write target through the bit switches BT1~BTn, so that the potential of the bit line and the source line in the memory cell string corresponding to the write target can be controlled by the write signal Sr. At the same time, through the source switches ST1~STn, the potential of the bit line and the source line in the memory cell string not corresponding to the write target can be controlled by the bias signal V CSL This ensures that the bit line and source line are kept at the same potential.

[0060] Figure 1B The equivalent circuit shown is a portion of the non-volatile memory 100. In some embodiments, a plurality of non-volatile memories 100 can be arranged or stacked to form a three-dimensional structure. Figure 2 FIG. 2 is a schematic diagram of a non-volatile memory 200 according to the present invention. In some embodiments, the non-volatile memory 200 includes a plurality of memory blocks B1 to Bn. The circuit structure of each memory block B1 to Bn is as follows: Figure 1B As shown, the memory cells 110 are electrically connected to the same common source line CSL and common bit line GBL. That is, the memory operation circuit 110 sends write signals to the memory cell arrays in the plurality of memory blocks respectively.

[0061] Figure 2 The non-volatile memory 200 shown includes N memory blocks B1-Bn. In some embodiments, the N memory blocks B1-Bn are used to form a memory sector. Multiple memory sectors can be stacked to form a three-dimensional memory structure.

[0062] See also Figure 3A to Figure 3E As shown, the operation mode of the non-volatile memory in different operation stages is described in sequence. Figure 3A 1 is a schematic diagram of the "write phase". In this embodiment, the first memory cell M13 in the first memory cell string A1 is the write target. Therefore, the first bit switch BT1 will be turned on, so that the memory operation circuit 110 can transmit the write signal Sr to the first memory cell string A1 through the first bit switch BT1 and the first bit line BL1. At the same time, the first source switch ST1 electrically connected to the first memory cell string A1 will be turned off to prevent the bias signal V CSL The write signal Sr is affected. In some embodiments, the write signal Sr is a low voltage signal (eg, 0-1.8 volts).

[0063] In the write phase, the third word line W3 corresponding to the first memory cell M13 transmits an enable signal (e.g., a high voltage signal of 15-25 volts) to the memory cells (e.g., memory cell M23) in the same row as the first memory cell M13 in the memory cell array A. These memory cells M13-Mn3 will be turned on in response to the voltage of the third word line W3. Through the turned-on first memory cell M13, the first bit line BL1 and the first source line SL1 will be maintained at the same potential.

[0064] Since the other memory cell strings A2-An do not need to receive the write signal at this time, the bit switches BT2-BTn electrically connected to the other memory cell strings A2-An will be turned off. In addition, the source switches ST2-STn electrically connected to the other memory cell strings A2-An will be turned on to receive the bias voltage of the bias circuit 120 through the source switches ST2-STn, so that the bit lines and source lines in each memory cell string A2-An that does not correspond to the write target can maintain the same potential. Taking the second memory cell string A2 as an example, the second memory cell M23 will be turned on in response to the voltage of the third word line W3, and the second bit switch BT2 will be turned off and the second source switch ST2 will be turned on. At this time, the second memory cell array A2 will receive the bias signal through the second source switch S2, and the second bit line BL2 and the second source line SL2 will be maintained at the same potential through the second memory cell M23.

[0065] See also Figure 3B As shown, the operation of the "reading phase" is described as follows. In the reading phase, only the bit switches and source switches corresponding to the "reading target" are turned on, and the remaining bit switches are turned off. Figure 3BFor example, the read target is the first memory cell M13. Therefore, the first bit switch BT1 is turned on, the first source switch ST1 is also turned on, and the third word line WL3 provides an enable signal (e.g., a voltage of 4 to 7 volts). The remaining bit switches BT2 to BTn and the remaining source switches ST2 to STn are turned off. In the read phase, the memory operation circuit 110 provides a low voltage signal (e.g., 0.5 to 1.5 volts), and the bias signal V CSL The potential is zero, so that the bias circuit 120 turns on the first memory unit M13 through the first source switch ST1 and the first source line SL1, and the memory operation circuit 110 can read the data stored in the first memory unit M13.

[0066] exist Figure 3B In the embodiment shown, only the first source switch ST1 corresponding to the read target is turned on, and the other source switches are turned off. In other embodiments, during the read phase, other source switches ST2-STn not corresponding to the read target may also be turned on. Figure 3C For example, when the read target is the first memory cell M13, the first bit switch BT1 is turned on, all the source switches ST1-STn are turned on, but the remaining bit switches BT2-BTn are turned off.

[0067] See also Figure 3D As shown, the operation of the "erasing phase" is described as follows. In one embodiment, when the data in the memory cell array A is to be erased, the source switch corresponding to the "erasing target" is turned on, but the bit switch corresponding to the "erasing target" is turned off. Figure 3D For example, if the elimination target is all memory cell strings A1-An in the same memory block, all source switches ST1-STn in the memory block are turned on, and all bit switches BT1-BTn in the memory block are turned off, so that the memory cell strings A1-An are turned on to the bias circuit 120 through the source switches ST1-STn, and receive the bias signal V CSL (about 8 volts). The word line corresponding to the "elimination target" will apply a reverse voltage (e.g. -12 volts) to the memory cell. At this time, the memory cell will be turned on through the gate induced drain leakage (GIDL) mechanism.

[0068] In addition, if Figure 3E As shown, in other embodiments, during the erasing stage, all bit switches BT1 ˜BTn corresponding to the erasing targets may be turned on to increase the speed of erasing data.

[0069] In the aforementioned Figure 3D and Figure 3EIn the embodiment shown, the erasure operation is performed on all memory cells in the same memory block. That is, the word lines WL1-WLn transmit reverse voltages to the memory cells in the same block. In other embodiments, only the memory cells corresponding to the same word line in the same sector may be erased. Please refer to 2 and Figure 3E As shown, when the erasure target is a portion of the rows in the plurality of memory blocks (e.g., the third row and the fourth row), the third word line WL3 and the fourth word line WL4 will transmit a reverse voltage (e.g., -12 volts) to erase the memory cells in two rows in the memory cell array A. The remaining word lines WL1, WL2, and WLn maintain the enable signal (e.g., 8 volts).

[0070] In some embodiments, the memory operation circuit 110 includes a cache circuit 111, a buffer circuit 112, and an amplifier circuit 113. The cache circuit 111 is used to receive a write signal Sr during a write phase. The buffer circuit 112 is electrically connected to the cache circuit 111 and the amplifier circuit 113, and is used to receive the write signal Sr and output the write signal Sr to a common bit line GBL through the amplifier circuit 113. In some embodiments, the memory cell series (e.g., Figure 1B The memory series A1-An shown are electrically connected to the same input and output terminal of the amplifier circuit 113, so that the size of the non-volatile memory can be kept compact.

[0071] See also Figure 4 As shown, the operation method of the non-volatile memory of the present invention is described here, including steps S401 to S408. In step S401, the memory operation circuit 110 receives a read / write instruction from an external processor. In step S402, the memory operation circuit 110 determines what the read / write instruction is. If the read / write instruction is "write data", step S403 is entered to perform the write phase.

[0072] In step S403 , taking the first memory cell M13 as the writing target, the first bit switch BT1 is turned on, and the third word line W3 transmits an enable signal, so that the writing signal is input to the first memory cell M13 in the first memory cell string A1 via the first bit switch BT1 and the first bit line BL1 .

[0073] In step S404, the first source switch ST1 is turned off, so that a circuit is formed between the first memory cell string A1 and the bias circuit 120. The first bit line BL1 and the first source line SL1 in the first memory cell string A1 maintain the same potential through the first memory cell M13.

[0074] In step S405, the remaining bit switches (ie, bit switches BT2 to BTn) are turned off, so that a circuit is formed between the remaining memory cell strings and the memory operation circuit 110. Figure 3A As shown, a circuit is formed between the second bit line BL2 of the second memory cell string A2 and the memory operation circuit 110. In step S406, the source switch not corresponding to the write target is turned on. For example: the second source switch ST2 is turned on, and one of the second memory cells (such as the second memory cell M23 located in the same horizontal column as the first memory cell M13) is also turned on in response to the voltage of the third word line WL3, so that the second memory cell M23 receives the bias signal from the bias circuit 120 via the second source line SL2. At this time, the second bit line BL2 and the second source line SL2 maintain the same potential through the second memory cell M23.

[0075] If the read / write instruction is "read data", the process proceeds to step S607 to execute the read phase. In step S407, the first bit switch BT1 and the first source switch ST1 are turned on, and all bit switches BT2 to BTn not corresponding to the read target are turned off, so that the first memory unit M13 is turned on in response to the voltage of the third word line W3. In other embodiments, in the read phase, the source switches ST2 to STn not corresponding to the read target are also turned on to receive the bias signal.

[0076] If the read / write instruction is "erase data", the process proceeds to step S408 to execute the erasing phase. In the erasing phase, all source switches ST1-STn are turned on (e.g., the first source switch ST1, the second source switch ST2, ...), so that the corresponding memory cell series are respectively turned on to the bias circuit 120 to receive the bias signal. In other embodiments, in the erasing phase, all bit switches ST1-STn are also turned on (e.g., the first bit switch ST1, the second bit switch ST2, ...), so that the corresponding memory cell series are respectively turned on to the memory operation circuit 110. Accordingly, since the memory operation circuit 110 and the bias circuit 120 each apply a voltage to the memory cell array A, the speed of data erasing can be increased.

[0077] Please refer to Figures 5A and 5B. Figure 5A FIG. 4 is a schematic diagram of potentials in a memory cell string corresponding to a write target. Figure 5B FIG. 1 is a schematic diagram of the potential in a memory cell string that does not correspond to the write target. Figure 5A As shown in FIG. 1 , when the word line has an enable signal so that the word line potential Vwl is high, the bit line potential Vbl and the source line potential Vsl corresponding to the write target remain the same. Similarly, Figure 5B As shown, the bit line potential Vbl and the source line potential Vsl not corresponding to the write target also remain the same.

[0078] The various elements, method steps or technical features in the aforementioned embodiments may be combined with each other and are not limited to the order of textual description or the order of presentation of the drawings in the present invention.

[0079] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A non-volatile memory comprising: a memory cell array comprising a plurality of memory cell strings; A plurality of bit switches electrically connect the memory cell series; a memory operation circuit electrically connected to the bit switches and used to transmit a write signal to the memory cell array via the bit switches during a write phase; and A plurality of source switches electrically connected to the memory cell strings, wherein at least one of the memory cell strings is used to receive a bias signal via at least one of the source switches; During the write phase, when a first bit switch among the bit switches is turned on so that a first memory cell string among the memory cell strings receives the write signal via the first bit switch, the source switches electrically connected to other memory cell strings among the memory cell strings will be turned on, and the other memory strings are configured to be disabled by the bias signal through at least one of the plurality of source switches so as to maintain the same potential through the bias signal.

2. The nonvolatile memory according to claim 1 , wherein in the write phase, when the first bit switch among the bit switches is turned on so that the first memory cell string among the memory cell strings receives the write signal, a first source switch among the source switches electrically connected to the first memory cell string is turned off; and During the writing phase, a first memory cell in the first memory cell string is turned on in response to a voltage of a word line, so that a first bit line and a first source line in the first memory cell string maintain the same potential through the first memory cell.

3. The nonvolatile memory according to claim 1 , wherein during the write phase, when the first bit switch among the bit switches is turned on so that the first memory cell string among the memory cell strings receives the write signal, the bit switches electrically connected to the other memory cell strings among the memory cell strings are turned off.

4. The nonvolatile memory according to claim 3, wherein during the write phase, a second bit switch corresponding to a second memory cell string among the memory cell strings is turned off, and a second source switch corresponding to the second memory cell string among the memory cell strings is turned on, so that the second memory cell string receives the bias signal via the second source switch; and a second memory cell in the second memory cell string is turned on in response to a voltage of a word line, so that a second bit line and a second source line in the second memory cell string are maintained at the same potential through the second memory cell.

5. The nonvolatile memory according to claim 1, wherein the memory operation circuit further comprises: a cache circuit for receiving the write signal; a buffer circuit electrically connected to the cache circuit; and An amplifier circuit is electrically connected to the buffer circuit and is used for receiving the write signal through the buffer circuit, wherein the memory cell series are electrically connected to the same input and output end of the amplifier circuit.

6. A method for operating a non-volatile memory, comprising: In a writing phase, a first bit switch is turned on so that a writing signal is input to a first memory cell in a first memory cell series via the first bit switch and a first bit line; Turning off a first source switch so that a circuit is formed between the first memory cell series and a bias circuit, and the first bit line and a first source line in the first memory cell series are maintained at the same potential through the first memory cell; In the writing phase, a second bit switch is turned off to form a disconnection between a second bit line of a second memory cell series and a memory operation circuit; and A second source switch is turned on so that a second memory cell in the second memory cell series receives a bias signal from the bias circuit via a second source line, and the second bit line and the second source line maintain the same potential through the second memory cell.

7. The method for operating a non-volatile memory according to claim 6, further comprising: In an elimination phase, the first source switch and the second source switch are turned on, so that the first memory cell series and the second memory cell series are respectively turned on to the bias circuit; and In the elimination phase, the first bit switch and the second bit switch are turned on, so that the first memory cell series and the second memory cell series are respectively connected to the memory operation circuit.

8. A non-volatile memory comprising: a memory cell array comprising a plurality of memory cell strings; A plurality of bit switches electrically connect the memory cell series; a memory operation circuit electrically connected to the bit switches and used to transmit a write signal to the memory cell array via the bit switches during a write phase; and A plurality of source switches electrically connected to the memory cell strings, wherein at least one of the memory cell strings is used to receive a bias signal via at least one of the source switches; During the write phase, when a first bit switch among the bit switches is turned on so that a first memory cell string among the memory cell strings receives the write signal, a first source switch among the source switches electrically connected to the first memory cell string will be turned off, and the source switches electrically connected to other memory cell strings among the memory cell strings will be turned on, and the other memory strings are configured to be disabled by a bias signal through at least one of the plurality of source switches so as to maintain the same potential through the bias signal.

9. The nonvolatile memory according to claim 8, wherein the first memory cell series further comprises: a plurality of first memory cells; a first bit line electrically connected to the memory operation circuit through the first bit switch; and a first source line electrically connected to a bias circuit through the first source switch; During the writing phase, one of the first memory cells is turned on in response to a voltage of a word line, so that the first bit line and the first source line maintain the same potential through the first memory cell.

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