Semiconductor memory device and method of operating a semiconductor memory device

Abstract

A semiconductor memory device includes an ECC circuit; an error information register; a scrub control circuit to count refresh row addresses and to output a scrub address of a scrub operation to be performed on at least one sub-page in a first memory cell row each time N refresh row addresses are counted; and control logic circuitry configured to: control the ECC circuit to sequentially read data corresponding to a first codeword, perform error detection on the first codeword, and provide error information based on the error detection, the error information indicating a count of errors in the first codeword; and record the error information in the error information register and selectively determine whether to write back a corrected first codeword to a memory location in which data corresponding to the first codeword is stored based on the error information.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0002000, filed on January 7, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The apparatus and methods consistent with the example embodiments relate to memory, and more specifically to semiconductor memory devices and methods of operating semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices can be classified into non-volatile memory devices (e.g., flash memory devices) and volatile memory devices (e.g., DRAM). The high-speed operation and cost efficiency of DRAM make it suitable for use as system memory. However, due to persistent size constraints in DRAM manufacturing design rules, bit errors in memory cells within DRAM can increase rapidly, and DRAM yields can decrease. Therefore, there is a need for improved reliability in semiconductor memory devices. Summary of the Invention

[0005] One or more example embodiments provide a semiconductor memory device with increased reliability and performance.

[0006] One or more example embodiments provide a method for operating a semiconductor memory device with increased reliability and performance.

[0007] According to an example embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory cell rows, each memory cell row including volatile memory cells; an error correction code (ECC) circuit; an error information register; a scrubbing control circuit configured to count refresh row addresses and output a scrubbing address whenever the scrubbing control circuit counts N refresh row addresses to control a scrubbing operation to be performed on at least one subpage in a first memory cell row of the plurality of memory cell rows, where N is an integer greater than 2; and control logic circuitry configured to: control the ECC circuitry to sequentially read data corresponding to a first codeword from M subpages in the first memory cell row, perform error detection on the first codeword, and provide error information based on the error detection, the error information indicating an error occurrence count in the first codeword, where M is an integer greater than 1; and record the error information in the error information register, and selectively determine, based on the error information, whether to write back the corrected first codeword to a memory location storing data corresponding to the first codeword.

[0008] According to an example embodiment, a method for operating a semiconductor memory device including a memory cell array comprising a plurality of memory cell rows, each memory cell row comprising a plurality of volatile memory cells, the method comprising: sequentially generating a first address based on a first command received from an external device; sequentially performing refresh operations on the plurality of memory cell rows based on the first address; selecting a first memory cell row corresponding to a second address from the plurality of memory cell rows each time N refresh operations are performed, where N is an integer greater than 2, the second address being generated in the semiconductor memory device; performing M ECC decoding operations on a codeword in the first memory cell row to detect error bits in an error correction code (ECC) circuit of the semiconductor memory device, where M is an integer greater than 1; generating a corrected codeword based on a codeword including correctable error bits in the ECC circuit; and writing the corrected codeword back to a memory location corresponding to the codeword including the correctable error bits.

[0009] According to an example embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory cell rows, each memory cell row including volatile memory cells; an error correction code (ECC) circuit; an error information register; a refresh control circuit configured to generate a refresh row address indicating a memory cell row based on a first command received from an external device; a flush control circuit configured to count refresh row addresses and output a flush address whenever the flush control circuit counts N refresh row addresses to control a flush operation to be performed on at least one subpage in a first memory cell row of the plurality of memory cell rows, where N is an integer greater than 2; and control logic circuit configured to: control the ECC circuit to sequentially read data corresponding to a first codeword from M subpages in the first memory cell row, perform error detection on the first codeword, and provide error information based on the error detection, the error information indicating an error occurrence count in the first codeword, where M is an integer greater than 1; and record the error information in the error information register and selectively determine, based on the error information, whether to write back the corrected first codeword to a memory location storing data corresponding to the first codeword. Attached Figure Description

[0010] The above and other aspects and features will become more apparent from the detailed description of the exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating a memory system according to an example embodiment.

[0012] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of a semiconductor memory device.

[0013] Figure 3 Show Figure 2 An example of a first bank array in a semiconductor memory device.

[0014] Figure 4 This illustrates an example embodiment. Figure 2 A block diagram of the refresh control circuit in a semiconductor memory device.

[0015] Figure 5 This illustrates an example embodiment. Figure 4 The circuit diagram shown is an example of a refresh clock generator.

[0016] Figure 6 This illustrates an example embodiment. Figure 4 A circuit diagram of another example of a refresh clock generator.

[0017] Figure 7 This illustrates an example embodiment. Figure 2 A block diagram of an example scrubbing control circuit in a semiconductor memory device.

[0018] Figure 8 This illustrates an example embodiment. Figure 7 Block diagram of the brushing address generator in the brushing control circuit.

[0019] Figure 9 This illustrates an example embodiment. Figure 1 A block diagram of another example of a semiconductor memory device.

[0020] Figure 10 This is a circuit diagram illustrating interference between memory cells in a semiconductor memory device.

[0021] Figure 11 This illustrates an example embodiment. Figure 9 A block diagram of an example of a victim address detector in a semiconductor memory device.

[0022] Figure 12 It is shown Figure 11 A block diagram of the interference detector in the address detector of the interfered object.

[0023] Figure 13 This illustrates an example embodiment. Figure 9 A block diagram of an example of a brush control circuit in a semiconductor memory device.

[0024] Figure 14 This illustrates an example embodiment. Figure 13 Block diagram of the brushing address generator in the brushing control circuit.

[0025] Figure 15 The example embodiment is shown in Figure 13 The weak codeword address generator in the brushing control circuit.

[0026] Figure 16 Shown during write operation Figure 2 It is part of a semiconductor memory device.

[0027] Figure 17 This is shown in refresh or read operations. Figure 2 It is part of a semiconductor memory device.

[0028] Figure 18 Showing according to an example embodiment Figure 2 Error information register in semiconductor memory devices.

[0029] Figure 19 This illustrates an example embodiment. Figure 2 A block diagram of an example ECC circuit in a semiconductor memory device.

[0030] Figure 20 Showing according to an example embodiment Figure 19 An example of an ECC encoder in an ECC circuit.

[0031] Figure 21 Showing according to an example embodiment Figure 19 An example of an ECC decoder in an ECC circuit.

[0032] Figure 22 Showing according to an example embodiment Figure 21 The operation of the ECC decoder.

[0033] Figure 23 Shown in Figure 2 Normal refresh and flush operations performed in semiconductor memory devices.

[0034] Figure 24 Shown in Figure 2 Refresh and flush operations performed in semiconductor memory devices.

[0035] Figure 25 Show Figure 23 or Figure 24 The timing of the scrubbing operation.

[0036] Figure 26 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0037] Figure 27 This is a flowchart illustrating a method for using a semiconductor memory device according to an example embodiment.

[0038] Figure 28 This is a diagram illustrating a semiconductor package including a stacked memory device according to an example embodiment. Detailed Implementation

[0039] Example embodiments will be described more fully below with reference to the accompanying drawings.

[0040] Figure 1 This is a block diagram illustrating a memory system according to an example embodiment.

[0041] refer to Figure 1 The memory system 20 may include a memory controller 100 and a semiconductor memory device 200.

[0042] The memory controller 100 can control the overall operation of the memory system 20. The memory controller 100 can control the overall data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 100 can write data to or read data from the semiconductor memory device 200 in response to a request from the host.

[0043] In addition, the memory controller 100 can issue operation commands to the semiconductor memory device 200 to control the semiconductor memory device 200.

[0044] In some example embodiments, the semiconductor memory device 200 is a memory device that includes dynamic memory cells, such as dynamic random access memory (DRAM), double data rate 4 (DDR4) synchronous DRAM (SDRAM), double data rate 5 (DDR5) SDRAM, low power DDR4 (LPDDR4) SDRAM, low power DDR5 (LPDDR5) SDRAM, or low power DDR6 (LPDDR6) DRAM.

[0045] The memory controller 100 sends the clock signal CLK, command CMD and address (signal) ADDR to the semiconductor memory device 200 and exchanges master data MD with the semiconductor memory device 200.

[0046] The semiconductor memory device 200 includes a memory cell array 300 for storing master data MD and parity data, an error correction code (ECC) circuit 400, a control logic circuit 210, a flush control circuit 500, and an error information register 580.

[0047] Under the control of the control logic circuit 210, the ECC circuit 400 can perform ECC encoding on the write data to be stored in the target page of the memory cell array 300, and can perform ECC decoding on the codewords read from the target page.

[0048] The flush control circuit 500 can generate a flush address such that when performing a refresh operation on multiple memory cell rows included in the memory cell array 300, a flush operation is performed on the first memory cell row among the multiple memory cell rows whenever a refresh operation is performed on N memory cell rows. Here, N is a natural number greater than 2. That is, the flush control circuit 500 can generate a flush address such that a flush operation is performed on the first memory cell row whenever the erase control circuit counts N refresh row addresses. The control logic circuit 210 can control the ECC circuit 400 such that the ECC circuit 400 sequentially reads data corresponding to the first codeword from the M subpages specified by the flush address in the first memory cell row, and in response to detecting an error in the first codeword, performs error detection on each of the first codewords read from the M subpages to generate an error generation signal. For example, refresh operations can be performed sequentially on multiple memory cell rows, and after N rows have been refreshed, the flush control circuit 500 can generate a flush address such that a flush operation is performed on the first memory cell row. Subsequently, as the refresh operation continues and another N rows have been refreshed, the flush control circuit 500 can generate a flush address, causing a flush operation to be performed on the first memory cell row among the multiple memory cell rows. For example, if N=5, then when the refresh operation is performed sequentially on 100 memory cell rows, the flush operation is performed 20 times.

[0049] Control logic circuit 210 records error information in error information register 580 and selectively determines whether to write back the corrected first codeword to the memory location where data is stored based on the error information. The error information includes an error count in the first codeword. Control logic circuit 210 can control ECC circuit 400 based on the error information, causing ECC circuit 400 to write back the corrected first codeword to the memory location in response to the first codeword including correctable error bits to be corrected by ECC circuit 400. In an example embodiment, control logic circuit 210 controls error information register 580 to provide error information as an error information signal EIS to memory controller 100.

[0050] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of a semiconductor memory device.

[0051] refer to Figure 2The semiconductor memory device 200 includes control logic circuitry 210, address register 220, memory bank control logic 230, refresh control circuitry 385, row address multiplexer 240, column address latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, I / O gating circuitry 290, ECC circuitry 400, flush control circuitry 500, and data I / O buffer 295.

[0052] The memory cell array 300 includes first to eighth memory cell arrays 310 to 380. The row decoder 260 includes first to eighth memory cell row decoders 260a to 260h coupled to the first to eighth memory cell arrays 310 to 380 respectively, the column decoder 270 includes first to eighth memory cell column decoders 270a to 270h coupled to the first to eighth memory cell arrays 310 to 380 respectively, and the sense amplifier unit 285 includes first to eighth memory cell sense amplifiers 285a to 285h coupled to the first to eighth memory cell arrays 310 to 380 respectively.

[0053] The first to eighth memory bank arrays 310 to 380, the first to eighth memory bank row decoders 260a to 260h, the first to eighth memory bank column decoders 270a to 270h, and the first to eighth memory bank sense amplifiers 285a to 285h can form the first to eighth memory banks. Each of the first to eighth memory bank arrays 310 to 380 includes multiple memory cells MC formed at the intersection of multiple word lines WL and multiple bit lines BTL.

[0054] Address register 220 receives address ADDR from memory controller 100, which includes bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR. Address register 220 provides the received bank address BANK_ADDR to bank control logic 230, the received row address ROW_ADDR to row address multiplexer 240, and the received column address COL_ADDR to column address latch 250.

[0055] The memory bank control logic 230 generates a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, one of the first to eighth memory bank row decoders 260a to 260h corresponding to the memory bank address BANK_ADDR is activated, and in response to the memory bank control signal, one of the first to eighth memory bank column decoders 270a to 270h corresponding to the memory bank address BANK_ADDR is activated.

[0056] The row address multiplexer 240 receives the row address ROW_ADDR from the address register 220 and the refresh row address REF_ADDR from the refresh control circuit 385. The row address multiplexer 240 selectively outputs either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 is applied to the row decoders 260a to 260h of the first to eighth memory banks.

[0057] The refresh control circuit 385 can sequentially change and output the refresh row address REF_ADDR in response to the first refresh control signal IREF1 or the second refresh control signal IREF2 from the control logic circuit 210.

[0058] When the command CMD from the memory controller 100 corresponds to an auto-refresh command, the control logic circuit 210, upon receiving the auto-refresh command, can apply a first refresh control signal IREF1 to the refresh control circuit 385. When the command CMD from the memory controller 100 corresponds to a self-refresh enter command, the control logic circuit 210 can apply a second refresh control signal IREF2 to the refresh control circuit 385, and the second refresh control signal IREF2 can be activated from the time the control logic circuit 210 receives the self-refresh enter command to the time the control logic circuit 210 receives the self-refresh exit command. The refresh control circuit 385 can sequentially increment or decrement the refresh row address REF_ADDR in response to receiving the first refresh control signal IREF1 or upon activating the second refresh control signal IREF2.

[0059] One of the first to eighth memory bank row decoders 260a to 260h, activated by the memory bank control logic 230, decodes the row address RA output from the row address multiplexer 240 and activates the word line corresponding to the row address RA. For example, the activated memory bank row decoder applies a word line drive voltage to the word line corresponding to the row address RA.

[0060] Column address latch 250 receives column address COL_ADDR from address register 220 and temporarily stores the received column address COL_ADDR. In some embodiments, in burst mode, column address latch 250 generates a column address that increments from the received column address COL_ADDR. Column address latch 250 applies the temporarily stored or generated column address to the first to eighth memory bank column decoders 270a to 270h.

[0061] One of the first to eighth memory bank column decoders 270a to 270h is activated via I / O gate circuit 290, which activates a sense amplifier corresponding to the memory bank address BANK_ADDR and the column address COL_ADDR.

[0062] I / O gating circuit 290 includes circuitry for gating input / output data, and further includes input data masking logic, a read data latch for storing data output from the first to eighth memory bank arrays 310 to 380, and a write driver for writing data to the first to eighth memory bank arrays 310 to 380.

[0063] A codeword CW read from one of the memory arrays 310-380 (first to eighth) is sensed by a sense amplifier coupled to the memory array from which data is to be read and stored in a read data latch. After ECC decoding of the codeword CW by the ECC circuit 400, the codeword CW stored in the read data latch can be provided to the memory controller 100 via the data I / O buffer 295.

[0064] The master data MD to be written to one of the first to eighth memory bank arrays 310-380 can be provided from the memory controller 100 to the data I / O buffer 295. The ECC circuit 400 can perform ECC encoding on the master data MD to generate parity data. The ECC circuit 400 can provide the master data MD and the parity data to the I / O gating circuit 290, and the I / O gating circuit 290 can write the master data MD and the parity data to a subpage of a target page in a memory bank array through a write driver.

[0065] The data I / O buffer 295 can provide the master data MD from the memory controller 100 to the ECC circuit 400 during the write operation of the semiconductor memory device 200 based on the clock signal CLK, and can also provide the master data MD from the ECC circuit 400 to the memory controller 100 during the read operation of the semiconductor memory device 200.

[0066] ECC circuit 400 performs ECC decoding on codewords read from subpages of the target page, and can provide an error generation signal EGS to control logic circuit 210 when correcting at least one error bit detected in the main data of the codeword.

[0067] As the refresh row address REF_ADDR changes sequentially, the flush control circuit 500 can count the changes. Whenever the flush control circuit 500 counts N refresh row addresses, it can output a normal flush address SCADDR. The normal flush address SCADDR can include a flush row address SRA and a flush column address SCA. The flush control circuit 500 can provide the flush row address SRA and the flush column address SCA to the row decoder 260 and the column decoder 270.

[0068] Control logic circuitry 210 can control the operation of semiconductor memory device 200. For example, control logic circuitry 210 can generate control signals for semiconductor memory device 200 to perform write or read operations. Control logic circuitry 210 includes: command decoder 211, which decodes commands CMD received from memory controller 100; and mode register 212, which sets the operating mode of semiconductor memory device 200.

[0069] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding write enable signals, row address strobe signals, column address strobe signals, chip select signals, etc. The control logic circuit 210 can generate a first control signal CTL1 for controlling the I / O gate circuit 290, a second control signal CTL2 for controlling the ECC circuit 400, and a third control signal CTL3 for controlling the flush control circuit 500. Furthermore, the control logic circuit 210 can provide the refresh control circuit 385 with a mode signal MS associated with the refresh period. The control logic circuit 210 can generate the mode signal MS based on a temperature signal representing the operating temperature of the semiconductor memory device 200.

[0070] Figure 3 Show Figure 2 An example of a first bank array in a semiconductor memory device.

[0071] refer to Figure 3 The first memory bank array 310 includes multiple word lines WL1 to WLm (m is a natural number greater than 2), multiple bit lines BTL1 to BTLn (n is a natural number greater than 2), and multiple volatile memory cells MC disposed at the intersections between the word lines WL1 to WLm and the bit lines BTL1 to BTLn. Each memory cell MC includes a unit transistor coupled to each of the word lines WL1 to WLm and each of the bit lines BTL1 to BTLn, and a unit capacitor coupled to that unit transistor.

[0072] Figure 4 This illustrates an example embodiment. Figure 2 A block diagram of the refresh control circuit in a semiconductor memory device.

[0073] refer to Figure 4 The refresh control circuit 385 may include a refresh clock generator 390 and a refresh counter 397.

[0074] The refresh clock generator 390 can generate a refresh clock signal RCK in response to a first refresh control signal IREF1, a second refresh control signal IREF2, and a mode signal MS. The mode signal MS can determine the refresh period of the refresh operation. As described above, the refresh clock generator 390 can generate the refresh clock signal RCK whenever it receives the first refresh control signal IREF1 or when the second refresh control signal IREF2 is activated.

[0075] The refresh counter 397 can generate refresh row addresses REF_ADDR that sequentially specify memory cell rows by performing a counting operation during the refresh clock signal RCK.

[0076] Figure 5 This illustrates an example embodiment. Figure 4 The circuit diagram shown is an example of a refresh clock generator.

[0077] refer to Figure 5 The refresh clock generator 390a may include multiple oscillators 391, 392, and 393, a multiplexer 394, and a decoder 395a. The decoder 395a decodes the first refresh control signal IREF1, the second refresh control signal IREF2, and the mode signal MS to output a clock control signal RCS1. The oscillators 391, 392, and 393 generate refresh clock signals RCK1, RCK2, and RCK3 with different time intervals. The multiplexer 394, in response to the clock control signal RCS1, selects one of the refresh clock signals RCK1, RCK2, and RCK3 to provide the refresh clock signal RCK.

[0078] Figure 6 This illustrates an example embodiment. Figure 4 A circuit diagram of another example of a refresh clock generator.

[0079] refer to Figure 6 The refresh clock generator 390b may include a decoder 395b, a bias unit 396a, and an oscillator 396b. The decoder 395b decodes the first refresh control signal IREF1, the second refresh control signal IREF2, and the mode signal MS to output a clock control signal RCS2. The bias unit 396a generates a control voltage VCON in response to the clock control signal RCS2. The oscillator 396b generates a refresh pulse signal RCK with a variable time interval based on the control voltage VCON.

[0080] Figure 7 This illustrates an example embodiment. Figure 2 A block diagram of an example of a brush control circuit in a semiconductor memory device.

[0081] refer to Figure 7The brushing control circuit 500 may include a counter 505 and a brushing address generator 510.

[0082] Counter 505 counts the refresh row address REF_ADDR, and when counter 505 has counted the refresh row address REF_ADDR a number of times specified by the count control signal CCS, it generates an internal flush signal ISRB, which is activated during a first interval. The first interval may correspond to the time interval used to refresh one memory cell row. For example, counter 505 may start counting whenever the refresh row address REF_ADDR is provided or changes as refresh operations are performed sequentially.

[0083] The flush address generator 510 responds to the internal flush signal ISRB to generate a normal flush address SCADDR associated with a normal flush operation for each codeword in a memory cell row, which gradually changes in the first flush mode.

[0084] A normal flush address SCADDR includes a flush row address (SRA) and a flush column address (SCA). The flush row address (SRA) specifies a page in a memory array, and the flush column address (SCA) specifies one of the codewords in that page. The flush address generator 510 provides the flush row address (SRA) to the corresponding row decoder and the flush column address (SCA) to the corresponding column decoder.

[0085] Since a flushing operation based on the normal flushing address SCADDR is performed on all codewords included in the memory cell array 300, the flushing operation based on the normal flushing address SCADDR can be called a normal flushing operation.

[0086] Figure 8 This illustrates an example embodiment. Figure 7 Block diagram of the brushing address generator in the brushing control circuit.

[0087] refer to Figure 8 The flush address generator 510 may include a page segment counter 511 and a row counter 513.

[0088] Page segment counter 511 increments the flush column address SCA by one when the internal flush signal ISRB is activated, and activates the maximum address detection signal MADT, resetting it whenever the flush column address SCA reaches its maximum value. Page segment counter 511 provides the maximum address detection signal MADT to row counter 513.

[0089] Row counter 513 begins counting when the internal flush signal ISRB is initially received, and increments the flush row address SRA by one each time the active maximum address detection signal MADT is received. Because the internal flush signal ISRB is activated during the first interval when a refresh operation is performed on a memory cell row, page segment counter 511 can generate the flush column address SCA associated with the codeword in a page during the first interval.

[0090] Figure 9 This illustrates an example embodiment. Figure 1 A block diagram of another example of a semiconductor memory device.

[0091] Figure 9 Semiconductor memory device 200a and Figure 2 The difference between the semiconductor memory device 200 and the semiconductor memory device 200a is that the semiconductor memory device 200a also includes an interference object address detector 560, and the brush control circuit 500a outputs the weak codeword address WCADDR in the second brush mode.

[0092] refer to Figure 9 The control logic circuit 210a can further generate a fourth control signal CTL 4 for controlling the address detector 560 of the interfered object.

[0093] The interfered object address detector 560 can count the number of accesses to a first memory region in the memory cell array 300, and generate at least one interfered object address VCT_ADDR specifying at least one neighboring memory region adjacent to the first memory region when the number of accesses counted during a reference interval reaches a reference number. The interfered object address VCT_ADDR can be stored in the address memory table of the flush control circuit 500a.

[0094] The scrubbing control circuit 500a can provide the scrubbing row address SRA and the scrubbing column address SCA to the row decoder 260 and column decoder 270 respectively in the first scrubbing mode. In the second scrubbing mode, the scrubbing control circuit 500a can output the address of the codeword associated with the address VCT_ADDR of the interfered object stored in the address storage table as the weak codeword address WCADDR. The weak codeword address WCADDR may include the weak codeword row address WCRA and the weak codeword column address WCCA. The scrubbing control circuit 500a can provide the weak codeword row address WCRA and the weak codeword column address WCCA to the row decoder 260 and column decoder 270 respectively in the second scrubbing mode.

[0095] Figure 10 This is a circuit diagram illustrating interference between memory cells in a semiconductor memory device.

[0096] refer to Figure 10 A portion of the semiconductor memory device 200a includes memory cells 51, 52 and 53, and a bit line sense amplifier 60.

[0097] Assume that each of memory cells 51, 52, and 53 is connected to the same bit line BTL. Additionally, memory cell 51 is connected to the word line WL. <g-1>Memory cell 52 is connected to word line WL <g>And memory cell 53 is connected to word line WL<g+1> .like Figure 10 As shown, the word line WL <g-1>and WL<g+1> Positioned as WL (with word line) <g>Adjacent to each other. Memory cell 51 includes an access transistor CT1 and a cell capacitor CC1. The gate terminal of the access transistor CT1 is connected to the word line WL. <g-1>Memory cell 52 includes an access transistor CT2 and a cell capacitor CC2. The gate terminal of access transistor CT2 is connected to word line WL. <g>Furthermore, one of its terminals is connected to the bit line BTL. Also, memory cell 53 includes an access transistor CT3 and a cell capacitor CC3. The gate terminal of the access transistor CT3 is connected to the word line WL.<g+1> And one of its terminals is connected to the bit line BTL.

[0098] Bit line sense amplifier 60 may include: an N sense amplifier that discharges low-level bit lines in bit lines BTL and BTLB; and a P sense amplifier that charges high-level bit lines in bit lines BTL and BTLB.

[0099] During a refresh operation, the bit line sense amplifier 60 rewrites the data stored by the N-sensor amplifier or the P-sensor amplifier to the selected memory cell. During a read or write operation, a selection voltage (e.g., Vpp) is supplied to the word line WL. <g>Then, due to capacitive coupling, even without applying a selection voltage, the adjacent word line WL... <g-1>and WL<g+1> The voltage also increases. This capacitive coupling is indicated by parasitic capacitances CcI1 and CcI2.

[0100] Without performing a refresh operation and repeatedly accessing the word line WL <g>At that time, it is stored connected to the word line WL <g-1>and WL<g+1> The charge in the cell capacitors CC1 and CC3 of memory cells 51 and 53 may gradually leak. In this case, the reliability of logic "0" stored in cell capacitor CC1 and logic "1" stored in cell capacitor CC3 may not be guaranteed. Therefore, it is necessary to perform a flushing operation on the memory cells at appropriate times.

[0101] Figure 11 This illustrates an example embodiment. Figure 9 A block diagram of an example of an address detector for a disturbed object in a semiconductor memory device.

[0102] refer to Figure 11 The interference object address detector 560 may include an interference detector 570 and an interference object address generator 577.

[0103] Interference detector 570 can count the number of accesses to a first memory region (i.e., at least one memory cell row) based on row address ROW_ADDR, and generate a first detection signal DET1 when the number of accesses counted during a reference (or predetermined) interval reaches a reference value.

[0104] The interfered object address generator 577 can generate at least one interfered object address, VCT_ADDR1, and VCT_ADDR2 in response to the first detection signal DET1. The at least one interfered object address, VCT_ADDR1, and VCT_ADDR2 can be row addresses specifying a second memory region and a third memory region located adjacent to the first memory region. The interfered object address generator 577 can provide at least one interfered object address, VCT_ADDR1, and VCT_ADDR2, to the address storage table in the flush control circuit 500a.

[0105] Figure 12 It is shown Figure 11 A block diagram of the interference detector in the address detector of the interfered object.

[0106] refer to Figure 12 The interference detector 570 may include an access counter 571, a threshold register 573, and a comparator 575.

[0107] Access counter 571 can count the number of accesses to a specified address (or a specified memory region) based on the row address ROW_ADDR. For example, access counter 571 can count the number of accesses to a specified word line. Accesses can be counted for a specific word line or a group of word lines comprising at least two word lines. Moreover, the counting of accesses can be performed through a specific block cell, memory bank cell, or chip cell.

[0108] Threshold register 573 can store a maximum interference occurrence count, which ensures the reliability of data in a specific word line or memory cell. For example, a threshold (or reference value) for a word line can be stored in threshold register 573. Alternatively, a threshold for a group of word lines, a block, a memory cell, or a chip cell can be stored in threshold register 573.

[0109] Comparator 575 compares a reference value stored in threshold register 573 with the number of accesses to a specific memory region counted by access counter 571. If a memory region exists with the counted accesses reaching the reference value, comparator 575 generates a first detection signal DET1. Comparator 575 provides the first detection signal DET1 to the interference target address generator 577.

[0110] Figure 13 This illustrates an example embodiment. Figure 9 A block diagram of an example of a brush control circuit in a semiconductor memory device.

[0111] refer to Figure 13 The brushing control circuit 500a may include a counter 505, a brushing address generator 510a, and a weak code word address generator 520a.

[0112] Operation of counter 505 and flush address generator 510a Figure 4 The operation of the counter and the flush address generator 510a is basically similar. The flush address generator 510a also receives the flush mode signal SMS and generates the normal flush address SCADDR in the first flush mode.

[0113] The weak codeword address generator 520a, in response to the internal flush signal ISRB and the flush mode signal SMS, generates a weak codeword address WCADDR associated with a weak flush operation related to a weak codeword in the same memory array in a second flush mode. The weak codeword address WCADDR includes a weak codeword row address WCRA and a weak codeword column address WCCA. When the flush mode signal SMS has a first logic level, it indicates a first flush mode; when it has a second logic level, it indicates a second flush mode. The flush mode signal SMS may be included in a third control signal CTL3. The weak codeword address generator 520a provides the weak codeword row address WCRA to the corresponding row decoder and the weak codeword column address SCA to the corresponding column decoder.

[0114] The weak codeword address generator 520a may include an address storage table, which may store the addresses of codewords associated with the address VCT_ADDR of the target object. Since a swiping operation is performed on the weak codewords, the swiping operation performed based on the weak codeword address WCADDR can be called a target swiping operation.

[0115] Figure 14 This illustrates an example embodiment. Figure 13 Block diagram of the brushing address generator in the brushing control circuit.

[0116] refer to Figure 14 The flush address generator 510a may include a page segment counter 511a and a row counter 513a.

[0117] In response to the internal flush signal ISRB and the flush mode signal SMS, the page segment counter 511a increments the flush column address SCA by one when the internal flush signal ISRB is activated in the first flush mode, and activates the maximum address detection signal MADT, which is reset whenever the flush column address SCA reaches its maximum value. The page segment counter 511a provides the maximum address detection signal MADT to the row counter 513a.

[0118] In response to the internal scrub signal ISRB and the scrub mode signal SMS, the row counter 513a starts counting when it initially receives the internal scrub signal ISRB, and increments the scrub row address SRA by one whenever it receives the active maximum address detection signal MADT.

[0119] Figure 15 The example embodiment is shown in Figure 13 The weak codeword address generator in the brushing control circuit.

[0120] refer to Figure 15 The weak codeword address generator 520a may include a table pointer 521, an address storage table 530, and a sensing unit 540.

[0121] Address storage table 530 stores the address information WCRA1~WCRAs and WCCA1~WCCAt (t is a positive integer greater than s) of weak codewords included in memory cell array 300.

[0122] A weak codeword can be all or part of a weak page in the memory bank array of a memory cell array, containing a number of error bits greater than a reference value. Additionally, a weak codeword can be the codeword of an adjacent page near a densely accessed memory region.

[0123] The pointer 521 can generate a pointer signal TPS providing position information for the address storage table 530 in response to the internal flush signal ISRB and the flush mode signal SMS during a first interval in a second flush mode, and provide the pointer signal TPS to the address storage table 530. The address storage table 530 may include a non-volatile storage device. Figure 11 At least one of the interference object addresses VCT_ADDR1 and VCT_ADDR2 provided by the interference object address generator 577 can be stored in the address storage table 530.

[0124] The pointer signal TPS gradually increases a predetermined number of times during the first interval, and each time the pointer signal TPS is applied, the address storage table 530 can output the weak codeword address stored at a certain location (indicated by the pointer signal TPS) as the weak codeword row address WCRA and the weak codeword column address WCCA through the sensing unit 540 in response to the pointer signal TPS. The sensing unit 540 provides the weak codeword row address WCRA to the corresponding row decoder and the weak codeword column address WCCA to the corresponding column decoder.

[0125] The control logic circuit 210a can apply different refresh periods to some memory cell rows based on the number of error bits detected in each memory cell row through the flushing operation.

[0126] Figure 16 Shown during write operation Figure 2 It is part of a semiconductor memory device.

[0127] exist Figure 16 The diagram shows a control logic circuit 210, a first memory array 310, an I / O gate circuit 290, and an ECC circuit 400.

[0128] refer to Figure 16 The first memory bank array 310 includes a normal cell array (NCA) and a redundant cell array (RCA). The normal cell array (NCA) includes multiple first memory blocks MB0 to MB15, i.e., 311 to 313, and the redundant cell array (RCA) includes at least a second memory block 314. The first memory blocks 311 to 313 are memory blocks that determine the memory capacity of the semiconductor memory device 200. The second memory block 314 is used for ECC and / or redundancy repair. Because the second memory block 314 used for ECC and / or redundancy repair is used for ECC, data line repair, and block repair to repair "failed" cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block. In each of the first memory blocks 311 to 313, multiple first memory cells are arranged in rows and columns. In the second memory block 314, multiple second memory cells are arranged in rows and columns. The first memory cells connected to the intersection of the word line WL and the bit line BTL can be dynamic memory cells. The second memory cell connected to the intersection of word line WL and bit line RBTL can be a dynamic memory cell.

[0129] I / O gating circuitry 290 includes a plurality of switching circuits 291a-291d respectively connected to the first memory blocks 311-313 and the second memory block 314. In semiconductor memory device 200, bit lines corresponding to burst length (BL) data can be accessed simultaneously to support BL, which indicates the maximum number of accessible column locations. For example, BL can be set to 8.

[0130] The ECC circuit 400 can be connected to the switching circuits 291a to 291d via the first data line GIO and the second data line EDBIO. The control logic circuit 210 can receive the command CMD and the address ADDR, and can decode the command CMD to generate a first control signal CTL1 for controlling the switching circuits 291a to 291d and a second control signal CTL2 for controlling the ECC circuit 400.

[0131] When the command CMD is a write command, the control logic circuit 210 provides the second control signal CTL2 to the ECC circuit 400, and the ECC circuit 400 performs ECC encoding on the master data MD to generate a parity bit associated with the master data MD, and provides the codeword CW, which includes the master data MD and the parity bit, to the I / O gating circuit 290. The control logic circuit 210 provides the first control signal CTL1 to the I / O gating circuit 290, so that the codeword CW will be stored in a subpage of the target page in the first memory array 310.

[0132] Figure 17 This is shown in refresh or read operations. Figure 2 It is part of a semiconductor memory device.

[0133] refer to Figure 17 When the command CMD is a refresh command (first command) used to specify a refresh operation, the control logic circuit 210 provides the first control signal CTL1 to the I / O gate circuit 290, so that the first (read) codeword RCW in each subpage of the target page stored in the first memory array 310 is provided to the ECC circuit 400.

[0134] During the refresh operation, in response to the detection of an error bit, the ECC circuit 400 performs ECC decoding on the codeword RCW and provides an error generation signal EGS to the control logic circuit 210. The control logic circuit 210 can count the error generation signals EGS for one page and record the error information EINF for one page in the error information register 580. The error information EINF may include: the address of the codeword containing the error bit, the number of codewords containing the error bit, and the address of the page. Additionally, the control logic circuit 210 can record the number of error bits in each codeword RCW in the error information register 580.

[0135] When error detection of codewords in a page is complete, control logic circuit 210 can selectively determine whether to write back the codewords in which erroneous bits were detected based on error information EINF. For example, control logic circuit 210 can control ECC circuit 400 and I / O gate circuit 290 based on error information EINF, such that ECC circuit 400 corrects the erroneous bits in codeword RCW in response to codeword RCW including erroneous bits to be corrected by ECC circuit 400 and writes the corrected codeword back to the memory location. Control logic circuit 210 can control ECC circuit 400 to execute the write-back of the corrected codeword to the memory location after error detection of M codewords is completed.

[0136] For example, control logic circuit 210 can control ECC circuit 400 based on error information EINF, such that ECC circuit 400 writes back the correctable codewords to their respective memory locations in response to the number of correctable codewords in the M codewords being less than K. K is a natural number greater than 2, and each correctable codeword includes error bits to be corrected by ECC circuit 400.

[0137] For example, control logic circuit 210 can control ECC circuit 400 and I / O gate circuit 290 based on error information EINF, such that ECC circuit 400 skips writing back the corrected codeword to the memory location in response to codeword RCW containing error bits that do not need to be corrected by ECC circuit 400. Furthermore, control logic circuit 210 can control ECC circuit 400 based on error information EINF, such that ECC circuit 400 skips writing back the correctable codeword to the corresponding memory location in response to the number of correctable codewords out of M codewords being equal to or greater than K.

[0138] When the command CMD corresponds to a read command, the ECC circuit 400 can provide the corrected master data C_MD to the data I / O buffer 295. In this case, the ECC circuit 400 can perform a selective flush operation to write back the codeword, including the correctable error bits, to the corresponding memory location.

[0139] Therefore, in the flush operation performed in response to a refresh command or read command, the ECC circuit 400 performs error detection (operation) on the codewords in the selected memory cell row, and in response to the error information, writes back the codewords, including correctable error bits, to the corresponding memory location. Thus, the ECC circuit 400 can reduce the time interval for performing the flush operation and can reduce the flushing period.

[0140] Figure 18 Showing according to an example embodiment Figure 2 Error information register in semiconductor memory devices.

[0141] refer to Figure 18 The error information register 580 includes a first register 581 and a second register 586.

[0142] Each of the indices (e.g., entries) Idx11, Idx12, ..., Idx1u (where u is a natural number greater than 2) in the first register 581 may include page fault information about the first set of pages of the memory cell array 300. Each entry may correspond to one of the pages. The first register 581 includes multiple columns 582, 583, 584, and 585.

[0143] Column 582 stores the address information ADDINF for each page in the first group of pages. In the example embodiment, the address information ADDINF includes at least one of the bank group address ("BGA"), bank address ("BA"), and row address ("RA").

[0144] Column 583 stores the number of errors that occurred for each page in the first set of pages (ECNT). For example, Figure 18 The first register 580 shows that the error count ECNT for the page with address A is 2 and the error count ECNT for the page with address B is 4.

[0145] Column 584 stores the number of subpages, including those with bit errors, in each page of the first set of pages, FCWCNT. Column 585 stores the row fault flag, RWF, for each page of the first set of pages. The row fault flag RWF indicates whether each page in the first set of pages contains K or more codewords with error bits. If the page contains K or more codewords with error bits, the row fault flag RWF has a second logic level (e.g., 1).

[0146] Each of the indices (e.g., entries) Idx21, Idx22, ..., Idx2v (where v is a natural number greater than 2) in the second register 586 may include error information about the codeword, including the error bit. The second register 586 includes multiple columns 587, 588, and 589.

[0147] Column 587 stores the address information ADDINF for each page in a set of pages. Column 588 stores the codeword address information FCWADD for each error codeword, including the error bits. Column 589 stores the flag FG for each error codeword, and the flag FG indicates whether each error codeword includes error bits to be corrected by the ECC circuit 400. If the error codeword includes error bits that cannot be corrected by the ECC circuit 400, the flag FG has a second logic level (e.g., 1).

[0148] Figure 19 This illustrates an example embodiment. Figure 2 A block diagram of an example ECC circuit in a semiconductor memory device.

[0149] refer to Figure 19 The ECC circuit 400 includes an ECC encoder 410, an ECC decoder 430, and an (ECC) memory 415. The memory 415 can store ECC 417. The ECC 417 can be a single error-corrected (SEC) code or a single error-corrected / double error-detected (SECDED) code.

[0150] ECC encoder 410 can use ECC 417 to generate parity data PRT associated with write data WMD to be stored in the normal cell array NCA of the first memory array 310. The parity data PRT can be stored in the redundant cell array RCA of the first memory array 310.

[0151] ECC decoder 430 can perform ECC decoding on read data RMD and parity data PRT read from the first memory array 310 using ECC 417. When read data RMD includes at least one error bit as a result of ECC decoding, ECC decoder 430 provides error generation signal EGS to control logic circuit 210, selectively corrects the error bits in read data RMD during a flushing operation, and outputs corrected master data C_MD during a read operation.

[0152] Figure 20 Showing according to an example embodiment Figure 19 An example of an ECC encoder in an ECC circuit.

[0153] refer to Figure 20 The ECC encoder 410 may include a parity generator 420. The parity generator 420 receives write data WMD and basic bits BB, and generates parity data PRT by performing, for example, an XOR array operation.

[0154] Figure 21 Showing according to an example embodiment Figure 19 An example of an ECC decoder in an ECC circuit.

[0155] refer to Figure 21 The ECC decoder 430 may include a corrector generation circuit 440, an error locator 460, a data corrector 470, a data latch 480, and a demultiplexer 485. The corrector generation circuit 440 may include a parity bit generator 441 and a corrector (syndrome) generator 443.

[0156] The parity bit generator 441 generates the parity bit CHB based on the read data RMD by performing an XOR array operation, and the parity generator 443 generates the parity sub-DR by comparing the corresponding bits of the parity data PRT with the parity bit CHB.

[0157] Error locator 460 generates an error position signal EPS indicating the location of an error bit in the read data RMD, and provides the error position signal EPS to data corrector 470 when all bits of the corrector SDR are not "zero". In addition, when the read data RMD includes an error bit, error locator 460 provides an error generation signal EGS to control logic circuit 210.

[0158] During a flush operation, data latch 480 receives page data PDT including multiple read data RMDs. In response to the operation mode signal OMS and the data control signal DCS, it provides read data RMDs including correctable error bits to data corrector 470 during a flush operation, or provides read data RMDs to data corrector 470 during a read operation, regardless of error bits. The operation mode signal OMS can specify either a flush operation or a read operation. The operation mode signal OMS and the control signal DCS can be included in... Figure 2 In the second control signal CTL2.

[0159] Data corrector 470 receives read data RMD, corrects the erroneous bits in the read data RMD based on the error position signal EPS when the read data RMD includes erroneous bits, and outputs the corrected main data C_MD. Demultiplexer 485 responds to the operation mode signal OMS, provides the corrected main data C_MD to I / O gate circuit 290 in flush mode, and provides the corrected main data C_MD to data I / O buffer 295 during read operations.

[0160] Figure 22 Showing according to an example embodiment Figure 21 The operation of the ECC decoder.

[0161] refer to Figure 21 and Figure 22 In a flush operation in response to a refresh command, the codeword CW includes the error bit EB1. The codeword CW is read from the first page and provided to the ECC circuit 400, as indicated by reference numeral 591. The ECC circuit 400 performs ECC decoding on the codeword CW to correct at least one error bit EB1, as indicated by reference numeral 592, and writes the corrected master data C_MD back to a subpage of the first page, as indicated by reference numeral 593.

[0162] Figure 23 Shown in Figure 2 Normal refresh and flush operations performed in semiconductor memory devices.

[0163] exist Figure 23 In this context, tRFC represents the refresh cycle and indicates the time it takes to refresh one row, while tREFI represents the refresh interval and indicates the interval between two consecutive refresh commands.

[0164] refer to Figure 23 Note that whenever N normal refresh operations REF are performed on a memory cell row in response to a refresh command, the flush control circuit 500 instructs the ECC circuit to perform S flush operations SCRB on the memory cell row. S is a natural number less than N. The flush operation SCRB for a memory cell row includes M flush error detection operations SCD1 to SCDM and at least one write-back operation SCWR. The ECC circuit 400 in the semiconductor memory device 200 sequentially reads data corresponding to codewords from each of the M subpages in the memory cell row, performs error detection on the M codewords, and writes back the codewords, including correctable error bits, to the corresponding memory locations. Therefore, the ECC circuit 400 can reduce the flushing time.

[0165] Figure 24 Shown in Figure 2 Refresh and flush operations performed in semiconductor memory devices.

[0166] refer to Figure 24 Note that whenever N normal refresh operations (NREF) are performed on a memory cell row in response to a refresh command, the flush control circuit 500 instructs the ECC circuit 400 to perform S flush operations (SCRB) on the memory cell row, and to perform L refresh operations (FREF) on the adjacent memory region corresponding to the address VCT_ADDR of the object being interfered with. Here, L is a natural number less than N, and S is a natural number less than L.

[0167] Figure 25 Show Figure 23 or Figure 24 The timing of the scrubbing operation.

[0168] refer to Figure 25 During the refresh cycle tRFC, when a refresh operation is performed on a memory cell row, the internal flush signal ISRB is activated at a logic high level. After the refresh command is applied and after a margin MG, the word line WL coupled to the memory cell row specified by the flush row address is activated. After the word line WL is activated and after the RAS to CAS delay time tRCD, flush error detection operations SCD1 to SCDM are sequentially performed on the M codewords in the memory cell row specified by the flush row address. A flush error detection operation is performed on a codeword during the time interval tCCD_scrb_RD. Some codewords that have detected at least one error bit, including error bits to be corrected by the ECC circuit 400, are corrected, and during the write time tWR, the corrected codewords are written back to the corresponding memory location. After the corrected codewords are written back to SCWR, the word line WL is deactivated. After the word line is deactivated and after the row precharge time tRP, the internal flush signal ISRB is deactivated. The Scrub operation SCRB_OP includes scrubbing error detection operations, error correction, and writing back certain codewords.

[0169] Therefore, when performing a refresh operation on another memory cell row, the ECC circuit 400 sequentially performs error detection operations on the M codewords in the memory cell row and writes back some codewords based on the error information EINF.

[0170] Figure 26 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0171] refer to Figure 26 The semiconductor memory device 600 may include a buffer die 610 and a set of dies 620, which provide soft error analysis and correction capabilities in a stacked chip structure.

[0172] The die set 620 may include multiple memory dies 620-1 to 620-p, which are stacked on the buffer die 610 and transmit data through multiple through silicon via (TSV) lines.

[0173] At least one of the memory dies 620-1 to 620-p may include: a cell core 622 comprising a memory cell array, an ECC circuit 625 for generating transmission parity bits (i.e., transmission parity data) based on transmission data to be sent to the buffer die 611, a refresh control circuit 624, and a flush control circuit 623. The ECC circuit 622 may be referred to as the "cell core ECC circuit". The ECC circuit 622 may employ... Figure 19 The ECC circuit 400. The refresh control circuit 624 can be used. Figure 4 The refresh control circuit 385. The brushing control circuit 623 can be adopted. Figure 7 The brush control circuit 500 or brush control circuit 500a. The ECC circuit 622 and the brush control circuit 623 can perform a brush operation on the codeword to correct error bits, and can reduce the brushing period by selectively determining whether to write back each codeword in the memory cell row based on the error information.

[0174] The buffer die 610 may include a via ECC circuit 612, which uses a transmission parity bit to correct the transmission error and generate error-corrected data when a transmission error is detected from the transmitted data received through the TSV line.

[0175] Semiconductor memory device 600 may be a stacked chip-type memory device or a stacked memory device that transmits data and control signals via TSV lines. TSV lines may also be referred to as "through electrodes".

[0176] A data TSV line group 632 formed at a memory die 620-p may include TSV lines L1 to Lp, and an odd-even TSV line group 634 may include TSV lines L10 to Lq.

[0177] The TSV lines L1 to Lp of the data TSV line group 632 and the parity TSV lines L10 to Lq of the parity TSV line group 634 can be connected to the microbumps MCB, which are correspondingly formed in the memory dies 620-1 to 620p.

[0178] At least one of the memory dies 620-1 to 620-p may include a DRAM cell, each DRAM cell including at least one access transistor and a storage capacitor.

[0179] The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host via the data bus B10. The buffer die 610 may be connected to the memory controller via the data bus B10.

[0180] The via ECC circuit 612 can determine whether a transmission error has occurred at the point of transmission data received via the data TSV line group 632 based on the transmission parity bit received via the parity TSV line group 634. When a transmission error is detected, the via ECC circuit 612 can use the transmission parity bit to correct the transmission error in the transmission data. When the transmission error is uncorrectable, the via ECC circuit 612 can output information indicating the occurrence of an uncorrectable data error.

[0181] Figure 27 This is a flowchart illustrating a method for using a semiconductor memory device according to an example embodiment.

[0182] refer to Figures 2 to 27 In a method of operating a semiconductor memory device including a memory cell array 300 (where the memory cell array 300 includes a plurality of memory cell rows, and each of the plurality of memory cell rows includes a plurality of volatile memory cells), a first address is sequentially generated in response to a first command received from an external memory controller 100 (S110). The first command may be a refresh command, and the first address may be a refresh row address REF_ADDR generated by refresh control circuitry 385.

[0183] The memory cell rows are refreshed sequentially based on the first address (S120). Whenever N refresh operations are performed on a memory cell row, a memory cell row is selected from the memory cell rows based on a second internal address generated in the semiconductor memory device 200 (S130). The ECC circuit 400 performs an M ECC decoding operation on the codewords in the selected memory cell row to detect error bits on a codeword basis (S140), and records error information in the error information register 580 in response to the detection of an error bit. The second internal address can be a flush address generated by the flush control circuit.

[0184] The control logic circuit 210 controls the ECC circuit 400 based on the error information stored in the error information, so that the ECC circuit 400 writes back the codeword including the correctable error bits to the corresponding memory location (S150).

[0185] Figure 28 This is a diagram illustrating a semiconductor package including a stacked memory device according to an example embodiment.

[0186] refer to Figure 28 The semiconductor package 900 may include one or more stacked memory devices 910 and graphics processing units (GPUs) 920. The GPU 920 may include a memory controller 925.

[0187] The stacked memory devices 910 and GPU 920 can be mounted on an interposer 930, and the interposer on which the stacked memory devices 910 and GPU 920 are mounted can be mounted on a package substrate 940. The memory controller 925 can employ... Figure 1 The memory controller 100 in the middle.

[0188] Each stacked memory device 910 can be implemented in various forms and can be a high-bandwidth memory (HBM) type memory device in which multiple layers are stacked. Therefore, each stacked memory device 910 may include buffer dies and multiple memory dies. Each memory die may include a memory cell array, ECC circuitry, and flush control circuitry.

[0189] Multiple stacked memory devices 910 may be mounted on an interposer layer 930, and a GPU 920 may communicate with the multiple stacked memory devices 910. For example, each of the stacked memory devices 910 and the GPU 920 may include a physical region, and communication may be performed between the stacked memory devices 910 and the GPU 920 through the physical region.

[0190] As described above, according to the example embodiment, the semiconductor memory device includes an ECC circuit and a flush control circuit. The ECC circuit sequentially performs error detection operations on codewords in a memory cell row specified by a flush address provided by the flush control circuit. The control logic circuit records error information associated with the error detection in an error information register, and the ECC circuit selectively writes back codewords containing correctable errors to the corresponding memory location based on the error information. Therefore, the semiconductor memory device can reduce flushing time while preventing the accumulation of error bits, and can enhance reliability and performance.

[0191] According to the example embodiment, such as Figure 1 , Figure 2 , Figures 4-17 , Figures 19-21 and Figure 26 At least one of the components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units represented by blocks can be embodied as various numbers of hardware, software, and / or firmware structures performing the corresponding functions described above. For example, at least one of these components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units can use direct circuit structures, such as memory, processors, logic circuits, lookup tables, etc., which can operate the corresponding functions under the control of one or more microprocessors or other control devices. Furthermore, at least one of these components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units can be specifically embodied as a portion of a module, program, or code containing one or more executable instructions for performing the specified logical function, and operated by one or more microprocessors or other control devices. Moreover, at least one of these components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units can further include, or be implemented by, a processor (such as a central processing unit (CPU)), microprocessor, etc., performing the corresponding function. Two or more of these components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units can be combined to form a single component, element, module, circuit, controller, device, generator, counter, oscillator, register, comparator, or unit that performs all the operations or functions of the combined two or more components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units. Furthermore, at least a portion of the function of at least one of these components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units can be performed by another of these components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units. Additionally, although a bus is not shown in the above block diagrams, communication between components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units can be performed via a bus. The functional aspects of the above exemplary embodiments can be implemented using algorithms running on one or more processors. Furthermore, components, elements, modules, circuits, controllers, devices, generators, counters, oscillators, registers, comparators, or units represented by blocks or processing steps may employ any number of related techniques for electronic configuration, signal processing and / or control, data processing, etc.

[0192] The aspects of this disclosure can be applied to systems using semiconductor memory devices employing ECC circuitry. For example, the aspects of this disclosure can be applied to systems using semiconductor memory devices as working memory, such as smartphones, navigation systems, laptop computers, desktop computers, and game consoles.

[0193] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that many variations and modifications can be made to the described exemplary embodiments without substantially departing from the principles of this disclosure as defined by the appended claims. < / g> < / g> < / g> < / g> < / g>

Claims

1. A semiconductor memory device, comprising: an array of memory cells including a plurality of rows of memory cells, each row of memory cells including volatile memory cells; an error correction code (ECC) circuit; an error information register; a scrub control circuit configured to count refresh row addresses and to output a scrub address each time the scrub control circuit counts N refresh row addresses to control a scrub operation to be performed on at least one sub-page in a first row of memory cells of the plurality of rows of memory cells, N being an integer greater than 2; and a control logic circuit configured to: control the ECC circuit to sequentially read data corresponding to a first codeword from M sub-pages in the first row of memory cells, perform error detection on the first codeword, and provide error information based on the error detection, the error information indicating an error occurrence count in the first codeword, M being an integer greater than 1; and record the error information in the error information register and selectively determine whether to write back a corrected first codeword to a memory location storing data corresponding to the first codeword based on the error information.

2. The semiconductor memory device of claim 1, further comprising: a refresh control circuit configured to generate refresh row addresses in response to a first command received from an external device, wherein the first command is a refresh command, and wherein the scrub control circuit is configured to sequentially generate scrub addresses specifying M codewords included in the first row of memory cells while performing refresh operations on one of the plurality of rows of memory cells.

3. The semiconductor memory device of claim 1, wherein, the control logic circuit is further configured to control the ECC circuit to write back the corrected first codeword to the memory location in response to error information indicating that the first codeword includes error bits to be corrected by the ECC circuit.

4. The semiconductor memory device of claim 3, wherein, the control logic circuit is further configured to control the ECC circuit to write back the corrected first codeword to the memory location after completing error detection on the M sub-pages in the first row of memory cells.

5. The semiconductor memory device of claim 1, wherein, the control logic circuit is further configured to control the ECC circuit to skip writing back the corrected first codeword to the memory location in response to error information indicating that the first codeword includes error bits that are not corrected by the ECC circuit.

6. The semiconductor memory device of claim 1, wherein, the control logic circuit is further configured to control the ECC circuit to write back correctable codewords to corresponding memory locations, respectively, in response to error information indicating that a number of correctable codewords for the M sub-pages in the first row of memory cells is less than K, K being a natural number greater than 2, each of the correctable codewords including error bits to be corrected by the ECC circuit.

7. The semiconductor memory device of claim 1, wherein, the control logic circuit is further configured to control the ECC circuit to skip writing back correctable codewords to corresponding memory locations based on error information indicating that a number of correctable codewords for the M sub-pages in the first row of memory cells is equal to or greater than K, K being a natural number greater than 2, each of the correctable codewords including error bits to be corrected by the ECC circuit.

8. The semiconductor memory device of claim 1, wherein, The scrub control circuit includes: a counter configured to count refresh row addresses, and to activate an internal scrub signal each time the counter counts N refresh row addresses; and a scrub address generator configured to generate, based on the internal scrub signal, a normal scrub address associated with a normal scrub operation of a first memory cell row.

9. The semiconductor memory device of claim 8, wherein, The normal scrub address includes a scrub row address specifying one memory cell row and a scrub column address specifying one of the codewords included in the one memory cell row, and wherein the scrub address generator includes: a page segment counter configured to, based on the internal scrub signal being activated, increment the scrub column address by one; and a row counter configured to, based on the scrub column address reaching a maximum value, increment the scrub column address by one.

10. The semiconductor memory device of claim 1, wherein, The scrub control circuit includes: a counter configured to count a number of refresh operations performed on the plurality of memory cell rows, and to activate an internal scrub signal each time the counter counts N refresh row addresses; a scrub address generator configured to generate, based on the internal scrub signal and a scrub mode signal, a normal scrub address associated with a normal scrub operation of a first memory cell row in a first scrub mode; and a weak codeword address generator configured to generate, based on the internal scrub signal and the scrub mode signal, a weak codeword address indicating a weak codeword in the first memory cell row in a second scrub mode.

11. The semiconductor memory device of claim 10, wherein, The weak codeword address generator includes: an address storage table configured to store address information of the weak codeword; and a table pointer configured to generate, based on the internal scrub signal, a pointer signal indicating position information of the address storage table.

12. The semiconductor memory device of claim 1, wherein, The control logic circuit is configured to: based on a second command from an external device, control the ECC circuit to read data corresponding to a second codeword from at least one sub-page in a second memory cell row of the plurality of memory cell rows specified by an access address, and based on detecting at least one error bit in the second codeword, provide an error generation signal to the control logic circuit; record address information of the second codeword in an error information register; and based on the second codeword including correctable error bits, control the ECC circuit to write back the corrected second codeword to a memory location where the data is stored; and wherein the second command corresponds to a read command.

13. The semiconductor memory device of claim 1, wherein, The ECC circuit includes an ECC decoder configured to perform an error detection operation on M codewords included in the first memory cell row.

14. The semiconductor memory device of claim 13, wherein, The ECC decoder includes: a data latch configured to store the M codewords; a syndrome generation circuit configured to generate a syndrome based on the main data and the parity data of each of the M codewords; an error locator configured to generate, based on the syndrome, an error location signal indicating a location of at least one error bit in the main data; and an error corrector configured to generate, based on the error location signal, a corrected codeword. a data corrector configured to receive K-1 codewords selected from the M codewords stored in the data latch based on the error information, and correct error bits of each of the K-1 codewords, K being a natural number greater than 2.

15. The semiconductor memory device of claim 1, further comprising: a victim address detector configured to count a number of accesses to a first memory region in the array of memory cells, and generate at least one victim address specifying at least one neighboring memory region adjacent to the first memory region based on the number of accesses reaching a threshold during a reference interval, wherein the victim address detector is further configured to provide the at least one victim address to the scrub control circuit, and wherein the scrub control circuit is configured to store the at least one victim address as a weak codeword address in the address storage table.

16. The semiconductor memory device of claim 1, wherein, the scrub operation includes performing a consecutive error detection operation on M codewords included in the first row of memory cells, and performing a read-back operation on K-1 codewords selected from the M codewords based on a result of the error detection operation.

17. The semiconductor memory device of claim 1, further comprising: at least one buffer die; and a plurality of memory dies provided on the at least one buffer die and configured to transfer data through a plurality of through silicon via (TSV) lines formed therethrough, wherein at least one of the plurality of memory dies includes an array of memory cells, an ECC circuit, a scrub control circuit, and a refresh control circuit configured to generate a refresh row address.

18. The semiconductor memory device of claim 17, wherein, the ECC circuit is configured to generate transfer parity bits based on transfer data to be transmitted to the at least one buffer die, and wherein the at least one buffer die includes a via ECC circuit configured to correct a transfer error using the transfer parity bits based on the transfer error being detected from the transfer data received through the plurality of TSV lines.

19. A method of operating a semiconductor memory device including an array of memory cells, the array of memory cells including a plurality of rows of memory cells, each row of memory cells including a plurality of volatile memory cells, the method comprising: counting, by a scrub control circuit of the semiconductor memory device, refresh row addresses, and outputting a scrub address each time the scrub control circuit counts N refresh row addresses to control a scrub operation to be performed on at least one sub-page in a first row of memory cells in the plurality of rows of memory cells, N being an integer greater than 2; controlling, by control logic circuitry of the semiconductor memory device, an error correcting code (ECC) circuit of the semiconductor memory device to sequentially read data corresponding to a first codeword from M sub-pages in the first row of memory cells, perform an error detection on the first codeword, and provide error information based on the error detection, the error information indicating an error occurrence count in the first codeword, M being an integer greater than 1; and record the error information in an error information register of the semiconductor memory device and selectively determine whether to write back the corrected first codeword to a memory location storing data corresponding to the first codeword based on the error information.

20. A semiconductor memory device, comprising: an array of memory cells including a plurality of rows of memory cells, each row of memory cells including volatile memory cells; an error correction code (ECC) circuit; an error information register; a refresh control circuit configured to generate a refresh row address indicative of a row of memory cells based on a first command received from an external device; a scrub control circuit configured to count the refresh row addresses and output a scrub address to control a scrub operation to be performed on at least one sub-page in a first row of memory cells of the plurality of rows of memory cells each time the scrub control circuit counts N refresh row addresses, N being an integer greater than 2; and a control logic circuit configured to: control the ECC circuit to sequentially read data corresponding to a first codeword from M sub-pages in the first row of memory cells, perform error detection on the first codeword, and provide error information based on the error detection, the error information being indicative of an error occurrence count in the first codeword, M being an integer greater than 1; and record the error information in the error information register and selectively determine whether to write back the corrected first codeword to a memory location storing data corresponding to the first codeword based on the error information.

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