Semiconductor packaging method and semiconductor packaging structure

Abstract

The present disclosure provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method includes: providing a chip; forming a first encapsulation layer around the chip; forming an embedded wiring layer at least on one side of the first encapsulation layer; forming a second encapsulation layer covering the first encapsulation layer and the embedded wiring layer, the second encapsulation layer forming a housing cavity corresponding to the chip area; forming a fan-out wiring layer on the side of the first encapsulation layer facing away from the second encapsulation layer, the fan-out wiring layer being electrically connected to the embedded wiring layer and the pins of the chip. The present disclosure can solve the problem of high packaging process difficulty caused by high wiring density.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging method and a semiconductor packaging structure. Background Art

[0002] With the rapid development of science and technology, semiconductor devices have been more and more widely used in social production and life. At present, people often package chips to form a packaging structure. However, the wiring density on the existing packaging structure is too high, which increases the difficulty of the packaging process. Summary of the invention

[0003] The purpose of the present disclosure is to provide a semiconductor packaging method and a semiconductor packaging structure, which can solve the problem of high packaging process difficulty caused by high wiring density.

[0004] According to one aspect of the present disclosure, there is provided a semiconductor packaging method, comprising:

[0005] Provide chips;

[0006] forming a first encapsulation layer around the chip;

[0007] forming an embedded wiring layer at least on one side of the first encapsulation layer;

[0008] forming a second encapsulation layer covering the first encapsulation layer and the embedded wiring layer, wherein the second encapsulation layer forms a containing cavity in a region corresponding to the chip;

[0009] A fan-out wiring layer is formed on a side of the first encapsulation layer facing away from the second encapsulation layer, and the fan-out wiring layer is electrically connected to the embedded wiring layer and the pins of the chip.

[0010] Further, forming a first encapsulation layer around the chip includes:

[0011] Providing a carrier board, forming a first encapsulation layer on the carrier board and mounting the chip, wherein the first encapsulation layer surrounds the chip, and the back side of the chip faces away from the carrier board;

[0012] Forming an embedded wiring layer at least on one side of the first encapsulation layer comprises:

[0013] forming an embedded wiring layer at least on a side of the first encapsulation layer facing away from the carrier board;

[0014] Forming a fan-out wiring layer on a side of the first encapsulation layer facing away from the second encapsulation layer comprises:

[0015] The carrier board is removed, and a fan-out wiring layer is formed on a surface of the first encapsulation layer facing away from the second encapsulation layer.

[0016] Further, the chip includes a first pin and a second pin, the embedded wiring layer includes an embedded line, and the fan-out wiring layer includes:

[0017] A first fan-out line, electrically connected to the embedded line and a first pin of the chip;

[0018] The second fan-out line is insulated from the first fan-out line and electrically connected to the second pin of the chip.

[0019] Further, forming an embedded wiring layer at least on one side of the first encapsulation layer comprises:

[0020] forming a plurality of via holes on the first encapsulation layer, and forming an embedded wiring layer on one side of the first encapsulation layer and in the via holes; or

[0021] forming a recessed portion on the first encapsulation layer, forming a plurality of via holes on a bottom wall of the recessed portion, and forming an embedded wiring layer filling the recessed portion and the via holes in the recessed portion and the via holes; or

[0022] A recessed portion is formed on the first encapsulation layer, a plurality of vias are formed on the bottom wall of the recessed portion, and a step structure is formed on the side wall of the recessed portion; an embedded wiring layer covering the bottom wall of the recessed portion and filling the vias is formed in the recessed portion and in the vias.

[0023] Furthermore, the fan-out wiring layer further includes:

[0024] A third fan-out line is provided on a surface of the first encapsulation layer facing away from the second encapsulation layer and is electrically connected to the embedded line;

[0025] The semiconductor packaging method further comprises:

[0026] Forming a conductive column layer, the conductive column layer comprising a first conductive column and a second conductive column, the first conductive column being arranged on a surface of the third fan-out line facing away from the second encapsulation layer and being electrically connected to the third fan-out line; the second conductive column being arranged on a surface of the second fan-out line facing away from the second encapsulation layer and being electrically connected to the second fan-out line;

[0027] A dielectric layer covering the fan-out wiring layer and the first encapsulation layer is formed, wherein the dielectric layer surrounds the first conductive pillar and the second conductive pillar.

[0028] Further, forming a first encapsulation layer around the chip includes:

[0029] A first encapsulation layer is formed, and a first window is formed in the first encapsulation layer, and the chip is disposed in the first window.

[0030] According to one aspect of the present disclosure, there is provided a semiconductor package structure, comprising:

[0031] chip;

[0032] An encapsulation body encapsulating the chip and comprising a first encapsulation layer and a second encapsulation layer stacked;

[0033] An embedded wiring layer is provided between the first encapsulation layer and the second encapsulation layer;

[0034] The fan-out wiring layer is arranged on a surface of the first encapsulation layer facing away from the second encapsulation layer and is electrically connected to the embedded wiring layer and the pins of the chip.

[0035] Furthermore, the surface of the second encapsulation layer facing the first encapsulation layer has an accommodating cavity;

[0036] The chip is arranged in the accommodating cavity, and the front side of the chip faces away from the accommodating cavity and is located outside the accommodating cavity;

[0037] The embedded wiring layer is arranged in a region outside the accommodating cavity.

[0038] Further, the chip includes a first pin and a second pin, the embedded wiring layer includes an embedded line, and the fan-out wiring layer includes:

[0039] A first fan-out line, electrically connected to the embedded line and a first pin of the chip;

[0040] The second fan-out line is insulated from the first fan-out line and electrically connected to the second pin of the chip.

[0041] Furthermore, the semiconductor packaging structure further includes:

[0042] A dielectric layer, disposed on a side of the first encapsulation layer away from the second encapsulation layer and covering the fan-out wiring layer;

[0043] A conductive column layer is at least partially formed in the dielectric layer, and the conductive column layer includes a first conductive column and a second conductive column, wherein the first conductive column is electrically connected to the buried line, and the second conductive column is electrically connected to the second fan-out line.

[0044] Furthermore, the first encapsulation layer is provided with a plurality of via holes, and the embedded wiring layer fills each of the via holes; or

[0045] The first encapsulation layer is provided with a recessed portion, a bottom wall of the recessed portion is provided with a plurality of via holes, and the embedded wiring layer is formed in the recessed portion and the via holes and fills the recessed portion and the via holes; or

[0046] The first encapsulation layer is provided with a recessed portion, a bottom wall of the recessed portion is provided with a plurality of vias, a side wall of the recessed portion is formed with a step structure, the embedded wiring layer is formed in the recessed portion and in the vias and covers the bottom wall of the recessed portion and fills the vias.

[0047] Furthermore, the material of the first encapsulation layer includes a photosensitive material.

[0048] The semiconductor packaging method and semiconductor packaging structure disclosed in the present invention include a second encapsulation layer and a first encapsulation layer which are stacked, an embedded wiring layer is arranged between the second encapsulation layer and the first encapsulation layer, and a fan-out wiring layer is arranged on a surface of the first encapsulation layer which is opposite to the second encapsulation layer, thereby reducing the wiring density on the second encapsulation layer and further solving the problem of high packaging process difficulty caused by high wiring density. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a schematic cross-sectional view of a chip according to an embodiment of the present disclosure.

[0050] Figure 2 is a schematic diagram of the chip according to an embodiment of the present disclosure from another perspective.

[0051] Figure 3 is a flow chart of a semiconductor packaging method according to an embodiment of the present disclosure.

[0052] Figure 4 It is a schematic diagram after the first encapsulation layer is formed in an embodiment of the present disclosure.

[0053] Figure 5 It is a schematic diagram after forming an embedded wiring layer in the semiconductor packaging method according to an embodiment of the present disclosure.

[0054] Figure 6 It is a schematic diagram after chip mounting in the semiconductor packaging method according to an embodiment of the present disclosure.

[0055] Figure 7 is another schematic diagram after forming an embedded wiring layer in the semiconductor packaging method according to an embodiment of the present disclosure.

[0056] Figure 8 It is a schematic diagram after a photoresist layer is formed in the semiconductor packaging method according to an embodiment of the present disclosure.

[0057] Fig. 9 It is another schematic diagram after the embedded wiring layer is formed in the semiconductor packaging method according to the embodiment of the present disclosure.

[0058] Fig.10 3 is a schematic diagram after forming a second encapsulation layer in the semiconductor packaging method according to an embodiment of the present disclosure.

[0059] Fig.11It is a schematic diagram of the semiconductor packaging method after removing the carrier board according to the embodiment of the present disclosure.

[0060] Fig.12 It is a schematic diagram after a fan-out wiring layer is formed in the semiconductor packaging method according to an embodiment of the present disclosure.

[0061] Fig.13 Schematic diagram of a semiconductor packaging method according to an embodiment of the present disclosure after a dielectric layer is formed.

[0062] Figure 14-16 yes Fig.13 AA cross-section of the structure shown.

[0063] Explanation of the reference numerals: 1. chip; 2. pin; 201. first pin; 202. second pin; 3. fan-out wiring layer; 301. first fan-out line; 302. second fan-out line; 303. third fan-out line; 4. embedded wiring layer; 401. embedded line; 5. first conductive column; 6. second conductive column; 7. second encapsulation layer; 8. first encapsulation layer; 9. dielectric layer; 10. recess; 11. via; 12. protective layer; 13. carrier; 14. adhesive layer; 15. step structure; 16. photoresist layer. DETAILED DESCRIPTION

[0064] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0065] The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. "Multiple" or "several" means two and more than two. Unless otherwise specified, words such as "front", "rear", "lower" and / or "upper" are only for the convenience of explanation and are not limited to one position or one spatial orientation. Words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a", "an", "said", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

[0066] The present disclosure provides a semiconductor packaging method. The semiconductor packaging method may include: providing a chip; forming a first encapsulation layer surrounding the chip; forming an embedded wiring layer at least on one side of the first encapsulation layer; forming a second encapsulation layer covering the first encapsulation layer and the embedded wiring layer, the second encapsulation layer forming a housing cavity corresponding to the chip area; forming a fan-out wiring layer on the side of the first encapsulation layer facing away from the second encapsulation layer, the fan-out wiring layer being electrically connected to the embedded wiring layer and the pins of the chip.

[0067] In the semiconductor packaging method of the embodiment of the present disclosure, the embedded wiring layer is arranged between the second encapsulation layer and the first encapsulation layer, and the fan-out wiring layer is arranged on the surface of the first encapsulation layer facing away from the second encapsulation layer, thereby reducing the wiring density on the second encapsulation layer, thereby solving the problem of high packaging process difficulty caused by high wiring density.

[0068] The following is a detailed description of each part of the semiconductor packaging method according to the embodiment of the present disclosure:

[0069] The chip may include a front side, a back side and a side side. The front side and the back side of the chip are arranged opposite to each other. The side side of the chip is connected between the front side and the back side. Figure 1As shown, the front side of the chip 1 may be provided with pins 2. The number of pins 2 of the chip 1 may be multiple. For example, Figure 2 As shown, the chip 1 may include a plurality of first pins 201 and a plurality of second pins 202, the first pins 201 and the second pins 202 are arranged at intervals, and the plurality of first pins 201 and the plurality of second pins 202 are distributed along a preset direction to form a pin row. Figure 1 As shown, the front side of the chip 1 may also be provided with a protective layer 12. The protective layer 12 covers the front side of the chip 1, and the protective layer 12 is provided with a through hole in the area corresponding to the pin 2. The material of the protective layer 12 may be resin or the like.

[0070] In one embodiment of the present disclosure, Figure 3 As shown, the forming of the first encapsulation layer may include step S100, the forming of the embedded wiring layer may include step S110, and the forming of the fan-out wiring layer may include step S130, wherein:

[0071] Step S100: providing a carrier board, forming a first encapsulation layer on the carrier board and mounting a chip, wherein the first encapsulation layer surrounds the chip, and the back side of the chip faces away from the carrier board.

[0072] like Figure 4 and Figure 5 As shown, the present disclosure can mount the chip 1 after forming the first encapsulation layer 8, specifically including: forming the first encapsulation layer 8 on the carrier 13; patterning the first encapsulation layer 8 to form a first window on the first encapsulation layer 8; mounting the chip 1 on the carrier 13 through the first window. Figure 6 As shown, there may also be a gap between the side wall of the first window and the chip 1. By arranging the chip 1 at the first window, the displacement of the chip 1 in the subsequent packaging process can be effectively reduced. The material of the first encapsulation layer 8 can be an insulating material. Further, the material of the first encapsulation layer 8 can be a photosensitive material. For example, the material of the first encapsulation layer 8 can be green oil, polyimide, PID, etc. In addition, there may be an adhesive layer 14 between the first encapsulation layer 8 and the carrier 13.

[0073] The first encapsulation layer 8 may also have an embedded region spaced apart from the first window. In the process of patterning the first encapsulation layer 8, the present disclosure may also form a plurality of via groups in the embedded region. The number of the via groups may be the same as the number of the first pins 201 of the chip 1, and the plurality of via groups may correspond to the plurality of first pins 201 one by one. Figure 5 As shown, each via hole group includes a plurality of via holes 11. For example, each via hole group includes two via holes 11. Further, as Figure 7 As shown, the present disclosure can first form a recessed portion 10 in the embedded area of ​​the first encapsulation layer 8 (see Figure 8), and a plurality of via groups are formed on the bottom wall of the recessed portion 10, and the subsequently formed embedded wiring layer 4 can be arranged in the recessed portion 10. Figure 8 and Fig. 9 As shown, the side wall of the recessed portion 10 can form a step structure 15, which is suitable for preparing a smaller via hole 11 and can also make the subsequently formed buried line 401 (see Fig.13 ) can be made smaller in line width and line spacing, thereby making the circuit more refined, thereby achieving further miniaturization of the packaged product. The step structure 15 can be formed by laser anvil hole, laser cutting, laser imaging, etc. Specifically, the present disclosure can form the step structure 15 by controlling the energy of laser imaging, but is not limited to one method and can be combined with multiple methods. In other embodiments of the present disclosure, the step structure 15 can be formed by a grayscale exposure process.

[0074] Step S110 , forming an embedded wiring layer at least on a side of the first encapsulation layer facing away from the carrier.

[0075] like Figure 5 As shown, the embedded wiring layer 4 can be prepared by an electroplating process. The embedded wiring layer 4 may include embedded wires 401 (see Fig.13 ). The number of the embedded wires 401 may be multiple, and the multiple embedded wires 401 are arranged at intervals, and the multiple embedded wires 401 correspond to the multiple via groups mentioned above. In the process of forming the embedded wiring layer 4, each embedded wire 401 can fill the multiple vias 11 in the corresponding via group. Taking the recess 10 formed on the first encapsulation layer 8 as an example, step 110 may include: forming an embedded wiring layer 4 filling the recess 10 and the via 11 in the recess 10 and the via 11, and the structure after the embedded wiring layer 4 is formed is as follows Figure 7 Taking the example of a recessed portion 10 formed on the first encapsulation layer 8 and a step structure 15 formed on the sidewall of the recessed portion 10, step 110 may include: forming an embedded wiring layer 4 in the recessed portion 10 and in the via hole 11, covering the bottom wall of the recessed portion 10 and filling the via hole 11, and the structure after the embedded wiring layer 4 is formed is as shown in FIG. Fig. 9 In addition, Figure 8 and Fig. 9 As shown, before electroplating, the present disclosure can form a photoresist layer 16 covering the first encapsulation layer 8, and pattern the photoresist layer 16 to form a second window in the region of the photoresist layer 16 corresponding to the above-mentioned buried region. The buried wiring layer 4 can be provided in the region of the first encapsulation layer 8 corresponding to the second window. In addition, in order to smoothly carry out electroplating, before forming the photoresist layer 16, the present disclosure can also form a copper seed layer on the first encapsulation layer 8.

[0076] Step S120: forming a second encapsulation layer covering the first encapsulation layer and the embedded wiring layer, wherein the second encapsulation layer forms a receiving cavity in a region corresponding to the chip.

[0077] like Fig.10 As shown, the second encapsulation layer 7 can be formed by injection molding, hot pressing, film pressing, etc. The second encapsulation layer 7 can also cover the back of the chip 1, that is, the accommodation cavity formed on the second encapsulation layer 7 has only one open end. Of course, the second encapsulation layer 7 can surround the chip 1, that is, the second encapsulation layer 7 only covers the side of the chip 1, that is, the accommodation cavity formed on the second encapsulation layer 7 is open at both ends.

[0078] Step S130, removing the carrier board, and forming a fan-out wiring layer on the surface of the first encapsulation layer facing away from the second encapsulation layer, wherein the fan-out wiring layer is electrically connected to the embedded wiring layer and the pins of the chip.

[0079] like Fig.11 , Fig.12 as well as Fig.13 As shown, the fan-out wiring layer 3 may include a first fan-out line 301 and a second fan-out line 302 arranged at intervals. In the related art, when the number of pins 2 of the chip 1 is large, in order to avoid the fan-out lines connecting the pins 2 from being staggered or short-circuited, the fan-out lines connecting the pins 2 are stacked, resulting in a larger thickness of the semiconductor package structure. The first fan-out line 301 and the second fan-out line 302 of the present invention are arranged in the same layer, which reduces the thickness of the semiconductor package structure. Fig.13 As shown, taking the pin 2 including the first pin 201 and the second pin 202 as an example, the fan-out wiring layer 3 may include a first fan-out line 301 and a second fan-out line 302, the first fan-out line 301 is electrically connected to the buried line 401 and the first pin 201 of the chip 1; the second fan-out line 302 is insulated from the first fan-out line 301, and the second fan-out line 302 is electrically connected to the second pin 202 of the chip 1. The number of the first fan-out lines 301 may be multiple, and the multiple first fan-out lines 301 are electrically connected to the multiple first pins 201 of the chip 1 in a one-to-one correspondence, and the multiple first fan-out lines 301 are electrically connected to the multiple buried lines 401 in a one-to-one correspondence. The number of the second fan-out lines 302 may be multiple, and the multiple second fan-out lines 302 are electrically connected to the multiple second pins 202 of the chip 1 in a one-to-one correspondence. The first fan-out line 301 may contact the area of ​​the buried line 401 located in a via 11, so that the first fan-out line 301 is electrically connected to the buried line 401. In a direction perpendicular to the thickness direction of the chip 1, one end of the embedded wire 401 close to the chip 1 is electrically connected to the first fan-out wire 301, and one end of the embedded wire 401 away from the chip 1 is located on a side of the second fan-out wire 302 away from the chip 1. In addition, the via group formed in the first encapsulation layer 8 can also be formed after removing the carrier 13, and a conductive material is added to the formed via 11 to facilitate the electrical connection between the first fan-out wire 301 and the embedded wire 401.

[0080] In addition, if Fig.12 As shown, the fan-out wiring layer 3 may further include a third fan-out line 303. The third fan-out line 303 is electrically connected to the buried line 401. The third fan-out line 303 is spaced apart from the first fan-out line 301 and the second fan-out line 302. Taking the above-mentioned via groups including two vias 11 as an example, the above-mentioned first fan-out line 301 contacts the region of the buried line 401 located in one via 11, and the third fan-out line 303 contacts the region of the buried line 401 located in another via 11.

[0081] like Fig.13 and Fig.14 As shown, after forming the fan-out wiring layer 3, the semiconductor packaging method of the present disclosure may further include: forming a conductive column layer, which may include a first conductive column 5 electrically connected to the third fan-out line 303 and a second conductive column 6 electrically connected to the second fan-out line 302. The first conductive column 5 may be arranged on the surface of the third fan-out line 303 facing away from the second encapsulation layer 7. The second conductive column 6 may be arranged on the surface of the second fan-out line 302 facing away from the second encapsulation layer 7. The semiconductor packaging method of the present disclosure may further include: forming a dielectric layer 9 covering the fan-out wiring layer 3 and the first encapsulation layer 8, the dielectric layer 9 surrounding the first conductive column 5 and the second conductive column 6. The end surface of the first conductive column 5 away from the second encapsulation layer 7, the end surface of the second conductive column 6 away from the second encapsulation layer 7, and the surface of the dielectric layer 9 away from the second encapsulation layer 7 are flush. Optionally, in a direction perpendicular to the thickness direction of the chip 1, the first conductive column 5 is located on the side of the second conductive column 6 away from the chip 1. Fig.14 The structure shown can be represented by Figure 5 The structure shown is formed, namely Fig.14 The structure shown corresponds to the above-mentioned situation where the recessed portion 10 is not formed in the embedded region; Fig.15 The structure shown can be represented by Figure 7 The structure shown is formed, namely Fig.15 The structure shown corresponds to the above-mentioned situation where the buried region forms a recessed portion 10; Fig.16 The structure shown can be represented by Fig. 9 The structure shown is formed, namely Fig.16 The structure shown corresponds to the situation where the sidewall of the recessed portion 10 formed by the buried region has a step structure 15 .

[0082] The present disclosure also provides a semiconductor packaging structure. The semiconductor structure can be prepared by the above-mentioned semiconductor packaging method. Figures 14 to 16 As shown, the semiconductor package structure may include a chip 1, an encapsulation body, an embedded wiring layer 4 and a fan-out wiring layer 3, wherein:

[0083] The encapsulation body encapsulates the chip 1, and includes a stacked second encapsulation layer 7 and a first encapsulation layer 8. The embedded wiring layer 4 is arranged between the second encapsulation layer 7 and the first encapsulation layer 8. The fan-out wiring layer 3 is arranged on the surface of the first encapsulation layer 8 facing away from the second encapsulation layer 7, and is electrically connected to the embedded wiring layer 4 and the pins 2 of the chip 1.

[0084] The surface of the second encapsulation layer 7 facing the first encapsulation layer 8 may have a receiving cavity. The chip 1 may be disposed in the receiving cavity. The front surface of the chip 1 faces away from the receiving cavity and is located outside the receiving cavity, that is, a portion of the chip 1 extends out of the receiving cavity. The embedded wiring layer 4 may be disposed in an area outside the receiving cavity.

[0085] In one embodiment of the present disclosure, the first encapsulation layer 8 may be provided with a plurality of vias 11. The embedded wiring layer 4 may fill each via 11. In another embodiment of the present disclosure, the first encapsulation layer 8 may be provided with a recessed portion 10, the bottom wall of the recessed portion 10 may be provided with a plurality of vias 11, the embedded wiring layer 4 is formed in the recessed portion 10 and in the vias 11 and fills the recessed portion 10 and the vias 11. In yet another embodiment of the present disclosure, the first encapsulation layer 8 is provided with a recessed portion 10, the bottom wall of the recessed portion 10 is provided with a plurality of vias 11, the side wall of the recessed portion 10 is formed with a step structure 15, the embedded wiring layer 4 is formed in the recessed portion 10 and in the vias 11 and covers the bottom wall of the recessed portion 10 and fills the vias 11.

[0086] The embedded wiring layer 4 may include an embedded wire 401. The fan-out wiring layer 3 may include a first fan-out wire 301 and a second fan-out wire 302. The first fan-out wire 301 is electrically connected to the embedded wire 401 and the first pin 201 of the chip 1. The second fan-out wire 302 is insulated from the first fan-out wire 301 and is electrically connected to the second pin 202 of the chip 1. In a direction perpendicular to the thickness direction of the chip 1, one end of the embedded wire 401 close to the chip 1 is electrically connected to the first fan-out wire 301. Optionally, the orthographic projection of the embedded wire 401 on the surface of the first encapsulation layer 8 facing away from the second encapsulation layer 7 coincides with the second fan-out wire 302.

[0087] The semiconductor packaging structure may further include a dielectric layer 9 and a conductive column layer. The dielectric layer 9 may be provided on a side of the first encapsulation layer 8 away from the second encapsulation layer 7 and cover the fan-out wiring layer 3. The conductive column layer is at least partially formed in the dielectric layer 9 and may include a first conductive column 5 and a second conductive column 6. The first conductive column 5 is electrically connected to the buried line 401, and the second conductive column 6 is electrically connected to the second fan-out line 302. Optionally, in a direction perpendicular to the thickness direction of the chip 1, the first conductive column 5 is located on a side of the second conductive column 6 away from the chip 1. The material of the first encapsulation layer 8 may include a photosensitive material.

[0088] The semiconductor packaging method and the semiconductor packaging structure provided in the embodiments of the present disclosure belong to the same inventive concept, and the descriptions of the relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0089] The above is only a preferred embodiment of the present disclosure and does not limit the present disclosure in any form. Although the present disclosure has been disclosed as a preferred embodiment as above, it is not used to limit the present disclosure. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A semiconductor packaging method, characterized in that: include: Providing a chip, the chip comprising a first pin and a second pin; forming a first encapsulation layer around the chip; forming an embedded wiring layer at least on one side of the first encapsulation layer, the embedded wiring layer comprising embedded wires; forming a second encapsulation layer covering the first encapsulation layer and the embedded wiring layer, wherein the second encapsulation layer forms a containing cavity in a region corresponding to the chip; A fan-out wiring layer is formed on a side of the first encapsulation layer facing away from the second encapsulation layer, wherein the fan-out wiring layer is electrically connected to the embedded wiring layer and the pins of the chip; The fan-out wiring layer comprises: A first fan-out line, electrically connected to the embedded line and a first pin of the chip; A second fan-out line, insulated from the first fan-out line and electrically connected to a second pin of the chip; The first fan-out line and the second fan-out line are arranged in the same layer.

2. The semiconductor packaging method according to claim 1, wherein: Forming a first encapsulation layer around the chip includes: Providing a carrier board, forming a first encapsulation layer on the carrier board and mounting the chip, wherein the first encapsulation layer surrounds the chip, and the back side of the chip faces away from the carrier board; Forming an embedded wiring layer at least on one side of the first encapsulation layer comprises: forming an embedded wiring layer at least on a side of the first encapsulation layer facing away from the carrier board; Forming a fan-out wiring layer on a side of the first encapsulation layer facing away from the second encapsulation layer comprises: The carrier board is removed, and a fan-out wiring layer is formed on a surface of the first encapsulation layer facing away from the second encapsulation layer.

3. The semiconductor packaging method according to claim 1 or 2, characterized in that: Forming an embedded wiring layer at least on one side of the first encapsulation layer comprises: forming a plurality of via holes on the first encapsulation layer, and forming an embedded wiring layer on one side of the first encapsulation layer and in the via holes; or forming a recessed portion on the first encapsulation layer, forming a plurality of via holes on a bottom wall of the recessed portion, and forming an embedded wiring layer filling the recessed portion and the via holes in the recessed portion and the via holes; or A recessed portion is formed on the first encapsulation layer, a plurality of vias are formed on the bottom wall of the recessed portion, and a step structure is formed on the side wall of the recessed portion; an embedded wiring layer covering the bottom wall of the recessed portion and filling the vias is formed in the recessed portion and in the vias.

4. The semiconductor packaging method according to claim 1, wherein: The fan-out wiring layer also includes: A third fan-out line is provided on a surface of the first encapsulation layer facing away from the second encapsulation layer and is electrically connected to the embedded line; The semiconductor packaging method further comprises: Forming a conductive column layer, the conductive column layer comprising a first conductive column and a second conductive column, the first conductive column being arranged on a surface of the third fan-out line facing away from the second encapsulation layer and being electrically connected to the third fan-out line; the second conductive column being arranged on a surface of the second fan-out line facing away from the second encapsulation layer and being electrically connected to the second fan-out line; A dielectric layer covering the fan-out wiring layer and the first encapsulation layer is formed, wherein the dielectric layer surrounds the first conductive pillar and the second conductive pillar.

5. The semiconductor packaging method according to claim 1, wherein: Forming a first encapsulation layer around the chip includes: A first encapsulation layer is formed, and a first window is formed in the first encapsulation layer, and the chip is disposed in the first window.

6. A semiconductor packaging structure, characterized in that: include: A chip, wherein the chip comprises a first pin and a second pin; An encapsulation body encapsulating the chip and comprising a first encapsulation layer and a second encapsulation layer stacked; An embedded wiring layer, disposed between the first encapsulation layer and the second encapsulation layer, the embedded wiring layer comprising embedded wires; A fan-out wiring layer, disposed on a surface of the first encapsulation layer facing away from the second encapsulation layer, and electrically connected to the embedded wiring layer and the pins of the chip; The fan-out wiring layer comprises: A first fan-out line, electrically connected to the embedded line and a first pin of the chip; A second fan-out line, insulated from the first fan-out line and electrically connected to a second pin of the chip; The first fan-out line and the second fan-out line are arranged in the same layer.

7. The semiconductor package structure according to claim 6, characterized in that: The surface of the second encapsulation layer facing the first encapsulation layer has an accommodating cavity; The chip is arranged in the accommodating cavity, and the front side of the chip faces away from the accommodating cavity and is located outside the accommodating cavity; The embedded wiring layer is arranged in a region outside the accommodating cavity.

8. The semiconductor package structure according to claim 6, wherein: The semiconductor packaging structure further includes: A dielectric layer, disposed on a side of the first encapsulation layer away from the second encapsulation layer and covering the fan-out wiring layer; A conductive column layer is at least partially formed in the dielectric layer, and the conductive column layer includes a first conductive column and a second conductive column, wherein the first conductive column is electrically connected to the buried line, and the second conductive column is electrically connected to the second fan-out line.

9. The semiconductor package structure according to claim 6 or 7, characterized in that: The first encapsulation layer is provided with a plurality of via holes, and the embedded wiring layer fills each of the via holes; or The first encapsulation layer is provided with a recessed portion, a bottom wall of the recessed portion is provided with a plurality of via holes, and the embedded wiring layer is formed in the recessed portion and the via holes and fills the recessed portion and the via holes; or The first encapsulation layer is provided with a recessed portion, a bottom wall of the recessed portion is provided with a plurality of vias, a side wall of the recessed portion is formed with a step structure, the embedded wiring layer is formed in the recessed portion and in the vias and covers the bottom wall of the recessed portion and fills the vias.

10. The semiconductor package structure according to claim 6 or 7, characterized in that: The material of the first encapsulation layer includes a photosensitive material.

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