Method for manufacturing an interconnect structure

Abstract

The present disclosure relates to a method for manufacturing an interconnect structure. A method for manufacturing a dual damascene interconnect comprises the following operations: depositing a metal hard mask over a dielectric layer; etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer to expose a top surface of a base conductive layer; modifying a sidewall of the metal hard mask opening; and depositing a conductive material in the metal hard mask opening and at least one interconnect opening.

Description

Technical Field

[0001] The present disclosure relates to methods for fabricating interconnect structures. Background Art

[0002] Dual damascene interconnects provide reliable interconnects between the various layers of an integrated circuit. Voids in the interconnects increase resistance and reduce the overall reliability of the integrated circuit, and can reduce the clock speed of the device. Summary of the invention

[0003] According to one embodiment of the present disclosure, a method for manufacturing an interconnect structure is provided, comprising: depositing a metal hard mask above a dielectric layer; etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer to expose a top surface of a base conductive layer; modifying the sidewalls of the metal hard mask opening by adding non-metallic atoms to a metallic layer of the metal hard mask; and depositing a conductive material in the metal hard mask opening and the at least one interconnect opening.

[0004] According to another embodiment of the present disclosure, a method for manufacturing an interconnect structure is provided, comprising: depositing a dielectric layer above a first copper interconnect structure; depositing a metal hard mask above the dielectric layer; etching a metal hard mask opening in the metal hard mask; etching a first portion of the interconnect structure opening in the dielectric layer; etching a second portion of the interconnect structure opening in the dielectric layer; modifying the sidewalls of the metal hard mask opening by heat treating the metal hard mask; and depositing a conductive material in the interconnect structure opening through the metal hard mask opening.

[0005] According to another embodiment of the present disclosure, a method for manufacturing an interconnect structure is provided, comprising: depositing a dielectric layer above a substrate; depositing a hard mask layer above the dielectric layer; exposing a top surface of the dielectric layer through an opening in the hard mask layer; etching an interconnect opening in the dielectric layer; modifying the sidewalls of the hard mask layer opening; and filling the interconnect opening with a conductive material through the hard mask layer opening having the modified sidewalls. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A-1Bis a cross-sectional view of a semiconductor device during a manufacturing process according to some embodiments.

[0008] Figure 2 is a cross-sectional view of a semiconductor device having a sloped sidewall profile during a manufacturing process according to some embodiments.

[0009] Figure 3 is a cross-sectional view of a semiconductor device having copper interconnects during a manufacturing process according to some embodiments.

[0010] Figure 4 is a cross-sectional view of a semiconductor device having copper interconnects during a manufacturing process according to some embodiments.

[0011] Figure 5 is a flow chart of a method of manufacturing a copper interconnect according to some embodiments.

[0012] Figure 6 is a cross-sectional view of multiple layers of an integrated circuit during a manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. Other components, values, operations, materials, arrangements, etc. are considered. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] When manufacturing a semiconductor device or integrated circuit with dual damascene interconnects, the conductive material added to the dual damascene structure opening is added in at least two processes. After forming grooves and via openings in one or more layers of dielectric material, a layer of seed material is deposited into the grooves and via openings. Before adding bulk conductive material to the dual damascene structure, a layer of seed material is also deposited on the conductive material below at the bottom of the dual damascene structure opening. In some cases, the seed material or seed layer is sputtered onto the sidewalls of the dual damascene structure and onto the exposed portion of the conductive material below. In some embodiments, the seed layer includes pure copper or a copper alloy. The bulk conductive material is filled into the dual damascene structure opening by electroplating, which produces a filled dual damascene structure and a layer of conductive material located on the top surface of the tube core forming the dual damascene structure. In some embodiments, the electroplated bulk conductive material is copper or a copper alloy. In some embodiments, the seed layer and the electroplated bulk conductive material are the same alloy. In some cases, the seed layer and the electroplated bulk conductive material are different materials to promote adhesion of the seed layer to a liner on the sidewalls of the dual damascene structure and / or to reduce voids in the electroplated bulk conductive material.

[0016] Because the electroplating of the conductive material is sensitive to the diffusion rate of the material into the opening (e.g., the dual damascene structure), obstacles or features that promote the deposition of a non-uniform seed layer during the electroplating process can affect the flow of dissolved ions of the conductive material into the dual damascene structure. The restriction of the ions of the conductive material into the opening causes voids to form in the resulting interconnect structure, while the resistance of the interconnect structure increases beyond the threshold interconnect structure resistance of the integrated circuit.

[0017] Reducing and / or eliminating voids in an interconnect structure results in an overall lower resistance of the integrated circuit including the interconnect structure. Lower resistance also contributes to faster overall switching times for transistors of the integrated circuit.

[0018] FIG. 1 is a cross-sectional view of a semiconductor device 100 during a manufacturing process according to some embodiments. Figure 5 1 is a flow chart of a method 500 of manufacturing a copper interconnect according to some embodiments. The operations of the method 500 are described below, and the description always refers to FIG. 1-1 (as representative of an embodiment of the present disclosure). Figure 4 The dual damascene trench structure and copper interconnect structure are used as the components.

[0019] Semiconductor device 100 includes a dual damascene structure 101 located above a base conductive layer 114. An etch stop layer 112 is located above the base conductive layer 114, and a dielectric layer 110 is located above the etch stop layer 112. In some embodiments, base conductive layer 114 is a contact. In some embodiments, base conductive layer 114 is a metal line. In some cases, base conductive layer 114 is a dual damascene type interconnect located in a lower layer of an integrated circuit. Therefore, a base conductive layer stack is formed by sputtering or plating to accommodate the profile of the opening to be filled and the integration scheme used in manufacturing the integrated circuit. In some embodiments, the base conductive layer is a contact located in a lower layer of the semiconductor device. In some embodiments, the base conductive layer is a metal line located on a lower layer of the semiconductor device. In some embodiments, the base conductive layer is a dual damascene structure located in different layers of the semiconductor device.

[0020] Etch stop layer 112 includes one or more layers of dielectric material having a lower etch selectivity to the etching process (compared to dielectric layer 110, under etching conditions to form interconnect openings in the dielectric layer). In some cases, the etch stop layer is composed of one or more layers of silicon nitride or silicon oxynitride deposited on the lower dielectric layer and directly below dielectric layer 110.

[0021] The dielectric layer 110 is an interlayer dielectric layer (ILD) deposited above the etch stop layer 112. The dielectric layer 110 is etched to form an opening for forming an interconnect structure therein. The interconnect structure includes a dual damascene interconnect structure having a via region and a bar / trench region. The dual damascene structure 101 has a trench opening in an upper region 116C and two or more via openings in a lower region 116D. According to some embodiments, the thickness of the upper region 116C and the thickness of the lower region 116D are approximately the same thickness. In some embodiments, the thickness of the upper region 116C and the thickness of the lower region 116D are different thicknesses. In some embodiments, the thickness of the upper region 116C is less than the thickness of the lower region 116D.

[0022] The dielectric layer 110 includes silicon dioxide, spin-on glass, borophosphorus spin-on glass (BPSG), fluorinated silica glass (FSG), or an organic low-k dielectric material (including, for example, silicon, oxygen, carbon, and hydrogen). Non-limiting examples of integrated circuits having organic low-k dielectric materials include low-k dielectric materials such as BLACK Porous silicon, etc. The material used for the dielectric layer 110 depends on the spacing and width between adjacent lines (or trenches) in the dielectric layer. Silicon dioxide is an example of a dielectric material that is deposited on the contact etch stop layer (CESL) by chemical vapor deposition (CVD). Chemical vapor deposition techniques include plasma enhanced chemical vapor deposition (PE-CVD), high pressure chemical vapor deposition (HP-CVD), etc. BPSG, FSG, and various low-K dielectric materials are deposited on the contact etch stop layer by various methods, including depositing a liquid matrix and then spinning the wafer to remove excess material, leaving a thin film of dielectric material on the substrate. Some examples of low-K dielectric materials are deposited onto the contact etch stop layer or other substrates by techniques similar to PE-CVD, where the dielectric material is the result of a chemical reaction in a plasma above the substrate where the deposition occurs.

[0023] In some embodiments, the dielectric layer 110 is a single film deposited in one process. In some embodiments, the dielectric layer 110 includes a plurality of dielectric materials deposited over the etch stop layer 112. The anti-reflective layer 106 of the metal hard mask 108 is located over the dielectric layer 110. In some embodiments, the anti-reflective layer 106 directly abuts against the top surface of the dielectric layer 110. The dual damascene structure 101 includes two openings 116A and 116B extending through the metal hard mask 108, the dielectric layer 110, and the etch stop layer 112 to expose the top surface of the base conductive layer 114.

[0024] Method 500 includes operation 505, wherein a metal hard mask (e.g., metal hard mask 108) is deposited above dielectric layer 110. Metal hard mask 108 includes anti-reflection layer 102, metallic layer 104A (e.g., metal nitride layer) and anti-reflection layer 106. In certain embodiments, metal hard mask includes a single anti-reflection layer and a metallic layer, rather than two anti-reflection layers and a metallic layer. When there are two anti-reflection layers in the metal hard mask, the first anti-reflection layer is located above the metallic layer, and the second anti-reflection layer is located below the metallic layer. In dual damascene structure 101, anti-reflection layers 102 and 106 located above and below metallic layer 104A are used to improve the photolithography of the metallic layer. Improved photolithography includes uniformity increased in opening width, improved flatness of opening edge and more vertical opening sidewall. In certain embodiments, a single anti-reflection layer is present above the metallic layer. In certain embodiments, a single anti-reflection layer is present below the metallic layer. The anti-reflective layer adjusts the photolithography process to achieve uniform line shape and profile of the sidewalls of the metallic layer or the underlying dielectric layer.

[0025] The number of anti-reflection layers included in the metal hard mask depends on the difficulty associated with passing through the metal hard mask and forming an opening in the dielectric layer below. For some combinations of dielectric layers and metal hard masks, a single anti-reflection layer located below the metallic layer is sufficient to maintain the uniform sidewall profile and line shape of the opening. When the sidewall of the opening through the nitride layer or in the dielectric layer has lateral vibration or wavy shape, a second anti-reflection layer is included to improve the shape of the opening through the metallic layer and into the dielectric layer.

[0026] According to some embodiments, metallic layer 104A is a titanium nitride layer, although nitrides of other metals are also contemplated within the scope of the present disclosure. Other metals used to make nitride layers for hard masks include, but are not limited to, titanium, zirconium, tantalum, niobium, vanadium, tungsten, chromium, cobalt, nickel, silicon, and zinc.

[0027] Metallic layer 104A has a thickness in the range of about 10nm to about 100nm. The thickness of the metallic layer greater than 100nm increases the cost of manufacturing integrated circuits, without producing additional benefits in terms of the line smoothness of the groove or through-hole of the improved dual-damascene structure. The metallic layer less than 10nm thick cannot resist the sufficiently long time of etching process, is not enough to fully reduce or prevent the accidental line roughness of the groove or through-hole of the dual-damascene structure. In addition, the metallic layer less than 10nm thick shows thickness variation, which affects the etching time of penetrating the metal hard mask layer, and can not change the depth of etching into the dielectric layer below. When the metal hard mask etching process penetrates the metal hard mask and enters the dielectric layer, the depth of the groove portion of the interconnect opening is uneven across the die, so that the circuit specifications of the interconnect structure resistance and the entire circuit are biased.

[0028] The anti-reflection layer 102 is deposited on the top of the dielectric layer 110 or the metallic layer 104A to create a more uniform structure developed by photolithography. The anti-reflection layer reduces and / or eliminates the swing curve, the standing wave in the photoresist, and the line width variation of the patterned line. The anti-reflection layer (e.g., anti-reflection layer 102, 106) helps to produce an interconnection with resistance and other electrical characteristics that meet the design specifications of the integrated circuit. The deviation of the interconnection structure electrical performance and the design specifications can have an adverse effect on the integrated circuit. Such deviations include increased resistance, slower switching time, parasitic capacitance, and electromigration. The anti-reflection layer 102, 106 each has a thickness of about 10nm to about 100nm. When the anti-reflection layer is thinner than about 10nm, in the integrated circuit manufacturing process, the anti-reflection layer cannot provide enough protection to prevent the above-mentioned lithography defects. When the anti-reflection layer is thicker than about 100nm, the anti-reflection layer will not provide additional benefits, but will consume more materials and increase the complexity of manufacturing integrated circuits. The increased complexity of manufacturing integrated circuits is associated with the processes of developing the photoresist, removing the photoresist, removing the anti-reflective layer, and cleaning residual particles from the surface during the manufacturing process. In some embodiments, the anti-reflective layer is a BARC layer, a topside ARC layer, or a DARC layer. In some cases, the anti-reflective layer does not contain nitrogen.

[0029] The method 500 includes an operation 510 in which an opening is etched in a metal hard mask. The opening in the hard mask is formed by depositing a layer of patterned material (e.g., photoresist) on a top surface of the metal hard mask, forming a pattern in the layer of patterned material (e.g., by photolithography, or electron beam lithography), and removing a portion of the pattern to expose a top layer of the metal hard mask. Etching the opening in the metal hard mask includes one or more plasma etching steps to remove portions of the hard mask exposed within the opening of the overlying patterned layer. The chemistry, pressure, and power settings of the plasma etching step for removing portions of the metal hard mask are adjusted based on the material of the metal hard mask and the size of the opening in the overlying patterned layer.

[0030] Method 500 also includes operation 515, in which at least one interconnect opening is formed below the metal hard mask. According to some embodiments, the interconnect opening extends through two layers of the metal hard mask, the dielectric layer, and the CESL in the semiconductor film stack. The interconnect opening is formed in multiple steps. One step of the operation of forming the interconnect opening includes: at least one etching process for forming one or more openings in the metal hard mask layer (e.g., metal hard mask 108). In some embodiments, one step of the operation for forming the interconnect opening includes: forming a trench in the upper portion of the dielectric layer, and then forming a through hole extending through the lower portion of the dielectric layer. In some cases, the through hole is formed first, and then the trench portion of the interconnect opening is formed. For the purpose of this discussion, the description of the operation for forming the interconnect opening will include a trench priority scheme, as described below, although the present disclosure also contemplates a through hole priority scheme. In some embodiments, one step of the operation for forming the interconnect opening also includes: forming an opening in the CESL located below the dielectric layer to expose the conductive base layer.

[0031] In a trench-first approach for making interconnect openings, the openings 116A, 116B in the metal hard mask 108 correspond to the profile of the trenches to be formed in the upper portion 116C of the dielectric layer 110. In the dual damascene structure 101, the upper portion 116C includes an opening in the upper portion of the dielectric layer 110 and an opening in the metal hard mask 108.

[0032] Once the trenches have been formed in the upper region 116C, any residual patterned material remaining on the top surface of the metal hard mask 108 is removed, and a second layer of patterned material is deposited on the top surface of the metal hard mask and within the trench openings in the upper region 116C. During the second patterning step, portions of the second patterned material are removed from the top surface of the metal hard mask 108 or from areas within the upper region 116C to form a second pattern on the die surface for etching vias. After forming the pattern in the second patterned material, a second etching process is performed to form vias in the lower region 116D. As shown in the dual damascene structure 101, the lower region 116D includes a lower portion of the dielectric material 110 and the etch stop layer 112. After the etching process for forming the vias in the lower region 116D, the second patterned material is removed from the die surface.

[0033] The dual damascene structure 101 is an unfilled structure in which two openings 116A and 116B extend through the metal hard mask 108 to expose some of the base conductive layer 114. The openings 116A and 116B of the dual damascene structure 101 have different diameters at positions above the base. Moving downward from the top surface of the metal hard mask, the openings 116A and 116B have a first width 118A at the level of the anti-reflective layer 102, a second width 118B at the level of the metallic layer 104A, a third width 118C at the interface of the dielectric layer 110 and the anti-reflective layer 106, a fourth width 118D at the bottom of the trench region 116C of the openings 116A and 116B, a fifth width 118E at the top of the via region 116D of the openings 116A and 116B, and a sixth width 118F at the bottom of the via region 116D. Moving downward again, the first width 118A is greater than the second width 118B, the second width 118B is greater than the third width 118C, the third width 118C is greater than the fourth width 118D, the fourth width 118D is greater than the fifth width 118E, and the fifth width 118E is greater than the sixth width 118F.

[0034] The sidewall 122A of anti-reflection layer 102 is not vertically aligned with the sidewall 122B of metallic layer 104A, as shown in the different widths 118A and 118B of opening 116A.Therefore, at the interface 120 between anti-reflection layer 102 and metallic layer 104A, step or " kink (kink)" is set so that the top surface 124 of metallic layer is exposed in the opening of dual inlay structure.When exposing the top surface 124 of metallic layer 104A, the seed layer of conductive material enters the position of the top surface 124 exposed at the step of the deposition of the dual inlay structure opening and is carried out more quickly.Therefore, during the deposition of seed layer, the seed layer growth is uneven.The fastest position of seed layer growth occurs at the position of the top surface 124 exposed, so that after seed layer deposition, the opening of dual metal inlay structure has a smaller diameter compared with the bottom of dual metal inlay structure.In the present disclosure, method 500 describes the process of forming interconnect structure when there is no above-mentioned non-uniform seed layer deposition.

[0035] According to some embodiments, method 500 includes operation 520, wherein a portion of the metal hard mask is modified to produce an inclined sidewall. In operation 520, the metal hard mask is modified by the following operations: the metal hard mask is processed to diffuse non-metal atoms into the metallic layer (or in some embodiments, the metal layer) to produce a material stack with different lattice constants at different positions in the material stack. As the lattice constant of the material changes, the size of the material also changes. In the present disclosure, adding non-metal atoms to the metal layer or metallic layer increases the lattice constant, and corresponds to the swelling or expansion of the metallic layer when the non-metal atoms are doped.

[0036] Processing metal hard mask includes annealing process and / or plasma process for heating metal hard mask. Plasma process also includes generating ionized atoms above the surface of semiconductor device during process, and the ionized atoms penetrate into one or more layers of metal hard mask to change the composition and shape of metal hard mask. As mentioned above, new layer or poisoned layer includes the composition of both metallic layer and anti-reflective layer, and has inclined sidewall to replace the step of metallic layer 104A or the exposed upper surface 124. Poisoning layer or material refers to modifying layer by diffusion of atoms from adjacent layer into poisoned layer.

[0037] Figure 1B is a cross-sectional view of a semiconductor device 150 during a manufacturing process according to some embodiments. Figure 1A The corresponding components Figure 1B The elements have the same reference numerals. It will be understood by those skilled in the art that the present disclosure relates to other embodiments different from the embodiment shown herein, and the features described herein are for convenience in describing the scope of the present disclosure and the method of manufacturing a semiconductor device.

[0038] Figure 1B A metal hard mask 104B including a surface 104C treated with non-metallic atoms. According to some embodiments, the metal hard mask 104B is deposited above the dielectric layer 110 and subsequently treated with non-metallic atoms to modify the interface between the metallic layer and one or more anti-reflective layers so that a portion of the metal hard mask 104B is converted into a metal region 104C rich in non-metallic atoms. In some embodiments, the process of adding non-metallic atoms to a layer including a metal hard mask is referred to as poisoning the layer. In some embodiments, the metal hard mask 104B is enriched with non-metallic atoms by the following operation: exposing the sidewall 122B of the metal hard mask 104B to a plasma of dissociated non-metallic atoms in the absence of oxygen, so that the atoms generated in the plasma are accelerated toward the exposed surface of the metal hard mask and penetrate into the metal hard mask. In some embodiments, the non-metallic atom is a nitrogen atom. In some embodiments, the non-metallic atom is a mixture of nitrogen and oxygen. For the following discussion, the non-metallic atom discussed is nitrogen, although other atoms can be envisioned in the present disclosure.

[0039] Adding nitrogen to the metal hard mask 104 changes the chemical composition of the metal hard mask layer and changes the lattice constant of the material. According to an embodiment, the lattice constant of the material determines the amount of strain in the material because the material transitions between layers of other materials above and below the material with the modified lattice. In some embodiments, adding a material to modify the lattice constant of the material causes the material to expand or increase in size because the lattice constant is larger after the modification (e.g., adding nitrogen to the metal hard mask) than before the modification. In some embodiments, adding non-metal atoms to the metal hard mask shrinks the lattice constant, thereby causing the material to shrink. In some embodiments, the metal hard mask is "poisoned" by adding nitrogen from a nitrogen-rich plasma before the anti-reflective layer 106 is opened to expose the substrate 110. In some embodiments, the metal hard mask is "poisoned" by adding nitrogen from a nitrogen-rich plasma after the anti-reflective layer 106 has been opened and the substrate 110 is exposed to the plasma. In addition to the exposed sidewalls of the metal hard mask layer 104B, exposing the substrate 110 to the nitrogen-rich plasma also modifies the exposed portion of the substrate 110. Poisoning the metal hard mask layer 104B before opening the anti-reflective layer 106 prevents modification of the chemical composition and physical structure of the substrate 110, making the etching process to form interconnect openings (see 116A and 116B) more uniform and faster (compared to a substrate rich in nitrogen).

[0040] The nitrogen-rich region 104C covers the entire exposed top and sidewalls of the metal hard mask material in the opening 116A. The nitrogen-rich region 104D covers the exposed top and upper portions of the sidewalls of the metal hard mask material in the opening 116B. The degree of coverage of the nitrogen-rich region on the sidewalls of the metal hard mask 104B varies with the plasma characteristics (e.g., ion acceleration characteristics) of the plasma used to generate the dissociated nitrogen atoms. As the etching plasma becomes more anisotropic, the sidewall coverage increases.

[0041] Figure 2 FIG. 2 is a cross-sectional view of a semiconductor device 200 having a sloped sidewall profile during a manufacturing process according to some embodiments. Figure 2 Elements of the same reference numerals (increased by 100) are provided. The sidewalls of the metal hard mask are modified by heating the antireflective layer and the metallic layer so that compounds from the antireflective layer and the metallic layer penetrate each other. Thus, the antireflective layer 202 and the metallic layer 204, which are directly opposite to each other in FIG. Figure 2The poisoned layers 203 are separated from each other. The anti-reflective layer 202 has an approximately vertical sidewall 221A. The metallic layer 204 has an approximately vertical sidewall 221C. The poisoned layer 203 has a non-vertical but inclined poisoned layer sidewall 221B, bridging the space between the sidewall 221A and the sidewall 221C, which are separated from each other in the lateral direction. The slope of the sidewall 221C is approximately the same as the slope of the sidewall 221D of the trench area in the dielectric 210. In some embodiments, the slope of the sidewall 221C is different from the slope of the sidewall 221D. The sidewall 221F is the upper part of the sidewall of the through-hole area of ​​the interconnect structure opening 216A / 216B, and the sidewall 221G is the sidewall of the lower part of the through-hole area of ​​the interconnect structure. The exposed surface 223 of the base connector layer 214 is located at the bottom of the interconnect structures 216A and 216B. Sidewall 221E is located between sidewalls 221D and 221F. In some embodiments, angle 225 is in the range of 10 degrees to 70 degrees, but other angles may also be considered within the scope of the present disclosure. According to theory and concept, an interconnect structure having an angle 225 less than 20° is prone to forming voids in the metal filling of the interconnect structure. In some embodiments, for angle values ​​less than 20°, the seed layer is deposited in the lower portion of the interconnect structure (e.g., along the portion of sidewall 221F) becomes sporadic or uneven. In embodiments of the interconnect structure in which angle 225 is less than 20°, the metal filling of the interconnect structure is prone to forming voids because the material is unevenly accumulated at the corner between sidewall 221E and sidewall 221F.

[0042] In some embodiments, modifying the metal hard mask sidewalls or poisoning the layers of the metal hard mask includes one or more steps related to annealing and / or treating the metal hard mask in a plasma. When the metal hard mask is poisoned by annealing, the annealing step includes one or more of rapid thermal processing (RTP), pulsed laser annealing, or other rapid annealing processes that facilitate interlayer diffusion of atoms without causing melting of one or more layers of the metal hard mask. Annealing or rapid thermal treatment of the metal hard mask layer involves heating the metal hard mask to a temperature of 600 degrees Celsius to 900 degrees Celsius and for a period of 60 seconds. In some embodiments, the elevated temperature from 600°C to 700°C is maintained for a period of 40 seconds to 60 seconds. In some embodiments, the elevated temperature from 700°C to 800°C is maintained for a period of 20 seconds to 40 seconds. In some embodiments, the elevated temperature from 800°C to 900°C is maintained for a period of 10 seconds to 20 seconds. In some embodiments, the elevated temperature from 900°C to 1000°C is maintained for a period of time from 1 second to 10 seconds. In some embodiments, in order to promote diffusion of atoms without melting the metal hard mask layer, the thermal treatment is performed at a temperature above 1000°C and an exposure time of less than one second is used at the peak temperature. In some cases, the peak temperature of the laser annealing process reaches more than 1300°, and the exposure time is in the order of milliseconds or microseconds.

[0043] In certain embodiments, modifying the metal hard mask sidewalls includes exposing the metal hard mask to nitrogen-containing plasma after forming the interconnect opening. Nitrogen-containing plasma generates nitrogen ions in plasma, which contaminate the exposed anti-reflective layer coating or sidewalls, and heats the metal hard mask to promote metal diffusion out of the metallic layer and into one or more anti-reflective layers present in the metal hard mask. During the exposure of the metal hard mask to nitrogen-containing plasma, little or no etching occurs. Instead, the nitrogen in the plasma is ionized, and the nitrogen ions react with the exposed portion of the anti-reflective layer. The reflective layer (usually an organic layer) is susceptible to the influence of nitrogen absorption of adjacent materials in the plasma or film stack.

[0044] Modify the metal hard mask to form a poisoned layer in the metal hard mask, including forming a poisoned layer with a thickness of about 0.1nm to about 10nm. The poisoned layer less than 0.1nm does not have enough vertical thickness to bridge the lateral gap between the sidewalls of the anti-reflective layer and the metallic layer in the metal hard mask. The poisoned layer with a thickness greater than 10nm will increase the risk of melting of the metal hard mask layer, thereby making it more difficult to partially or completely remove the metal hard mask after the conductive material is deposited into the interconnect opening. The poisoned layer (or the poisoned metal layer) has a composition ratio of metal to non-metal atoms between 0.25:1 and 1:1. When the metal composition ratio is less than 0.25:1, the sidewall of the poisoned metal layer does not have a slope to avoid excessive collection of seed layer materials. When the metal composition ratio is greater than 1:1, the sidewall of the poisoned metal layer has a slope to avoid excessive collection of seed layer materials, but the larger thickness of the poisoned metal layer will not promote the reduction of seed layer uniformity. A poisoned metal layer having a composition ratio of less than 0.25:1 may not adequately mix the metallic layer and the anti-reflective layer to achieve a sloped sidewall compatible with void-free bulk conductive material electroplating.

[0045] The metal compound in the metallic layer 104A has a chemical formula A x B y , wherein A is a metal and B is a non-metal atom. The metal compound (metallic layer) of the metal hard mask has a composition ratio (x:y) of metal to non-metal atoms between 1:1 and 1:3. When the nitrogen composition ratio of the metallic layer is less than 1:1, there is not enough nitrogen in the metallic layer to form a poisoned metallic layer showing reduced seed layer material collection. When the nitrogen composition ratio of the metallic layer is greater than 1:3, the metallic layer does not have enough metal to form a poisoned metallic layer with the anti-reflective layer. In some embodiments, metal A is titanium (Ti), and the non-metal atom is nitrogen (N). In some embodiments, metal atom A is titanium, and the non-metal is a mixture of nitrogen and oxygen (O) such that A x B y It is Ti x N y O z In some embodiments, other combinations of metals and non-metals are used according to semiconductor manufacturing processes known to those skilled in the art.

[0046] Method 500 includes operation 525, wherein a conductive material is deposited into at least one opening in the dielectric layer. When manufacturing a dual damascene structure in an integrated circuit, the conductive material is deposited in several steps. In one step of operation 525, a seed layer of conductive material is sputtered onto the top surface of the metal hard mask 308 and onto the sidewalls 221A-221G of the interconnect structure. Another step of operation 525 includes electroplating the conductive material into the interconnect opening (at least one opening in the dielectric layer). The seed layer (not shown) serves as an electrode for performing an electroplating process. Because the poisoned layer 203 has an inclined sidewall 221B, when the conductive material is electroplated into the interconnect opening, the possibility of forming a void or pocket in the interconnect is less because there is no junction at the level of the interconnect opening corresponding to the level of the poisoned layer 203.

[0047] According to some embodiments, the seed layer (not shown) and the electroplated bulk conductive material are the same material. In some cases, the seed layer and the overall electroplated conductive material are different materials. Conductive materials for forming dual damascene interconnect structures include copper and copper alloys. Copper alloys include copper mixed with aluminum, zinc and other metals to promote uniform electrodeposition of materials within the interconnect opening and reduce the grain size of the electroplated conductive material. In some embodiments after operation 525, one or more layers on the dielectric layer are removed by, for example, chemical mechanical polishing (CMP) to prepare for the deposition of another dielectric material (e.g., a contact etch stop layer (for example, a dual damascene structure), or a dielectric layer in which a conductor is to be manufactured) of the integrated circuit.

[0048] Figure 3 is a cross-sectional view of a semiconductor device 300 having a copper interconnect structure 301 according to some embodiments. Figure 2 Components similar to Figure 3 316C and 316D. The interconnect structures 316A and 316B have line regions 316C and via regions 316D. The regions 316D of each interconnect structure are electrically connected to the base conductor 314.

[0049] Because the poisoned layer 303 has sloped sidewalls 321B, depositing a seed layer 326 of conductive material (copper or copper alloy) onto the sidewalls of the interconnect openings does not create a pinch point at the top of the interconnect openings. By eliminating the formation of pinch points at the tops of the interconnect openings, the interconnect structures 318A and 318B do not have voids or recesses therein. In some embodiments, after etching through the dielectric material, the seed layer 326 is deposited into the interconnect openings (see FIG. Figure 2 216B) to prevent oxidation of the exposed metal of the base conductor 314 (e.g., a metal-filled via or trench in a lower level of the semiconductor device). By depositing the seed layer immediately after exposing the metal of the base conductor 314, the formation of metal oxides on the base conductor is reduced, which reduces the resistance at the interface at the bottom of the interconnect after metal filling occurs. In some embodiments, the seed layer covers the anti-reflective layer 302, the poisoned layer 303, the metal hard mask 304, and the inner sidewalls of the anti-reflective layer 306. In some embodiments, the poisoned layer 303 is the inner sidewall of the metal hard mask 304 (see Figure 1B In some embodiments, the poisoned layer is the top portion of the exposed metal hard mask 104 material (see Figure 1B Component 104D).

[0050] Figure 4 is a cross-sectional view of a semiconductor device 400 having a copper interconnect structure 401 according to some embodiments. The method 500 includes an operation 530, wherein the copper interconnects formed in the operation 530 are electrically isolated from each other. The electrical isolation of the copper interconnect structure is achieved by a chemical mechanical polishing (CMP) process performed on the top surface of the die or semiconductor wafer. When the interconnect is placed laterally (see Figure 4 Electrical isolation of the copper interconnects is considered complete when there is significantly less material between the interconnects 418A and 418B).

[0051] exist Figure 4 1 , elements similar to the structure previously described in FIG. 1 share the same reference numerals (increased by 300). Interconnect 418A and interconnect 418B extend through metal hard mask 408, dielectric material 410, and etch stop layer 412 to make electrical connections with base conductive layer 414. Interconnect 418A has an upper portion 418A1 having a first width W1 at the top of upper portion 418A1. The first width corresponds to the uppermost portion of upper portion 418A1, which is at the same vertical distance from substrate 410 as compared to poisoned layer 403. The first width W1 is greater than the width of the remainder of upper portion 418A1. Strip regions 416C of dual-damascene interconnect structures 418A and 418B are formed in the groove portions of the interconnect structure openings. The through-hole regions 416D of interconnect structures 418A and 418B extend through the lower region of dielectric layer 410. Depending on the material of the metallic layer, Figure 4The metal hard mask 408 shown is optionally removed from the top surface of the dielectric layer 410. In some embodiments, the metal hard mask 408 includes a silicon nitride layer, and after removing bulk conductive material (e.g., electroplated copper) from the top surface of the metal hard mask, the metal hard mask is retained, thereby isolating the dual damascene interconnect structures from each other. The silicon nitride layer does not have a sufficiently high electrical conductivity to allow current to flow between the interconnect structures. The metallic layer including, for example, titanium nitride has enough electrical conductivity so that the metallic layer is removed to prevent leakage current between the interconnect structures. The metallic layer is removed from the top surface of the dielectric layer 410 by, for example, chemical mechanical polishing (CMP).

[0052] Figure 6601 is a cross-sectional view of various layers of an integrated circuit 600 during a manufacturing process according to some embodiments. The present disclosure relates to an integrated circuit formed by a method that smoothes the sidewalls of an integrated circuit interconnect opening before filling the interconnect opening with a metal to form an interconnect structure (e.g., a through hole in a dual damascene structure of a trench and layer of an integrated circuit). Integrated circuit 600 has an interface 606 between a first layer 602 and a second layer 604. In some embodiments, the first layer is a metallic layer and the second layer is an anti-reflective layer. In some embodiments, the first layer is an anti-reflective layer and the second layer is a metallic layer. The metallic layer is a layer such as a metal nitride or metal oxynitride layer. In structure 601, the first and second layers are depicted before heat treatment to smooth the sidewalls. Structure 610 depicts a first layer 612 (compared to the first layer 602) and a second layer 614 (compared to the second layer 604) after the structure undergoes heat treatment. Thermal treatment of structure 601 generates a "poisoned" layer at the location of interface 601, where materials from the first layer and the second layer diffuse into each other to form a third material or interface layer 616, whose properties are between those of the first layer 612 and the second layer 614. The properties of interface layer 616 that are between those of the first layer 612 and the second layer 614 are (1) chemical composition and (2) lattice constant. The chemical composition of the interface layer ranges from the composition of the first layer 612 located on the top side of the interface layer to the chemical composition of the second layer 614 located on the bottom side of the interface layer. The variation in chemical composition over the vertical thickness of interface layer 616 causes the lattice constant of the interface film to vary over the vertical thickness of the interface. By diffusing the materials of the two thin films into each other, the intermediate layer smoothly transitions the sidewall profile from the first layer to the second layer to remove kinks associated with different opening diameters in the interconnect layer opening (before metal deposition) at different layers of the metal hard mask (e.g., metal / metallic layer, and an anti-reflective layer). In certain embodiments, the first layer is a metallic layer (metal layer or metal nitride layer), and the second layer is an anti-reflection layer. In certain embodiments, the first layer is an anti-reflection layer, and the second layer is a metallic layer. No matter whether the anti-reflection layer of the metallic layer is located at the top of the film stack, the thermal treatment described in the method of the present disclosure is all used to make the kink at the interface of the metallic layer and the anti-reflection layer smooth.

[0053] A method comprising the following operations: depositing a metal hard mask over a dielectric layer; etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer to expose a top surface of a base conductive layer; modifying the sidewalls of the metal hard mask opening; depositing a conductive material in the metal hard mask opening and at least one interconnect opening. In some embodiments, the method further comprises: removing a portion of the conductive material located on the top surface of the metal hard mask. In some embodiments, the method further comprises: removing the metal hard mask to electrically isolate the conductive material in each of the at least one interconnect opening. In some embodiments, depositing the metal hard mask further comprises: depositing a first anti-reflective layer over the dielectric layer; and depositing a metallic layer over the dielectric layer. In some embodiments, the method further comprises: depositing a second anti-reflective layer over the dielectric layer such that the metallic layer is located between the first anti-reflective layer and the second anti-reflective layer. In some embodiments, etching at least one interconnect opening further comprises: etching at least one trench in the dielectric layer through the metal hard mask opening; depositing a layer of mask material over the metal hard mask and in the at least one trench; patterning the mask material to form an opening through the mask material in the at least one trench; etching at least one through hole through the dielectric layer to expose the base conductive layer located below the dielectric layer. In some embodiments, depositing the conductive material further comprises: depositing a seed layer on the sidewalls of the metal hard mask, the trench sidewalls of at least one trench, and the through hole sidewalls of at least one through hole. In some embodiments, modifying the sidewalls of the metal hard mask opening further comprises: annealing the metal hard mask to diffuse metal atoms of the metallic layer into the first anti-reflective layer, wherein the metallic layer is located between the first anti-reflective layer and the dielectric layer. In some embodiments, modifying the sidewalls of the metal hard mask opening further comprises: exposing the first anti-reflective layer and the metallic layer to a nitrogen-containing plasma.

[0054] Aspects of the present disclosure relate to a method of manufacturing an interconnect structure, comprising: depositing a dielectric layer over a first copper interconnect structure; depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask; etching a first portion of the interconnect structure opening in the dielectric layer; etching a second portion of the interconnect structure opening in the dielectric layer; poisoning a layer of the metal hard mask located over the dielectric layer; and depositing a conductive material in the interconnect structure opening through the metal hard mask opening. In some embodiments, depositing the metal hard mask further comprises: depositing a first anti-reflective layer on a metallic layer located over the dielectric layer. In some embodiments, poisoning the layer of the metal hard mask further comprises: annealing the metal hard mask so that the metallic layer and the first anti-reflective layer diffuse into each other. In some embodiments, poisoning the layer of the metal hard mask further comprises: exposing the layer of the metal hard mask to a nitrogen-containing plasma. In some embodiments, depositing the conductive material further comprises: sputtering a copper seed layer on the sidewalls of the poisoned metal hard mask and the sidewalls of the interconnect structure opening located in the dielectric layer. In some embodiments, etching a second portion of the interconnect structure opening in the dielectric layer further comprises: depositing a mask layer over the metal hard mask and the first portion of the interconnect structure opening; patterning the mask layer so that the opening extends into the first portion of the interconnect structure; and etching a lower portion of the dielectric layer.

[0055] Aspects of the present disclosure relate to a device comprising: a metal hard mask layer located above a dielectric layer; and an interconnect structure extending through the metal hard mask layer and the dielectric layer and electrically connected to a base conductive layer located below the dielectric layer; wherein the metal hard mask layer has a poisoned layer. In some embodiments of the device, the metal hard mask further comprises: a metallic layer abutting the poisoned layer. In some embodiments, the interconnect structure has a first diameter at the top layer of the metal hard mask, a second diameter at the metallic layer of the metal hard mask, and a third diameter at the poisoned layer of the metal hard mask, wherein the third diameter is smaller than the first diameter and larger than the second diameter. In some embodiments, the interconnect structure further comprises copper or a copper alloy. In some embodiments, the metallic layer further comprises titanium nitride.

[0056] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0057] Example 1. A method for manufacturing an interconnect structure, comprising: depositing a metal hard mask above a dielectric layer; etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer to expose a top surface of a base conductive layer; modifying the sidewalls of the metal hard mask opening by adding non-metallic atoms to a metallic layer of the metal hard mask; and depositing a conductive material in the metal hard mask opening and the at least one interconnect opening.

[0058] Example 2. The method according to Example 1 further includes: removing a portion of the conductive material located on the top surface of the metal hard mask.

[0059] Example 3. The method according to Example 2 further includes: removing the metal hard mask.

[0060] Example 4. The method of Example 1, wherein depositing a metal hard mask further comprises: depositing a first anti-reflective layer over the dielectric layer; and depositing the metallic layer over the dielectric layer.

[0061] Example 5. A method according to Example 4, wherein modifying the sidewalls of the metal hard mask opening further comprises: annealing the metal hard mask to diffuse metal atoms of the metallic layer into the first anti-reflective layer, wherein the metallic layer is located between the first anti-reflective layer and the dielectric layer.

[0062] Example 6. The method of Example 4, wherein modifying the sidewalls of the metal hard mask opening further comprises: exposing the first antireflective layer and the metallic layer to a nitrogen-containing plasma.

[0063] Example 7. The method according to Example 4 further includes: depositing a second anti-reflective layer over the dielectric layer so that the metallic layer is located between the first anti-reflective layer and the second anti-reflective layer.

[0064] Example 8. A method according to Example 1, wherein etching the at least one interconnect opening further includes: etching at least one trench in the dielectric layer through the metal hard mask opening; depositing a layer of mask material above the metal hard mask and in the at least one trench; patterning the mask material to form an opening through the mask material in the at least one trench; and etching at least one through-hole through the dielectric layer to expose the base conductive layer located below the dielectric layer.

[0065] Example 9. The method of Example 1, further comprising: changing a slope of the metal hard mask layer by poisoning the metal hard mask layer.

[0066] Example 10. A method for manufacturing an interconnect structure, comprising: depositing a dielectric layer over a first copper interconnect structure; depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask; etching a first portion of the interconnect structure opening in the dielectric layer; etching a second portion of the interconnect structure opening in the dielectric layer; modifying the sidewalls of the metal hard mask opening by heat treating the metal hard mask; and depositing a conductive material in the interconnect structure opening through the metal hard mask opening.

[0067] Example 11. The method of Example 10, wherein depositing the metal hard mask further comprises: depositing a first anti-reflective layer on the dielectric layer, depositing a metallic layer over the first anti-reflective layer, and depositing a second anti-reflective layer over the metallic layer.

[0068] Example 12. The method of Example 11, wherein thermally treating the metal hard mask further comprises annealing the metal hard mask to a temperature between 600 degrees Celsius and 1000 degrees Celsius for an annealing time in a range from 60 seconds to 1 second.

[0069] Example 13. The method of Example 10, wherein poisoning the layer of the metal hard mask further comprises: exposing the layer of the metal hard mask to a nitrogen-containing plasma.

[0070] Example 14. The method of Example 10, wherein depositing a conductive material further comprises: sputtering a copper seed layer on sidewalls of the poisoned metal hard mask and sidewalls of the interconnect structure opening located in the dielectric layer.

[0071] Example 5. The method according to Example 10 further includes: changing the slope of the sidewall of the metal hard mask layer by thermal treatment.

[0072] Example 16. A method for manufacturing an interconnect structure, comprising: depositing a dielectric layer above a substrate; depositing a hard mask layer above the dielectric layer; exposing a top surface of the dielectric layer through an opening in the hard mask layer; etching an interconnect opening in the dielectric layer; modifying the sidewalls of the hard mask layer opening; and filling the interconnect opening with a conductive material through the hard mask layer opening having the modified sidewalls.

[0073] Example 17. The method of Example 16, wherein depositing the hard mask layer further comprises depositing an anti-reflective layer over the dielectric layer, and depositing a metallic layer over the dielectric layer.

[0074] Example 18. The method of Example 17, wherein modifying the sidewalls of the hard mask layer opening further comprises: interlayer diffusion of the anti-reflective layer and the metallic layer.

[0075] Example 19. The method of Example 16, wherein modifying the sidewalls of the hard mask layer opening further comprises annealing the hard mask layer.

[0076] Example 20. The method of Example 18, wherein filling the interconnect opening further comprises: depositing a seed layer on the dielectric layer sidewalls and the hard mask layer opening having the modified sidewalls; and electroplating a conductive material over the seed layer.

Claims

1. A method for manufacturing an interconnect structure, comprising: depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer to expose a top surface of the base conductive layer; modifying the sidewalls of the metal hard mask opening by adding non-metallic atoms to the metallic layer of the metal hard mask and changing the slope of the metal hard mask by poisoning the metal hard mask; as well as A conductive material is deposited in the metal hard mask opening and the at least one interconnect opening.

2. The method according to claim 1, further comprising: A portion of the conductive material located on a top surface of the metal hard mask is removed.

3. The method according to claim 2, further comprising: The metal hard mask is removed.

4. The method according to claim 1, wherein: Depositing a metal hard mask also includes: depositing a first antireflective layer over the dielectric layer; and The metallic layer is deposited over the dielectric layer.

5. The method according to claim 4, wherein: Modifying the sidewalls of the metal hard mask opening further includes annealing the metal hard mask to diffuse metal atoms of the metallic layer into the first anti-reflective layer, wherein the metallic layer is located between the first anti-reflective layer and the dielectric layer.

6. The method according to claim 4, wherein: Modifying the sidewalls of the metal hard mask opening further includes exposing the first antireflective layer and the metallic layer to a nitrogen-containing plasma.

7. The method according to claim 4, further comprising: A second anti-reflective layer is deposited over the dielectric layer such that the metallic layer is between the first anti-reflective layer and the second anti-reflective layer.

8. The method according to claim 1, wherein: Etching the at least one interconnect opening further comprises: etching at least one trench in the dielectric layer through the metal hard mask opening; depositing a layer of mask material over the metal hard mask and in the at least one trench; patterning the mask material to form an opening through the mask material in the at least one trench; and At least one via is etched through the dielectric layer to expose the base conductive layer beneath the dielectric layer.

9. A method of manufacturing an interconnect structure, comprising: depositing a dielectric layer over the first copper interconnect structure; depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask; etching a first portion of an interconnect structure opening in the dielectric layer; etching a second portion of the interconnect structure opening in the dielectric layer; modifying the sidewalls of the metal hard mask opening by thermally treating the metal hard mask, wherein modifying the sidewalls of the metal hard mask opening comprises: poisoning a layer of the metal hard mask, and the poisoning comprises exposing the layer of the metal hard mask to a nitrogen-containing plasma; and A conductive material is deposited in the interconnect structure opening through the metal hard mask opening.

10. The method according to claim 9, wherein: Depositing the metal hard mask further includes depositing a first anti-reflective layer on the dielectric layer, depositing a metallic layer over the first anti-reflective layer, and depositing a second anti-reflective layer over the metallic layer.

11. The method according to claim 10, wherein: Thermally treating the metal hard mask further includes annealing the metal hard mask to a temperature between 600 degrees Celsius and 1000 degrees Celsius for an annealing time ranging from 60 seconds to 1 second.

12. The method according to claim 9, wherein: Depositing the conductive material further includes sputtering a copper seed layer on sidewalls of the poisoned metal hard mask and sidewalls of the interconnect structure opening located in the dielectric layer.

13. The method according to claim 9, further comprising: The slope of the sidewall of the metal hard mask is changed by thermal treatment.

14. A method of manufacturing an interconnect structure, comprising: depositing a dielectric layer over the substrate; depositing a hard mask layer over the dielectric layer; opening through the hard mask layer to expose a top surface of the dielectric layer; etching interconnect openings in the dielectric layer; Modifying the sidewalls of the hard mask layer opening includes: annealing the hard mask layer; as well as The interconnect opening is filled with a conductive material through the hard mask layer opening having the modified sidewalls.

15. The method according to claim 14, wherein: Depositing the hard mask layer further includes depositing an anti-reflective layer over the dielectric layer, and depositing a metallic layer over the dielectric layer.

16. The method according to claim 15, wherein: Modifying the sidewall of the hard mask layer opening further includes: interlayer diffusion of the anti-reflective layer and the metallic layer.

17. The method according to claim 16, wherein: Filling the interconnect opening further comprises: depositing a seed layer on the dielectric layer sidewalls and the hard mask layer opening having the modified sidewalls; and A conductive material is electroplated over the seed layer.

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