semiconductor devices
By designing conductive pillars and pads, the problems of high cost and low yield of high-end packaging products are solved, achieving fine-line connection and electrical reliability, reducing packaging costs and improving the yield of semiconductor devices.
Patent Information
- Application Number
- CN202110219075.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-02-26
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2041-02-26
AI Technical Summary
High-end packaging products are expensive and have low yields, mainly because the packaging structure requires the use of the entire substrate, which makes it impossible to miniaturize the circuitry and requires a multi-layer rewiring structure, increasing costs and yield losses.
The design employs conductive pillars and pads. The conductive pillars include vertical and horizontal extensions, and the pads have a grooved structure. They are connected by conductive adhesive to ensure good bonding between the conductive pillars and the pads. The substrate and fan-out structure are fixed by an adhesive layer to achieve fine line connections.
This has improved the yield of semiconductor devices, reduced packaging costs, reduced issues such as line misalignment and poor contact, and improved the reliability of electrical connections.
Smart Images
Figure CN113161313B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of this application relate to semiconductor devices. Background Technology
[0002] The high cost of high-end packaging products (such as 2.5D / 3D) is mainly due to the requirement of using a full substrate for the packaging structure, with the cost of a single substrate typically accounting for more than 50% of the total price. This high price is because it cannot fabricate finer lines (e.g., linewidth / spacing (L / S) > 10μm / 10μm), necessitating the use of multilayer redistribution (RDL) structures. In fact, more layers can provide more inputs / outputs (I / O), however, the cost and yield losses are relatively higher. Summary of the Invention
[0003] In view of the problems existing in related technologies, the purpose of this invention is to provide a semiconductor device to increase the yield of semiconductor devices.
[0004] To achieve the above objectives, the present invention provides a semiconductor device comprising: a conductive post including a vertical extension and a horizontal extension; a pad having a groove structure; and conductive adhesive located in the groove structure. The conductive post is connected to the pad via the conductive adhesive. The maximum diameter of the vertical extension of the conductive post is smaller than the maximum diameter of the groove structure, the maximum diameter of the groove structure is smaller than the diameter of the horizontal extension, and the diameter of the horizontal extension is smaller than the maximum diameter of the pad.
[0005] In some embodiments, the device further includes: a substrate having pads; and a fan-out structure having conductive pillars, the fan-out structure being fixedly connected to the substrate via an adhesive layer.
[0006] In some embodiments, the device further includes a chip located on the fan-out structure and electrically connected to the substrate via the fan-out structure.
[0007] In some embodiments, the thickness of the adhesive layer is in the range of 15 μm to 30 μm.
[0008] In some embodiments, the linewidth / spacing of the first trace electrically connected to the pad in the substrate is less than 10 μm / 10 μm.
[0009] In some embodiments, the linewidth / spacing of the second trace electrically connected to the conductive post in the fan-out structure is less than 2 μm / 2 μm.
[0010] In some embodiments, the pad is located at the end of the support post of the substrate.
[0011] In some embodiments, the adhesive layer encapsulates the interlocking conductive pillars, conductive adhesive, and pads.
[0012] In some embodiments, multiple conductive posts and multiple pads are connected in a one-to-one correspondence, and the top surfaces of the multiple pads have different heights.
[0013] In some embodiments, a portion of the conductive post is offset relative to its corresponding ground pad.
[0014] In some embodiments, both the conductive post and the pad include a seed layer and a metallic material surrounded by the seed layer, the seed layer being conformal to the metallic material.
[0015] In some embodiments, the thickness of the seed layer is in the range of 0.1 μm to 0.5 μm.
[0016] In some embodiments, the thickness of the metallic material is in the range of 1 μm to 5 μm.
[0017] In some embodiments, the seed layer is made of Ti, W, or Ni.
[0018] In some embodiments, the metallic material includes Cu, Ag, Au, Ni, or Pd.
[0019] In some embodiments, the height of the conductive post is in the range of 10 μm to 30 μm.
[0020] In some embodiments, the diameter of the conductive post is in the range of 10 μm to 30 μm.
[0021] In some embodiments, the bottom surface of the horizontal extension is curved.
[0022] In some embodiments, the conductive adhesive is solder.
[0023] In some embodiments, the conductive adhesive completely covers the bottom surface of the conductive post and the top surface of the pad. Attached Figure Description
[0024] Figures 1 to 12 The sequential formation process of forming a fan-out structure according to an embodiment of this application is shown.
[0025] Figures 13 to 20 The sequential formation process of the substrate according to an embodiment of this application is illustrated.
[0026] Figures 21 to 23B The process of assembling a semiconductor device according to an embodiment of this application is illustrated.
[0027] Figures 24 to 30 Different embodiments of the semiconductor device according to the present application are shown. Detailed Implementation
[0028] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.
[0029] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.
[0030] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values is less than or equal to ±10% of the average of the values (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values can be considered "substantially" the same.
[0031] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.
[0032] Additionally, quantities, ratios, and other numerical values are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values explicitly specified as range limits, but also all individual numerical values or subranges covered within the range, as if each numerical value and subrange were explicitly specified.
[0033] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.
[0034] Currently, front-end photolithography or micro-bumping processes offer advantages in structural thinning and circuit miniaturization. Thinning facilitates the fabrication of micro-circuits (e.g., L / S > 2µm / 2µm) and reduces product thickness, while circuit miniaturization reduces the number of RDL layers, lowering costs and improving yield. However, front-end photolithography processes incur high costs and have long development timelines due to circuit miniaturization. Since fan-out package structures utilize micro-bumping technology, their cost is significantly higher than RDL fabrication using traditional resin substrate methods. Therefore, finding methods to reduce the number of layers and achieve thinning is crucial for improving the cost and yield of high-end packaged products.
[0035] Currently, there are structures that bond the fan-out structure to the substrate structure together. However, how to achieve a perfect electrical connection between the two is a problem. In addition, due to the large variation of the pads in the final circuit structure presented by the substrate process (the top surface height of the pads is not uniform), the connecting posts of the fan-out structure will be skewed, bent and offset during the docking process, resulting in the inability to make an electrical connection.
[0036] The semiconductor device of this application will now be explained in detail with reference to the accompanying drawings.
[0037] Reference Figure 1 A first seed layer 12 and a first metal layer 14 are formed on the carrier 10, and the first seed layer 12 and the first metal layer 14 have the same pattern.
[0038] Reference Figure 2 A second dielectric layer 20 is formed covering the first seed layer 12 and the first metal layer 14. In an embodiment, the second dielectric layer 20 may include a polyamide (PA) material, and a first exposure process 21 is performed on the second dielectric layer 20 to cure it.
[0039] See Figure 3 An opening is formed in the second dielectric layer 20 to expose the first metal layer 14, and a second seed layer 30 is formed in the opening and on the second dielectric layer 20.
[0040] See Figure 4 The second seed layer 30 is patterned and a second metal layer 40 conforming to the patterned second seed layer 30 is formed. Similar to the above steps, a third dielectric layer 42 and a third seed layer 44 and a third metal layer 46 located in and on the third dielectric layer 42 are formed.
[0041] See Figure 5 A first mask layer 50 is formed covering the third dielectric layer 42, the third seed layer 44, and the third metal layer 46. In an embodiment, the first mask layer 50 may include a polyamide (PA) material, and a second exposure process 51 is performed on the first mask layer 50 to cure it.
[0042] See Figure 6 A fifth dielectric layer 60 is formed on the first mask layer 50. The fifth dielectric layer 60 may include a photoresist (PR) material, and a third exposure process 61 is performed to cure the fifth dielectric layer 60.
[0043] See Figure 7 A portion of the fifth dielectric layer 60 is removed to form a first opening 70 that exposes the first mask layer 50.
[0044] See Figure 8 Further, a portion of the first mask layer 50 is removed to expose the third metal layer 46 in the first opening 70, and a fourth seed layer 80 is formed in the first opening 70 and on the fifth dielectric layer 60.
[0045] See Figure 9 A second mask layer 90 is formed on the fourth seed layer 80. The second mask layer 90 may include a photoresist (PR) material, and a fourth exposure process 91 is performed to cure the second mask layer 90.
[0046] See Figure 10 The second mask layer 90 is patterned to expose the fourth seed layer 80. A first buffer layer 100, a first conductive layer 102, and a first conductive adhesive 104 are then formed on the exposed fourth seed layer 80. In this embodiment, the fourth seed layer 80 and the first buffer layer 100 are conformally oriented. In this embodiment, the first buffer layer 100 is made of a metallic material.
[0047] See Figures 11 to 12 The first mask layer 50 and the second mask layer 90 are removed to form conductive pillars 110. This forms the fan-out structure 120 located on the carrier 10 of this application.
[0048] See Figure 13 The substrate 130 provides a sixth dielectric layer 112 and a support pillar 114 extending through the sixth dielectric layer 112. A first pad 116 is provided at the end of the support pillar 114. The multiple first pads 116 have different thicknesses, resulting in different heights of their top surfaces. In this embodiment, the diameter of the support pillar 114 is less than 10 μm.
[0049] See Figure 14A third mask layer 140 is formed on a plurality of first pads 116. The third mask layer 140 may include a photoresist (PR) material, and a fifth exposure process 141 is performed to cure the third mask layer 140.
[0050] See Figure 15 The third mask layer 140 is partially removed using an etching process 151 to expose the first pad 116.
[0051] See Figure 16 The etching process 151 further recesses the top surface of the first pad 116. The third mask layer 140 is removed, and a fifth seed layer 160 is formed covering the first pad 116.
[0052] See Figure 17 A fourth mask layer 170 is formed on the fifth seed layer 160. The fourth mask layer 170 may include a photoresist (PR) material, and a sixth exposure process 171 is performed to cure the fourth mask layer 170.
[0053] See Figure 18 The fourth mask layer 170 is partially removed to expose the fifth seed layer 160, and a second buffer layer 180 is formed on the fifth seed layer 160. In an embodiment, the fifth seed layer 160 and the second buffer layer 180 are conformal. In an embodiment, the second buffer layer 180 is made of a metallic material.
[0054] See Figure 19 A second conductive adhesive 190 is formed on the second buffer layer 180.
[0055] See Figure 20 The fourth mask layer 170 and the fifth seed layer 160 in contact with the fourth mask layer 170 are removed to form a pad 200 composed of the fifth seed layer 160 and the second buffer layer 180. The pad 200 is located at the end of the support pillar 114. At this point, the formation of the substrate 130 is completed.
[0056] See Figures 21 to 23BThe fan-out structure 120 is bonded to the substrate 130, wherein a first conductive adhesive 104 and a second conductive adhesive 190 are bonded together to form a conductive adhesive 220, and an adhesive layer 210 is disposed between the fan-out structure 120 and the substrate 130. The adhesive layer 210 encapsulates the mutually bonded conductive pillars 110, conductive adhesive 220, and pads 200, and the adhesive layer 210 includes a non-conductive film (NCF) and / or a non-conductive paste (NCP). Multiple conductive pillars 110 and multiple pads 200 are connected in a one-to-one correspondence, and the top surfaces of the multiple pads 200 have different heights, causing some conductive pillars 110 to bend and offset relative to their corresponding pads 200. The carrier 10 is removed to expose the first seed layer 12. In this embodiment, the thickness of the adhesive layer is 15 μm to 30 μm. The conductive pillar 110 includes a vertical extension 113 and a horizontal extension 111, forming a T-shaped structure, which ensures sufficient bonding area between the conductive pillar 110 and the pad 200. The pad 200 has a groove structure 201, and conductive adhesive 220 is located in the groove structure 201. The conductive post 110 is connected to the pad 200 through the conductive adhesive 220. The maximum diameter of the vertical extension 113 of the conductive post 110 (the diameter at the connection with the horizontal extension 111) is smaller than the maximum diameter of the groove structure 201. The maximum diameter D1 of the groove structure 201 is smaller than the diameter D2 of the horizontal extension 111, and the diameter D2 of the horizontal extension 111 is smaller than the maximum diameter D3 of the pad 200. Due to the relationship between the above dimensions, this application ensures a good electrical connection between the conductive post 110 and the pad 200. In some embodiments, the height of the conductive post 110 is in the range of 10 μm to 30 μm. In some embodiments, the diameter of the conductive post 110 is in the range of 10 μm to 30 μm. In some embodiments, the bottom surface of the horizontal extension 111 is curved when electrically connected to the pad 200. In some embodiments, the conductive adhesive 200 is solder. In some embodiments, the conductive adhesive completely covers the bottom surface of the conductive post 200 and the top surface of the pad 200.
[0057] See Figures 22 to 23BThe first seed layer 12 is removed using etching process 221 to expose the first metal layer 14. This forms the semiconductor device 230 of this application. In the semiconductor device 230, the traces in the substrate 130 and the fan-out structure 120 have different dimensions. The linewidth / spacing of the first trace electrically connected to the pad 200 in the substrate 130 is less than 10 μm / 10 μm, and the linewidth / spacing of the second trace electrically connected to the conductive pillar 110 in the fan-out structure 120 is less than 2 μm / 2 μm. In embodiments of this application, the thickness of each sublayer is 0.1 μm to 0.5 μm, and the thickness of each metal material is 1 μm to 5 μm. In some embodiments, the materials of the various sublayers include Ti, W, or Ni. In some embodiments, the metal materials include Cu, Ag, Au, Ni, or Pd. In the embodiments, each dielectric layer of this application uses organic materials such as polyamide (PA), polyimide (PI), epoxy resin, polybenzoxazole (PBO), flame retardant grade 4 material (FR4), prepreg (PP), Ajinomoto build-up film (ABF), etc., and / or inorganic materials such as silicon, glass, ceramics, oxides (e.g., SiOx, TaOx), etc. The adhesive layer 210 uses liquid and / or film-like organic materials such as non-conductive film (NCF), non-conductive paste (NCP), adaptively coupled plasma (ACP), anisotropic conductive film (ACF), polyimide (PI), epoxy resin, resin, prepreg (PP), Ajinomoto build-up film (ABF), adhesive layer, etc. In this embodiment, processes such as printing, lamination, potting, and coating are used to manufacture the adhesive layer 210 and each dielectric layer. In this embodiment, sputtering, electroplating, electroless plating, and / or printing, lamination, and / or potting processes are used to form various sublayers and various metal materials.
[0058] See Figure 24 ,and Figure 23A In contrast, a chip 240 is also provided that is bonded to a third metal layer 46.
[0059] See Figure 25 ,and Figure 23A In contrast, leads 250 for electrical connection are provided between the third metal layers 46.
[0060] See Figure 26 ,and Figure 23A In contrast, additional traces 260 are provided in the adhesive layer 210.
[0061] See Figure 27 ,and Figure 23A In contrast, fan-out structures 120 are provided on both sides of the substrate 130.
[0062] See Figure 28 ,and Figure 23A In contrast, the support post 114 also includes a through-hole 280. In one embodiment, the sixth dielectric layer 112 is inorganic, and the through-hole 280 is a through-silicon via (TSV) / through-glass via (TGV). In another embodiment, the sixth dielectric layer 112 is organic, and the through-hole 280 is a through-organic via (TOV).
[0063] See Figure 29 ,and Figure 23A In contrast, the fan-out structure 120 is formed as a single-layer structure.
[0064] See Figure 30 ,and Figure 23A In contrast, it also includes a chip 300 electrically connected to the first metal layer 14 via a second pad 302. The chip 300 is electrically connected to the substrate 130 via a fan-out structure 120.
[0065] In this embodiment, a pad 200 with a groove structure 201 is designed on a first pad 116 with varying heights. This groove structure 201 is paired with a conductive post 110 with a horizontal extension 111 in the configuration of the fan-out structure 120. Even if the groove structure 201 on the substrate 130 is at different horizontal positions, when the conductive post 110 with the horizontal extension 111 is bonded to the pad 200 with the groove structure 201, the conductive adhesive can still be retained in the groove structure 201, and the conductive post 110 will not have contact problems caused by misalignment. In addition, this horizontal extension 111 can also increase the bonding area and reduce the contact resistance.
[0066] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A semiconductor device, characterized in that, include: A conductive post, including a vertical extension and a horizontal extension; The pad has a grooved structure; Conductive adhesive is located within the groove structure, and the conductive post is connected to the pad via the conductive adhesive. The maximum diameter of the vertical extension of the conductive post is smaller than the maximum diameter of the groove structure, the maximum diameter of the groove structure is smaller than the diameter of the horizontal extension, and the diameter of the horizontal extension is smaller than the maximum diameter of the pad.
2. The semiconductor device according to claim 1, characterized in that, Also includes: Substrate having the aforementioned pad; The fan-out structure has the aforementioned conductive pillars. The fan-out structure is fixedly connected to the substrate via an adhesive layer.
3. The semiconductor device according to claim 2, characterized in that, Also includes: The chip is located on the fan-out structure and is electrically connected to the substrate through the fan-out structure.
4. The semiconductor device according to claim 2, characterized in that, The pad is located at the end of the support post of the substrate.
5. The semiconductor device according to claim 2, characterized in that, The adhesive layer encapsulates the conductive pillars, the conductive adhesive, and the pads that are joined together.
6. The semiconductor device according to claim 1, characterized in that, The conductive posts and the pads are connected in a one-to-one correspondence, and the top surfaces of the pads are at different heights.
7. The semiconductor device according to claim 6, characterized in that, Some of the conductive posts are offset relative to the corresponding pads.
8. The semiconductor device according to claim 1, characterized in that, Both the conductive post and the pad include a seed layer and a metal material surrounded by the seed layer, wherein the seed layer and the metal material are conformally oriented.
9. The semiconductor device according to claim 1, characterized in that, The bottom surface of the horizontal extension is curved.
10. The semiconductor device according to claim 1, characterized in that, The conductive adhesive is a solder.
Citation Information
Patent Citations
Semiconductor device and manufacturing method thereof
CN107359149A
Expanded head pillar for bump bonds
CN111316432A