Partial page sensing mode, method, and apparatus for 3D NAND

Abstract

The present invention provides a partial page sensing method and system, wherein when a bit line voltage (VBLC) is applied to a first bit line of a first partial page of a memory cell array, a second bit line of a second partial page is floated. The second bit line of the second partial page is a bit line that intersects with the first bit line of the first partial page. Bit lines associated with one or more additional partial pages can be grounded or floating. Bit lines associated with additional partial pages adjacent to one of the first bits can be floating.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. non-provisional application serial number 16 / 453,202, filed on June 26, 2019. Background Art 1. Technical Field

[0004] Systems, apparatus, and methods consistent with exemplary embodiments relate to scanning of three-dimensional (3D) NAND flash memory, and more particularly to partial page sensing (PPS), including biasing bit lines (BLs) of unselected partial pages of a 3D NAND flash memory device.

[0005] 2. Description of related art

[0006] 3D NAND flash memory is a type of non-volatile flash memory in which memory cells are stacked vertically in multiple layers. 3D NAND was developed to address challenges encountered in scaling two-dimensional (2D) NAND technology, enabling higher density at a lower cost per bit.

[0007] A memory cell is an electronic device or component capable of storing electronic information. Non-volatile memory may utilize floating-gate transistors, charge-trapping transistors, or other transistors as memory cells. The ability to adjust the threshold voltage of a floating-gate transistor or a charge-trapping transistor allows the transistor to act as a non-volatile storage element (i.e., a memory cell), such as a single-level cell (SLC) that stores a single bit of data. In some cases, more than one bit of data per memory cell may be provided (e.g., in a multi-level cell) by programming and reading multiple threshold voltages or threshold voltage ranges, such cells including, but not limited to, multi-level cells (MLCs) that store two bits per cell; triple-level cells (TLCs) that store three bits per cell; and quad-level cells (QLCs) that store four bits per cell.

[0008] Figure 1 Shown is a diagram of an exemplary 3D NAND memory 100. The memory 100 includes multiple physical layers monolithically formed over a substrate 34, such as a silicon substrate.

[0009] Storage elements, such as memory cells 301, are arranged in an array in the physical layer. Memory cell 301 includes a charge trapping structure 44 located between a word line 300 and a conductive channel 42. Charge can be injected into or extracted from charge trapping structure 44 via the biasing of conductive channel 42 relative to word line 300. For example, charge trapping structure 44 can include silicon nitride and can be separated from word line 300 and conductive channel 42 by a gate dielectric (such as silicon oxide). The amount of charge in charge trapping structure 44 affects the amount of current through conductive channel 42 during a read operation of memory cell 301 and indicates one or more bit values stored in memory cell 301.

[0010] 3D memory 100 includes a plurality of erase blocks 80. Each block 80 includes a "vertical slice" of a stack of physical layers including word lines 300. A plurality of conductive channels 42 (having a substantially vertical orientation, such as Figure 1 ) extending through the stack of word lines 300. Each conductive channel 42 is coupled to a storage element in each word line 300, thereby forming a NAND string of storage elements extending along the conductive channel 42. For clarity of illustration, Figure 1 Three blocks 80, five word lines 300 in each block 80, and three conductive channels 42 in each block 80 are shown. However, 3D memory 100 may have more than three blocks, more than five word lines per block, and more than three conductive channels per block.

[0011] The read / write circuit 68 is coupled to the conductive channel 420 via a plurality of conductive lines: bit lines, shown as a first bit line BL0, a second bit line BL1, and a third bit line BL2 at a first end of the conductive channel (e.g., the end furthest from the substrate 34); and source lines, shown as a first source line SL0, a second source line SL1, and a third source line SL2 at a second end of the conductive channel (e.g., the end closer to or within the substrate 234). The read / write circuit 68 is illustrated as being coupled to the bit lines BL0-BL2 via a "P" control line, to the source lines SL0-SL2 via an "M" control line, and to the word line 300 via an "N" control line. Each of P, M, and N can have a positive integer value based on the specific configuration of the 3D memory 100.

[0012] Each of the conductive channels 42 is coupled to a bit line BL at a first end and to a source line SL at a second end. Thus, a group of conductive channels 42 can be coupled in series to a particular bit line BL and different source lines SL.

[0013] It should be noted that although each conductive channel 42 is shown as a single conductive channel, each of the conductive channels 42 may include multiple conductive channels in a stacked configuration. The multiple conductive channels in the stacked configuration may be coupled by one or more connectors. In addition, as will be understood by those skilled in the art, additional layers and / or transistors (not shown) may be included.

[0014] Read / write circuits 68 facilitate and / or implement read and write operations performed on 3D memory 100. For example, data may be stored to storage elements coupled to word lines 300, and read / write circuits 68 may read bit values from memory cells 301 using one or more sense blocks 36.

[0015] The read / write circuit 68 includes one or more sense blocks 36. The sense block 36 is used to read or sense one or more values stored in the memory cell 301. In one approach, one sense block 36 is provided for a group of NAND strings, each NAND string being coupled to a specific bit line BL. Each sense block 36 may include a memory controller ( Figure 1 ). Each sense block 36 also includes a sense module for each NAND string. Alternatively, the sense blocks 36 can be coupled to intervals of bit lines, such as even or odd bit lines.

[0016] During a read operation, the controller may receive a request from a host device such as a computer, smartphone, or laptop. The controller may cause the read / write circuit 68 to read a bit from a particular storage element of the 3D memory 100 by applying an appropriate signal to a control line to cause the storage element of the selected word line to be sensed. Thus, the 3D memory 100 having multiple conductive channels in a stacked configuration may be configured to read data from one or more storage elements and write data to one or more storage elements.

[0017] Figure 2A and Figure 2B Exemplary adjacent bit lines, drive signals applied to the bit lines, and resulting array signals during a sensing operation are shown. Figure 2A Three exemplary adjacent bit lines during a sensing operation are shown, where a drive signal is applied to each of the three bit lines as shown. For example, the drive signal may be ramped from 0V to 0.5V. As will be appreciated by those skilled in the art, when a signal is applied to a drive line (e.g., Figure 2A The resulting array signal will experience some delay, resulting in a "smooth" array signal, such as Figure 2A As shown. Figure 2A For example, the same drive signal is applied to all bit lines, so there is no interaction between the bit lines and no capacitance is generated between adjacent bit lines. Therefore, the corresponding array signal is quickly ramped up to the final 5V, as shown in Figure 2. Figure 2AThe steep rising edge of

[0018] Figure 2B The figure shows three exemplary adjacent bit lines during a sensing operation, where only the center bit line is driven, for example, from 0V to 0.5V, while the other bit lines remain at 0V. In this case, the voltage difference between the driven bit line and the adjacent bit lines causes capacitive coupling between the center bit line and the adjacent bit lines, as shown. Consequently, this capacitance slows the slope of the array signal corresponding to the center bit line. At this point, due to the capacitive coupling, the array signal corresponding to the non-driven bit line ramps up slightly before ramping back down to 0V.

[0019] Therefore, it is important that when a bit line is driven adjacent to a bit line held at 0V, the corresponding array signal ramps up slowly.

[0020] During programming of 3D NAND word lines, the programming cycle consists of three phases: a precharge phase, a programming phase, and a verification phase. During the precharge phase, a very low precharge voltage is applied to all cells being programmed. During the programming phase, a programming voltage (VPGM) is applied to a specific word line and a pass voltage (VUSEL) is applied to other word lines. VPGM can be, for example, 20V. During the verification phase, a verification voltage (VCGRV) is applied to a specific word line and a bit line voltage (VBLC) is applied to the bit line, and then sensing is performed. VBLC can be, for example, 0.3V. If sensing is performed too quickly after applying VBLC, the timing of the sensing operation is important, there is not enough time for a full ramp-up, and the sensing is inaccurate. Alternatively, if the sensing delay is too long, the programming time increases and programming performance is reduced.

[0021] In some cases, for high-performance applications, instead of programming an entire string (i.e., a "page"), partial page programming (PPP) and partial page sensing (PPS) can be used, where the page is divided into two or more "partial pages" and only a single partial page in the partial page is programmed at a time. Due to the unique 3D NAND multi-string architecture, PPP and PPS are only used in conjunction with single-level cells (SLC). PPS is designed to provide faster sensing (for read and verify operations) and a lower class correlation coefficient (Icc).

[0022] Figure 3 A cross-sectional view of a cell layer in a 3D NAND memory is shown, and four cell strings are shown (String 0, String 1, String 2, and String 3). The vertical lines represent the bit lines connected to the cells shown. Figure 3String 0 is shown divided into two partial pages. In this case, the block is divided into two partial pages, each of which includes 50% of the memory cells in the block. Sensing using a block divided into two partial pages is called 1 / 2 partial page sensing (2PPS). When the block is divided into four partial pages, each of which includes 25% of the cells, sensing is called 1 / 4 partial page sensing (4PPP).

[0023] Figure 4A 、 Figure 4B and Figure 4C Illustrations of full page sensing, ½ partial page sensing (2PPP), and ¼ partial page sensing (4PPP), along with corresponding bit lines, are illustrated.

[0024] Figure 4A An illustration of a full page sense performed on string 0 is provided. During the verify phase of a program loop in which a full page sense is performed, a verify voltage VBLC (eg, 0.3 V) is applied to all bit lines, as shown in FIG. Figure 4A Therefore, the same voltage VBLC is applied to all adjacent bit lines.

[0025] Figure 4B An illustration of 1 / 2 partial page sensing (2PPS) performed on one partial page of string 0 is provided. According to this example, the partial page includes the first two rows of memory wells or the last two rows of memory wells. Therefore, VBLC is applied only to the first two rows or the last two rows of memory wells, and the other partial pages are grounded. Due to the staggered bit lines, this corresponds to "interphase BL charging", meaning that VBLC is applied to every other bit line (i.e., the interphase bit lines), as shown in FIG. Figure 4B , as shown by the thick solid line in [ 1 ]. In this case, PP#1 is selected and the bit line corresponding to PP#1 (shown by the thick black line) is driven to VBLC. The adjacent bit line corresponding to the unselected PP#0, shown by the dashed line, is grounded. It should be noted that although some bit lines are shown with dashed lines to distinguish them from those shown with solid lines, all bit lines are continuous conductors with no breaks. Therefore, each bit line charged to VBLC (e.g., 0.3V) is adjacent to two bit lines held at 0V.

[0026] Figure 4CAn illustration of 1 / 4 partial page sensing (4PPS) performed on a partial page of string 0 is provided. According to this example, the partial page includes half of the first two rows of memory wells or half of the last two rows of memory wells. Note that although only one area of each of PP#0, PP#1, PP#2, and PP#3 is shown, this is only the smallest repeatable physical unit. In other words, the area shown can be repeated to include PP#0, PP#1, PP#2, and PP#3. Therefore, VBLC is applied to only one partial page and the other partial pages are grounded. In this case, PP#2 is selected and the bit line corresponding to PP#2 (shown in thick solid line) is driven to VBLC. The bit lines corresponding to the unselected PP#0, PP#1, and PP#3 shown in dashed lines are grounded. This corresponds to interphase BL charging of the bit lines of PP#2 and PP#0.

[0027] Figure 5A and Figure 5B shows the different sensing times for full page sensing compared to 2PPS where the page is divided into two partial pages ( Figure 5A As mentioned above, PPS is intended to provide faster sensing because only a portion of the string is sensed. Figure 5A and Figure 5B As shown, the inventors have found that PPS exhibits significant failures during programming. Specifically, PPS unexpectedly requires a much longer verify time than full page sensing, and the Icc is also unexpectedly high. Therefore, this is a clear problem that renders the related art PPP and PPS operations practically useless.

[0028] As described above, for the related art 2PPS, interphase bit line charging results in strong bit line-bit line capacitive coupling between adjacent bit lines, thus causing the above reference Figure 2B Similarly, for the related art 4PPS, when sensing one partial page, the bit lines charged to VBLC intersect with the bit lines of another partial page, and the bit line-bit line capacitive coupling between the bit lines significantly slows down the sensing / reading time. Summary of the Invention

[0029] The exemplary embodiments may address at least the above problems and / or disadvantages and other disadvantages not described above. In addition, the exemplary embodiments are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.

[0030] According to one aspect of an exemplary embodiment, a partial page sensing method may include applying a bit line voltage to a first bit line of a memory cell array, wherein the memory cell array includes a plurality of memory cell strings, each memory cell string being divided into a plurality of partial pages, the plurality of partial pages including a first partial page connected to the first bit line and a second partial page connected to a second bit line interleaved with the first bit line. The method further includes floating the second bit line while applying the bit line voltage to the first bit line, and additionally performing one of reading memory cells or sensing memory cells within the first partial page.

[0031] In addition to a first partial page connected to a first bit line and a second partial page connected to a second bit line interleaved with the first bit line, the partial pages may further include a third partial page connected to a third bit line and a fourth partial page connected to a fourth bit line interleaved with the third bit line. The method may further include grounding the third and fourth bit lines while applying a bit line voltage to the first bit line and floating the second bit line.

[0032] The method may further include floating the third and fourth bit lines while applying the bit line voltage to the first bit line and floating the second bit line.

[0033] The method may further include, when applying the bit line voltage to the first bit line: grounding the third bit line; floating a boundary fourth bit line that is one of the fourth bit lines and is adjacent to one of the first bit lines; and grounding a fourth bit line that is not adjacent to any of the first bit lines.

[0034] The method may further include, when applying the bit line voltage to the first bit line: grounding the third bit line; applying a verification voltage to a boundary fourth bit line that is one of the fourth bit lines, the boundary fourth bit line being adjacent to one of the first bit lines; and grounding a fourth bit line that is not adjacent to any of the first bit lines.

[0035] According to one aspect of another exemplary embodiment, a nonvolatile memory storage system includes: a memory cell array coupled to a word line, the memory cell array including a plurality of memory cell strings, each memory cell string being divided into a plurality of partial pages, the plurality of partial pages including a first partial page connected to a first bit line and a second partial page connected to a second bit line interleaved with the first bit line; and a partial page circuit including an operating circuit and a sensing circuit. The operating circuit is configured to apply a bit line voltage to the first bit line and, when the bit line voltage is applied to the first bit line, float the second bit line. The sensing circuit is configured to perform one of reading memory cells and sensing memory cells within the first partial page.

[0036] The operating circuit may be further configured to ground the third and fourth bit lines while applying the bit line voltage to the first bit line.

[0037] The operating circuit may be further configured to float the third and fourth bit lines while applying the bit line voltage to the first bit line.

[0038] The operating circuit can also be configured to, while applying a bit line voltage to the first bit line: ground the third bit line; float a boundary fourth bit line that is one of the fourth bit lines and is adjacent to one of the first bit lines; and ground a fourth bit line that is not adjacent to any of the first bit lines.

[0039] According to another aspect of the exemplary embodiments, there may be provided a non-volatile computer-readable medium having recorded thereon a program that, when executed by a processor, causes the processor to perform a method according to one or more of the aspects discussed above. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and / or other aspects will become more apparent and easier to understand through the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0041] Figure 1 A diagram of an exemplary 3D NAND memory 100 is shown;

[0042] Figure 2A and Figure 2B illustrates exemplary adjacent bit lines, drive signals applied to the bit lines, and resulting array signals during a sensing operation;

[0043] Figure 3 shows a cross-sectional view of a cell layer in a 3D NAND memory;

[0044] Figure 4A 、 Figure 4B and Figure 4C 1. Full page sensing, 1 / 2 partial page sensing (2PPS), and 1 / 4 partial page sensing (4PPS) and diagrams of corresponding bit lines are respectively illustrated;

[0045] Figure 5A and Figure 5B shows the different sensing times for full page sensing compared to 2PPS ( Figure 5A );

[0046] Figure 6A and Figure 6B are diagrammatic illustrations of 2PPS according to the related art and according to an exemplary embodiment, respectively;

[0047] Figure 7 Shown with Figure 6A Compared with the related technologies, Figure 6B exemplary improvements in ramp-up speed of exemplary embodiments of;

[0048] Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D According to the relevant technology ( Figure 8A ) and exemplary embodiments ( Figure 8B 、 Figure 8C and Figure 8D ) of the 4PPS;

[0049] Figure 9 is a schematic block diagram illustrating a system and apparatus configured to implement PPS according to an exemplary embodiment; and

[0050] Figure 10 is a block diagram illustrating a partial page circuit according to an exemplary embodiment. DETAILED DESCRIPTION

[0051] Reference will now be made in detail to the exemplary embodiments illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the exemplary embodiments may have different forms and are not to be construed as limited to the descriptions set forth herein.

[0052] It should be understood that when used in this specification, the terms “including”, “comprise” and / or “comprising” specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0053] It should also be understood that although the terms "first," "second," "third," etc., and "primary," "secondary," etc. may be used herein to describe various operations, elements, components, regions, layers, and / or sections, these operations, elements, components, regions, layers, and / or sections may not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section.

[0054] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of...", when preceding a list of elements, modify the entire list of elements and do not modify the individual elements in the list. In addition, terms such as "unit," "device," "module," and "device" described in this specification refer to elements for performing at least one function or operation and can be implemented in hardware, software, or a combination of hardware and software.

[0055] Various terms are used to refer to specific system components. Different companies may refer to a component by different names – this document is not intended to distinguish between components that differ in name but not function.

[0056] Detailed descriptions of issues of these exemplary embodiments that are obvious to one of ordinary skill in the technical field to which these exemplary embodiments pertain may be omitted here.

[0057] As described above, the related art 2PPS and 4PPS have problems in that interphase bit line charging causes strong bit line-to-bit line capacitive coupling and slows down ramp-up.

[0058] Figure 6A and Figure 6B are respectively a diagrammatic illustration of 2PPS according to the related art and an exemplary embodiment; Figure 6A As shown, the bit line corresponding to the selected PP#1 (shown in bold solid line) is driven to VBLC, and the bit line corresponding to the unselected PP#0 (shown in dashed line) is grounded. As described above, this results in undesirable capacitive coupling between adjacent bit lines and long sensing / reading times.

[0059] according to Figure 6B In the exemplary embodiment shown, cells in the unselected partial page are floated rather than grounded. Consequently, the bit line corresponding to the selected PP#1 (shown as a thick solid line) is driven to VBLC, and the floated bit lines corresponding to the unselected cells of PP#0 are shown as thin solid lines. Compared to the related art where the unselected bit lines are grounded, the floating of the unselected bit lines results in significantly reduced capacitive coupling, leading to faster ramp-up / ramp-down speeds in the selected partial page and shorter sensing / reading times.

[0060] Figure 7 Shown with Figure 6A Compared with the related technologies, Figure 6B An exemplary improvement in the ramp-up speed of an exemplary embodiment of Figure 6B The exemplary embodiment of , in which the bit lines corresponding to unselected local pages are floated, can provide significantly faster ramp-up times, which results in faster sensing / reading times.

[0061] Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D According to the relevant technology ( Figure 8A ) and exemplary embodiments ( Figure 8B 、 Figure 8C and Figure 8D ) is a graphic illustration of 4PPS. Figure 8A As shown, the bit line corresponding to the selected PP#2 (shown in bold solid line) is driven to VBLC, and the bit lines corresponding to the unselected PP#0, PP#1, and PP#3 (shown in dashed lines) are grounded. As described above, this results in undesirable capacitive coupling and long sensing / reading times.

[0062] according to Figure 8B In the exemplary embodiment shown, cells in the unselected partial pages corresponding to bit lines interleaved with the bit lines of the selected partial page are floated rather than grounded, and the bit lines corresponding to other unselected partial pages are grounded. Compared to the related art where the unselected bit lines are grounded, the floating of the unselected, interleaved bit lines results in significantly reduced capacitive coupling, thereby resulting in faster ramp-up / ramp-down speeds in the selected partial page and shorter sensing / reading times. Figure 8B As shown, the bit line corresponding to the selected PP#2 (shown as a thick solid line) is driven to VBLC. The bit line corresponding to the unselected PP#0 is floated, which is physically adjacent to the bit line of the selected PP#2 and is shown as a thin solid line. The bit lines corresponding to the unselected PP#1 and PP#3 are shown as dashed lines and are grounded. Compared to the related art in which all bit lines of the unselected partial pages are grounded, this arrangement results in faster ramp-up / ramp-down speeds in the selected partial page and shorter sensing / reading times.

[0063] However, it should be noted that according to Figure 8B In the exemplary embodiment of the present invention, one of the bit lines of the selected local page #2 (driven to VBLC) is adjacent to the bit line of the unselected local page #1 (grounded). This can result in undesirable capacitive coupling and longer sensing / reading times for cells associated with that single bit line of the selected local page #2.

[0064] according to Figure 8C The exemplary embodiment shown in Figure 8B In the exemplary embodiment of the present invention, cells in the unselected partial pages corresponding to bit lines interleaved with the bit lines of the selected partial page are floated rather than grounded. Figure 8BCompared to the exemplary embodiment of FIG. 1 , one of the bit lines of the unselected PP#1 is floated, as shown by the thin solid line. This floating of the single unselected bit line of PP#1 solves the above-mentioned problem regarding the single bit line of the selected PP#3.

[0065] according to Figure 8D In the exemplary embodiment shown, all cells in the unselected partial pages PP#0, PP#1, and PP#3 are floating instead of being grounded. Figure 8B and Figure 8C As discussed in the embodiments of the present invention, the floating of unselected bit lines results in significantly reduced capacitive coupling, resulting in faster ramp-up / ramp-down speeds and shorter sensing / reading times compared to the related art.

[0066] Figure 9 is a schematic block diagram illustrating a system 200 and a device 250 configured to implement PPS according to the exemplary embodiments described above. The computing device 250 includes one or more local paging circuits 240 for the memory medium 222 of the memory device 220.

[0067] The memory device 220 may operate at least partially on and / or communicate with the memory system 200 of the computing device 250, which may include a processor 211, a volatile memory 212, and a communication interface 213. The processor 211 may include one or more central processing units (CPUs), one or more general-purpose processors, one or more special-purpose processors, one or more processor cores, etc.

[0068] The local page circuits 240 may be disposed at or toward the edges and / or perimeters of the memory elements 223, adjacent to and / or proximate to the array of memory media 222, similar to the above description regarding the memory elements 223. Figure 1 Alternatively, the local page circuit 240 may be provided at a different level, layer, and / or plane of the integrated circuit device than the memory medium 222 array (e.g., a CMOS or other circuit below, parallel to, offset from, etc. the array). The local page circuit may automatically perform the exemplary embodiments described herein, including, but not limited to, for example, automatically applying VBLC, automatically applying a ground voltage to one or more bit lines, automatically floating one or more bit lines, automatically defining two or more local pages, automatically selecting one of the two or more local pages for programming and / or reading / scanning, and automatically performing reading and / or scanning by reading the bit value of the cell of the storage element and / or sensing the threshold voltage (Vt) of the cell of the storage element.

[0069] Figure 10is a block diagram illustrating a partial page circuit 240 according to an exemplary embodiment. The partial page circuit 240 may include an operating circuit 252, which may be any circuit configured to automatically apply VBLC, automatically apply a ground voltage to one or more bit lines, and automatically float one or more bit lines. The partial page circuit may also include a sensing circuit, which may be any circuit configured to automatically perform reading and / or scanning of a selected partial page by reading the bit value of a cell and / or sensing the threshold voltage (Vt) of a cell.

[0070] The memory device 220 can be disposed in any one or more of a variety of locations relative to the computing device 210 and can include one or more memory elements 223, such as semiconductor chips or packages or other integrated circuit devices disposed on one or more printed circuit boards, storage enclosures, and / or other mechanical and / or electrical support structures. For example, the memory device 220 can include one or more in-line memory modules (DIMM) cards, one or more expansion cards and / or daughter cards, memory cards, universal serial bus (USB) drives, solid-state drives (SSDs), or other hard drive devices, and / or can have another memory and / or storage form factor. The memory device 220 can be integrated with and / or mounted on the motherboard of the computing device 210, mounted in a port and / or slot of the computing device 210, mounted on a different computing device 210, and / or on a dedicated storage device on the network 215, communicate with the computing device 210 via an external bus (e.g., an external hard drive), etc.

[0071] Element 223 of the memory medium 222 may include volatile memory medium 222, such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, static RAM (SRAM), thyristor RAM (T-RAM), zero capacitance RAM (Z-RAM), etc. Alternatively, the element 223 of the memory medium 222 may include a non-volatile memory medium 222, such as ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, bidirectional unified memory, chalcogenide RAM or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon oxide-based sub-10 nm process memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, programmable metallization cell (PMC) memory, conductive bridging RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, tape), optical storage media, etc. Therefore, the memory device 220 may rely on, for example, a stored voltage level or a stored resistance level. In some embodiments, one or more elements 223 of the memory medium 222 include storage class memory (SCM). The above description of Figure 1 The 3D NAND memory is an example of the element 223 of the memory medium 222 .

[0072] The memory device 220 may be provided on a memory bus of the processor 211 (e.g., on the same memory bus as the volatile memory 212, on a different memory bus than the volatile memory 212, in place of the volatile memory 212, etc.). Alternatively, the memory device 220 may be provided on a peripheral bus of the computing device 210, such as a Peripheral Component Interconnect Express (PCI Express or PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switch (PCIe-AS) bus, etc. Alternatively, the memory device 220 may be provided on a data network 215, such as an Ethernet network, an Infiniband network, a Small Computer System Interface (SCSI) remote direct memory access (RDMA) over the network 215, a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and / or wireless network 215, etc.

[0073] The computing device 250 may further include a non-transitory computer-readable storage medium 214. The computer-readable storage medium 214 may have executable instructions stored thereon that are configured to cause the computing device 210 (eg, the processor 211) to perform operations according to one or more exemplary embodiments described herein.

[0074] The local page circuit 240 may include hardware of the memory element 223, computer executable program code of a device driver, firmware of the memory controller 226 and / or a memory medium controller for the memory element 223, another electronic component, etc. The local page circuit 240 may be integrated on the memory element 223 (e.g., on-chip local page circuit 240 and / or other integrated hardware). The non-volatile memory controller 226 may be communicatively coupled to the non-volatile memory medium 222 via a bus 227.

[0075] The memory device 220 may include a memory controller 226 that manages one or more memory devices 220 and / or memory elements 223, wherein one or more memory devices 220 and / or memory elements 223 may include on-chip local page circuitry 240. The one or more memory devices 220 may include a record, memory, and / or storage device, such as one or more solid-state memory devices and / or one or more semiconductor memory devices, which are arranged and / or divided into a plurality of addressable media storage locations. As used herein, a media storage location refers to any physical unit of memory (e.g., any number of physical storage media on the memory device 220). Memory units and / or regions may include, but are not limited to, pages, memory partitions, blocks, sectors, collections or sets of physical storage locations (e.g., logical pages, logical blocks), etc.

[0076] Figure 10 The local page circuit 240 shown can be configured as described with respect to Figure 1 The bit lines, source lines, and word lines discussed are coupled to the conductive channel of the memory element 223. In this manner, the local page circuit can apply VBLC to one or more of the bit lines and / or can ground or float any one or more of the bit lines. The sensing circuit 251 can read a bit value from a memory cell of the memory element 223 or can sense the threshold voltage of a memory cell of the memory element in a verify operation.

[0077] It should be understood that the exemplary embodiments described herein may be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each exemplary embodiment may be considered applicable to other similar features or aspects in other exemplary embodiments.

[0078] Although exemplary embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A local page sensing method, comprising: applying a bit line voltage to a first bit line of a memory cell array, wherein the memory cell array includes a plurality of memory cell strings, each memory cell string is divided into a plurality of partial pages, the plurality of partial pages including a first partial page connected to the first bit line and a second partial page connected to a second bit line interleaved with the first bit line, and each of the plurality of partial pages has the same number of memory cells; floating the second bit line while applying the bit line voltage to the first bit line; as well as One of reading memory cells and sensing memory cells is performed within the first partial page.

2. The method of claim 1 , wherein the plurality of partial pages include the first partial page connected to the first bit line, the second partial page connected to the second bit line interleaved with the first bit line, the third partial page connected to the third bit line, and the fourth partial page connected to the fourth bit line interleaved with the third bit line, and wherein the method further comprises: While the bit line voltage is applied to the first bit line and the second bit line is floated, the third bit line and the fourth bit line are grounded.

3. The method of claim 1 , wherein the plurality of partial pages include the first partial page connected to the first bit line, the second partial page connected to the second bit line interleaved with the first bit line, the third partial page connected to the third bit line, and the fourth partial page connected to the fourth bit line interleaved with the third bit line, and wherein the method further comprises: While the bit line voltage is applied to the first bit line and the second bit line is floated, the third bit line and the fourth bit line are floated.

4. The method of claim 1 , wherein the plurality of partial pages include the first partial page connected to the first bit line, the second partial page connected to the second bit line interleaved with the first bit line, the third partial page connected to the third bit line, and the fourth partial page connected to the fourth bit line interleaved with the third bit line, and wherein the method further comprises: When the bit line voltage is applied to the first bit line: grounding the third bit line, floating a boundary fourth bit line that is one of the fourth bit lines, the boundary fourth bit line being adjacent to one of the first bit lines, and The fourth bit line that is not adjacent to any of the first bit lines is grounded.

5. A non-volatile memory storage system comprising: a memory cell array coupled to the word lines, the memory cell array comprising a plurality of memory cell strings, each memory cell string being divided into a plurality of partial pages, the plurality of partial pages comprising a first partial page connected to a first bit line and a second partial page connected to a second bit line interleaved with the first bit line, and each of the plurality of partial pages having the same number of memory cells; and a local page circuit, the local page circuit comprising an operating circuit and a sensing circuit; wherein the operating circuit is configured to apply a bit line voltage to the first bit line and float the second bit line when the bit line voltage is applied to the first bit line, and Wherein the sensing circuit is configured to perform one of reading memory cells and sensing memory cells within the first partial page.

6. The system of claim 5 , wherein the plurality of partial pages comprises the first partial page connected to the first bit line, the second partial page connected to the second bit line interleaved with the first bit line, the third partial page connected to the third bit line, and the fourth partial page connected to the fourth bit line interleaved with the third bit line; and The operation circuit is further configured to ground the third bit line and the fourth bit line while applying the bit line voltage to the first bit line.

7. The system of claim 5 , wherein the plurality of partial pages comprises the first partial page connected to the first bit line, the second partial page connected to the second bit line interleaved with the first bit line, the third partial page connected to the third bit line, and the fourth partial page connected to the fourth bit line interleaved with the third bit line; and wherein the operating circuit is further configured to float the third bit line and the fourth bit line while applying the bit line voltage to the first bit line.

8. The system of claim 5 , wherein the plurality of partial pages comprises the first partial page connected to the first bit line, the second partial page connected to the second bit line interleaved with the first bit line, the third partial page connected to the third bit line, and the fourth partial page connected to the fourth bit line interleaved with the third bit line; and The operating circuit is further configured to, while applying the bit line voltage to the first bit line: ground the third bit line; float a boundary fourth bit line that is one of the fourth bit lines, the boundary fourth bit line being adjacent to one of the first bit lines; and ground the fourth bit line that is not adjacent to any of the first bit lines.

9. A non-transitory computer-readable medium having recorded thereon a program, the program, when executed by a processor, causing the processor to perform a method comprising: applying a bit line voltage to a first bit line of a memory cell array, wherein the memory cell array includes a plurality of memory cell strings, each memory cell string is divided into a plurality of partial pages, the plurality of partial pages including a first partial page connected to the first bit line and a second partial page connected to a second bit line interleaved with the first bit line, and each of the plurality of partial pages has the same number of memory cells; floating the second bit line while applying the bit line voltage to the first bit line; as well as A voltage of each of the memory cells of the first partial page is determined.

10. The non-transitory computer-readable medium of claim 9, wherein the plurality of partial pages include the first partial page connected to the first bit line, the second partial page connected to the second bit line interleaved with the first bit line, the third partial page connected to a third bit line, and the fourth partial page connected to a fourth bit line interleaved with the third bit line, and wherein the method further comprises: While the bit line voltage is applied to the first bit line and the second bit line is floated, the third bit line and the fourth bit line are grounded.

11. The non-transitory computer-readable medium of claim 9 , wherein the plurality of partial pages include the first partial page connected to the first bit line, the second partial page connected to the second bit line interleaved with the first bit line, the third partial page connected to the third bit line, and the fourth partial page connected to the fourth bit line interleaved with the third bit line, and wherein the method further comprises: While the bit line voltage is applied to the first bit line and the second bit line is floated, the third bit line and the fourth bit line are floated.

12. The non-transitory computer-readable medium of claim 9 , wherein the plurality of partial pages include the first partial page connected to the first bit line, the second partial page connected to the second bit line interleaved with the first bit line, the third partial page connected to the third bit line, and the fourth partial page connected to the fourth bit line interleaved with the third bit line, and wherein the method further comprises: When the bit line voltage is applied to the first bit line: grounding the third bit line, floating a boundary fourth bit line that is one of the fourth bit lines, the boundary fourth bit line being adjacent to one of the first bit lines, and The fourth bit line that is not adjacent to any of the first bit lines is grounded.

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