Drive the adjacent word line of the NAND string to the target voltage level

Abstract

Methods of operating an integrated circuit device and an apparatus so configured may include: applying a first voltage level to a first conductor while applying a second voltage level to a second conductor; applying a third voltage level to the first conductor while applying a fourth voltage level to the second conductor; and applying a fifth voltage level to the first conductor while applying the second voltage level to the second conductor. The second voltage level may correspond to a target voltage level for the second conductor. The difference between the third voltage level and the first voltage level may have a polarity opposite to the polarity of the difference between the fourth voltage level and the second voltage level, and may have the same polarity as the polarity of the difference between the fifth voltage level and the first voltage level. The fifth voltage level may correspond to the target voltage level for the first conductor.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuit operation and, in particular, in one or more embodiments, to driving a conductor to a target voltage level. Background Art

[0002] Integrated circuit devices traverse a wide range of electronic devices. One specific type includes memory devices, often simply referred to as memory. Memory devices are typically provided as internal semiconductor integrated circuit devices in a computer or other electronic device. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Flash memory has developed into a ubiquitous source of nonvolatile memory for a wide range of electronic applications. Flash memory typically uses a single-transistor memory cell that allows for high storage density, high reliability, and low power consumption. Changes in the threshold voltage (Vt) of the memory cell through programming of a charge storage structure (such as a floating gate or a charge trap), which is often referred to as writing, or other physical phenomena (such as a phase change or polarization), determine the data state (such as the data value) of each memory cell. Common uses for flash memory and other nonvolatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and removable memory modules, and the uses of nonvolatile memory continue to expand.

[0004] NAND flash memory is a common type of flash memory device, and therefore requires a logical form of arrangement of the basic memory cell configuration. Typically, the memory cell array of a NAND flash memory device is arranged so that the control gates of each memory cell of a row of the array are connected together to form an access line, such as a word line. The columns of the array include strings of memory cells (commonly referred to as NAND strings) connected together in series between a pair of select gates, such as a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, and each drain select transistor may be connected to a data line, such as a column bit line. Variations are known that use more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line.

[0005] Integrated circuit devices typically contain multiple conductors that are often in close proximity. The dimensions of the conductors are typically small, and a particular dimension may be about 25 nm or less. And a conductor may also be positioned about 25 nm or less from two or more adjacent conductors. These characteristics may lead to significant resistive and capacitive coupling issues, which may adversely affect the ability to drive the conductors to a target voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a simplified block diagram of a memory in communication with a processor as part of an electronic system according to an embodiment.

[0007] Figure 2A to 2B Is it available for reference Figure 1 A schematic diagram of a portion of a memory cell array depicting a type of memory.

[0008] Figure 2C Is it available for reference Figure 1 A perspective view of elements of a portion of a memory cell array in a memory of the type described.

[0009] Figure 3A is a conceptual depiction of a conductor demonstrating its resistance and capacitance characteristics for use with the embodiments.

[0010] Figure 3B Is to describe overdrive Figure 3A A graph of an idealized waveform depicting the advantages of the type of conductor.

[0011] Figure 3C yes Figure 3A Conceptual depiction of adjacent conductors of the type depicted in FIG.

[0012] Figure 4A Is it available for reference Figure 1 A schematic diagram of a portion of a memory cell array in a memory device of the type described.

[0013] Figure 4B Is it possible to Figure 4A Schematic diagram of a portion of a memory cell array used together with a global access line driver configuration.

[0014] 5A-5B depict waveforms of adjacent conductors and their drivers for various overdrive conditions using related techniques.

[0015] Figure 6 is a conceptual depiction of threshold voltage distributions of a plurality of memory cells after a programming operation for use with embodiments.

[0016] Figure 7 Waveforms of adjacent conductors and their drivers are depicted using conditions according to an embodiment compared to overdrive conditions of the related art.

[0017] Figures 8A to 8B Waveforms of an adjacent conductor and its driver are depicted during a sensing operation using conditions according to an embodiment compared to an overdrive condition of the related art.

[0018] Fig. 9Conceptually depicted are expected applied voltage levels for adjacent conductors using an overdrive condition according to an embodiment.

[0019] Fig.10 is a flow chart of a method of driving a conductor according to an embodiment.

[0020] Fig.11 is a flow chart of a method of driving a conductor according to another embodiment.

[0021] Fig.12 is a flowchart of a method of operating a memory according to an embodiment.

[0022] Fig.13 is a flow chart of a method of driving a conductor according to another embodiment. DETAILED DESCRIPTION

[0023] In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which specific embodiments are shown by way of illustration. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed in a limiting sense.

[0024] The term "semiconductor" as used herein may refer to, for example, a material layer, a wafer, or a substrate, and includes any base semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor structure, and other semiconductor structures well known to those skilled in the art. In addition, when reference is made to a semiconductor in the following description, previous process steps may have been utilized to form regions / junctions in the base semiconductor structure, and the term semiconductor may include underlying layers containing such regions / junctions.

[0025] Unless otherwise apparent from the context, the term "conductive" and its various related forms (e.g., conductive, conductively, conducting, conductive, conductivity, etc.) as used herein refer to electrical conduction. Similarly, unless otherwise apparent from the context, the term "connecting" and its various related forms (e.g., connect, connected, connection, etc.) as used herein refer to electrical connection.

[0026] It should be recognized herein that even in cases where the expected values ​​may be equal, the variability and accuracy of industrial processes and operations may result in differences from their expected values. These variability and accuracy will generally depend on the technology used in the manufacture and operation of integrated circuit devices. Thus, if the expected values ​​are equal, then those values ​​are considered equal regardless of their resulting values.

[0027] The timing of bringing a conductor to a target voltage level can be an important factor in the operating speed of an integrated circuit device. As noted, conductors of an integrated circuit device can have small dimensions and be placed in close proximity to adjacent conductors. These characteristics can adversely affect the speed at which a conductor can be driven to a target (e.g., desired) voltage level. Various embodiments seek to facilitate improving the timing of bringing a conductor to a target voltage level. Although the various embodiments will be discussed with particular reference to word lines of a memory, the concepts can be applied to other types of adjacent conductors.

[0028] Figure 1 1 is a simplified block diagram of a first device (in the form of a memory (e.g., memory device) 100) communicating with a second device (in the form of a processor 130) as part of a third device (in the form of an electronic system) according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and the like. Processor 130 (e.g., a controller external to memory device 100) may be a memory controller or other external host device.

[0029] Memory device 100 includes an array of memory cells 104 that is logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line), while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1 ) can be programmed to one of at least two target data states.

[0030] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 for managing the input of commands, addresses, and data to memory device 100 and the output of data and status information from memory device 100. Address registers 114 communicate with I / O control circuitry 112 and row decoding circuitry 108 and column decoding circuitry 110 to latch address signals prior to decoding. Command registers 124 communicate with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0031] The controller (e.g., control logic 116 inside the memory device 100) controls access to the memory cell array 104 in response to commands and generates status information for the external processor 130, that is, the control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read operations and verification operations], programming operations, and / or erasing operations) on the memory cell array 104, and may be configured to perform methods according to embodiments. The control logic 116 communicates with the row decoding circuit system 108 and the column decoding circuit system 110 to control the row decoding circuit system 108 and the column decoding circuit system 110 in response to addresses.

[0032] The control logic 116 also communicates with cache registers 118. The cache registers 118 latch incoming or outgoing data to temporarily store data while the memory cell array 104 is busy writing or reading other data (respectively) according to the direction of the control logic 116. During a programming operation (e.g., a write operation), data may be transferred from the cache registers 118 to the data registers 120 for transmission to the memory cell array 104; then, the new data may be latched in the cache registers 118 from the I / O control circuitry 112. During a read operation, data may be transferred from the cache registers 118 to the I / O control circuitry 112 for output to the external processor 130; then, the new data may be transferred from the data registers 120 to the cache registers 118. The cache registers 118 and / or the data registers 120 may form a page buffer of the memory device 100 (e.g., may form part of a page buffer of the memory device 100). The page buffer may further include a sensing device (eg, a sensing device) for sensing the data state of a memory cell in the memory cell array 104, such as by sensing the state of a data line connected to the memory cell. Figure 1 1 . The status register 122 may communicate with the I / O control circuitry 112 and the control logic 116 to latch status information for output to the processor 130.

[0033] The memory device 100 receives control signals from the processor 130 via a control link 132 at the control logic 116. The control signals may include chip enable CE#, command latch enable CLE, address latch enable ALE, write enable WE#, read enable RE#, and write protect WP#. Additional or alternative control signals (not shown) may be further received via the control link 132 depending on the nature of the memory device 100. The memory device 100 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via the I / O bus 134.

[0034] For example, a command may be received at the I / O control circuitry 112 via input / output (I / O) pins [7:0] of the I / O bus 134, and then may be written into the command register 124. An address may be received at the I / O control circuitry 112 via input / output (I / O) pins [7:0] of the I / O bus 134, and then may be written into the address register 114. Data may be received at the I / O control circuitry 112 via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device, and then may be written into the cache register 118. The data may then be written into the data register 120 to program the memory cell array 104. For another embodiment, the cache register 118 may be omitted, and the data may be written directly into the data register 120. Data may also be output via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference may be made to I / O pins, they may include any conductive node that provides electrical connection to the memory device 100 by an external device (e.g., processor 130), such as a commonly used conductive pad or conductive bump.

[0035] It will be appreciated by those skilled in the art that additional circuitry and signals may be provided and that the Figure 1 It should be appreciated that the reference Figure 1 The functionality of the various block components described may not necessarily be separated into distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1 Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1 The functionality of a single block component.

[0036] Additionally, while specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0037] Figure 2A Is it available for reference Figure 1 Schematic diagram of a portion of a memory cell array 200A (eg, a NAND memory array) in a memory of the type described (eg, as a portion of the memory cell array 104). The memory array 200A includes access lines (eg, word lines 202 0 By 202 N ) and data lines (eg, bit lines 204 0 To 204 M). The word lines 202 may be connected to the Figure 2A For some embodiments, memory array 200A may be formed on a semiconductor, for example, which may be conductively doped to have a certain conductivity type (e.g., p-type conductivity, such as for forming a p-well, or n-type conductivity, such as for forming an n-well).

[0038] The memory array 200A may be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column may include a string of memory cells (eg, nonvolatile memory cells) connected in series, such as a NAND string 206. 0 To 206 M Each NAND string 206 may be connected (eg, selectively connected) to a common source (SRC) 216 and may include a memory cell 208. 0 To 208 N The memory cells 208 may represent non-volatile memory cells for data storage. The memory cells 208 of each NAND string 206 may be connected in series to a select gate 210 (eg, a field effect transistor) (eg, select gate 210 0 To 210 M One of the transistors (eg, which may be a source select transistor, commonly referred to as a select gate source) and a select gate 212 (eg, a field effect transistor) (eg, select gate 212 0 To 212 M The select gate 210 is connected to one of the drain select transistors (for example, which may be a drain select transistor, often referred to as a select gate drain). 0 To 210 M The select gates 212 may be connected to a select line 214 (eg, a source select line (SGS)). 0 To 212 M may be commonly connected to a select line 215, such as a drain select line (SGD). Although depicted as conventional field effect transistors, select gates 210 and 212 may utilize a structure similar to (e.g., the same as) memory cell 208. Select gates 210 and 212 may represent a plurality of select gates connected in series, where each select gate in the series is configured to receive the same or an independent control signal.

[0039] The source of each select gate 210 may be connected to the common source 216. The drain of each select gate 210 may be connected to the memory cell 208 of the corresponding NAND string 206. 0 For example, select gate 210 0 The drain of the NAND string 206 may be connected to the corresponding 0 The memory unit 208 0Thus, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to a common source 216. A control gate of each select gate 210 can be connected to a select line 214.

[0040] The drain of each select gate 212 may be connected to the bit line 204 of the corresponding NAND string 206. For example, the select gate 212 0 The drain of the NAND string 206 may be connected to the corresponding 0 The bit line 204 0 The source of each select gate 212 may be connected to the memory cell 208 of the corresponding NAND string 206. N For example, select gate 212 0 The source of the NAND string 206 may be connected to the corresponding 0 The memory unit 208 N Thus, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204. A control gate of each select gate 212 can be connected to a select line 215.

[0041] Figure 2A The memory array in may be a quasi-two-dimensional memory array and may have a substantially planar structure, such as where the common source 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2A The memory array in can be a three-dimensional memory array, for example, where the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and a plane containing the bit lines 204 can extend substantially parallel to the plane containing the common source 216 .

[0042] The typical construction of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, or other structure configured to store charge) that can determine the data state of the memory cell (e.g., through a change in threshold voltage), and a control gate 236, such as Figure 2A 2. The data storage structure 234 may include both conductive structures and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases formed of) the word line 202.

[0043] A column of memory cells 208 may be a NAND string 206 or multiple NAND strings 206 selectively connected to a given bit line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but need not) include all memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may generally be divided into physical pages of one or more groups of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 commonly connected to a given word line 202. For example, a physical page of memory cells 208 commonly connected to a word line 202 may include every other memory cell 208 commonly connected to a word line 202. N and selectively connected to even bit lines 204 (eg, bit line 204 0 , 204 2 , 204 4 The memory cells 208 of the plurality of memory cells 208 (eg, even-numbered memory cells) may be memory cells 208 of a physical page and are commonly connected to the word line 202. N and selectively connected to odd bit lines 204 (eg, bit lines 204 1 , 204 3 , 204 5 The memory cell 208 of another physical page (e.g., an odd-numbered memory cell) may be a memory cell 208 of another physical page (e.g., an odd-numbered memory cell). Figure 2A The bit line 204 is not clearly depicted. 3 To 204 5 , but it is obvious from the figure that the bit line 204 of the memory cell array 200A can be 0 are numbered consecutively to bit lines 204 M Other groups of memory cells 208 commonly connected to a given word line 202 may also define a physical page of memory cells 208. For a particular memory device, all memory cells commonly connected to a given word line may be considered a physical page of memory cells. A portion (which may still be a full row in some embodiments) of a physical page of memory cells that is read during a single read operation or programmed during a single program operation (e.g., an upper page or lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as a row of memory cells connected to a word line 202. 0 By 202 N 2. Unless explicitly distinguished, references herein to a page of memory cells refer to memory cells of a logical page of memory cells.

[0044] although Figure 2AThe examples are discussed in conjunction with NAND flash, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0045] Figure 2B Is it available for reference Figure 1 Another schematic diagram of a portion of a memory cell array 200B (eg, as a portion of memory cell array 104) in a memory of the type described. Figure 2B Like numbered elements in correspond to those in Figure 2A Description provided. Figure 2B Additional details of one example of a three-dimensional NAND memory array structure are provided. The three-dimensional NAND memory array 200B can incorporate a vertical structure that can include semiconductor pillars, where a portion of the pillars can be used as a channel region for the memory cells of the NAND strings 206. Each of the NAND strings 206 can be selectively connected to a bit line 204 through a select transistor 212 (e.g., which can be a drain select transistor, commonly referred to as a select gate drain). 0 To 204 M The plurality of NAND strings 206 can be selectively connected to the same bit line 204. A subset of the NAND strings 206 can be selectively connected to the common source 216 by biasing the select line 215. 0 To 215 K Each particular select transistor 212 between the NAND string 206 and the bit line 204 is selectively activated to connect to its corresponding bit line 204. The select transistors 210 can be activated by biasing the select line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. The rows of memory cells commonly connected to each other by a particular word line 202 can be collectively referred to as a level.

[0046] Figure 2C Is it available for reference Figure 1 A perspective view of elements of a portion of a memory cell array 200C in a memory of the type described. Figure 2C Like numbered elements in correspond to those in Figure 2A Description provided. Figure 2CAlternative details of one example of a three-dimensional NAND memory array structure are provided. The three-dimensional NAND memory array 200C can incorporate a vertical structure that can include semiconductor pillars 218, where a portion of the pillars 218 can be used as a channel region for the memory cells of the NAND string. Each of the pillars 218 can be connected to the bit line 204 and the source 216 in a many-to-one relationship. The select transistor (e.g., drain select transistor) 212 ( Figure 2C A selection transistor (eg, source selection transistor) 210 (eg, source selection transistor) 215 may be formed at each intersection of the pillar 218 and the selection line (eg, drain selection line) 215. Figure 2C 214) may be formed at each intersection of a pillar 218 and a select line (eg, source select line) 214. Memory cell 208 ( Figure 2C 2 (not shown) may be formed at each intersection of a pillar and an access line (e.g., word line) 202. The three-dimensional NAND memory array 200C depicts that the word lines 202 may be formed as conductive plates (e.g., parallel conductive plates), and each word line 202 may be adjacent to (e.g., immediately adjacent to) at least one other word line 202.

[0047] Figure 3A 302 is a conceptual depiction of a conductor 302 demonstrating its resistance and capacitance characteristics for use with an embodiment. Conductor 302 may be a distributed RC (resistance-capacitance) circuit and may correspond to word line 202. Each portion 304 of conductor 302 may have a corresponding resistance 306 that may be caused by its construction material and its dimensions, and may have a corresponding capacitance 308 that may be caused by its separation from adjacent conductors. The corresponding resistance 306 and capacitance 308 of a portion 304 of conductor 302 may be the same or different from the corresponding resistance or capacitance of other portions of conductor 302. That is, conductor 302 may have consistent construction materials and dimensions and have consistent relationships with adjacent conductors, or, as is likely the case in industrial manufacturing, conductor 302 may be different in construction materials, dimensions, and / or relationships with adjacent conductors. Regardless, if a voltage level is applied to one end of conductor 302, the RC characteristics of conductor 302 will generally result in a delay before the other end of conductor 302 reaches that voltage level.

[0048] Figure 3B Is to describe overdrive Figure 3A 302. Line 310 may represent a target voltage level (V target ). If the target voltage level V target will be applied to the proximal end of conductor 302, then line 312 may represent the voltage level at the distal end of conductor 302 over time. To reduce the voltage level V at the distal end of conductor 302, targetThe voltage level applied to the proximal end of conductor 302 may be overdriven for a desired length of time. For example, the voltage level applied to the proximal end of conductor 302 may be overdriven for a desired length of time. od V can be added target A part of K od (For example, K od *V target ). Product K od *V target It can be called the overdrive voltage difference V od , and the time period T od It can be called overdrive time T od .

[0049] If the overdrive voltage difference V od During the overdrive time T od is applied to the proximal end of conductor 302 and then reduced to a target voltage level V target , then line 316 may represent the voltage level at the far end of conductor 302 over time. It can be seen that the overdrive time T od The overdrive voltage difference within V od This use of can be used to reduce the time required for the far end of conductor 302 to reach its target voltage level V target It should be understood that if the over-driving voltage difference V od If applied for too long, the conductor 302 will exceed its target voltage level V target .

[0050] Figure 3C yes Figure 3A Conceptual depiction of adjacent conductors 302 of the type depicted in FIG. Figure 3C Describing conductor 302 x The conductor 302 may be adjacent to (eg, in close proximity to) the conductor 302. x+1 and conductor 302 x-1 . Conductor 302 x Can be parallel to conductor 302 x+1 and conductor 302 x-1 . Conductor 302 x In the conductor 302 x+1 There may be a capacitor element 308 between x+1 . Conductor 302 x In the conductor 302 x-1 There may be a capacitor component 308 between x-1 .although Figure 3C Not shown, but conductor 302 x There may be a capacitive component between conductors (although typically to a lesser extent) and other adjacent conductors. For example, if conductor 302 x Corresponds to Figure 2AWord line 202 x , then word line 202 x may have a word line 202 adjacent thereto x+1 With value C 1 The first capacitor element and its secondary adjacent word line 202 x+2 With value C 2 The second capacitor element and its third adjacent word line 202 x+3 With value C 3 The third capacitance component, etc., where C 1 >C 2 >C 3 >……. Word line 202 x There may be corresponding capacitive components on the other side thereof, such as other word lines 202 on the source 216 side. These capacitive components may interfere with the conductor 302. x The voltage level stabilization time.

[0051] Applying voltage levels to conductors may utilize voltage drivers. In the case of a memory device, the voltage levels applied to the access lines may be distributed to various portions of the memory cell array that further use global access lines. Figure 4A Is it available for reference Figure 1 A schematic diagram of a portion of an array of memory cells in a memory device of the type described and depicting a many-to-one relationship between local access lines (eg, word line 202) and global access lines (eg, global word line 402).

[0052] like Figure 4A , a plurality of memory blocks 432 may have their local access lines (e.g., word lines 202) selectively connected in common to a plurality of global access lines (e.g., global word lines 402). A memory block 432 may include a plurality of memory strings 206 that are commonly coupled to a particular set of word lines 202. For example, Figure 2A Memory string 206 0 To 206 M Or some portion thereof may represent memory block 432. Although Figure 4A Only memory block 432 is depicted 0 and 432 1 (Block 0 and Block 1), but the additional memory block 432 can have its word lines 202 commonly connected to the global word line 402 in a similar manner. Similarly, although Figure 4A Only four word lines 202 are depicted, but the memory block 432 may include fewer or more word lines 202 .

[0053] To facilitate memory access operations to specific memory blocks 432 that are commonly coupled to a given set of global word lines 402, each memory block 432 may have a corresponding set of block select transistors 430 in a one-to-one relationship with its word line 202. The control gates of the set of block select transistors 430 for a given memory block 432 may have their control gates commonly connected to a corresponding block select line 456. For example, for a memory block 432 0 , word line 202 00 The block selection transistor 430 00 is selectively connected to the global word line 402 0 , word line 202 01 The block selection transistor 430 01 is selectively connected to the global word line 402 1 , word line 202 02 The block selection transistor 430 02 is selectively connected to the global word line 402 2 , and word line 202 03 The block selection transistor 430 03 is selectively connected to the global word line 402 3 , and the block selection transistor 430 00 to 430 03 In response to the block select line 456 0 The control signal received on.

[0054] The global access lines are typically connected to driver circuitry (eg, voltage drivers) to apply various voltage levels to the global access lines for various access operations. Figure 4B Is it possible to Figure 4A Schematic diagram of a portion of a memory cell array used together with a global access line driver configuration. Figure 4B The global access lines (eg, global word lines 402) are shown. 0 to 402 3 ) can be respectively selected by the driver transistor 436 0 To 436 3 is selectively connected to a global access line driver (eg, global word line driver 434 0 To 434 3 ). Although the driver selection transistor 436 0 To 436 3 are shown as being commonly connected to a single driver select line 438 so that all global word lines 402 0 to 402 3 Commonly connected to their corresponding global word line drivers 434 0 To 434 3 or together with its corresponding global word line driver 4340 To 434 3 isolated, but each driver select transistor 436 may receive its own control signal to allow individual connection or isolation.

[0055] 5A-5B depict waveforms of adjacent conductors and their drivers for various overdrive conditions using related techniques. The examples of FIGS. 5A and 5B each depict in the left side of the figure a waveform at an overdrive time T od Overdrive voltage difference V od The right side of Figure 5A depicts the situation where the overdrive voltage difference V od Increased ΔV od The right side of FIG5B depicts the overdrive time T od Increased ΔT od In FIGS. 5A and 5B , line 540 may represent a line connected to a selected circuit for overdriving at a time T od Overdrive voltage difference V od 544 may represent a voltage level (e.g., a pass voltage Vpass1) applied to a first end (e.g., a near end) of a word line (SelWL) for a sensing operation (e.g., a read operation or a verify operation). Line 546 may represent a voltage level (e.g., a read voltage Vwlrv) applied by a voltage driver at a first end (e.g., a near end) of a word line (SelWL) for a sensing operation (e.g., a read operation or a verify operation). Line 542 may represent a voltage level at a second end (e.g., a far end) of the selected word line SelWL. Line 544 may represent a voltage level (e.g., a pass voltage Vpass1) applied to a first end (e.g., a near end) of a word line (WL±1) that is not selected for the sensing operation and is adjacent to (e.g., immediately adjacent to) the selected word line SelWL. Line 547 may represent a target voltage level V target , and line 549 may represent a target voltage level for the pass voltage Vpass1.

[0056] Although line 544 does not exhibit voltage level fluctuations, this is due to the effects of the unselected word line WL±1 being driven (e.g., capacitive coupling effects), and does not indicate a desire to change the voltage level applied to the unselected word line WL±1. Therefore, as used herein, applying a particular voltage level to a conductor means that the expected voltage level of the applied voltage has a particular voltage level. For example, a charge pump (not shown) is typically utilized to generate voltages utilized in the operation of an integrated circuit device, and the charge pump can be used to supply the voltage level to a driver circuit system. The charge pump typically utilizes feedback control to maintain its output voltage level at a certain target voltage level. If the load of the charge pump (e.g., the conductor receiving the output voltage level) experiences a voltage level change, the output voltage level of the charge pump may tend to follow the change in voltage level until the feedback control is able to respond in a manner to return the output voltage level to its target voltage level. Therefore, as used herein, such fluctuations do not represent a change in the applied voltage level.

[0057] In FIG. 5A , line 540 a may represent a line connected to a selected overdrive time T od Overdrive voltage difference V od +ΔV od The voltage level (e.g., read voltage Vwlrv) applied by the voltage driver at the first end (e.g., near end) of the word line (SelWL) for the sensing operation. Line 542a may represent the voltage level at the second end (e.g., far end) of the selected word line SelWL. Line 544a may represent the voltage level (e.g., pass voltage Vpass1) applied to the first end (e.g., near end) of the word line (WL±1) that is not selected for the sensing operation and is adjacent to (e.g., immediately adjacent to) the selected word line SelWL. Line 546a may represent the voltage level at the second end (e.g., far end) of the unselected word line WL±1.

[0058] In FIG. 5B , line 540 b may represent a line connected to a selected overdrive time T od +ΔT od Overdrive voltage difference V od The voltage level (e.g., read voltage Vwlrv) applied by the voltage driver at the first end (e.g., near end) of the word line (SelWL) for the sensing operation. Line 542b may represent the voltage level at the second end (e.g., far end) of the selected word line SelWL. Line 544b may represent the voltage level (e.g., pass voltage Vpass1) applied to the first end (e.g., near end) of the word line (WL±1) that is not selected for the sensing operation and is adjacent to (e.g., immediately adjacent to) the selected word line SelWL. Line 546b may represent the voltage level at the second end (e.g., far end) of the unselected word line WL±1.

[0059] In FIG. 5A and FIG. 5B , at the overdrive time T od Overdrive voltage difference V od The example demonstrates that, due to the capacitive coupling between the selected word line SelWL and the unselected word lines WL±1, overdriving the selected word line SelWl may cause the voltage level of line 546 to increase during the overdriving time T. od It should be appreciated that although it may be desirable to increase the overdrive time T od The pass voltage Vpass1 is applied to the unselected word lines WL±1 for a duration of 540, but coupling effects can interfere with the ability of the voltage driver to maintain that voltage level. Once the voltage level of line 540 is reduced, capacitive coupling between the selected word line SelWL and the unselected word lines WL±1 can cause the voltage level of line 542 to decrease before it returns to its target voltage level 547, thereby increasing the settling time of the selected word line SelWL. It is well known to use increased overdrive voltages and / or overdrive times to mitigate such effects.

[0060] The overdrive time T on the right side of FIG5A od Overdrive voltage difference V od +ΔV od The example of 542a exhibits a similar capacitive coupling effect between the selected word line SelWL and the unselected word lines WL±1. However, the voltage level of line 542a can be controlled by the overdrive time T od Overdrive voltage difference V od +ΔV od and is forced to exceed its target voltage level V target In this way, once the voltage level of line 540a is reduced, capacitive coupling between the selected word line SelWL and the unselected word lines WL±1 may cause the voltage level of line 542a to decrease, but it may return to its target voltage level 547 more quickly than the case on the left side of FIG. 5A .

[0061] The overdrive time T on the right side of FIG5B od +ΔT od Overdrive voltage difference V od The example of again shows a similar capacitive coupling effect between the selected word line SelWL and the unselected word lines WL±1. However, the voltage level of line 542b can be controlled by the overdrive time T od +ΔT od Overdrive voltage difference V od and is forced to exceed its target voltage level V targetIn this way, once the voltage level of line 540b is reduced, capacitive coupling between the selected word line SelWL and the unselected word lines WL±1 may cause the voltage level of line 542b to decrease, but it may return to its target voltage level 547 faster than the case on the left side of FIG. 5B .

[0062] While increasing the overdrive voltage difference and / or increasing the overdrive time can be used to increase the settling time of a conductor, the resulting overshoot of the voltage level of the conductor beyond its target voltage level can have an adverse effect on the operation of the integrated circuit device. For example, in a memory device, sensing (e.g., reading or verifying) the data state of a memory cell typically involves detecting whether the memory cell is activated in response to a particular voltage applied to a control gate of the memory cell, such as by detecting whether a data line connected to the memory cell experiences a change in voltage level caused by current flow through the memory cell. Increasing the voltage level of a word line selected for a sensing operation can result in activation of memory cells that would not be activated if the target voltage level were applied. This can result in unintended current flow, which may require additional settling time for the data line before effective sensing can be performed.

[0063] Figure 6 is a conceptual depiction of threshold voltage distributions of a plurality of memory cells after a programming operation for use with embodiments. Figure 6 Threshold voltage distribution 618 d To 618 d+2 may represent a portion of a distribution used to represent a corresponding data state. Typically, when a programming operation is completed, threshold voltage distribution 618 d To 618 d+2 A certain margin or dead zone may be separated. However, these threshold voltage distributions 618 d To 618 d+2 It is not uncommon for widening to occur over time, allowing Figure 6 The overlap depicted in .

[0064] During a sensing operation in a NAND memory, various increasing voltage levels may be applied to the control gates of the memory cells selected for the sensing operation, while the remaining memory cells in the series-connected string of memory cells may receive pass voltages (e.g., those memory cells that are desired to be activated regardless of their data state). For example, read voltage 620 d can be applied to the threshold voltage distribution 618 d To 618 d+2 The control gate of the memory cell and responds to the read voltage 620 d The memory cell activated first can be considered to have a threshold voltage distribution corresponding to 618. d Data state. Read voltage 620 d+1The threshold voltage distribution 618 may then be applied to d To 618 d+2 The control gate of the memory cell and responds to the read voltage 620 d+1 The memory cell activated first can be considered to have a threshold voltage distribution corresponding to 618. d+1 However, as indicated in reference to FIGS. 5A and 5B , the expected read voltage is, for example, a read voltage 620 d , but the voltage level applied to the control gate of the memory cell rises above this target voltage level (e.g., shifts to Figure 6 ), threshold voltage distribution 618 d+1 Memory cells (eg, more memory cells) may be activated, resulting in unintended current flow. Various embodiments seek to mitigate this overshoot caused by overdriving conductors, while further seeking to mitigate the adverse effects of capacitive coupling of adjacent conductors increasing settling time.

[0065] Figure 7 Waveforms of adjacent conductors and their drivers are depicted using conditions according to an embodiment compared to overdrive conditions of the related art. Figure 7 An example of the overdrive time T od The overdrive voltage difference V od Applied to the conductor. Overdrive voltage difference V od and overdrive time T od The value of may be selected so that the voltage level of the conductor reaches its target voltage level without exceeding its target voltage level by a certain predefined tolerance. The selection of such values ​​is well understood and may be determined, for example, by experimentation, experience, or by simulation. In contrast to the examples of FIGS. 5A and 5B , adjacent conductors may be driven at an overdrive time T od That is, the overdrive voltage difference V od In the case of a positive voltage difference, adjacent conductors may have an overdrive time T od The reduced voltage level applied within.

[0066] exist Figure 7 5A and 5B, and may depict the related art at an overdrive time T. od Overdrive voltage difference V od Line 740 may represent a line connected to a selected sensing circuit for the overdrive time T according to an embodiment. od Overdrive voltage difference V odThe voltage level (e.g., read voltage Vwlrv) applied by a voltage driver to a first end (e.g., proximal end) of a word line (SelWL) performing a sensing operation. Line 742 may represent the voltage level of a second end (e.g., distal end) of a selected word line SelWL according to an embodiment. Line 744 may represent the voltage level (e.g., via voltage Vpass1) applied to a first end (e.g., proximal end) of a word line (WL±1) that is not selected for the sensing operation and is adjacent (e.g., immediately adjacent) to the selected word line SelWL according to an embodiment. Line 746 may represent the voltage level of the second end (e.g., distal end) of the unselected word line WL±1 according to an embodiment. Although not depicted in Figure 7 Figure 7 , word lines at higher adjacent levels (e.g., WL±2, WL±3, etc.) may have the same target voltage level 549 as the word line WL±1, or they may have different target voltage levels (or corresponding different target voltage levels), e.g., lower or higher than the target voltage level 549. For example, in a sensing operation, various strategies for reducing read interference may see the word line WL±1 having a higher target voltage level or a lower target voltage level than word lines at higher adjacent levels.

[0067] By cross-driving the unselected word line WL±1 at a reduced voltage level during an over-drive time T as represented by line 744, the voltage level of the unselected word line WL±1 as represented by line 746 may not rise as much as in an example of the related art, where, as represented by line 544, the unselected word line WL±1 is driven at its target voltage level 549 during the over-drive time T od od . Therefore, the voltage level of the selected word line SelWL represented by line 742 may not rise as fast as the voltage level of the selected word line SelWL represented by line 542. However, the voltage level of the selected word line SelWL represented by line 742 may also not be pulled down as low at the end of the over-drive time T od od as the voltage level of the selected word line SelWL represented by line 542. Thus, the use of cross-driving according to an embodiment may reduce the settling time of the selected word line SelWL. od od

[0068] The cross-driving voltage difference V cd may have a magnitude less than the magnitude of the over-drive voltage difference V od od . For example, the magnitude of the cross-driving voltage difference V cd may be equal to |X * V od od |, where 0 < X < 1. As an example, the value X = 0.25 as compared to using the same V odRelated technologies of values can facilitate reducing the settling time, such as the time to reach and stabilize within ±10 mV of its target voltage level. Similarly, the value X = 0.25 can facilitate reducing V that can produce a settling time similar to (e.g., the same or lower) that of related technologies. od Values. Other X values are expected to facilitate improvements over related technologies that rely only on overdriving. For some embodiments, 0.125 <= X <= 0.5. For example, as noted regarding sensing operations in a memory, facilitating a reduction in the overdrive voltage difference V od without sacrificing the settling time can provide industrial advantages.

[0069] The cross-drive voltage difference V cd can further have a polarity opposite to that of the overdrive voltage difference V od . For example, during the overdrive time T od , if the difference between the voltage level applied to the selected word line SelWL and its target voltage level 547 has a first magnitude and a first polarity (e.g., positive), then during the overdrive time T od , the difference between the voltage level applied to the unselected word line WL±1 and its target voltage level 549 has a second magnitude less than the first magnitude and a second polarity opposite to the first polarity (e.g., negative).

[0070] The magnitude of the cross-drive voltage difference V cd in the immediate vicinity of the conductor is equal to |X * V od | (where 0 < X < 1). In this case, the magnitude of the cross-drive voltage difference V cd of the secondary adjacent conductor can be less than |X * V od |. This concept can be extended such that the magnitude of the cross-drive voltage difference V cd of the third adjacent conductor can be less than the magnitude of the cross-drive voltage difference V cd of the secondary adjacent conductor, and so on. For example, the magnitude of the cross-drive voltage difference V cd of the Nth-level adjacent conductor can be equal to |X^N * V od |. Alternatively, the magnitude of the cross-drive voltage difference V cd of the Nth-level adjacent conductor can be equal to |X / N * V od |.

[0071] Similarly, the magnitude of the cross-drive voltage difference V cd of the Nth-level adjacent conductor can be equal to the absolute value of the product of V od and some other function of X, where the magnitude of the cross-drive voltage difference V cd of a particular adjacent level is less than or equal to the magnitude of the cross-drive voltage difference V cd of any lower adjacent level. For example, the function of X can be f(X, n) = {Y1 ,Y 2 ,……,Y N}, where for n=1 to N, 1>Y 1 >Y 2 >……>Y N >0. It should be recognized that higher adjacent levels can be expected to show diminishing returns in promoting the improvements described herein. Therefore, for some adjacent levels, the cross-drive voltage difference V cd The expected magnitude of may be equal to zero.

[0072] Although the examples have depicted a positive overdrive voltage difference V od , but the concepts discussed in this article can be applied to negative overdrive voltage differences V od Therefore, if the overdrive time T od The difference between the voltage level applied to the selected word line SelWL and its target voltage level 547 during the overdrive time T od The difference between the voltage level applied to the unselected word lines WL±1 and their target voltage level 549 during the period may have a second magnitude less than the first magnitude and a positive polarity.

[0073] Figures 8A to 8B Waveforms of an adjacent conductor and its driver are depicted during a sensing operation using conditions according to an embodiment compared to an overdrive condition of the related art. Fig. 8A For example, compared to Figure 7 Additional details for a more complete sensing operation. Figure 8B Additional details are provided as to the differences that may be expected between driving word lines in the related art and driving word lines according to embodiments.

[0074] In FIG. 8 , lines 540 , 542 , 544 , 546 , 547 , and 549 may correspond to the discussion on the left side of FIGS. 5A and 5B , and may depict the related art at an overdrive time T od Overdrive voltage difference V od Line 840 may represent a line connected to a selected sensing circuit for the overdrive time T according to an embodiment. od Overdrive voltage difference V odA voltage level (e.g., a read voltage Vwlrv) applied by a voltage driver at a first end (e.g., a near end) of a word line (SelWL) for a sensing operation. Line 842 may represent a voltage level at a second end (e.g., a far end) of a selected word line SelWL according to an embodiment. Line 844 may represent a voltage level (e.g., a pass voltage Vpass1) applied to a first end (e.g., a near end) of a word line (WL±1) that is not selected for a sensing operation and is adjacent to (e.g., immediately adjacent to) the selected word line SelWL according to an embodiment. Line 846 may represent a voltage level at a second end (e.g., a far end) of an unselected word line WL±1 according to an embodiment.

[0075] During a sensing operation of a memory, the same voltage level is typically applied to all word lines during the first portion of the sensing operation, followed by a reduction in the voltage level applied to the selected word lines until the unselected word lines reach a target voltage level for the pass voltage. Fig. 8A In the example, all word lines (e.g. Figure 2A All word lines 202 of the NAND string 206 0 By 202 N ) may be connected to receive the voltage levels represented by line 544 of the related art and by line 844 according to an embodiment at time t0. At time t1, the selected word line (e.g. Figure 2A Word line 202 x+1 ) may be connected to receive the voltage level represented by the related art line 540 and the line 840 according to the embodiment. At time t2, the voltage level represented by the related art line 540 and the line 840 according to the embodiment may be increased to the first target voltage level to maintain the selected word line while waiting for the unselected word lines to reach their target voltage levels. At time t3, the voltage level represented by the related art line 540 and the line 840 according to the embodiment may be increased to the target voltage level V corresponding to the selected word line. target Add overdrive voltage difference V od Still at time t3, the voltage level represented by line 540 of the related art may be maintained at the target voltage of the unselected word line, while the voltage level represented by line 840 according to the embodiment may be reduced by the cross-driving voltage difference V cd At time t4, the voltage level represented by the line 540 of the related art and the line 840 according to the embodiment may be lowered to a target voltage level V corresponding to the selected word line. target Also at time t4, the voltage level represented by the related art line 540 may be maintained at the target voltage of the unselected word line, and the voltage level represented by the line 840 according to the embodiment may be increased to the target voltage of the unselected word line.

[0076] exist Figure 8BDescribed in more detail in Fig. 8A 848. Specifically, Figure 8B Depicting the overdrive time T according to an embodiment od During the use of cross drive voltage difference V cd Compared with the related art, the overdrive time T od The voltage level of the selected word line is maintained during the period of time. The line 842 according to the embodiment can be regarded as having stabilized at time t4a, for example, reaching and maintaining a specific voltage level within a specific tolerance. In contrast, the line 542 of the related art can be regarded as not being stable until time t4b. In addition, the overshoot of the line 542 exceeding the target voltage level 547 can cause unintended current flow during the sensing operation of the related art.

[0077] Fig. 9 Conceptually depicting the expected applied voltage levels of adjacent conductors using an overdrive condition according to an embodiment. Fig. 9 , line 940 may represent a voltage level (e.g., an expected voltage level) that will be applied to a first conductor at various times. Line 944 may represent a voltage level (e.g., an expected voltage level) that will be applied to a second conductor at various times. The second conductor may be adjacent to (e.g., immediately adjacent to) the first conductor. Alternatively, the second conductor may represent a secondary adjacent conductor or another subsequent adjacent conductor.

[0078] At time t0, line 940 may have a voltage level (e.g., an initial voltage level) that is different from (e.g., lower than) target voltage level 947 for the first conductor, while line 944 may have a voltage level (e.g., an initial voltage level) corresponding to target voltage level 949 for the second conductor. At time t1, line 940 may have a voltage level that is different from (e.g., higher than) target voltage level 947 by an amount equal to the overdrive voltage difference V od , while line 944 may have a voltage level that is different from (eg, lower than) the target voltage level 949 by a value equal to the cross-drive voltage difference V cd At time t2, line 940 may have a voltage level equal to target voltage level 947, and line 944 may have a voltage level equal to target voltage level 949.

[0079] Fig.101 is a flow chart of a method for driving a conductor according to an embodiment. At 1051, a first voltage level may be applied to a first conductor while a second voltage level is applied to a second conductor. The second voltage level may correspond to a target voltage level for the second conductor. At 1053, for example, after 1051, a third voltage level may be applied to the first conductor while a fourth voltage level is applied to the second conductor. The difference between the third voltage level and the first voltage level may have a specific polarity, and the difference between the fourth voltage level and the second voltage level may have a polarity opposite to the specific polarity. At 1055, for example, after 1053, a fifth voltage level may be applied to the first conductor while a second voltage level is applied to the second conductor. The difference between the fifth voltage level and the first voltage level may have the specific polarity. The fifth voltage level may correspond to a target voltage level for the first conductor. The difference between the third voltage level and the first voltage level may have a magnitude greater than the difference between the fifth voltage level and the first voltage level.

[0080] The first conductor may be adjacent to (eg, immediately adjacent to) the second conductor. For example, the first conductor may correspond to word line 202. x , and the second conductor may correspond to the adjacent word line 202 x-1 or 202 x+1 For some embodiments, Fig.10 The method can be performed for different adjacent levels. For example, the first conductor can correspond to word line 202 x , and the second conductor may correspond to the secondary adjacent word line 202 x-2 or 202 x+2 .

[0081] also, Fig.10 The method may be performed concurrently (e.g., simultaneously) for multiple adjacent levels. For example, Fig.10 The method may be respectively directed to the word lines 202 x The first conductor and the corresponding adjacent word line 202 x-1 or 202 x+1 The second conductor of the word line 202 x and corresponding to the secondary adjacent word line 202 x-2 or 202 x+2 Similarly, Fig.10 The method may be directed to a word line 202 corresponding to x The first conductor and the corresponding adjacent word line 202 x-1 The second conductor of the word line 202 x The first conductor and the corresponding adjacent word line 202 x+1 The second conductor executes concurrently.

[0082] For some embodiments, Fig.10 The method may be performed to apply a third voltage level to a first conductor and a fourth voltage level to a second conductor at 1053, wherein the second conductor is a proximate conductor and the third voltage level is applied to a third conductor that is a different proximate conductor. That is, two (or more) proximate conductors may receive an overdrive voltage difference V od .

[0083] Fig.11 1 is a flow chart of a method for driving a conductor according to another embodiment. At 1161, a first voltage level may be applied to a first conductor while a second voltage level is applied to a second conductor and a third conductor. The second voltage level may correspond to a target voltage level for the second conductor and the third conductor. The second conductor may be between the first conductor and the third conductor. At 1163, for example, after 1161, a third voltage level may be applied to the first conductor while a fourth voltage level is applied to the second conductor, and a fifth voltage level may be applied to the third conductor. The difference between the third voltage level and the first voltage level may have a specific polarity, the difference between the fourth voltage level and the second voltage level may have a polarity opposite to the specific polarity and a specific magnitude, and the difference between the fifth voltage level and the second voltage level may have a polarity opposite to the specific polarity and a magnitude less than the specific magnitude. At 1165, for example, after 1163, a sixth voltage level may be applied to the first conductor while a second voltage level is applied to the second conductor and the third conductor. The difference between the sixth voltage level and the first voltage level may have the specific polarity. The sixth voltage level may correspond to a target voltage level for the first conductor. The difference between the third voltage level and the first voltage level may have a magnitude greater than the difference between the sixth voltage level and the first voltage level. Similar to reference Fig.10 As described, Fig.11 The method may be performed concurrently for other conductors of different adjacent levels to the first conductor, and for other conductors of the same adjacent level to the first conductor.

[0084] Fig.12 is a flowchart of a method for operating a memory according to an embodiment. Fig. 8A At time t0, 1271, a first voltage level may be applied to the selected access line, while a first voltage level may be applied to the unselected access lines. The first voltage level may correspond to a target voltage level for the unselected access lines. Fig. 8A At time t2 1273, a second voltage level lower than the first voltage level may be applied to the selected access line, while the first voltage level is applied to the unselected access lines. Fig. 8A At time t3 1275, a third voltage level higher than the second voltage level may be applied to the selected access line, while a fourth voltage level lower than the first voltage level may be applied to the unselected access lines. Fig. 8A At time t4, a fifth voltage level lower than the third voltage level may be applied to the selected access line, while the first voltage level is applied to the unselected access lines. The difference between the third voltage level and the fifth voltage level may be greater than the difference between the first voltage level and the fourth voltage level. The fifth voltage level may correspond to a target voltage level for the selected access line. Similar to reference Fig.10 As described, Fig.12 The method may be performed concurrently for other unselected word lines of different neighboring levels of the selected word line, and for other unselected word lines of the same neighboring level of the selected word line.

[0085] Fig.13 1381, a first voltage level may be applied to a first conductor, a second voltage level may be applied to a second conductor, and a third voltage level may be applied to a third conductor. The second voltage level may correspond to a target voltage level for the second conductor. The third voltage level may correspond to a target voltage level for the third conductor. The third voltage level may be lower or higher than the second voltage level. The second conductor may be between the first conductor and the third conductor. At 1383, for example, after 1381, a fourth voltage level may be applied to the first conductor, a fifth voltage level may be applied to the second conductor, and a sixth voltage level may be applied to the third conductor. The difference between the fourth voltage level and the first voltage level may have a specific polarity, the difference between the fifth voltage level and the second voltage level may have a polarity opposite to the specific polarity and a specific magnitude, and the difference between the sixth voltage level and the third voltage level may have a polarity opposite to the specific polarity and a magnitude less than the specific magnitude. At 1385, e.g., after 1383, a seventh voltage level may be applied to the first conductor while the second voltage level is applied to the second conductor and the third voltage level is applied to the third conductor. The difference between the seventh voltage level and the first voltage level may have the particular polarity. The seventh voltage level may correspond to a target voltage level for the first conductor. The difference between the fourth voltage level and the first voltage level may have a magnitude greater than the difference between the seventh voltage level and the first voltage level. Similar to reference Fig.10 As described, Fig.13 The method may be performed concurrently for other conductors of different adjacent levels to the first conductor, and for other conductors of the same adjacent level to the first conductor.

[0086] in conclusion

[0087] Although specific embodiments have been illustrated and described herein, it should be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Therefore, this application is intended to cover any adaptation or variation of the embodiments.

Claims

1. A method of operating an integrated circuit device, wherein include: applying a first voltage level to a first conductor while applying a second voltage level to a second conductor, wherein the second voltage level corresponds to a target voltage level for the second conductor; applying a third voltage level to the first conductor and simultaneously applying a fourth voltage level to the second conductor, wherein a difference between the third voltage level and the first voltage level has a particular polarity and a difference between the fourth voltage level and the second voltage level has a polarity opposite to the particular polarity; and A fifth voltage level is applied to the first conductor while the second voltage level is applied to the second conductor, wherein a difference between the fifth voltage level and the first voltage level has the particular polarity and the fifth voltage level corresponds to a target voltage level for the first conductor.

2. The method of claim 1 , wherein the second voltage level is applied to the second conductor include: The second voltage level is applied to the second conductor in close proximity to the first conductor.

3. The method according to claim 2, further comprising: include: applying the second voltage level to a third conductor while applying the first voltage level to the first conductor and while applying the second voltage level to the second conductor, wherein the second voltage level further corresponds to a target voltage level for the third conductor; applying the fourth voltage level to the third conductor while simultaneously applying the third voltage level to the first conductor and simultaneously applying the fourth voltage level to the second conductor; and applying the second voltage level to the third conductor while simultaneously applying the fifth voltage level to the first conductor and while simultaneously applying the second voltage level to the second conductor; The first conductor is between the second conductor and the third conductor.

4. The method according to claim 2, further comprising: include: applying the second voltage level to a third conductor while applying the first voltage level to the first conductor and while applying the second voltage level to the second conductor, wherein the second voltage level further corresponds to a target voltage level for the third conductor; applying a sixth voltage level to the third conductor while the third voltage level is applied to the first conductor and while the fourth voltage level is applied to the second conductor, wherein a difference between the sixth voltage level and the second voltage level has a polarity opposite to the particular polarity; and applying the second voltage level to the third conductor while simultaneously applying the fifth voltage level to the first conductor and while simultaneously applying the second voltage level to the second conductor; wherein the second conductor is between the first conductor and the third conductor; and Wherein a difference between the sixth voltage level and the second voltage level has a magnitude less than a magnitude of the difference between the fourth voltage level and the second voltage level.

5. The method according to claim 2, further comprising: include: applying a sixth voltage level to a third conductor while applying the first voltage level to the first conductor and while applying the second voltage level to the second conductor, wherein the sixth voltage level corresponds to a target voltage level for the third conductor; applying a seventh voltage level to the third conductor while the third voltage level is applied to the first conductor and while the fourth voltage level is applied to the second conductor, wherein a difference between the seventh voltage level and the sixth voltage level has a polarity opposite to the particular polarity; and applying the sixth voltage level to the third conductor while simultaneously applying the fifth voltage level to the first conductor and while simultaneously applying the second voltage level to the second conductor; wherein the second conductor is between the first conductor and the third conductor; and Wherein a difference between the seventh voltage level and the sixth voltage level has a magnitude less than a magnitude of the difference between the fourth voltage level and the second voltage level.

6. The method according to claim 2, further comprising: include: applying the first voltage level to a third conductor while simultaneously applying the first voltage level to the first conductor and simultaneously applying the second voltage level to the second conductor; applying the third voltage level to the third conductor while simultaneously applying the third voltage level to the first conductor and simultaneously applying the fourth voltage level to the second conductor; and applying the fifth voltage level to the third conductor while simultaneously applying the fifth voltage level to the first conductor and while simultaneously applying the second voltage level to the second conductor; The first conductor is adjacent to the second conductor and adjacent to the third conductor.

7. The method according to claim 6, further comprising: include: applying the second voltage level to a fourth conductor while applying the first voltage level to the first conductor and the third conductor and while applying the second voltage level to the second conductor, wherein the second voltage level further corresponds to a target voltage level for the fourth conductor; applying the fourth voltage level to the fourth conductor while simultaneously applying the third voltage level to the first conductor and the third conductor, and simultaneously applying the fourth voltage level to the second conductor; and applying the second voltage level to the fourth conductor while simultaneously applying the fifth voltage level to the first conductor and the third conductor and while simultaneously applying the second voltage level to the second conductor; wherein the first conductor is between the third conductor and the second conductor; and The third conductor is between the fourth conductor and the first conductor.

8. The method of claim 1, wherein the first voltage level is applied to the first conductor while the second voltage level is applied to the second conductor include: The first voltage level is applied to a first conductive plate, while the second voltage level is applied to a second conductive plate.

9. The method of claim 1, wherein the first voltage level is applied to the first conductor while the second voltage level is applied to the second conductor include: The first voltage level is applied to a first conductive plate, while the second voltage level is applied to a second conductive plate that is parallel to and immediately adjacent to the first conductive plate.

10. A method of operating an integrated circuit device, wherein include: applying a first voltage level to a first conductor and simultaneously applying a second voltage level to a second conductor and a third conductor, wherein the second voltage level corresponds to a target voltage level for the second conductor and the third conductor, and wherein the second conductor is between the first conductor and the third conductor; applying a third voltage level to the first conductor, simultaneously applying a fourth voltage level to the second conductor and simultaneously applying a fifth voltage level to the third conductor, wherein a difference between the third voltage level and the first voltage level has a particular polarity, a difference between the fourth voltage level and the second voltage level has a polarity opposite to the particular polarity and a particular magnitude, and a difference between the fifth voltage level and the second voltage level has the polarity opposite to the particular polarity and a magnitude less than the particular magnitude; and A sixth voltage level is applied to the first conductor while the second voltage level is applied to the second conductor and the third conductor, wherein a difference between the sixth voltage level and the first voltage level has the particular polarity, and wherein the sixth voltage level corresponds to a target voltage level for the first conductor.

11. The method of claim 10, wherein the second voltage level is applied to the second conductor and the third conductor include: The second voltage level is applied to the second conductor immediately adjacent to the first conductor in a first direction, and the second voltage level is applied to the third conductor immediately adjacent to the second conductor in the first direction.

12. The method according to claim 10, further comprising: include: applying the fourth voltage level to a fourth conductor while applying the third voltage level to the first conductor, while applying the fourth voltage level to the second conductor, and while applying the fifth voltage level to the third conductor; The fourth conductor has the same proximity level to the first conductor as the second conductor.

13. The method according to claim 12, further comprising: include: applying the fifth voltage level to a fifth conductor while applying the third voltage level to the first conductor, applying the fourth voltage level to the second conductor and the fourth conductor, and applying the fifth voltage level to the third conductor; The fifth conductor has the same proximity level to the first conductor as the third conductor.

14. The method according to claim 10, wherein the difference between the second voltage level and the fourth voltage level is equal to X times the difference between the third voltage level and the sixth voltage level, where 0 < X < 1, wherein the difference between the second voltage level and the fifth voltage level is equal to a specific factor multiplied by the difference between the third voltage level and the sixth voltage level, and wherein the specific factor is less than X.

15. The method according to claim 14, wherein the specific factor is selected from the group consisting of X^2 and X / 2.

16. The method according to claim 10, further comprising: applying the second voltage level to a fourth conductor while applying the first voltage level to the first conductor and while applying the second voltage level to the second conductor and the third conductor, wherein the second voltage level corresponds to a target voltage level of the fourth conductor, and wherein the first conductor is between the fourth conductor and the second conductor; applying the fourth voltage level to the fourth conductor while applying the third voltage level to the first conductor, applying the fourth voltage level to the second conductor, and applying the fifth voltage level to the third conductor; and applying the second voltage level to the fourth conductor while applying the sixth voltage level to the first conductor, and applying the second voltage level to the second conductor and the third conductor.

17. The method according to claim 16, further comprising: applying the second voltage level to a fifth conductor while applying the first voltage level to the first conductor and while applying the second voltage level to the second conductor, the third conductor, and the fourth conductor, wherein the second voltage level corresponds to a target voltage level of the fifth conductor, and wherein the fourth conductor is between the fifth conductor and the first conductor; applying the fifth voltage level to the fifth conductor while applying the third voltage level to the first conductor, applying the fourth voltage level to the second conductor and the fourth conductor, and applying the fifth voltage level to the third conductor; and applying the second voltage level to the fifth conductor while applying the sixth voltage level to the first conductor, and applying the second voltage level to the second conductor, the third conductor, and the fourth conductor.

18. A method of operating an integrated circuit device, which comprises: applying a first voltage level to a first conductor while applying a second voltage level to a second conductor and while applying a third voltage level to a third conductor, wherein the second voltage level corresponds to a target voltage level of the second conductor, wherein the third voltage level corresponds to a target voltage level of the third conductor, and wherein the second conductor is between the first conductor and the third conductor; Apply a fourth voltage level to the first conductor while applying a fifth voltage level to the second conductor and while applying a sixth voltage level to the third conductor, wherein the difference between the fourth voltage level and the first voltage level has a specific polarity, the difference between the fifth voltage level and the second voltage level has a polarity opposite to the specific polarity and a specific magnitude, and the difference between the sixth voltage level and the third voltage level has a polarity opposite to the specific polarity and a magnitude less than the specific magnitude; and Apply a seventh voltage level to the first conductor while applying the second voltage level to the second conductor and while applying the third voltage level to the third conductor, wherein the difference between the seventh voltage level and the first voltage level has the specific polarity, and wherein the seventh voltage level corresponds to a target voltage level of the first conductor.

19. The method according to claim 18, wherein applying the second voltage level to the second conductor comprises: Applying the second voltage level to the second conductor adjacent to the first conductor in a first direction, and applying the second voltage level to a fourth conductor adjacent to the first conductor in a second direction different from the first direction, and wherein applying the third voltage level to the third conductor comprises: applying the third voltage level to the third conductor adjacent to the second conductor in the first direction, and applying the third voltage level to a fifth conductor adjacent to the fourth conductor in the second direction.

20. The method according to claim 18, wherein the difference between the second voltage level and the fifth voltage level is equal to X times the difference between the fourth voltage level and the seventh voltage level, where 0 < X < 1, wherein the difference between the third voltage level and the sixth voltage level is equal to a specific factor multiplied by the difference between the fourth voltage level and the seventh voltage level, and wherein the specific factor is less than X.

21. The method according to claim 18, wherein applying the second voltage level to the second conductor while applying the third voltage level to the third conductor comprises: The second voltage level is higher than the third voltage level.

22. The method according to claim 18, which further comprises: Applying an eighth voltage level to a fourth conductor while applying the first voltage level to the first conductor, while applying the second voltage level to the second conductor and while applying the third voltage level to the third conductor, wherein the eighth voltage level corresponds to a target voltage level of the fourth conductor, and wherein the third conductor is between the second conductor and the fourth conductor; applying a ninth voltage level to the fourth conductor while applying the fourth voltage level to the first conductor, while applying the fifth voltage level to the second conductor and while applying the sixth voltage level to the third conductor, wherein a difference between the ninth voltage level and the eighth voltage level has a polarity opposite to the particular polarity and a magnitude less than the difference between the sixth voltage level and the third voltage level; and The eighth voltage level is applied to the fourth conductor while the seventh voltage level is applied to the first conductor while the second voltage level is applied to the second conductor and the third voltage level is applied to the third conductor.

23. An integrated circuit device, include: Multiple conductors; and A controller, wherein the controller is configured to perform the method of any one of claims 1 to 22.

24. A device, wherein include: a memory cell array comprising a plurality of grouped memory cells; a plurality of access lines, each of the plurality of access lines connected to control gates of a corresponding group of memory cells of the plurality of groups of memory cells; and A controller for accessing the memory cell array, wherein the controller is configured to: applying a first voltage level to a selected access line of an access operation while applying the first voltage level to unselected access lines of the access operation, wherein the first voltage level corresponds to a target voltage level for the unselected access lines of the access operation; applying a second voltage level lower than the first voltage level to the selected access line while applying the first voltage level to the unselected access lines; applying a third voltage level higher than the second voltage level to the selected access line while applying a fourth voltage level lower than the first voltage level to the unselected access lines; and applying a fifth voltage level lower than the third voltage level to the selected access line while applying the first voltage level to the unselected access lines; wherein a difference between the third voltage level and the fifth voltage level is greater than a difference between the first voltage level and the fourth voltage level; and Wherein the fifth voltage level corresponds to a target voltage level of the selected access line of the access operation.

25. The apparatus of claim 24, wherein the controller is further configured to concurrently transition the selected access line from the second voltage level to the third voltage level and the unselected access lines from the first voltage level to the fourth voltage level.

26. The apparatus of claim 25, wherein the controller is further configured to concurrently transition the selected access line from the third voltage level to the fifth voltage level and the unselected access lines from the fourth voltage level to the first voltage level.

27. The apparatus of claim 24, wherein the selected access line is a first conductive plate, and wherein the unselected access line is a second conductive plate.

28. The apparatus of claim 27, wherein the first conductive plate is parallel to the second conductive plate.

29. The apparatus of claim 24, wherein the unselected access line is a particular unselected access line of a plurality of unselected access lines for the access operation, and wherein the controller is further configured to: applying the first voltage level to the selected access line of the access operation while applying the first voltage level to each unselected access line of the plurality of unselected access lines, wherein the first voltage level corresponds to a target voltage level for each unselected access line of the plurality of unselected access lines; applying the second voltage level to the selected access line while applying the first voltage level to each unselected access line of the plurality of unselected access lines; applying the third voltage level to the selected access line while applying the fourth voltage level to each unselected access line of the plurality of unselected access lines; and The fifth voltage level is applied to the selected access line while the first voltage level is applied to each unselected access line of the plurality of unselected access lines.

30. The apparatus of claim 24, wherein the selected access line is connected to control gates of memory cells in a series-connected string of memory cells, and wherein the first voltage level is applied to the selected access line for the access operation while the first voltage level is applied to each unselected access line of the plurality of unselected access lines. include: The first voltage level is applied to a respective control gate of each memory cell in the series-connected string of memory cells.

31. The apparatus of claim 24, wherein the unselected access line is a particular unselected access line of a plurality of unselected access lines for the access operation, and wherein the controller is further configured to: applying the first voltage level to the selected access line of the access operation, while applying the first voltage level to the particular unselected access line and while applying a sixth voltage level to a different unselected access line of the plurality of unselected access lines, wherein the sixth voltage level corresponds to a target voltage level for the different unselected access line, and wherein the particular unselected access line is between the selected access line and the different unselected access line; applying the second voltage level to the selected access line while applying the first voltage level to the particular unselected access line and while applying the sixth voltage level to the different unselected access line; applying the third voltage level to the selected access line while applying the fourth voltage level to the particular unselected access line and while applying a seventh voltage level to the different unselected access line; and Apply the fifth voltage level to the selected access line while applying the first voltage level to the specific unselected access line and while applying the sixth voltage level to the different unselected access lines; where the difference between the sixth voltage level and the seventh voltage level is less than the difference between the first voltage level and the fourth voltage level.

32. The apparatus according to claim 31, wherein the controller is configured to apply the first voltage level to the specific unselected access line comprising: The controller is configured to apply the first voltage level to the specific unselected access line adjacent to the selected access line in a first direction, and to apply the first voltage level to additional unselected access lines among the plurality of access lines adjacent to the selected access line in a second direction different from the first direction, and wherein the controller is configured to apply the sixth voltage level to the different unselected access lines comprises: the controller is configured to apply the sixth voltage level to the different unselected access line adjacent to the specific unselected access line in the first direction, and to apply the sixth voltage level to another unselected access line among the plurality of access lines adjacent to the additional unselected access line in the second direction.

33. The apparatus according to claim 31, wherein the difference between the first voltage level and the fourth voltage level is equal to X times the difference between the third voltage level and the fifth voltage level, where 0 < X < 1, wherein the difference between the sixth voltage level and the seventh voltage level is equal to a specific factor multiplied by the difference between the third voltage level and the fifth voltage level, and wherein the specific factor is less than X.

34. The apparatus according to claim 31, wherein the controller is configured to apply the first voltage level to the specific unselected access line while applying the sixth voltage level to the different unselected access lines comprising: The first voltage level is higher than the sixth voltage level.

35. The apparatus according to claim 31, wherein the controller is further configured to: Apply an eighth voltage level to an additional unselected access line among the plurality of access lines while applying the second voltage level to the selected access line, while applying the first voltage level to the specific unselected access line and while applying the sixth voltage level to the different unselected access lines, wherein the eighth voltage level corresponds to the target voltage level of the additional unselected access line, and wherein the different unselected access line is between the specific unselected access line and the additional unselected access line; applying a ninth voltage level to the additional unselected access line while applying the third voltage level to the selected access line while applying the fourth voltage level to the particular unselected access line and while applying the seventh voltage level to the different unselected access line, wherein a difference between the eighth voltage level and the ninth voltage level is less than the difference between the sixth voltage level and the seventh voltage level; and The eighth voltage level is applied to the additional unselected access line while the fifth voltage level is applied to the selected access line while the first voltage level is applied to the particular unselected access line and the sixth voltage level is applied to the different unselected access line.

36. The apparatus of claim 24, wherein the unselected access line is a first unselected access line for the access operation, and wherein the controller is further configured to: applying the first voltage level to a second unselected access line of the access operation while applying the first voltage level to the selected access line and while applying the first voltage level to the first unselected access line, wherein the first voltage level corresponds to a target voltage level for the second unselected access line of the access operation; applying the fourth voltage level to the second unselected access line while applying the third voltage level to the selected access line and while applying the fourth voltage level to the first unselected access line; and applying the first voltage level to the second unselected access line while applying the fifth voltage level to the selected access line and while applying the first voltage level to the first unselected access line; Wherein the selected access line is immediately adjacent to the first unselected access line and immediately adjacent to the second unselected access line.

37. The apparatus of claim 36, wherein the controller is further configured to: applying the first voltage level to a third unselected access line of the access operation while applying the first voltage level to the selected access line, the first unselected access line, and the second unselected access line, wherein the first voltage level corresponds to a target voltage level for the third unselected access line of the access operation; applying a sixth voltage level lower than the first voltage level to the third unselected access line while applying the third voltage level to the selected access line and applying the fourth voltage level to the first unselected access line and the second unselected access line; and applying the first voltage level to the third unselected access line while applying the fifth voltage level to the selected access line and while applying the first voltage level to the first unselected access line and the second unselected access line; wherein a magnitude of a difference between the sixth voltage level and the first voltage level is less than a magnitude of a difference between the fourth voltage level and the first voltage level; wherein the third unselected access line is immediately adjacent to the first unselected access line; and The first unselected access line is between the selected access line and the third unselected access line.

38. The apparatus of claim 37, wherein the controller is further configured to: applying the first voltage level to a fourth unselected access line of the access operation while applying the first voltage level to the selected access line, the first unselected access line, the second unselected access line, and the third unselected access line, wherein the first voltage level corresponds to a target voltage level for the fourth unselected access line of the access operation; applying the first voltage level to the fourth unselected access line while applying the third voltage level to the selected access line, applying the fourth voltage level to the first unselected access line and the second unselected access line while applying the sixth voltage level to the third unselected access line; and applying the first voltage level to the fourth unselected access line while applying the fifth voltage level to the selected access line and while applying the first voltage level to the first unselected access line, the second unselected access line, and the third unselected access line; wherein the fourth unselected access line is immediately adjacent to the third unselected access line; and Wherein the third unselected access line is between the first unselected access line and the fourth unselected access line.

39. The apparatus of claim 24, wherein the unselected access line is a first unselected access line for the access operation, and wherein the controller is further configured to: applying the first voltage level to a second unselected access line of the access operation while applying the first voltage level to the selected access line and while applying the first voltage level to the first unselected access line, wherein the first voltage level corresponds to a target voltage level for the second unselected access line of the access operation; applying the first voltage level to the second unselected access line while applying the third voltage level to the selected access line and while applying the fourth voltage level to the first unselected access line; and applying the first voltage level to the second unselected access line while applying the fifth voltage level to the selected access line and while applying the first voltage level to the first unselected access line; wherein the first unselected access line is separated from the selected access line by a first distance; and Wherein the second unselected access line is separated from the selected access line by a second distance greater than the first distance.

40. The apparatus of claim 24, wherein the unselected access line is a first unselected access line for the access operation, and wherein the controller is further configured to: applying a sixth voltage level different from the first voltage level to a second unselected access line of the access operation while applying the first voltage level to the selected access line and while applying the first voltage level to the first unselected access line, wherein the sixth voltage level corresponds to a target voltage level for the second unselected access line of the access operation; applying the sixth voltage level to the second unselected access line while applying the third voltage level to the selected access line and while applying the fourth voltage level to the first unselected access line; and applying the sixth voltage level to the second unselected access line while applying the fifth voltage level to the selected access line and while applying the first voltage level to the first unselected access line; wherein the first unselected access line is separated from the selected access line by a first distance; and Wherein the second unselected access line is separated from the selected access line by a second distance greater than the first distance.

41. The apparatus of claim 40, wherein the sixth voltage level is lower than the first voltage level.

Images