Split gate non-volatile memory cells with finfet structures and hkmg memory and logic gates and methods of making the same

Abstract

A memory device has a plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin, and a logic device formed on a second fin. The memory cell includes a source region and a drain region in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including a side surface and a top surface of the first fin, a metal select gate extending along a second portion of the channel region including the side surface and the top surface of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes a source region and a drain region in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including a side surface and a top surface of the second fin.

Description

[0001] Priority Statement

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 208,150, filed on December 3, 2018, entitled "Split Gate Non-volatile Memory Cells With FINFET Structure And HKMG Memory And Logic Gates, And Method Of Making Same". Technical Field

[0003] This invention relates to non-volatile flash memory cell arrays. Background Technology

[0004] Split-gate nonvolatile memory devices are well known in the art. For example, U.S. Patent 7,927,994 discloses a split-gate nonvolatile memory cell. Figure 1 An example of such a split-gate memory cell formed on a semiconductor substrate 12 is shown. A source region 16 and a drain region 14 are formed in the substrate 12 as diffused regions, defining a channel region 18 between them. The memory cell includes four conductive gates: a floating gate 22 disposed over a first portion of the channel region 18 and a portion of the source region 16 and insulated from both the first and second portions of the channel region; a control gate 26 disposed over the floating gate 22 and insulated from it; an erase gate 24 disposed over the source region 16 and insulated from it; and a select gate 20 disposed over a second portion of the channel region 18 and insulated from it. Conductive contacts 10 may be formed to be electrically connected to the drain region 14. Because the channel region is formed along a flat surface of the semiconductor substrate, the total area (e.g., width) of the channel region decreases as the device geometry decreases. This reduces the current flow between the source and drain regions, thus requiring a particularly sensitive sense amplifier to detect the state of the memory cell.

[0005] Because reducing the lithography size and thus the channel width affects all semiconductor devices, fin-type field-effect transistor (FET) structures have been proposed. In a fin-type FET structure, a fin-shaped member of the semiconductor material connects the source region to the drain region. The fin-shaped member includes two side surfaces that terminate at a top surface. Current can then flow from the source region to the drain region along the two side surfaces and the top surface. Therefore, the width of the channel region increases, thereby increasing the current. However, by "folding" the channel region into two side surfaces and a top surface to increase the width of the channel region without sacrificing more semiconductor substrate surface area, the "coverage area" of the channel region is reduced. Non-volatile memory cells using such fin-type FETs have been disclosed, in which the floating gate is positioned adjacent to one of the side surfaces of the fin-shaped member. Some examples of prior art fin-type FET non-volatile memory structures (although the number and configuration of gates differ) are also provided. Figure 1 The planar examples described above include U.S. Patent Nos. 7,423,310, 7,410,913, and 8,461,640, and U.S. Patent Publication 2017 / 0345,840. Forming logic devices on fin-shaped members is also proposed. See, for example, U.S. Patent Publication 2017 / 0125,429 and pending U.S. Patent Application 15 / 933,124.

[0006] However, these prior art fin field-effect transistor structures have disclosed the use of floating gates in stacked gate configurations, or the use of trapping materials, or the use of silicon-rich oxide (SRO) or nanocrystalline silicon to store charge, or other more complex memory cell configurations, which may increase the cost of fabrication equipment. Summary of the Invention

[0007] The aforementioned problems and needs are addressed by a memory device comprising: a semiconductor substrate having an upper surface having a plurality of upwardly extending fins, wherein each fin includes a first side surface and a second side surface opposite to each other and terminating on the top surface; memory cells formed on the first fin of the plurality of fins; and logic devices formed on the second fin of the plurality of fins. The memory cell includes: a first source region and a first drain region spaced apart in a first fin, wherein a first channel region of the first fin extends between the first source region and the first drain region along a top surface and an opposite side surface of the first fin; a floating gate made of polysilicon extending along a first portion of the first channel region, wherein the floating gate extends along a first side surface, a second side surface, and a top surface of the first fin and is insulated from the first side surface, the second side surface, and the top surface of the first fin; a select gate made of metal extending along a second portion of the first channel region, wherein the select gate extends along a first side surface, a second side surface, and a top surface of the first fin and is insulated from the first side surface, the second side surface, and the top surface of the first fin; a control gate made of polysilicon extending along the floating gate and insulated from the floating gate; and an erase gate made of polysilicon extending along the first source region and insulated from the first source region. The logic device includes: a second source region and a second drain region spaced apart in a second fin, wherein a second channel region of the second fin extends between the second source region and the second drain region along a top surface and an opposite side surface of the second fin; and a first logic gate of metallic material extending along the second channel region, wherein the first logic gate extends along a first side surface, a second side surface, and a top surface of the second fin and is insulated from the first side surface, the second side surface, and the top surface of the second fin.

[0008] A method of forming a memory device includes: forming a plurality of upwardly extending fins in an upper surface of a semiconductor substrate, wherein each fin includes a first side surface and a second side surface opposite to each other and terminating in a top surface; forming a memory cell on a first fin of the plurality of fins; and forming a logic device on a second fin of the plurality of fins. A memory cell is formed by: forming a first source region and a first drain region spaced apart in a first fin, wherein a first channel region of the first fin extends between the first source region and the first drain region along the top surface and opposite side surface of the first fin; forming a floating gate of polysilicon material extending along a first portion of the first channel region, wherein the floating gate extends along a first side surface, a second side surface, and a top surface of the first fin and is insulated from the first side surface, the second side surface, and the top surface of the first fin; forming a select gate of metallic material extending along a second portion of the first channel region, wherein the select gate extends along a first side surface, a second side surface, and a top surface of the first fin and is insulated from the first side surface, the second side surface, and the top surface of the first fin; forming a control gate of polysilicon material extending along the floating gate and insulated from the floating gate; and forming an erase gate of polysilicon material extending along the first source region and insulated from the first source region. The logic device is formed by: forming a second source region and a second drain region spaced apart in a second fin, wherein a second channel region of the second fin extends between the second source region and the second drain region along the top surface and opposite side surface of the second fin; and forming a first logic gate of metallic material extending along the second channel region, wherein the first logic gate extends along the first side surface, the second side surface and the top surface of the second fin and is insulated from the first side surface, the second side surface and the top surface of the second fin.

[0009] Other objects and features of the invention will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0010] Figure 1 This is a side sectional view of a conventional non-volatile memory cell.

[0011] Figure 2 This is a top view of the memory area, showing various cross-sectional views in the other accompanying figures.

[0012] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figures 11A to 11C , Figures 12A to 12D , Figures 13A to 13D , Figures 14A to 14D , Figures 15A to 15D , Figures 16A to 16D , Figures 17A to 17D , Figures 18A to 18D , Figures 19A to 19D , Figures 20A to 20D , Figures 22A to 22D , Figures 23A to 23B , Figures 24A to 24B , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A and Figure 32A These are side sectional views of different cross-sectional positions and orientations of the memory region, illustrating the steps involved in forming the memory device of the present invention.

[0013] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11D , Figure 12E , Figure 13E , Figure 14E , Figure 15E , Figure 16E , Figure 17E , Figure 18E , Figure 19E , Figure 20E , Figure 21 , Figures 25B to 25C , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B and Figure 32B This is a side sectional view of the logic device region, illustrating the steps involved in forming the memory device of the present invention.

[0014] Figure 9C This is a top view of the memory region, showing the vertically and horizontally extending fins of the substrate.

[0015] Figure 33A and Figure 34A This is a side cross-sectional view of a memory region according to an alternative embodiment of the present invention, illustrating the steps of forming a memory device.

[0016] Figure 33B and Figure 34B This is a side cross-sectional view of the logic device region according to an alternative embodiment of the present invention, showing the steps of forming a memory device. Detailed Implementation

[0017] This embodiment implements a memory device with fin field-effect transistor split-gate memory cells, each cell having four gates: a floating gate 28, a control gate 30, a select gate 32, and an erase gate 34. The fin field-effect transistor logic devices are formed on the same substrate as the memory cells. Figure 2 This is a top view showing the configuration of a mirror pair of memory cells in a memory region of a substrate. The mirror pair of memory cells share a common source region 36 (i.e., a region of the substrate having a second conductivity type different from a first conductivity type of the substrate), wherein a drain region 38 (of the second conductivity type) is shared between adjacent pairs of memory cells (not shown). The substrate includes cross-fin portions 40 and 41 on the upper surface of a semiconductor substrate 42. Memory cells are formed on the fin portions 40. Figure 2 The cross-sectional directions a, b, c, d, and e for use in the figures described below are also shown.

[0018] The manufacturing process begins with the selective implantation of different regions into the semiconductor substrate 42. The various regions of the substrate 42 are... Figure 3A and Figure 3B The text shows (i.e., Figure 3A and Figure 3B Different regions of the same substrate 42 are shown, wherein the substrate has four regions associated with memory cells and logic devices: memory region 42a (where memory cells are formed), HV region 42b (where high-voltage logic devices are formed), logic core region 42c (where core logic devices are formed), and logic I / O region 42d (where input / output logic devices are formed). Regions 42b, 42c, and 42d are collectively referred to herein as logic regions. Preferably, selective implantation begins by covering the substrate except for the HV region with a masking material, the HV region undergoing one or more implantation steps (e.g., punch-through implantation, which will prevent source-to-drain leakage in the high-voltage logic devices formed in the region). This can be repeated for memory region 42a (e.g., covering other regions with a masking material and performing punch-through implantation, which will prevent source-to-drain leakage in the memory cells formed in the region).

[0019] Then, compared to the logic region of substrate 42, the upper surface of the memory region 42a of the substrate is recessed (lowered), such as... Figure 4A and Figure 4BAs shown. This is preferably accomplished by forming a material (e.g., silicon nitride) layer on substrate 42, followed by a masking step (i.e., photoresist deposition, selective photolithography exposure, and selective photoresist removal) that leaves photoresist on the silicon nitride in the logic region but exposes the silicon nitride in the memory region 42a. The silicon nitride is removed from the memory region 42a using silicon nitride etching, exposing the substrate surface. After photoresist removal, the exposed portion of substrate 42 (in memory region 42a) is oxidized, followed by wet oxide etching to remove the oxidized portion of the substrate, which effectively removes the top portion of the substrate (effectively lowering / recessing its upper surface). These steps can be repeated until the desired level of surface recess R (e.g., 300 nm to 500 nm) is achieved. The nitride is then removed from the logic region using nitride etching.

[0020] Fins are then formed on the upper surface of the substrate. Specifically, cross fins are formed in memory region 42a, while parallel fins are formed in the logic region. A silicon dioxide (oxide) layer 46 is formed on the upper surface of all four regions of the substrate 42 (memory region 42a, HV region 42b, logic core region 42c, and logic IO region 42d). A silicon nitride (nitride) layer 48 is formed on the oxide layer 46. A hard mask material (e.g., amorphous carbon) 50 is formed on the nitride layer 48. A photoresist 52 is formed on the hard mask material 50 and patterned using a masking step to expose a grid of intersecting stripes of the hard mask material 50, such as... Figure 5A and Figure 5B As shown. Etching is performed to remove the exposed portions of the hard mask material, leaving strips of hard mask material 50, as... Figure 6A and Figure 6B As shown (after removing the photoresist).

[0021] An oxide layer 54 is formed on top of the structure. This layer is conformal in the logic region because the spacing between the hard mask material strips in the logic region is larger than the spacing in the memory region 42a (where the layer fills the space between the hard mask material strips), such as... Figure 7A and Figure 7B As shown. Next, anisotropic oxide etching is performed, which leaves oxide spacers on the vertical sidewalls of the sufficiently spaced hard mask strips. Carbon wet strip etching is used to remove the carbon hard mask material, as shown. Figure 8A and Figure 8B As shown. In memory region 42a Figure 6A The spacing between two adjacent patterns of the hard mask material 50 is preferably less than or equal to twice the thickness of the oxide layer 54, in order to form a shape such that... Figure 8AThe merged spacers are shown. Photoresist is formed over the structure and patterned to leave photoresist strips that cover alternating oxide spacers / blocks in memory region 42a and may cover some oxide spacers in logic regions. Those remaining oxide spacers exposed by the photoresist are then removed using oxide etching. After photoresist removal, one or more etching operations are performed to remove portions of the nitride 48, oxide 46, and upper portion of the substrate 42 that are not below the remaining oxide spacers. This results in the formation of trenches 56 extending into the substrate, leaving thin fin structures 58 of the substrate 42 between adjacent trenches 56, such as... Figures 9A to 9B As shown (after removing the oxide spacers). Fins 58 extend in the memory region 42a in both the vertical (column) and horizontal (row) directions (i.e., they are the same as fins 40 and 41 mentioned above). Figure 9C A top view of memory region 42a is shown, in which fins 58 extend in a grid pattern in both row and column directions (i.e., vertically extending fins with lengths extending in the column direction intersect horizontally extending fins with lengths extending in the row direction in a grid-like manner). In memory region 42a, the final width of each fin 58 may be approximately 10 nm to 50 nm.

[0022] Although Figure 9B Only one fin 58 is shown in each of the HV region 42b, the logic core region 42c, and the logic IO region 42d, and Figure 9A Only two fins 58 in memory region 42a are shown, but multiple fins are formed in each region. Although not shown, the spacing between the fins will vary based on the region. For example, the distance between adjacent fins in logic core region 42c is preferably smaller than the distance between adjacent fins in memory region 42a. An insulating material 60 (e.g., oxide) (including filling trenches 56 with oxide 60) is formed over these structures, followed by oxide planarization (e.g., CMP) to remove any portion of the oxide 60 on top of the nitride 48. A hard mask layer (e.g., nitride) 62 is formed over the logic region but not over memory region 42a. Oxide etching is then used to recess the oxide 60 in memory region 42a (i.e., remove the upper portion of the oxide). The resulting structure is... Figure 10A and Figure 10B As shown in the image.

[0023] The nitride 48 and oxide 46 on top of the fins 58 in memory region 42a are removed using nitride etching and oxide etching (using photoresist to protect the nitride layer 62 in the logic region). After removing the photoresist, an oxide layer 64 is then formed on both side surfaces and the top surface of each fin 58 in memory region 42a (e.g., by oxidation). A polysilicon conformal layer 66 is then formed structurally (including on the oxide 64), such as... Figures 11A to 11D As shown. Then, in-situ doping of the polysilicon layer 66 is performed. A masking step and polysilicon etching are performed to remove selected portions of the polysilicon layer 66 at the bottom of the trench 56 (between fins 58) in the memory region 42a, as shown. Figures 12A to 12E As shown. An insulating layer 67 (e.g., ONO having oxide-nitride-oxide sublayers) is formed on these structures. Then, a thick polysilicon layer 68 is formed on the ONO layer 67 (which can withstand in-situ doping). Then, a hard mask layer 69 (e.g., amorphous carbon or nitride) is formed on the polysilicon layer 68. The resulting structure is shown in Figures 13A to 13E middle.

[0024] A masking step and one or more etching steps are performed to remove selected portions of the hard mask layer 69, polysilicon layer 68, and ONO layer 67 along the top of the fins 58 in memory region 42a, thereby leaving paired gate stack structures (stacks S1 and S2) (which include polysilicon blocks 68a and insulating blocks 69a) on the top surface of each fin 58 in memory region 42a, as shown. Figures 14A to 14E As shown.

[0025] A masking step is used to cover the portion of memory region 42a between a pair of stacks S1 / S2 with photoresist, followed by polysilicon etching that removes the exposed portion of the polysilicon layer 66 in memory region 42a adjacent to the outer side of the stacks S1 / S2. A separate masking and etching process is used to remove the hard mask layer 69, polysilicon layers 68 and 66, and ONO layer 67 from the logic region. The resulting structure is shown in… Figures 15A to 15E (After removing the photoresist)

[0026] High-temperature oxide (HTO) deposition and annealing are performed to form an oxide layer 70 along the sidewalls of gate stacks S1 and S2. Nitride deposition and etching are performed to form a nitride layer 71 along the oxide layer 70. Sacrificial oxide spacers 72 are formed along the nitride layer 71 by oxide deposition and etching. The resulting structure is shown in... Figures 16A to 16E In the middle, the exposed portion of the floating gate polysilicon layer 66 is removed using polysilicon etching (between stack S1 and stack S2 of memory region 42a), as shown. Figures 17A to 17EAs shown. A photoresist 74 is formed between each of the gate stack pairs S1 and S2 using a masking step. Then, word line Vt (WLVT) implantation is performed, followed by oxide etching that removes the oxide spacers 72 on the outer sides of the stack pairs S1 and S2 (and slightly recesses the exposed portions of the oxide 60), as shown. Figures 18A to 18E As shown.

[0027] After removing the photoresist, a masking step is used to cover the memory region 42a with photoresist, and nitride etching is used to remove the nitride layer 62 covering the logic region. After removing the photoresist, a masking step is used to cover the structure except for the HV region 42b with photoresist, which undergoes oxide etching and nitride etching to remove the nitride 48 and oxide 46 on the fin 58, and to recess the oxide 60 on either side of the fin 58. An oxide layer 80 is then formed on the exposed fins 58 in the HV region 42b (e.g., rapid thermal oxidation (RTO) + HTO and annealing) and the memory region 42a, as... Figures 19A to 19E As shown.

[0028] A masking step is used to cover the structure except for the region between each of the gate stack pairs S1 and S2 in memory region 42a with photoresist. Implantation is performed in the substrate between each of the gate stack pairs S1 and S2 (i.e., source line implantation for forming source lines SL, i.e., source region 36 as shown in cross section b; and source lines SL in the fins 58 extending in the horizontal / row direction as shown in cross sections a and c). Oxides 80 and 72 in the same region are then removed using oxide etching, after which a tunnel oxide layer 84 is formed on the exposed surface of the polysilicon layer 66 and on the inner sidewalls of the gate stacks S1 and S2 (e.g., by wet or partially wet deposition to thicken the oxide on the substrate, followed by HTO deposition to achieve the desired thickness on the polysilicon layer 66, and annealing), as shown. Figures 20A to 20E As shown (after removing the photoresist).

[0029] Memory regions 42a and HV regions 42b are covered with photoresist, and logic core regions 42c and logic I / O regions 42d undergo nitride etching to remove nitride 48 on the top of the fins, oxide etching to remove oxide 46 on the top of the fins, and recessed oxide 60, as... Figure 21As shown (after photoresist removal). Before photoresist removal, one or more implants are performed (preferably including anti-penetration implants that will prevent source-to-drain leakage in the logic devices formed in these regions). A masking step is used to cover the area between each of the gate stacks S1 and S2 in the memory region 42a and the logic region with photoresist. Then, oxide etching is used to remove the exposed oxide along the vertical outer surfaces of the stacks S1 / S2 and the exposed oxide on the top and side surfaces of the fins 58 on the outer side of the stacks, as shown. Figures 22A to 22D As shown.

[0030] Photoresist is then formed on memory regions 42a and HV regions 42b, followed by oxide 86 formed on exposed fins 58 in logic core regions 42c and logic I / O regions 42d (and other exposed portions of substrate 42). The oxide 86 on the fins 58 in logic core regions 42c and logic I / O regions 42d is preferably formed by CVD and is thinner than the oxide 80 on the fins 58 in HV region 42b. After removing the photoresist, a polysilicon layer 88 is formed over the structure, as shown below. Figures 23A to 23B As shown (for memory region structure). Chemical mechanical polishing (CMP) is used to remove the upper portion of the structure and planarize it, as... Figures 24A to 24B As shown (for memory region structure). A portion of the polysilicon layer 88 between adjacent gate stack pairs is removed using a masking step and polysilicon etching, leaving a polysilicon block 88a between each of the gate stacks S1 and S2, and polysilicon blocks 88b and 88c on the outer portions of each pair of gate stacks S1 and S2. Polysilicon etching also removes a portion of the polysilicon layer 88 in the logic region, leaving a polysilicon block 88d over fin 58. Nitride 90 is formed over polysilicon blocks 88a-88d. The resulting structure is shown in... Figures 25A to 25C (among them) Figure 25C An orthogonal view of the logic core region 42c is shown, for example, along the top of a fin that extends in the same direction as the fin in memory region 42a on which memory cells are formed.

[0031] One or more implantation steps are performed to form source and drain regions in a substrate 42 for memory cells and logic devices. Specifically, a memory cell drain region 38 is formed in a memory region 42a adjacent to polysilicon blocks 88b and 88c, and logic source and drain regions 92 / 94 are formed in an HV region 42b, a logic core region 42c, and a logic I / O region 42d adjacent to a remaining polysilicon block 88d. Preferably, these regions are enhanced prior to implantation by performing a masking step and oxide etching to expose the substrate surface above the locations where the memory drain and logic source / drain regions are to be formed. An epitaxial growth step is performed to grow silicon (Si) or silicon-carbon (SiC) on the substrate surface, thereby leaving raised silicon regions 96 on the substrate surface. Subsequent implantation at least partially forms the memory drain region 38 and the logic source / drain region 92 in these raised silicon regions 96, as shown below. Figures 26A to 26B As shown.

[0032] A nitride layer 98 is formed over the structure. A thick insulating layer (ILD oxide) 100 is formed over the nitride 98. Chemical mechanical polishing is then performed to remove the oxide 100 down to the top layer of nitride 98 above the polysilicon blocks 88a / 88b / 88c / 88d (i.e., using nitride 98 as an etch stop layer). Oxide etchback is used to recess the upper surface of the oxide 100 below the exposed upper surface of the nitride, as... Figures 27A to 27B As shown. Photoresist 102 is formed over the structure, followed by a masking step to remove portions of the photoresist 102 over the polysilicon blocks 88b / 88c / 88d. Nitride etching is then performed to expose the polysilicon blocks 88b / 88c / 88d, as... Figures 28A to 28B As shown. Then, polysilicon etching is used to remove the exposed polysilicon blocks 88b / 88c / 88d, leaving trench 104, as... Figures 29A to 29B As shown. Optionally, the oxide layer on the substrate fin exposed by removing the polysilicon block 88d in the logic region (at the bottom of trench 104) can be removed and / or replaced (using photoresist to protect the corresponding oxide in memory region 42a). A thin oxide layer 106 (interface layer (IL)) is formed at the bottom of trench 104. A high-k dielectric material (i.e., having a dielectric constant K greater than that of oxides such as HfO2, ZrO2, TiO2, Ta2O5, or other suitable materials) layer 108 is formed on the oxide layer 106 of trench 104. Then, a metal material block 110 is formed in trench 104 (e.g., by metal deposition and CMP). A nitride layer 112 is then formed on the structure. The resulting structure is shown in Figures 30A to 30B middle.

[0033] An insulating layer (e.g., ILD oxide) 114 is formed over the structure and planarized (e.g., by CMP). Contact holes are formed in the insulating material 114, extending to and exposing the drain region 38, the metal block 110, and the polysilicon blocks 88a and 68a. The contact holes are then filled with metal to form metal contacts 116 electrically connected to the drain region 38, the metal block 110, and the polysilicon blocks 88a and 68a, as shown. Figures 31A to 31B As shown.

[0034] The final structure on fin 58 in memory region 42a is Figure 32A As shown in the diagram. Memory cells are formed end-to-end along each fin 58. Each memory cell includes a channel region 118 of the substrate extending between the source region 36 and the drain region 38 (i.e., those portions of the substrate along the two side surfaces and the top surface of the fin 58 between the source region 36 and the drain region 38). Polysilicon block 66a is a floating gate 28 disposed above and insulated from a first portion of the channel region 118. Polysilicon block 68a is a control gate 30 extending above and insulated from the floating gate 28. Metal blocks 110 adjacent to the control gate 30 are each select gate 32, each of these select gates disposed above and insulated from a second portion of the channel region 118. Polysilicon block 88a is an erase gate 34 adjacent to and insulated from the pair of floating gates 28, and above and insulated from the source region 36. The erase gate 34 includes a pair of notches, each facing a corner of one of the floating gates. Fin 58 has two opposing side surfaces and a top surface. Floating gate 28 is wound around fin 58 such that it is adjacent to and insulated from the two opposing side surfaces and the top surface of fin 58. Select gate 32 is also wound around fin 58 such that it is adjacent to and insulated from the two opposing side surfaces and the top surface of fin 58. Therefore, one advantage of this configuration is that the surface area of ​​channel region 118 is larger in size relative to a memory cell of equal size above a planar channel region (i.e., the amount of surface overlap between the floating gate and select gate and the substrate is greater than the horizontal area of ​​the substrate occupied by these elements).

[0035] The final structures on and around the fins 58 in HV region 42b, logic core region 42c, and logic IO region 42d are similar in that the gate is wound around the respective fin 58 such that it is adjacent to and insulated from the two opposing side and top surfaces of the fin 58. Therefore, another advantage of this configuration is that the surface area of ​​the channel region of each logic device in the logic device is larger in size relative to a logic device of equal size above a planar channel region (i.e., the surface overlap between the logic gate and the substrate is greater than the horizontal area of ​​the substrate occupied by the element). For example, the final structure in logic core region 42c is shown in… Figure 32BIn the middle. Each logic device includes a channel region 120 of a substrate extending between a source region 92 and a drain region 94 (i.e., those portions of the substrate along the two side surfaces and the top surface of the fin 58 between the source region 92 and the drain region 94). A metal block 110 is a logic gate 122 disposed above the channel region 120 and insulated from the channel region (and controlling the conductivity of the channel region).

[0036] Two separate, non-limiting exemplary operating voltages for the memory cells in memory region 42a are provided in Tables 1 and 2 below.

[0037] Table 1

[0038] programming erase Read Drain 38 1μA-2μA 0V 0.5V-1.1V Select gate 32 0.5V-1.2V 0V 0.5V-2.5V Control gate 30 5.5V-13.5V 0V 0.5V-2.5V Erasure gate 34 3.5V-5.5V 8.5V-15.5V 0V Source 36 3.5V-5.5V 0V 0V

[0039] Table 2

[0040] programming erase Read Drain 38 1μA-2μA 0V 0.5V-1.1V Select gate 32 0.5V-1.2V 0V 0.5V-2.5V Control gate 30 5.5V-13.5V -10V to -15V 0.5V-2.5V Erasure gate 34 3.5V-5.5V 8.5V-12V 0V Source 36 3.5V-5.5V 0V 0V

[0041] In an alternative implementation, the above description relative to [the previous text] can be omitted. Figure 4A and Figure 4B The recess on the upper surface of the substrate makes the fins 58 initially formed in the memory region and logic region equal to each other, such as... Figure 33A and Figure 33B As shown. Then, before, during, or after the oxide 60 recess in memory region 42a, the top of the fin 58 in memory region 42a is removed by silicon etching, thereby effectively reducing the height of the fin 58 in memory region 42a by an amount R relative to the height of the fin 58 in the logic region, as shown. Figure 34A and Figure 34B As shown. Forming memory cells on fins 58 of reduced height in memory region 42a will similarly result in higher memory cell gates having upper surfaces equal to those of logic device gates.

[0042] The various features of this invention offer numerous advantages. Using high-k dielectrics and metals for the select gate 32 and logic gate 122 increases conductivity and performance without increasing cell and logic device size (and in fact, helps to scale down memory cell size), while using polysilicon for the erase gate 34 and floating gate 28 maintains control over critical tunneling performance between these two gates. Conformal gates wound around the top surface and two side surfaces of the fin 58 are formed in both the memory region 42a (i.e., the floating gate, erase gate, and select gate) and the logic region (i.e., the logic gate), allowing for further size reduction without compromising the coupling surface area. Furthermore, by recessing the fins in the memory region 42a, the tops of the finished memory cells and logic devices are approximately equal to each other (i.e., the tops of the select and erase gates of the memory cells are flush with the tops of the logic gates in the logic region), improving manufacturability even if the gate stack of the memory cells is higher than the logic gates of the logic devices. Furthermore, memory cells and up to three different types of logic devices are formed on a finned substrate structure on the same semiconductor substrate, with each memory cell formed on a single fin and each logic device formed on a single fin, allowing for reduced inter-fin spacing. Each source line in the source line SL extends along one of the horizontally extending fins 58 and through a row of memory cells, providing a continuous source line that extends across the isolation region between adjacent cells (in the row direction). This allows cells to be scaled down to a smaller size because this configuration does not require forming source line contacts for each pair of memory cells. Instead, the continuous source lines extending along the fins can be electrically connected to the strips via periodic strip contacts (e.g., every 32 or 64 columns). By having one contact every 32 or 64 columns instead of one contact per column, the size is that of a memory cell, thus significantly reducing the memory array size. The nitride 69a above the control gate 30 reduces alignment issues and helps protect the stacked gate structure (including the control gate 30 and the floating gate 28) during subsequent processing. Finally, when removing the virtual polysilicon blocks 88b / 88c / 88d and replacing them with high-K dielectric and metal (HKMG), the nitride 90 protecting these structures above the gate 34 and stack S1 / S2 is erased.

[0043] It should be understood that the invention is not limited to the embodiments described above and shown herein, but covers any and all variations within the scope of any claims supported therein. For example, references to the invention herein are not intended to limit the scope of any claims or claim terms, but only to one or more features that may be covered by one or more claims. The examples of materials, processes, and values ​​described above are merely illustrative and should not be construed as limiting any claims. Furthermore, not all method steps need to be performed in the exact order shown. Fins may extend continuously between memory regions and logic regions. For example, one or more fins in memory region 42a (on which memory cells are formed) may extend continuously out of memory region 42a and into a logic region (on which logic devices are formed), in which case the memory devices and logic devices may be formed on the same continuously formed fin. Finally, a single material layer may be formed as multiple such or similar material layers, or vice versa.

[0044] It should be noted that, as used herein, the terms “above” and “on” inclusively include “directly on” (without intermediate material, elements, or space between) and “indirectly on” (with intermediate material, elements, or space between). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, elements, or space between) and “indirectly adjacent” (with intermediate material, elements, or space between), “mounted to” includes “directly mounted to” (without intermediate material, elements, or space between) and “indirectly mounted to” (with intermediate material, elements, or space between), and “electrically coupled to” includes “directly electrically coupled to” (without intermediate material or elements electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or elements electrically connecting the elements together). For example, forming an element “above a substrate” can include forming the element directly on the substrate without intermediate material / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. A memory device comprising: a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces opposite one another and terminating at a top surface; a memory cell formed on a first fin of the plurality of fins, the memory cell comprising: first source and drain regions spaced apart in the first fin with a first channel region of the first fin extending between the first source and drain regions along the top surface and the opposite side surfaces of the first fin, a floating gate of polysilicon material extending along a first portion of the first channel region, wherein the floating gate wraps around the first fin such that the floating gate is adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, a select gate of metal material extending along a second portion of the first channel region, wherein the select gate wraps around the first fin such that the select gate is adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, a control gate of polysilicon material extending along and insulated from the floating gate, and an erase gate of polysilicon material extending along and insulated from the first source region; a logic device formed on a second fin of the plurality of fins, the logic device comprising: second source and drain regions spaced apart in the second fin with a second channel region of the second fin extending between the second source and drain regions along the top surface and the opposite side surfaces of the second fin, and a first logic gate of metal material extending along the second channel region, wherein the first logic gate wraps around the second fin such that the first logic gate is adjacent to and insulated from the first and second side surfaces and the top surface of the second fin.

2. The memory device of claim 1, wherein a high-K dielectric material is disposed between the select gate and the second portion of the first channel region, and wherein a high-K dielectric material is disposed between the first logic gate and the second channel region.

3. The memory device of claim 1, wherein the top surface of the first fin is recessed relative to the top surface of the second fin.

4. The memory device of claim 1, wherein the top surface of the first fin includes a first raised portion of the substrate relative to a portion of the top surface of the first fin along which the first channel region extends, and wherein the first drain region is at least partially formed in the first raised portion.

5. The memory device of claim 4, wherein the top surface of the second fin includes a second raised portion and a third raised portion of the substrate relative to a portion of the top surface of the second fin along which the second channel region extends, and wherein the second source region is formed at least partially in the second raised portion and the second drain region is formed at least partially in the third raised portion.

6. The memory device of claim 1, further comprising: a third fin of the plurality of fins having a length extending in a first direction, wherein the first fin has a length extending in a second direction perpendicular to the first direction, and wherein the first source region is formed in the first fin at an intersection of the first fin and the third fin.

7. The memory device of claim 6, wherein the erase gate extends along and is insulated from the first side surface and the second side surface and the top surface of the first fin and extends along and is insulated from the first side surface and the second side surface and the top surface of the third fin.

8. The memory device of claim 1, wherein the erase gate extends along and is insulated from an upper edge of the floating gate, and wherein the erase gate includes a notch facing the upper edge of the floating gate.

9. The memory device of claim 1, further comprising: a second logic device formed on a third fin of the plurality of fins, the second logic device comprising: a third source region and a third drain region spaced apart in the third fin, wherein a third channel region of the third fin extends along the top surface and the opposing side surfaces of the third fin between the third source region and the third drain region, and a second logic gate extending along the third channel region, wherein the second logic gate wraps around the third fin to have the second logic gate adjacent to and insulated from the first side surface and the second side surface and the top surface of the third fin.

10. The memory device of claim 9, wherein: the first logic gate is insulated from the second fin by a first insulating material; the second logic gate is insulated from the third fin by a second insulating material; a thickness of the second insulating material is greater than a thickness of the first insulating material.

11. A method of forming a memory device, comprising: forming a plurality of upwardly extending fins in an upper surface of a semiconductor substrate, wherein each of the fins includes first and second side surfaces opposite each other and terminating at a top surface; forming a memory cell on a first fin of the plurality of fins by: forming a floating gate along the first and second side surfaces and the top surface of the first fin, the floating gate including a first recessed portion facing the first side surface and a second recessed portion facing the second side surface of the first fin, and forming an erase gate along and insulated from the first and second side surfaces and the top surface of the first fin, the erase gate including a first notch facing the first recessed portion and a second notch facing the second recessed portion of the floating gate. forming a first source region and a first drain region spaced apart in the first fin with a first channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the first source region and the first drain region, forming a poly material floating gate extending along a first portion of the first channel region with the floating gate wrapped around the first fin to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, forming a metal material select gate extending along a second portion of the first channel region with the select gate wrapped around the first fin to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin, forming a poly material control gate extending along and insulated from the floating gate, and forming a poly erase gate extending along and insulated from the first source region; forming a logic device on a second fin of the plurality of fins by: forming a second source region and a second drain region spaced apart in the second fin with a second channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the second source region and the second drain region, and forming a metal material first logic gate extending along the second channel region with the first logic gate wrapped around the second fin to be adjacent to and insulated from the first and second side surfaces and the top surface of the second fin.

12. The method of claim 11, wherein the forming the select gate, the erase gate, and the first logic gate comprises: forming a poly layer over the substrate; removing portions of the poly layer such that a first piece of the poly layer extends along and is insulated from the first source region, a second piece of the poly layer extends along and is insulated from the second portion of the first channel region, and a third piece of the poly layer extends along and is insulated from the second channel region; removing the second piece of the poly layer and replacing the second piece with a first metal material piece; and removing the third piece of the poly layer and replacing the third piece with a second metal material piece; wherein the first piece of the poly layer is the erase gate, the first metal material piece is the select gate, and the second metal material piece is the first logic gate.

13. The method of claim 12, further comprising: forming an insulating layer over the erase gate and the control gate prior to the removing of the second and third pieces of the poly layer.

14. The method of claim 11, wherein the forming of the select gate includes forming a high-K dielectric material disposed between the select gate and the second portion of the first channel region, and wherein the forming of the first logic gate includes forming a high-K dielectric material disposed between the first logic gate and the second channel region.

15. The method of claim 11, wherein the top surface of the first fin is recessed relative to the top surface of the second fin.

16. The method of claim 11, further comprising: forming a first raised portion in the top surface of the first fin relative to a portion of the first channel region in the top surface of the first fin along which the first channel region extends, wherein the first drain region is at least partially formed in the first raised portion.

17. The method of claim 16, further comprising: forming a second raised portion in the top surface of the second fin relative to a portion of the second channel region in the top surface of the second fin along which the second channel region extends, wherein the second source region is at least partially formed in the second raised portion; forming a third raised portion in the top surface of the second fin relative to the portion of the second channel region in the top surface of the second fin along which the second channel region extends, wherein the second drain region is at least partially formed in the third raised portion.

18. The method of claim 11, further comprising: forming a third fin of the plurality of fins having a length extending in a first direction, wherein the first fin has a length extending in a second direction perpendicular to the first direction, and wherein the first source region is formed in the first fin at an intersection of the first fin and the third fin.

19. The method of claim 18, wherein the erase gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, and extends along and is insulated from the first and second side surfaces and the top surface of the third fin.

20. The method of claim 11, wherein the erase gate extends along and is insulated from an upper edge of the floating gate, and wherein the erase gate includes a notch facing the upper edge of the floating gate.

21. The method of claim 11, further comprising: forming a second logic device on a third fin of the plurality of fins by: forming a third source region and a third drain region spaced apart in the third fin, wherein a third channel region of the third fin extends between the third source region and the third drain region along the top surface and the opposing side surfaces of the third fin, and forming a second logic device on a third fin of the plurality of fins by: forming a third source region and a third drain region spaced apart in the third fin, wherein a third channel region of the third fin extends between the third source region and the third drain region along the top surface and the opposing side surfaces of the third fin, and a second logic gate is formed, the second logic gate extending along the third channel region, wherein the second logic gate wraps around the third fin such that the second logic gate is adjacent to and insulated from the first and second side surfaces and the top surface of the third fin.

22. The method of claim 21, wherein: the first logic gate is insulated from the second fin by a first insulating material; the second logic gate is insulated from the third fin by a second insulating material; a thickness of the second insulating material is greater than a thickness of the first insulating material.

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