Three-dimensional planar NAND memory device with curved memory elements and method of manufacturing the same

Abstract

The present invention discloses a three-dimensional memory device, which includes alternating stacks of conductive strips and spacer strips, which are located above a substrate and are laterally spaced apart from each other by memory stack assemblies. These spacer strips may include air gap strips or insulating strips. Each of these memory stack assemblies includes two two-dimensional arrays of lateral protrusion areas. Each of these lateral protrusion areas includes corresponding curved charge storage elements. These charge storage elements may be discrete elements located in the corresponding lateral protrusion areas, or may be part of a charge storage material layer extending vertically above a plurality of conductive strips. Each of these memory stack assemblies may include two rows of vertical semiconductor channels laterally covering the corresponding vertical stacks of charge storage elements.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority from U.S. non-provisional patent application serial numbers 16 / 278,426 and 16 / 278,488, filed on February 18, 2019, and the entire contents of these applications are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to a three-dimensional planar NAND memory device including a curved memory element and a method of manufacturing the same. Background Art

[0004] The configuration of the three-dimensional NAND memory device uses a flat memory cell in which the tunnel dielectric has a flat vertical surface. Hang-Ting Lue et al. describe such a flat memory device in an article entitled "A 128Gb (MLC) / 192Gb (TLC) Single-gate Vertical Channel (SGVC) Architecture 3D NAND using only 16 Layers with Robust Read Disturb, Long-Retention and Excellent Scaling Capability", IEDM Proceedings (2017), page 461. Summary of the invention

[0005] According to one embodiment of the present disclosure, a three-dimensional memory device is provided, which includes: alternating stacks of conductive strips and air gap strips, which are located above a substrate and are laterally spaced apart from each other by memory stack assemblies, wherein the memory stack assemblies extend laterally along a first horizontal direction and are spaced apart from each other along a second horizontal direction, wherein: each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion areas; each lateral protrusion area protrudes laterally outward from a corresponding vertical plane, which corresponding vertical plane includes an interface between an air gap strip within a corresponding one of the memory stack assemblies and a corresponding one of the alternating stacks; each of these lateral protrusion areas includes a corresponding curved charge storage element; each of these memory stack assemblies includes two rows of vertical semiconductor channels; and each vertical semiconductor channel within the two rows of vertical semiconductor channels laterally covers a corresponding vertical stack of charge storage elements.

[0006] According to another embodiment of the present disclosure, a method for forming a three-dimensional memory device is provided; forming alternating stacks of a first sacrificial material strip and a second sacrificial material strip above a substrate, wherein the alternating stacks are laterally spaced apart from each other by line grooves extending laterally in a first horizontal direction; modifying the line grooves to provide a two-dimensional array of lateral recesses on each sidewall of the line grooves, wherein each two-dimensional array of lateral recesses is laterally bounded by a corresponding two-dimensional array of lateral recessed surfaces of the second sacrificial material strip; forming a memory stack assembly in each volume, each volume including a combination of the volume of the line grooves and the volumes of two adjacent two-dimensional arrays of lateral recesses, wherein each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion areas, and each of the lateral protrusion areas includes a corresponding charge storage element; replacing the remaining portion of the second sacrificial material strip with a conductive strip; and forming an air gap strip by removing the first sacrificial material strip.

[0007] According to another embodiment of the present disclosure, a three-dimensional memory device is provided, which includes: alternating stacks of conductive strips and insulating strips, which are located above a substrate and are laterally spaced apart from each other by memory stack assemblies, wherein the memory stack assemblies extend laterally along a first horizontal direction and are spaced apart from each other along a second horizontal direction, wherein: each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion areas; the lateral protrusion areas protrude laterally outward from corresponding vertical planes including interfaces between the memory stack assemblies and a subset of the air gap strips; and each of the lateral protrusion areas includes a corresponding charge storage element, which has a pair of concave inner sidewall segments and a pair of convex outer sidewall segments, the pair of concave inner sidewall segments having corresponding horizontal concave profiles in a horizontal cross-sectional view, and the pair of convex outer sidewall segments having corresponding horizontal convex profiles in a horizontal cross-sectional view.

[0008] According to yet another embodiment of the present disclosure, a method of forming a three-dimensional memory device is provided, the method comprising: forming alternating stacks of insulating strips and sacrificial material strips above a substrate, wherein the alternating stacks are laterally spaced apart from each other by line trenches extending laterally in a first horizontal direction; modifying the line trenches to provide a two-dimensional array of lateral recesses on each sidewall of the line trenches, wherein each two-dimensional array of lateral recesses is laterally bounded by a corresponding two-dimensional array of laterally recessed surfaces of the sacrificial material strips; forming a memory stack assembly in each volume, each volume comprising a volume of the line trenches and two adjacent two-dimensional arrays of lateral recesses; A combination of volumes of columns, wherein each of these memory stack assemblies includes two rows of material stack strips, which extend vertically and laterally over the side walls of a corresponding one of the alternating stacks, and each row of material stack strips includes a corresponding plurality of material stack strips laterally spaced apart along a first horizontal direction, and each of the material stack strips includes a corresponding charge storage material layer, which corresponding charge storage material layer includes a charge storage element within each corresponding vertical stack of lateral recesses selected from a two-dimensional array of lateral recesses; and replacing the sacrificial material layer with a conductive strip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic vertical cross-sectional view of a first exemplary structure after forming a vertically alternating sequence of first and second sacrificial material layers and an insulating capping layer according to the first embodiment of the present disclosure.

[0010] Figure 2 is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped terrace and a backward stepped dielectric material portion according to the first embodiment of the present disclosure.

[0011] Figure 3A is a schematic vertical cross-sectional view of a first exemplary structure after forming a linear trench according to the first embodiment of the present disclosure.

[0012] Figure 3B yes Figure 3A A top view of the first exemplary structure. The vertical plane A-A' is Figure 3A The plane of the section.

[0013] Figure 4A yes Figure 3A and Figure 3B A vertical cross-sectional view of a portion of a wire trench in a first exemplary structure.

[0014] Figure 4B is along Figure 4A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Figure 4AA plane of a vertical section.

[0015] Figure 4C is along Figure 4A The horizontal cross-sectional view of the structure taken through plane C-C'. The vertical plane C-C' corresponds to Figure 4A A plane of a vertical section.

[0016] Figure 5A is a vertical cross-sectional view of a portion of a linear trench after forming a silicon oxide layer, a diffusion barrier layer, and a first mask material track according to the first embodiment of the present disclosure.

[0017] Figure 5B is along Figure 5A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Figure 5A A plane of a vertical section.

[0018] Figure 5C is along Figure 5A The horizontal cross-sectional view of the structure taken through plane C-C'. The vertical plane C-C' corresponds to Figure 5A A plane of a vertical section.

[0019] Fig. 6A is a vertical cross-sectional view of a portion of a linear trench after forming a two-dimensional array of pillars of mask material according to a first embodiment of the present disclosure.

[0020] Figure 6B is along Fig. 6A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig. 6A A plane of a vertical section.

[0021] Figure 6C is along Fig. 6A The horizontal cross-sectional view of the structure taken along plane C-C'. The vertical plane A-A' corresponds to Fig. 6A A plane of a vertical section.

[0022] Fig. 7A is a vertical cross-sectional view of a portion of a line trench after forming a diffusion barrier strip according to the first embodiment of the present disclosure.

[0023] Figure 7B is along Fig. 7A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig. 7A A plane of a vertical section.

[0024] Figure 7C is along Fig. 7A The horizontal cross-sectional view of the structure taken along plane C-C'. The vertical plane A-A' corresponds to Fig. 7AA plane of a vertical section.

[0025] Fig. 8A is a vertical cross-sectional view of a portion of a linear trench after removing the two-dimensional array of pillars of mask material and forming a semiconductor oxide layer having a two-dimensional array of thickened portions through an oxidation process according to the first embodiment of the present disclosure.

[0026] Figure 8B is along Fig. 8A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig. 8A A plane of a vertical section.

[0027] Figure 8C is along Fig. 8A The horizontal cross-sectional view of the structure taken along plane C-C'. The vertical plane A-A' corresponds to Fig. 8A A plane of a vertical section.

[0028] Fig. 9A is a vertical cross-sectional view of a portion of a line trench after removal of the diffusion barrier strip and the semiconductor oxide layer according to the first embodiment of the present disclosure.

[0029] Fig. 9B is along Fig. 9A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig. 9A A plane of a vertical section.

[0030] Fig. 9C is along Fig. 9A The horizontal cross-sectional view of the structure taken along plane C-C'. The vertical plane A-A' corresponds to Fig. 9A A plane of a vertical section.

[0031] Fig. 10A is a vertical cross-sectional view of a portion of a linear trench after forming a blocking dielectric layer and a charge storage material layer according to the first embodiment of the present disclosure.

[0032] Fig. 10B is along Fig. 10A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig. 10A A plane of a vertical section.

[0033] Fig. 10C is along Fig. 10A The horizontal cross-sectional view of the structure taken along plane C-C'. The vertical plane A-A' corresponds to Fig. 10A A plane of a vertical section.

[0034] Fig.11Ais a vertical cross-sectional view of a portion of a line trench after forming discrete charge storage elements by anisotropically etching a layer of charge storage material according to a first embodiment of the present disclosure.

[0035] Fig. 11B is along Fig.11A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.11A A plane of a vertical section.

[0036] Fig. 11C is along Fig.11A The horizontal cross-sectional view of the structure taken along plane C-C'. The vertical plane A-A' corresponds to Fig.11A A plane of a vertical section.

[0037] Fig. 12A is a vertical cross-sectional view of a portion of a line trench after forming a tunneling dielectric layer, a semiconductor channel material layer, and a second mask material track according to the first embodiment of the present disclosure.

[0038] Fig. 12B is along Fig. 12A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig. 12A A plane of a vertical section.

[0039] Fig. 12C is along Fig. 12A The horizontal cross-sectional view of the structure taken along plane C-C'. The vertical plane A-A' corresponds to Fig. 12A A plane of a vertical section.

[0040] Fig.13A is a vertical cross-sectional view of a portion of a linear trench after forming a two-dimensional array of pillars of mask material according to a first embodiment of the present disclosure.

[0041] Fig. 13B is along Fig.13A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.13A A plane of a vertical section.

[0042] Fig. 13C is along Fig.13A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.13A A plane of a vertical section.

[0043] Fig.14A is a vertical cross-sectional view of a portion of a line trench after dividing a semiconductor channel material layer into vertical semiconductor channels according to the first embodiment of the present disclosure.

[0044] Fig. 14B is along Fig.14A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.14A A plane of a vertical section.

[0045] Fig. 14C is along Fig.14A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.14A A plane of a vertical section.

[0046] Fig.15A is a vertical cross-sectional view of a portion of a linear trench after removal of the two-dimensional array of pillars of masking material according to the first embodiment of the present disclosure.

[0047] Fig. 15B is along Fig.15A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.15A A plane of a vertical section.

[0048] Fig. 15C is along Fig.15A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.15A A plane of a vertical section.

[0049] Fig.16A is a vertical cross-sectional view of a portion of a wire trench after forming a dielectric core according to the first embodiment of the present disclosure.

[0050] Fig. 16B is along Fig.16A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.16A A plane of a vertical section.

[0051] Fig. 16C is along Fig.16A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.16A A plane of a vertical section.

[0052] Fig.17A yes FIG. 16A to FIG. 16C Vertical cross-sectional view of the first exemplary structure after the processing steps of .

[0053] Fig. 17B yes Fig.13A A top view of the first exemplary structure. The vertical plane A-A' is Fig.13A The plane of the section.

[0054] Fig.18Ais a vertical cross-sectional view of the first exemplary structure after forming a drain region according to the first embodiment of the present disclosure.

[0055] Fig.18B yes Fig.18A A top view of the first exemplary structure. The vertical plane A-A' is Fig.18A The plane of the section.

[0056] Fig.19A is a vertical cross-sectional view of the first exemplary structure after forming a backside via cavity according to the first embodiment of the present disclosure.

[0057] Fig.19B yes Fig.19A A top view of the first exemplary structure. The vertical plane A-A' is Fig.19A The plane of the section.

[0058] Fig. 20 is a schematic vertical cross-sectional view of a first exemplary structure after forming a backside recess according to the first embodiment of the present disclosure.

[0059] Fig.21 is a schematic vertical cross-sectional view of a first exemplary structure after forming a conductive strip in a backside recess according to the first embodiment of the present disclosure.

[0060] Fig.22A is Fig.21 Vertical cross-section of a portion of a wire trench after the processing steps.

[0061] Fig. 22B is along Fig.22A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.22A A plane of a vertical section.

[0062] Fig. 22C is along Fig.22A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.22A A plane of a vertical section.

[0063] Fig.23 is a schematic vertical cross-sectional view of the first exemplary structure after removing the first sacrificial material strips and forming the air gap strips according to the first embodiment of the present disclosure.

[0064] Fig.24A is Fig.23 Vertical cross-section of a portion of a wire trench after the processing steps.

[0065] Fig. 24B is along Fig.24AThe horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.24A A plane of a vertical section.

[0066] Fig.24C is along Fig.24A The horizontal cross-sectional view of the structure is taken along the plane BB'. The vertical plane AA' corresponds to Fig.24A A plane of a vertical section.

[0067] Fig.25A is a schematic vertical cross-sectional view of a first exemplary structure after forming air gap pillars in a backside via cavity according to the first embodiment of the present disclosure.

[0068] Fig.25B yes Fig.25A A top view of the first exemplary structure. The vertical plane A-A' is Fig.25A The plane of the section.

[0069] Fig.26 is a schematic vertical cross-sectional view of a second exemplary structure after forming a vertically alternating sequence of insulating layers and sacrificial material layers and forming an insulating capping layer according to the second embodiment of the present disclosure.

[0070] Fig. 27 is a schematic vertical cross-sectional view of a second exemplary structure after forming a stepped terrace and a backward stepped dielectric material portion according to a second embodiment of the present disclosure.

[0071] Fig.28A is a schematic vertical cross-sectional view of a second exemplary structure after forming a linear trench according to the second embodiment of the present disclosure.

[0072] Fig.28B yes Fig.28A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.28A The plane of the section.

[0073] Fig.29A yes Fig.28A and Fig.28B A first vertical cross-sectional view of a region of a second exemplary structure.

[0074] Fig.29B yes Fig.29A A second vertical cross-sectional view of a region of a second exemplary structure.

[0075] Fig.29C is along Fig.29A and Fig.29B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.29A The horizontal plane B-B' corresponds to Fig.29B A plane of a vertical section.

[0076] Fig. 30A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a first mask track according to the second embodiment of the present disclosure.

[0077] Fig. 30B yes Fig. 30A A second vertical cross-sectional view of a region of a second exemplary structure.

[0078] Fig. 30C is along Fig. 30A and Fig. 30B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig. 30A The horizontal plane B-B' corresponds to Fig. 30B A plane of a vertical section.

[0079] Fig.31A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a two-dimensional array of pillars of mask material according to the second embodiment of the present disclosure.

[0080] Fig.31B yes Fig.31A A second vertical cross-sectional view of a region of a second exemplary structure.

[0081] Fig.31C is along Fig.31A and Fig.31B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.31A The horizontal plane B-B' corresponds to Fig.31B A plane of a vertical section.

[0082] Fig.32A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a two-dimensional array of lateral recesses on each sidewall of a wire trench according to a second embodiment of the present disclosure.

[0083] Fig.32B yes Fig.32A A second vertical cross-sectional view of a region of a second exemplary structure.

[0084] Fig.32C is along Fig.32A and Fig.32B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.32A The horizontal plane B-B' corresponds to Fig.32B A plane of a vertical section.

[0085] Fig.33Ais a first vertical cross-sectional view of a region of a second exemplary structure after removal of the two-dimensional array of pillars of masking material according to the second embodiment of the present disclosure.

[0086] Fig.33B yes Fig.33A A second vertical cross-sectional view of a region of a second exemplary structure.

[0087] Fig.33C is along Fig.33A and Fig.33B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.33A The horizontal plane B-B' corresponds to Fig.33B A plane of a vertical section.

[0088] Fig.34A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a sequential layer stack of a blocking dielectric layer, a charge storage material layer, and a tunneling dielectric layer according to the second embodiment of the present disclosure.

[0089] Fig.34B yes Fig.34A A second vertical cross-sectional view of a region of a second exemplary structure.

[0090] Fig.34C is along Fig.34A and Fig.34B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.34A The horizontal plane B-B' corresponds to Fig.34B A plane of a vertical section.

[0091] Fig.35A is a first vertical cross-sectional view of a region of a second exemplary structure after anisotropically etching a stack of successive layers according to a second embodiment of the present disclosure.

[0092] Fig.35B yes Fig.35A A second vertical cross-sectional view of a region of a second exemplary structure.

[0093] Fig.35C is along Fig.35A and Fig.35B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.35A The horizontal plane B-B' corresponds to Fig.35B A plane of a vertical section.

[0094] Fig.36A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a semiconductor channel material layer according to the second embodiment of the present disclosure.

[0095] Fig.36B yes Fig.36A A second vertical cross-sectional view of a region of a second exemplary structure.

[0096] Fig.36C is along Fig.36A and Fig.36B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.36A The horizontal plane B-B' corresponds to Fig.36B A plane of a vertical section.

[0097] Fig.37A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a mask material layer according to the second embodiment of the present disclosure.

[0098] Fig.37B yes Fig.37A A second vertical cross-sectional view of a region of a second exemplary structure.

[0099] Fig.37C is along Fig.37A and Fig.37B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.37A The horizontal plane B-B' corresponds to Fig.37B A plane of a vertical section.

[0100] Fig.38A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a second mask track according to a second embodiment of the present disclosure.

[0101] Fig.38B yes Fig.38A A second vertical cross-sectional view of a region of a second exemplary structure.

[0102] Fig.38C is along Fig.38A and Fig.38B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.38A The horizontal plane B-B' corresponds to Fig.38B A plane of a vertical section.

[0103] Fig.39A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a two-dimensional array of pillars of mask material according to the second embodiment of the present disclosure.

[0104] Fig.39B yes Fig.39A A second vertical cross-sectional view of a region of a second exemplary structure.

[0105] Fig.39C is along Fig.39A and Fig.39B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.39A The horizontal plane B-B' corresponds to Fig.39B A plane of a vertical section.

[0106] Fig.40A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a material stack strip including a blocking dielectric layer, a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel according to the second embodiment of the present disclosure.

[0107] Fig.40B yes Fig.40A A second vertical cross-sectional view of a region of a second exemplary structure.

[0108] Fig.40C is along Fig.40A and Fig.40B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.40A The horizontal plane B-B' corresponds to Fig.40B A plane of a vertical section.

[0109] Fig.41A is a first vertical cross-sectional view of a region of a second exemplary structure after removal of the two-dimensional array of pillars of masking material according to the second embodiment of the present disclosure.

[0110] Fig.41B yes Fig.41A A second vertical cross-sectional view of a region of a second exemplary structure.

[0111] Fig.41C is along Fig.41A and Fig.41B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.41A The horizontal plane B-B' corresponds to Fig.41B A plane of a vertical section.

[0112] Fig.42A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a dielectric core according to a second embodiment of the present disclosure.

[0113] Fig.42B yes Fig.42A A second vertical cross-sectional view of a region of a second exemplary structure.

[0114] Fig.42C is along Fig.42A and Fig.42BThe horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.42A The horizontal plane B-B' corresponds to Fig.42B A plane of a vertical section.

[0115] Fig.43A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a drain region according to a second embodiment of the present disclosure.

[0116] Fig.43B yes Fig.43A A second vertical cross-sectional view of a region of a second exemplary structure.

[0117] Fig.43C is along Fig.43A and Fig.43B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.43A The horizontal plane B-B' corresponds to Fig.43B A plane of a vertical section.

[0118] Fig.43D yes FIG. 43A to FIG. 43C A top view of a region of a second exemplary structure.

[0119] Fig.44A yes FIG. 43A to FIG. 43D Vertical cross-sectional view of a second exemplary structure after the processing steps of .

[0120] Fig.44B yes Fig.44A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.44A The plane of the section.

[0121] Fig.45A is a vertical cross-sectional view of a second exemplary structure after forming a backside via cavity according to the second embodiment of the present disclosure.

[0122] Fig.45B yes Fig.45A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.45A The plane of the section.

[0123] Fig.46 is a schematic vertical cross-sectional view of a second exemplary structure after forming a backside recess according to a second embodiment of the present disclosure.

[0124] Fig.47 is a schematic vertical cross-sectional view of a second exemplary structure after forming a conductive strip in a backside recess according to a second embodiment of the present disclosure.

[0125] Fig.48Ayes Fig.47 A first vertical cross-sectional view of a region of a second exemplary structure.

[0126] Fig.48B yes Fig.48A A second vertical cross-sectional view of a region of a second exemplary structure.

[0127] Fig.48C is along Fig.48A and Fig.48B The horizontal section of plane C-C'. The vertical plane A-A' corresponds to Fig.48A The horizontal plane B-B' corresponds to Fig.48B A plane of a vertical section.

[0128] Fig.49A is a schematic vertical cross-sectional view of a second exemplary structure after forming a dielectric post in a backside via cavity according to a second embodiment of the present disclosure.

[0129] Fig.49B yes Fig.49A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.49A The plane of the section. DETAILED DESCRIPTION

[0130] As discussed above, the present disclosure relates to three-dimensional planar NAND memory devices including high-mobility vertical semiconductor channels and methods of manufacturing the same, various embodiments of which are described in detail herein. Specifically, in various embodiments disclosed herein, curved memory elements in planar memory devices may be desirable because geometric effects reduce the required operating voltage of planar memory devices by enhancing electric field strength.

[0131] The accompanying drawings are not drawn to scale. Multiple instances of elements may be repeated in the case of a single instance of an element, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first", "second" and "third" are only used to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The same reference numerals represent the same elements or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition. As used herein, a first element "on" a second element may be located on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element.

[0132] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0133] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolith" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels before bonding, but since the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. Various three-dimensional memory devices disclosed herein include monolithic three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein.

[0134] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded therein, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0135] See also Figure 1 , shows a first exemplary structure according to a first embodiment of the present disclosure, which can be used, for example, to manufacture a device structure including a vertical NAND memory device. The first exemplary structure includes a substrate (9, 10), which can be a semiconductor substrate. The substrate may include a substrate semiconductor layer 9 and an optional semiconductor material layer 10. The substrate semiconductor layer 9 may be a semiconductor wafer or a semiconductor material layer, and may include at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor material layer 10 may have a first conductivity type of doping, and the substrate semiconductor layer 9 may have a second conductivity type of doping opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa.

[0136] As used herein, "semiconductor material" refers to a semiconductor material having a -6 S / cm to 1.0×10 5 S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm, and can produce materials with electrical conductivity in the range of 1.0 S / cm to 1.0×105 S / cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / cm. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -6 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a conductivity greater than 1.0×10 5 S / cm). A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -6 S / cm to 1.0×10 5 S / cm) in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0137] A vertically alternating sequence of a first sacrificial material layer 132L and a second sacrificial material layer 142L may be formed above the substrate (9, 10). As used herein, a "vertical alternating sequence" refers to an alternating sequence of multiple instances of a first element and multiple instances of a second element that are vertically alternating, such that an instance of the second element overlies each instance of the first element and / or potentially underlies each instance of the first element, and an instance of the first element overlies each instance of the second element and / or potentially underlies each instance of the first element. The vertically alternating sequence may include a stack of alternating multiple first sacrificial material layers 132L and second sacrificial material layers 142L. As used herein, a "material layer" refers to a layer that includes a material throughout its entirety. As used herein, an alternating multiple first and second elements refers to a structure in which instances of the first element and instances of the second element are alternating. Each instance of a first element that is not an end element of an alternating multiple element is adjacent to two instances of the second element on both sides, and each instance of a second element that is not an end element of an alternating multiple element is adjacent to two instances of the first element on both ends. Therefore, the vertical alternating sequence of the first element and the second element can be an alternating plurality of first elements and second elements, wherein the alternation of the first element and the second element occurs in the vertical direction. The first element can have the same thickness therein, or can have different thicknesses. The second element can have the same thickness therein, or can have different thicknesses. The alternating plurality of first material layers and second material layers can start with an instance of the first material layer or an instance of the second material layer, and can end with an instance of the first material layer or an instance of the second material layer. In one embodiment, the instance of the first element and the instance of the second element can form a unit that is periodically repeated in the alternating plurality of elements.

[0138] The alternating plurality of first sacrificial material layers 132L and second sacrificial material layers 142L may constitute a prototype stack or an in-process stack including alternating layers of first sacrificial material layers 132L and second sacrificial material layers 142L. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in shape or composition of at least one component thereof.

[0139] The second material of the second sacrificial material layer 142L is a sacrificial material that is selectively removable with respect to the first material of the first sacrificial material layer 132L. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0140] In one embodiment, the first sacrificial material layer 132L may include a first sacrificial semiconductor material, and the second sacrificial material layer 142L may include a second sacrificial semiconductor material that is selectively removable with respect to the first sacrificial semiconductor material. In one embodiment, the first sacrificial semiconductor material may include and / or consist essentially of single crystal silicon, polycrystalline silicon, or amorphous silicon, and the second sacrificial semiconductor material may include and / or consist essentially of single crystal silicon, polycrystalline silicon, or amorphous silicon. The first sacrificial semiconductor material may include undoped silicon, i.e., silicon deposited without any intentional doping. In one embodiment, the first sacrificial semiconductor material may include undoped amorphous silicon. In one embodiment, the atomic concentration of germanium in the first sacrificial semiconductor material may be zero, and the atomic concentration of germanium in the second sacrificial semiconductor material may be in the range of 10% to 50% (e.g., 20% to 40%), although smaller and larger atomic concentrations of germanium may also be used.

[0141] The first sacrificial material layer 132L and the second sacrificial material layer 142L may be deposited by a chemical vapor deposition process. The thickness of the first sacrificial material layer 132L and the second sacrificial material layer 142L may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each first sacrificial material layer 132L and each second sacrificial material layer 142L. The number of repetitions of the paired first sacrificial material layer 132L and the second sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 142L may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each first sacrificial material layer 132L and each second sacrificial material layer 142L in the vertically alternating sequence (132L, 142L) may have a uniform thickness that is substantially constant within each respective second sacrificial material layer 142L.

[0142] See also Figure 2, the vertically alternating sequence of the first sacrificial material layer 132L and the second sacrificial material layer 142L may be patterned to form a stepped surface that continuously extends from the bottommost layer of the vertically alternating sequence (132L, 142L) to the topmost layer of the alternating sequence (132L, 142L) in the contact region 300. A stepped cavity may be formed in the contact region 300 between the memory array region 100 and a peripheral device region (not shown), the peripheral device region including at least one semiconductor device for a peripheral circuit. The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the cavity depth by one or more steps, the second type of etching process laterally extending the area to be vertically etched in a subsequent etching process of the first type. As used herein, a "level" of a structure comprising an alternating plurality is defined as the relative position of a pair of first and second material layers within the structure.

[0143] By forming a stepped cavity, a stepped surface is formed at the peripheral portion of the vertically alternating sequence (132L, 142L). As used herein, "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface, and adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. "Stepped cavity" refers to a cavity having a stepped surface.

[0144] The terrace region is formed by patterning the vertically alternating sequence (132L, 142L). Each second sacrificial material layer 142L except the topmost second sacrificial material layer 142L in the vertically alternating sequence (132L, 142L) extends laterally further than any overlying second sacrificial material layer 142L in the vertically alternating sequence (132L, 142L). The terrace region includes a stepped surface of the vertically alternating sequence (132L, 142L) that extends continuously from the bottommost layer in the vertically alternating sequence (132L, 142L) to the topmost layer in the vertically alternating sequence (132L, 142L).

[0145] By depositing a dielectric material therein, a backward stepped dielectric material portion 65 (i.e., an insulating filling material portion) can be formed in the stepped cavity. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. The excess portion of the deposited dielectric material can be removed from above the top surface of the topmost first sacrificial material layer 132L, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity can constitute the backward stepped dielectric material portion 65. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the backward stepped dielectric material portion 65, the silicon oxide of the backward stepped dielectric material portion 65 may be doped with a dopant or may not be doped with a dopant, such as B, P, and / or F.

[0146] See also Figure 3A , Figure 3B and FIG. 4A to FIG. 4C A photolithographic material stack (not shown) including at least a photoresist layer may be formed above the topmost first sacrificial material layer 132L and the backward stepped dielectric material portion 65, and may be photolithographically patterned to form a linear opening therein. The linear opening extends laterally along a first horizontal direction hd1, and has a uniform width along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The pattern in the photolithographic material stack may be transferred through the backward stepped dielectric material portion 65 and through the vertically alternating sequence (132L, 142L) by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask. The portion of the vertically alternating sequence (132L, 142L) below the linear opening in the patterned photolithographic material stack may be etched to form a linear groove 49. As used herein, a "linear groove" refers to a groove extending laterally straight in a horizontal direction.

[0147] The line grooves 49 extend laterally through the vertically alternating sequence (132L, 142L) along the first horizontal direction hd1. In one embodiment, the line grooves 49 have a corresponding uniform width that does not change during translation along the first horizontal direction hd1. In one embodiment, the line grooves 49 may have the same width throughout, and the spacing between adjacent pairs of line grooves 49 may be the same. In this case, the line grooves 49 may constitute a one-dimensional periodic array of line grooves 49, which has a spacing along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The width of the line grooves 49 along the second horizontal direction hd2 may be in the range of 30nm to 500nm, such as 60nm to 250nm, but smaller and larger widths may also be used.

[0148] Line trench 49 extends through each layer of the vertically alternating sequence (132L, 142L) and the rear stepped dielectric material portion 65. The chemical properties of the anisotropic etching process used to etch the material through the vertically alternating sequence (132L, 142L) can be alternating to optimize the etching of the first material and the second material in the vertically alternating sequence (132L, 142L). The anisotropic etching can be, for example, a series of reactive ion etching. The sidewalls of line trench 49 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0149] The line groove 49 may extend laterally through the entire memory array area 100, and may extend laterally into the contact area 300. The line groove 49 may extend laterally through the entire contact area 300 along the first horizontal direction hd1, or may extend laterally through only a portion of the width of the contact area 300 rather than the entire width along the first horizontal direction hd1 of the contact area. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each line groove 49, over-etching of the semiconductor material layer 10 may be optionally performed. The over-etching may be performed before or after removing the photolithography material stack. In other words, the recessed surface of the semiconductor material layer 10 may be vertically offset from the non-recessed top surface of the semiconductor material layer 10 by a recessed depth. The recessed depth may be in the range of, for example, 1 nm to 50 nm, but smaller and larger depths may also be used. Over-etching is optional and may be omitted. If over-etching is not performed, the bottom surface of the line groove 49 may be coplanar with the topmost surface of the semiconductor material layer 10. Reference Figure 3B The semiconductor material layer 10 may be exposed through the linear trench 49 in both embodiments where the optional over-etch is used and in embodiments where the over-etch is not performed.

[0150] Each of the linear grooves 49 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate. The substrate semiconductor layer 9 and the semiconductor material layer 10 together constitute the substrate (9, 10), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the linear grooves 49 may extend to the top surface of the substrate semiconductor layer 9. Although Figure 3B An exposed semiconductor material layer 10 is shown, but in embodiments where the semiconductor material layer 10 may be omitted, the substrate semiconductor layer 9 may be exposed.

[0151] The vertically alternating sequence (132L, 142L) may be divided into discrete portions by the line grooves 49. Each remaining portion of the vertically alternating sequence (132L, 142L) between a pair of line grooves 49 constitutes an alternating stack of a remaining portion of the first sacrificial material layer 132L and a remaining portion of the second sacrificial material layer 142. Each remaining portion of the first sacrificial material layer 132L may have a rectangular strip shape extending laterally along the first horizontal direction hd1 and having a uniform width along the second horizontal direction hd2, and is referred to herein as a first sacrificial material strip 132. Each remaining portion of the second sacrificial material layer 142L may have a rectangular strip shape extending laterally along the first horizontal direction hd1 and having a uniform width along the second horizontal direction hd2, and is referred to herein as a second sacrificial material strip 142. An alternating stack of the first sacrificial material strip 132 and the second sacrificial material strip 142 may be formed between each adjacent pair of line grooves 49 above the substrate (9, 10). The alternating stacks ( 132 , 142 ) may be laterally spaced apart from each other by linear grooves 49 extending laterally along the first horizontal direction hd1 .

[0152] See also FIG. 5A to FIG. 5C , silicon oxide layer 121 and diffusion barrier layer 123 may be sequentially deposited by a conformal deposition process. Silicon oxide layer 121 may have a thickness in the range of 1 nm to 10 nm, although smaller and larger thicknesses may also be used. Diffusion barrier layer 123 may have a thickness in the range of 4 nm to 10 nm, although smaller and larger thicknesses may also be used. Diffusion barrier layer 123 includes a material that may block oxygen diffusion in subsequent processing steps. In one embodiment, diffusion barrier layer 123 may include silicon nitride.

[0153] The mask material may be deposited in the remaining volume of the line groove 49. Excess portions of the mask material may be removed from above the top surface of the horizontal portion of the diffusion barrier layer 123 covering the alternating stack (132, 142). The remaining portion of the mask material in the line groove 49 constitutes a first mask material track 124R. As used herein, "track" or "track structure" refers to a structure extending laterally in a horizontal direction. In one embodiment, the first mask material track 124R may have a uniform vertical cross-sectional shape in a plane perpendicular to the longitudinal direction of the line groove 49 (i.e., the first horizontal direction hd1). In one embodiment, the vertical cross-sectional shape of the first mask material track 124R may be a rectangle or a trapezoid with a top width greater than a bottom width. In one embodiment, the first mask material track 124R may include a carbon-based material. In one embodiment, the first mask material track 124R may include spin-coated carbon that may be applied by spin coating and then dried.

[0154] See also FIG. 6A to FIG. 6C, a photoresist layer (not shown) may be applied above the first exemplary structure, and may be subsequently patterned to form an array of openings. In one embodiment, the array of openings in the photoresist layer may be a two-dimensional periodic array of discrete openings. In one embodiment, the two-dimensional periodic array of discrete openings may include multiple rows of openings covering a corresponding one in the line groove 49. The row-to-row spacing in the two-dimensional periodic array of discrete openings may be the same as the center-to-center spacing between the line grooves 49. Each row of openings may have a periodic one-dimensional array of openings, and the periodic one-dimensional array has a regular spacing P, which is the center-to-center distance between adjacent pairs of openings in the photoresist layer. In one embodiment, these rows may be numbered sequentially with integers from one end to the other. In a top view, even-numbered rows may be laterally offset by half of the regular spacing P relative to odd-numbered rows.

[0155] An anisotropic etching process (which etches the material of the first mask material rail 124R selectively to the material of the alternating stack (132, 142), the silicon oxide layer 121, and the diffusion barrier layer 123) may be performed to transfer the pattern of the openings in the photoresist layer through the first mask material rail 124R. Each remaining portion of the first mask material rail 124R may have a rectangular column shape and is referred to herein as a first mask material pillar 124. Adjacent pairs of first mask material pillars 124 in the line trench 49 may be laterally spaced apart by first columnar cavities 125'. Each first columnar cavity 125' may have a rectangular horizontal cross-sectional shape. A two-dimensional array of first mask material pillars 124 may be formed within the line trench 49.

[0156] See also 7A to 7C , an isotropic etching process may be performed that selectively etches the material of the diffusion barrier layer 123 with respect to the material of the silicon oxide layer 121 and the first mask material pillars 124. Physically exposed portions of the diffusion barrier layer 123 that are not masked by the two-dimensional array of mask material pillars 125' may be removed by the isotropic etching process. For example, if the diffusion barrier layer 123 includes silicon nitride, wet etching using hot phosphoric acid may be performed to isotropically etch the unmasked portions of the diffusion barrier layer 123. Each remaining portion of the diffusion barrier layer 123 extends vertically and is referred to herein as a diffusion barrier strip 123'. A row of diffusion barrier strips 123' may be formed on each sidewall of the line trench 49. Thus, two rows of diffusion barrier strips 123' may be formed within each line trench 49.

[0157] See also FIG. 8A to FIG. 8C, the first mask material pillars 124 may be removed selectively to the diffusion barrier strips 123' and the silicon oxide layer 121. For example, the first mask material pillars 124 may be removed by performing an ashing process. A memory cavity 125 may be formed within each memory opening resulting from the removal of the first mask material pillars 124. Each memory cavity 125 may include the volume of the mask material pillars 125' and the volume of the void formed by removing a row of the first mask material pillars 124 within the line trench 49.

[0158] A thermal oxidation process (e.g., similar to a LOCOS process) may be performed to convert surface portions of the first sacrificial material strips 132 and the second sacrificial material strips 142 that are adjacent to portions of the silicon oxide layer 121 that are not covered by the diffusion barrier strips 123'. Oxygen atoms diffuse through portions of the silicon oxide layer 121 that are not covered by the diffusion barrier strips 123' and enter surface portions of the first sacrificial material strips 132 and the second sacrificial material strips 142. Surface portions of the first sacrificial material strips 132 and the second sacrificial material strips 142 that are adjacent to the gaps between the diffusion barrier strips 123' are oxidized at a higher oxidation rate than surface portions of the first sacrificial material strips 132 and the second sacrificial material strips 142 that are adjacent to the diffusion barrier strips 123'. The oxidized surface portions of the first sacrificial material strips 132 and the second sacrificial material strips 142 are added to the silicon oxide layer 121 to form a semiconductor oxide layer 122.

[0159] The semiconductor oxide layer 122 may include a semiconductor oxide material including silicon, germanium, and oxygen with a composition modulation. The semiconductor oxide layer 122 includes a higher atomic percentage of germanium atoms at a thicker location than at a thinner location (e.g., a bird's beak effect location). Because the diffusion barrier strip 123' prevents oxygen from diffusing therethrough, the semiconductor oxide layer 122 may be formed as shown in FIG. Figure 8B and Figure 8C As shown, the semiconductor oxide layer 122 is formed to have a lateral thickness modulation. Specifically, the semiconductor oxide layer 122 is thicker in the area without the diffusion barrier strip 123' than in the area behind the diffusion barrier strip 123'. In addition, under the same oxidation conditions, the oxidation rate of the silicon-germanium alloy is faster than that of silicon. Therefore, the oxidation rate of the second sacrificial material strip 142 is faster than that of the first sacrificial material strip 132, and the semiconductor oxide layer 122 is thicker at the level of the second sacrificial material strip 142 than at the level of the first sacrificial material strip 132. Therefore, the semiconductor oxide layer 122 has a vertical thickness modulation (i.e., a modulation of the lateral thickness in the vertical direction), so that the semiconductor oxide layer 122 is thicker at the level of the second sacrificial material strip 142 than at the level of the first sacrificial material strip 132.

[0160] The ratio of the maximum lateral thickness of the semiconductor oxide layer 122 at the level of the second sacrificial material strips 142 to the maximum lateral thickness of the semiconductor oxide layer 122 at the level of the first sacrificial material strips 132 can be in the range of 1.2 to 5.0, such as 1.5 to 3.0, but smaller and larger ratios can also be used. The ratio of the maximum lateral thickness of the semiconductor oxide layer 122 at the level of the second sacrificial material strips 142 to the minimum lateral thickness of the semiconductor oxide layer 122 at the level of the second sacrificial material strips 142 can be in the range of 1.5 to 10, such as 3 to 6, but smaller and larger ratios can also be used. The ratio of the maximum lateral thickness of the semiconductor oxide layer 122 at the level of the first sacrificial material strips 132 to the minimum lateral thickness of the semiconductor oxide layer 122 at the level of the first sacrificial material strips 132 can be in the range of 1.2 to 3, such as 1.3 to 2, but smaller and larger ratios can also be used. The maximum lateral thickness of the semiconductor oxide layer 122 (which occurs at the level of the second sacrificial material strips 142) can be in the range of 10nm to 60nm, such as 15nm to 30nm, although smaller and larger thicknesses can also be used. The interface between the semiconductor oxide layer 122 and the second sacrificial material strips 142 can have a greater profile (i.e., have a greater curvature) than the interface between the semiconductor oxide layer 122 and the first sacrificial material strips 132. The semiconductor oxide layer 122 can be formed into a two-dimensional array of vertically stacked thickened portions. The thickened portion occurs at each level of the second sacrificial material strips 142.

[0161] See also 9A to 9C , the diffusion barrier strip 123' may be removed by performing an isotropic etching process such as a wet etching process using hydrofluoric acid. The semiconductor oxide layer 122 may then be removed by another isotropic etching process such as a wet etching process using dilute hydrofluoric acid. The memory cavity 125 may be expanded by the volume of the removed material portions of the diffusion barrier strip 123' and the semiconductor oxide layer 122. Therefore, the line groove 49 may be modified to provide a two-dimensional array of lateral recesses on each sidewall of the line groove 49. Each two-dimensional array of lateral recesses may be laterally bounded by a corresponding two-dimensional array of lateral recessed surfaces of the second sacrificial material strip 142. Each two-dimensional array of lateral recesses may extend in a lateral direction parallel to the longitudinal direction of the line groove 49 and in a vertical direction.

[0162] See also FIG. 10A to FIG. 10C, the blocking dielectric layer 52 can be directly formed on the sidewalls and bottom surfaces of the line groove 49 by a conformal deposition process. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may be essentially composed of at least one metal element and oxygen, or may be essentially composed of at least one metal element, oxygen and at least one other non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). Alternatively or in addition thereto, the blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride or a combination thereof. The thickness of the blocking dielectric layer 52 may be in the range of 3nm to 20nm, but smaller and larger thicknesses may also be used.

[0163] Subsequently, a charge storage material layer 54L may be formed. After forming the two-dimensional array of lateral recesses, a charge storage material layer 54L may be deposited over the blocking dielectric 52. In one embodiment, the charge storage material layer 54L may be a dielectric charge trapping material, which may be, for example, silicon nitride. The charge storage material layer 54L may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the charge storage material layer 54L may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0164] See also FIG. 11A to FIG. 11C , an anisotropic etching process may be performed to remove vertical portions of the charge storage material layer 54L that are not covered by the blocking dielectric layer 52. The anisotropic etching process is used to remove portions of the charge storage material layer 54L that are located outside the two-dimensional array of lateral recesses. Each remaining portion of the charge storage material layer 54L constitutes a discrete charge storage element 54. The two-dimensional array of discrete charge storage elements 54 may be formed on each longitudinal sidewall of the linear groove 49. Each two-dimensional array of discrete charge storage elements 54 may be formed within a corresponding two-dimensional array of corresponding lateral recesses into a vertical stack of second sacrificial material strips 142 within a corresponding alternating stack (132, 142). Each discrete charge storage element 54 may have the shape of a curved sheet having a curvature in a horizontal cross-sectional view and having a curvature in a vertical cross-sectional view. Each discrete charge storage element 54 may have a concave inner sidewall and a convex outer sidewall. During the anisotropic etching process, horizontal portions of the charge storage material layer 54L and the blocking dielectric layer 52 may be removed from the bottom of each line trench 49 .

[0165] See also FIG. 12A to FIG. 12C , a tunneling dielectric layer 56 may be formed on the physically exposed surfaces of the blocking dielectric layer 52 and the discrete charge storage element 54. The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by Fowler-Nordheim tunneling. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide or hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used. A set of blocking dielectric layers 52 , discrete charge storage elements 54 , and tunneling dielectric layers 56 constitute the memory film 50 .

[0166] A tunneling dielectric layer 56 may be formed over each two-dimensional array of discrete charge storage elements within a corresponding two-dimensional array of lateral recesses. A horizontal portion of the tunneling dielectric layer 56 may be removed from a bottom portion of each line trench 49 by an anisotropic etching process. A sacrificial capping material layer (not shown) may be used to protect the vertical portion of the tunneling dielectric layer 56 during the anisotropic etching process and may be removed thereafter.

[0167] Subsequently, a semiconductor channel material layer 60L may be optionally formed on the memory film 50. The semiconductor channel material layer 60L may directly contact the physically exposed top surface of the semiconductor material layer 10. The semiconductor channel material layer 60L includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. In one embodiment, the semiconductor channel material layer 60L may have a first conductivity type doping that is the same as the conductivity type of the doping of the semiconductor material layer 10. In one embodiment, the semiconductor channel material layer 60L may include a semiconductor material that includes an atomic concentration of 1.0×10 14 / cm3 to 1.0×10 18 / cm 3 range of electrical dopants.

[0168] The mask material may be deposited in the remaining volume of the line groove 49. Excess portions of the mask material may be removed from above the top surface of the horizontal portion of the semiconductor channel material layer 60L overlying the alternating stack (132, 142). The remaining portion of the mask material in the line groove 49 constitutes a second mask material track 126R. The second mask material track 126R may have a laterally modulated horizontal cross-sectional profile in a horizontal cross-sectional view, and may have a laterally modulated vertical cross-sectional profile in a vertical cross-sectional view perpendicular to the longitudinal direction of the second mask material track 126R. In one embodiment, the second mask material track 126R may include a carbon-based material. In one embodiment, the second mask material track 126R may include spin-on carbon that may be applied by spin coating and then dried.

[0169] See also FIG. 13A to FIG. 13C , a photoresist layer (not shown) may be applied over the first exemplary structure and may subsequently be patterned to form an array of openings. In one embodiment, the array of openings in the photoresist layer may be a two-dimensional periodic array of discrete openings. In one embodiment, the two-dimensional periodic array of discrete openings may include multiple rows of openings overlying a corresponding one of the linear grooves 49. The row-to-row spacing within the two-dimensional periodic array of discrete openings may be the same as the center-to-center spacing between the linear grooves 49. Each row of openings may have a periodic one-dimensional array of openings having a regular spacing P, which is the lateral distance between the center points of the two-dimensional array of lateral recesses within the second sacrificial material strips 142 in the alternating stack (132, 142). In one embodiment, the positions of the openings in the photoresist layer may be the same as in FIG. 6A to FIG. 6C The positions of the openings in the photoresist layer used at the processing step are laterally offset by half the regular pitch p.

[0170] An anisotropic etching process (which selectively etches the material of the second mask material rail 124R for the material of the alternating stack (132, 142), the memory film 50, and the semiconductor channel material layer 60L) may be performed to transfer the pattern of the opening in the photoresist layer through the second mask material rail 126R. Each remaining portion of the second mask material rail 126R may have a rectangular column shape and is referred to herein as a second mask material column 126. A two-dimensional array of second mask material columns 126 may be formed. Adjacent pairs of second mask material columns 126 in the line trench 49 are laterally spaced apart by second columnar cavities 127. Each second columnar cavity 127 may have a rectangular horizontal cross-sectional shape. A row of second mask material columns 126 is formed in each line trench 49. Each row of second mask material columns 126 may be staggered with a row of second columnar cavities 127 in the corresponding line trench 49. Second mask material pillars 126 may be formed in regions where a pair of concave sidewalls of two second sacrificial material rails 142 facing the same line of trenches 49 are laterally spaced apart by a maximum lateral spacing. Second pillar cavities 127 may be formed in gap regions between adjacent pairs of discrete charge storage elements 54.

[0171] See also FIG. 14A to FIG. 14C , an isotropic etching process may be performed to etch physically exposed portions of the semiconductor channel material layer 60L surrounding each second columnar cavity 127. For example, a wet etching process using tetramethylammonium hydroxide (TMAH) may be performed to etch the semiconductor material of the semiconductor channel material layer 60L. Each remaining portion of the semiconductor channel material layer 60L covered by the second mask material pillars 126 constitutes a vertical semiconductor channel 60. Each combination of a vertical semiconductor channel 60 and an adjacent portion of the memory film 50 constitutes a memory stack structure 55. Each memory stack structure 55 includes a vertical stack of memory elements embodied as a vertical stack of discrete charge storage elements 54. A row of vertical semiconductor channels 60 is formed above each tunnel dielectric layer 56. Each vertical semiconductor channel 60 within two rows of vertical semiconductor channels 60 laterally covers a corresponding vertical stack of discrete charge storage elements 54.

[0172] See also FIG. 15A to FIG. 15C , the second mask material pillars 126 may be removed selectively to the vertical semiconductor channels 60 and the memory film 50 . For example, the second mask material pillars 126 may be removed by ashing. A line cavity 129 may be formed within each unfilled volume of the line trench 49 .

[0173] See also FIG. 16A to FIG. 16C , Fig.17A and Fig. 17B, a dielectric material such as undoped silicate glass or doped silicate glass may be deposited in the remaining volume of the line trenches 49. Portions of the dielectric material located above the horizontal plane including the topmost first sacrificial material strip 132 may be removed by a planarization process such as recess etching or chemical mechanical planarization. Each remaining portion of the dielectric material constitutes a dielectric core 62. In one embodiment, each dielectric core 62 contacts two rows of vertical semiconductor channels 60 and two tunneling dielectric layers 56.

[0174] See also FIG. 18A to FIG. 18B The upper end of each dielectric core 62 may be vertically recessed, for example, by applying a photoresist layer over the first exemplary structure and patterning it to form an opening covering the dielectric core 62 and vertically recessing by performing an etching process, which may be an anisotropic etching process or an isotropic etching process. The photoresist layer may be removed, and a doped semiconductor material having a second conductivity type may be deposited in the recessed portion to form a drain region 63. The second conductivity type may be opposite to the first conductivity type, and the atomic concentration of the second conductivity type dopant in the drain region 63 may be between 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 range, but smaller and larger atomic concentrations may also be used.

[0175] See also Fig.19A and 19B , backside via cavities 79 may be formed through the isolation regions of the dielectric core 62 such that the remaining material portion within each line trench 49 includes at least one memory stack assembly 409. Each memory stack assembly 409 includes two rows of vertical semiconductor channels 60 connected to a row of drain regions 63. The positions of the backside via cavities 79 may be selected such that each second sacrificial material strip 142 contacts at least one of the backside via cavities 79. Additionally, the positions of the backside via cavities 79 may be selected such that each point within the second sacrificial material strip 142 is laterally spaced apart from the nearest backside via cavity in the backside via cavities 79 by a lateral distance that does not exceed a lateral etching distance during a subsequent isotropic etching process.

[0176] The memory stack assembly 409 is formed in each volume, each of which includes a combination of the volume of the initially formed line trench 49 and the volume of the two adjacent two-dimensional arrays of lateral recesses formed above the sidewalls of the second sacrificial material strip 142. Each of the memory stack assemblies 409 includes two two-dimensional arrays of lateral protrusion areas, and each of the lateral protrusion areas includes a corresponding charge storage element, i.e., a discrete charge storage element 54. Each of the memory stack assemblies 409 includes two rows of vertical semiconductor channels 60.

[0177] See also Fig. 20 , an etchant may be introduced into the backside via cavity 79, for example, using an isotropic etching process, which selectively etches the material of the second sacrificial material strip 142 relative to the material of the first sacrificial material strip 132, the blocking dielectric layer 52, and the dielectric core 62. The backside recess 143 may be formed in the volume from which the second sacrificial material strip 142 was removed. In one embodiment, the second sacrificial material strip 142 may include a silicon-germanium alloy, and the material of the first sacrificial material strip 132 may include silicon. In this case, the isotropic etching process may include a wet etching process using a combination of phosphoric acid and hydrogen peroxide.

[0178] The duration of the isotropic etching process can be selected so that the second sacrificial material strips 142 are completely removed from each alternating stack (132, 142) of the first sacrificial material strips 132 and the second sacrificial material strips 142. Each backside recess 143 can be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 143 can be greater than the height of the backside recess 143.

[0179] In one embodiment, the memory array area 100 includes a single three-dimensional NAND string array having a plurality of device levels disposed above the substrate (9, 10). In this case, each backside recess 143 may define a space for receiving a corresponding word line of the single three-dimensional NAND string array. Each backside recess in the plurality of backside recesses 143 may extend substantially parallel to the top surface of the substrate (9, 10). The backside recess 143 may be vertically defined by the top surface of the first sacrificial material strip 132 below and the bottom surface of the overlying first sacrificial material strip 132. In one embodiment, each backside recess 143 may have a uniform height throughout. The memory stack assembly 409 provides structural support for the first exemplary structure during the formation of the backside recess 143.

[0180] See also Fig.21 and FIG. 22A to FIG. 22C, a backside blocking dielectric layer (not shown) may optionally be formed in the backside recess 143 by a conformal deposition process. For example, the backside blocking dielectric layer may include a dielectric metal oxide (such as aluminum oxide). The conformal deposition process may include, for example, an atomic layer deposition (ALD) process. The thickness of the backside blocking dielectric layer may be in the range of 1 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0181] At least one conductive material may be deposited in the remaining volume of the backside recess 143. For example, without using a backside blocking dielectric layer, the metal barrier layer 146A may be deposited directly on the physically exposed surface of the backside blocking dielectric layer in the backside recess 143, or on the physically exposed surfaces of the blocking dielectric 52 and the first sacrificial material strip 132. The metal barrier layer 146A includes a conductive metal material that may serve as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited metal fill material. The metal barrier layer 146A may include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer 146A may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer 146A may be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier layer 146A may consist essentially of a conductive metal nitride such as TiN.

[0182] The metal filler material 146B is deposited in the remaining volume of the backside recess 143, on the sidewalls of at least one backside through-hole cavity 79, and above the topmost first sacrificial material strip 132. The metal filler material 146B can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filler material 146B can be substantially composed of at least one elemental metal. The at least one elemental metal of the metal filler material 146B can be selected from, for example, tungsten, cobalt, ruthenium, molybdenum, titanium, and tantalum. In one embodiment, the metal filler material 146B can be substantially composed of a single elemental metal. In one embodiment, the metal filler material 146B can be deposited using a fluorine-containing precursor gas such as WF6. In one embodiment, the metal filler material 146B may include tungsten, which includes a residual level of boron, fluorine, or silicon atoms as impurities.

[0183] A plurality of conductive strips 146 (i.e., conductive strips having a strip shape) may be formed in the plurality of backside recesses 143, and a continuous metal material layer may be formed on the sidewalls of each backside via cavity 79 and over the topmost first sacrificial material strip 132. Each conductive strip 146 includes a portion of a metal barrier layer 146A and a metal fill material 146B located between vertically adjacent pairs of first sacrificial material strips 132.

[0184] The deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each backside via cavity 79 and from above the topmost first sacrificial material strip 132, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metal material in the backside recess 143 constitutes a conductive strip 146. Each conductive strip 146 can be a conductive line structure. Therefore, the second sacrificial material strip 142 can be replaced with a conductive strip 146.

[0185] Each conductive strip 146 can be used as a combination of a plurality of control gate electrodes at the same level and a word line electrically interconnected (i.e., electrically shorted) with the plurality of control gate electrodes at the same level. The plurality of control gate electrodes within each conductive strip 146 are control gate electrodes for the NAND strings in the line trench 49. In other words, each conductive strip 146 can be a word line used as a common control gate electrode for the plurality of vertical memory devices. Each vertical semiconductor channel 60 has a laterally undulating vertical cross-sectional profile and includes a vertical stack of lateral bump portions, which are located at the level of the conductive strip 146 within the lateral recess, into the concave surface of the conductive strip 146. A two-dimensional array of lateral protrusion areas 410 is provided on each longitudinal sidewall of the line trench 49.

[0186] See also Fig.23 and FIG. 24A to FIG. 24C , the first sacrificial material strip 132 may be selectively removed for the conductive strip 146, the semiconductor material layer 10, and the outermost layer of the memory film 50 (i.e., the blocking dielectric layer 52). A cavity free of solid material may be formed in the volume from which the first sacrificial material strip 132 is removed. Each of the cavities has the shape of a strip and is referred to herein as an air gap strip 133. As used herein, an "air gap" element refers to any element that does not contain any solid material therein. The air gap strip may be under vacuum, or may be filled with at least one gas phase material, which may be an inert backfill gas or dry air.

[0187] See also Fig.25A and Fig.25B, a dielectric material such as silicon oxide is anisotropically deposited within the backside via cavity 79 and in the volume of the topmost air gap strip 133. The anisotropic deposition of the dielectric material can be performed by plasma enhanced chemical vapor deposition (PECVD), in which the dielectric material is directionally deposited. Excess portions of the deposited dielectric material can be removed from above a horizontal plane including the top surface of the rear stepped dielectric material portion 65. Each portion of the deposited dielectric material in the backside via cavity 79 forms an air gap column 76 enclosing a void therein. The voids in the air gap column 76 may not contain any solid phase material. The portion of the deposited dielectric material in the topmost air gap strip 133 constitutes the insulating cap layer 70. The curvature of the elements shown in the aforementioned close-up figures is not shown in FIG. Fig.25B It is shown in Fig.25B The figure is an unfolded top view, in which the curvature is not visible given the scale of the figure.

[0188] See also Figures 1 to 25B And according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which includes alternating stacks of conductive strips 146 and air gap strips 133, which are located above the substrate (9, 10) and are laterally spaced apart from each other by memory stack assemblies 409. The memory stack assemblies 409 extend laterally along a first horizontal direction hd1 and are spaced apart from each other along a second horizontal direction hd2. Each of the memory stack assemblies 409 includes two two-dimensional arrays of lateral protrusion areas 410 (e.g., when viewed in a vertical cross-sectional view). Each lateral protrusion area 410 protrudes laterally outward (i.e., away from the center of the memory stack assembly 409) from a corresponding vertical plane, which includes an interface between a corresponding one of the memory stack assemblies 409 and an air gap strip within a corresponding one of the alternating stacks (146, 133). Each of the lateral protrusion regions 410 includes a corresponding charge storage element 54 , each of the memory stack components 409 includes two rows of vertical semiconductor channels 60 , and each vertical semiconductor channel 60 within the two rows of vertical semiconductor channels 60 laterally covers a corresponding vertical stack of the charge storage element 54 .

[0189] In one embodiment, each of the memory stack assemblies 409 includes two tunneling dielectric layers 56 ; and each of the two tunneling dielectric layers 56 contacts a corresponding row of vertical semiconductor channels 60 selected from the two rows of vertical semiconductor channels 60 .

[0190] In one embodiment, each memory stack assembly in the memory stack assembly 409 includes a dielectric core 62 that extends laterally along the first horizontal direction hd1 and contacts the inner sidewalls of each vertical semiconductor channel 60 within the two rows of vertical semiconductor channels 60. In one embodiment, the vertical semiconductor channels 60 within each row of vertical semiconductor channels 60 are laterally spaced apart along the first horizontal direction hd1 by a vertically extending region in which the dielectric core 62 contacts one of the two tunneling dielectric layers 56.

[0191] In one embodiment, each of the two tunneling dielectric layers 56 contacts the two-dimensional array of charge storage elements 54 located in the two-dimensional array of lateral protrusion regions 410 .

[0192] In one embodiment, each vertical semiconductor channel 60 within the two rows of vertical semiconductor channels 60 includes a vertical stack of lateral bump portions at the level of the conductive strips 146 .

[0193] In one embodiment, each of the memory stack assemblies 409 includes two blocking dielectric layers 52; and each of the two blocking dielectric layers 52 contacts a respective one of the two tunneling dielectric layers 56 at each level of the air gap strips 133 and between each adjacent pair of vertical stacks of the charge storage elements 54. In one embodiment, each of the conductive strips 146 includes a respective metal barrier layer 146A and a respective portion of a metal fill material 146B formed within the respective metal barrier layer 146A; and each of the two blocking dielectric layers 52 contacts the sidewalls of a subset of the metal barrier layers 146A.

[0194] In one embodiment, charge storage elements 54 include discrete floating gate or dielectric charge trapping material portions that are not in contact with each other. In one embodiment, each of charge storage elements 54 includes a concave inner sidewall having a horizontal concave profile in a horizontal cross-sectional view and a convex outer sidewall having a horizontal convex profile in a horizontal cross-sectional view.

[0195] In one embodiment, in the vertical cross-sectional view, the concave inner side wall has a vertical concave profile at the upper edge region and the lower edge region of the corresponding charge storage element 54; and in the vertical cross-sectional view, the convex outer side wall has a vertical convex profile at the upper edge region and the lower edge region of the corresponding charge storage element 54.

[0196] In one embodiment, each of the charge storage elements 54 is located between a first horizontal plane that includes a top surface of a corresponding one of the conductive strips 146 and a second horizontal plane that includes a bottom surface of a corresponding one of the conductive strips 146 .

[0197] See also Fig.26 , shows a second exemplary structure according to a second embodiment of the present disclosure, which includes substrates ( 9 , 10 ) that may be the same as the substrates ( 9 , 10 ) of the first exemplary structure.

[0198] A vertically alternating sequence of first material layers (such as insulating layers 32L) and second material layers (such as spacer material layers) is formed above the substrate (9, 10). The vertically alternating sequence may include a stack of alternating multiple first material layers (which may be insulating layers 32L) and second material layers (which may be sacrificial material layers 42L). Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32L, and each second material layer may be a sacrificial material layer. In this case, the stack may include alternating multiple insulating layers 32L and sacrificial material layers 42L, and constitute a prototype stack including alternating layers of insulating layers 32L and sacrificial material layers 42L.

[0199] In one embodiment, the vertically alternating sequence (32L, 42L) may include an insulating layer 32L composed of a first material and a sacrificial material layer 42L composed of a second material, wherein the second material is different from the material of the insulating layer 32L. The first material of the insulating layer 32L may be at least one insulating material. Therefore, each insulating layer 32L may be an insulating material layer. Insulating materials that can be used for the insulating layer 32L include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layer 32L may be silicon oxide. The second material of the sacrificial material layer 42L is a sacrificial material that can be selectively removed for the first material of the insulating layer 32.

[0200] The sacrificial material layer 42L may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42L may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42L may be a spacer material layer including silicon nitride or a semiconductor material including at least one of silicon and germanium.

[0201] In one embodiment, insulating layer 32L may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of insulating layer 32L may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulating layer 32L, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42L may be formed, for example, by CVD or atomic layer deposition (ALD).

[0202] The thickness of the insulating layer 32L and the sacrificial material layer 42L can be in the range of 20nm to 50nm, but smaller and larger thicknesses can be used for each insulating layer 32L and each sacrificial material layer 42L. The number of repetitions of the paired insulating layer 32L and sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 42L can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. The top gate electrode and the bottom gate electrode in the stack can be used as select gate electrodes. In one embodiment, each sacrificial material layer 42L in the vertically alternating sequence (32L, 42L) can have a uniform thickness that is substantially constant within each corresponding sacrificial material layer 42L.

[0203] Optionally, a continuous insulating capping layer 70L may be formed above the vertically alternating sequence (32L, 42L). The continuous insulating capping layer 70L includes a dielectric material different from the material of the sacrificial material layer 42L. In one embodiment, the continuous insulating capping layer 70L may include a dielectric material that can be used for the insulating layer 32L as described above. The continuous insulating capping layer 70L may have a thickness greater than each of the insulating layers in the insulating layer 32L. The continuous insulating capping layer 70L may be deposited, for example, by chemical vapor deposition. In one embodiment, the continuous insulating capping layer 70L may be a silicon oxide layer.

[0204] See also Fig. 27, the vertically alternating sequence of the insulating layer 32L and the spacer material layer (i.e., the sacrificial material layer 42L) may be patterned to form a stepped surface extending continuously from the bottommost layer of the vertically alternating sequence (32L, 42L) to the topmost layer of the alternating sequence (32L, 42L) in the contact region 300. A stepped cavity may be formed in the contact region 300 which may be located between the memory array region 100 and a peripheral device region (not shown), the peripheral device region including at least one semiconductor device for a peripheral circuit. The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the cavity depth by one or more steps, the second type of etching process laterally extending the area to be vertically etched in a subsequent etching process of the first type.

[0205] A stepped surface is formed at a peripheral portion of the vertically alternating sequence (32L, 42L) by forming a stepped cavity. A terrace region is formed by patterning the vertically alternating sequence (32L, 42L). Each sacrificial material layer 42L except the topmost sacrificial material layer 42L in the vertically alternating sequence (32L, 42L) extends laterally farther than any covering sacrificial material layer 42L in the vertically alternating sequence (32L, 42L). The terrace region includes a stepped surface of the vertically alternating sequence (32L, 42L) that extends continuously from the bottommost layer in the vertically alternating sequence (32L, 42L) to the topmost layer in the vertically alternating sequence (32L, 42L).

[0206] A backward stepped dielectric material portion 65 (i.e., an insulating filling material portion) may be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from above the top surface of the continuous insulating cap layer 70L, for example, by chemical mechanical planarization (CMP). The remaining portions of the deposited dielectric material that fill the stepped cavity constitute the backward stepped dielectric material portion 65. If silicon oxide is used for the backward stepped dielectric material portion 65, the silicon oxide of the backward stepped dielectric material portion 65 may or may not be doped with a dopant, such as B, P, and / or F.

[0207] See also Fig.28A , Fig.28B and FIG. 29A to FIG. 29CA photolithographic material stack (not shown) including at least a photoresist layer may be formed over the continuous insulating cap layer 70L and the backward stepped dielectric material portion 65, and may be photolithographically patterned to form a linear opening therein. The linear opening extends laterally along a first horizontal direction hd1, and has a uniform width along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The pattern in the photolithographic material stack may be transferred through the continuous insulating cap layer 70L or the backward stepped dielectric material portion 65 and through the vertically alternating sequence (32L, 42L) by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask. The portion of the vertically alternating sequence (32L, 42L) below the linear opening in the patterned photolithographic material stack is etched to form a linear groove 49. As used herein, "linear groove" refers to a groove extending laterally straight in a horizontal direction.

[0208] The line grooves 49 extend laterally along the first horizontal direction hd1 through the vertically alternating sequence (32L, 42L). In one embodiment, the line grooves 49 have a corresponding uniform width that does not change during translation along the first horizontal direction hd1. In one embodiment, the line grooves 49 may have the same width throughout, and the spacing between adjacent pairs of line grooves 49 may be the same. In this case, the line grooves 49 may constitute a one-dimensional periodic array of line grooves 49, which has a spacing along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The width of the line grooves 49 along the second horizontal direction hd2 may be in the range of 30nm to 500nm, such as 60nm to 250nm, but smaller and larger widths may also be used.

[0209] Line trench 49 extends through each layer of the vertically alternating sequence (32L, 42L) and the rear stepped dielectric material portion 65. The chemical properties of the anisotropic etching process used to etch the material through the vertically alternating sequence (32L, 42L) can be alternating to optimize the etching of the first material and the second material in the vertically alternating sequence (32L, 42L). The anisotropic etching can be, for example, a series of reactive ion etching. The sidewalls of line trench 49 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0210] The line groove 49 extends laterally through the entire memory array area 100 and laterally into the contact area 300. The line groove 49 may extend laterally through the entire contact area 300 along the first horizontal direction hd1, or may extend laterally through only a portion of the width of the contact area 300 rather than the entire width along the first horizontal direction hd1 of the contact area. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each line groove 49, overetching of the semiconductor material layer 10 may be optionally performed. Overetching may be performed before or after removing the photolithographic material stack. In other words, the recessed surface of the semiconductor material layer 10 may be vertically offset from the non-recessed top surface of the semiconductor material layer 10 by a recessed depth. The recessed depth may be in the range of, for example, 1 nm to 50 nm, but smaller and larger depths may also be used. Overetching is optional and may be omitted. If over-etching is not performed, the bottom surface of the line trench 49 may be coplanar with the topmost surface of the semiconductor material layer 10 (or with the substrate semiconductor layer 9 in embodiments where the semiconductor material layer 10 is not used).

[0211] Each of the linear grooves 49 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate. The substrate semiconductor layer 9 and the semiconductor material layer 10 together constitute the substrate (9, 10), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the linear groove 49 may extend to the top surface of the substrate semiconductor layer 9.

[0212] The vertically alternating sequence (32L, 42L) and the continuous insulating capping layer 70L are divided into discrete portions by the line grooves 49. Each remaining portion of the vertically alternating sequence (32L, 42L) between a pair of line grooves 49 constitutes an alternating stack of a remaining portion of the insulating layer 32L and a remaining portion of the sacrificial material layer 42L. Each remaining portion of the insulating layer 32L may have a rectangular strip shape extending laterally along the first horizontal direction hd1 and having a uniform width along the second horizontal direction hd2, and is referred to herein as an insulating strip 32. Each remaining portion of the sacrificial material layer 42L may have a rectangular strip shape extending laterally along the first horizontal direction hd1 and having a uniform width along the second horizontal direction hd2, and is referred to herein as a sacrificial material strip 42. The alternating stack of the insulating strip 32 and the sacrificial material strip 42 is formed between each adjacent pair of line grooves 49 above the substrate (9, 10). The alternating stacks (32, 42) are laterally spaced apart from each other by line trenches 49 extending laterally in a first horizontal direction hd1. Each remaining portion of the continuous insulating capping layer 70L is referred to herein as an insulating capping layer 70 that overlies a respective one of the alternating stacks (32, 42).

[0213] See also FIG. 30A to FIG. 30C , the mask material may be deposited in the remaining volume of the line groove 49. Excess portions of the mask material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70. The remaining portion of the mask material in the line groove 49 constitutes a first mask material track 222R. In one embodiment, the first mask material track 222R may have a uniform vertical cross-sectional shape in a plane perpendicular to the longitudinal direction of the line groove 49. In one embodiment, the vertical cross-sectional shape of the first mask material track 222R may be a rectangle or a trapezoid with a top width greater than a bottom width. In one embodiment, the first mask material track 222R may include a carbon-based material. In one embodiment, the first mask material track 222R may include spin-on carbon that may be applied by spin coating and then dried.

[0214] See also FIG. 31A to FIG. 31C , a photoresist layer (not shown) may be applied above the first exemplary structure, and may be subsequently patterned to form an array of openings. In one embodiment, the array of openings in the photoresist layer may be a two-dimensional periodic array of discrete openings. In one embodiment, the two-dimensional periodic array of discrete openings may include multiple rows of openings covering a corresponding one in the line groove 49. The row-to-row spacing in the two-dimensional periodic array of discrete openings may be the same as the center-to-center spacing between the line grooves 49. Each row of openings may have a periodic one-dimensional array of openings, and the periodic one-dimensional array has a regular spacing P, which is the center-to-center distance between adjacent pairs of openings in the photoresist layer. In one embodiment, these rows may be numbered sequentially with integers from one end to the other. In a top view, even-numbered rows may be laterally offset by half of the regular spacing P relative to odd-numbered rows.

[0215] An anisotropic etching process (which etches the material of the first mask material rails 222R selectively to the material of the alternating stack (32, 42)) may be performed to transfer the pattern of the openings in the photoresist layer through the first mask material rails 222R. Each remaining portion of the first mask material rails 222R may have a rectangular column shape and is referred to herein as a first mask material pillar 222. Adjacent pairs of first mask material pillars 222 in the line trench 49 are laterally spaced apart by first columnar cavities 223. Each first columnar cavity 223 may have a rectangular horizontal cross-sectional shape. A two-dimensional array of first mask material pillars 222 is formed within the line trench 49.

[0216] See also FIG. 32A to FIG. 32C, an isotropic etching process is performed to laterally recess the physically exposed surface of the sacrificial material strip 42 selectively with respect to the material of the insulating strip 32, the insulating cap layer 70, and the semiconductor material layer 10. When the two-dimensional array of first mask material pillars 222 in the line trench 49 is present within the line trench 49, the sacrificial material strip 42 is laterally recessed selectively with respect to the insulating strip 32, thereby blocking the isotropic etchant from reaching the masked portion of the sacrificial material strip 42. For example, if the sacrificial material strip 42 comprises silicon nitride, a wet etching process using hot phosphoric acid may be used to isotropically recess the sidewalls of the sacrificial material strip 42 to form a lateral recessed portion, i.e., an area where the sidewalls of the sacrificial material strip 42 are laterally recessed with respect to the sidewalls of the overlying or underlying insulating strip 32. The two-dimensional array of lateral recessed portions may be formed on each sidewall of the line trench 49. The lateral recess distance between the recessed sidewalls of the sacrificial material strip 42 and the overlying or underlying insulating strip 32 may be in the range of 3 nm to 60 nm, such as 6 nm to 30 nm, although smaller and larger recess distances may also be used.

[0217] See also FIG. 33A to FIG. 33C , the first mask material pillars 222 may be selectively removed for the alternating stack (32, 42) and the insulating capping layer 70. For example, the first mask material pillars 222 may be removed by performing an ashing process. The line trenches 49 are modified to provide a two-dimensional array of lateral recesses on each sidewall of the line trenches 49. Each two-dimensional array of lateral recesses may be laterally bounded by a corresponding two-dimensional array of lateral recessed surfaces of the sacrificial material strips 42. Each longitudinal sidewall of the line trenches 49 may include a two-dimensional array of lateral recesses.

[0218] See also FIG. 34A to FIG. 34C, a continuous layer stack of a blocking dielectric layer 52, a charge storage material layer 54L, and a tunneling dielectric layer 56 may be formed on the sidewalls of the line groove 49. The blocking dielectric layer 52 is formed directly on the sidewalls and bottom surface of the line groove 49 by a conformal deposition process. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one other non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). Alternatively or in addition thereto, the blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. The thickness of the blocking dielectric layer 52 may be in the range of 3 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0219] Subsequently, a charge storage material layer 54L may be formed. After forming the two-dimensional array of lateral recesses, a charge storage material layer 54L may be deposited over the remaining portions of the alternating strips 42. In one embodiment, the charge storage material layer 54L may be a dielectric charge trapping material, which may be, for example, silicon nitride. The charge storage material layer 54L may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the charge storage material layer 54L may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0220] In an alternative embodiment, the floating gate structure may be formed by anisotropically etching the charge storage material layer 54L. In this case, the portion of the charge storage material layer 54L located within the lateral recess is not removed by the anisotropic etching process, and the portion of the charge storage material layer 54L located outside the lateral recess may be removed by the anisotropic etching process. A two-dimensional array of discrete floating gate structures may be formed within each two-dimensional array of lateral recesses located on each longitudinal sidewall of the linear trench 49. The collection of all two-dimensional arrays of discrete floating gate structures constitutes a three-dimensional array of discrete floating gate structures.

[0221] The tunneling dielectric layer 56 is formed on the charge storage material layer 54L or the three-dimensional array of discrete floating gate structures. The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by Fowler-Nordheim tunneling. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide or hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used.

[0222] See also FIG. 35A to FIG. 35C , an anisotropic etching process may be performed to remove horizontal portions of the continuous layer stack of the blocking dielectric layer 52, the charge storage material layer 54L, and the tunneling dielectric layer 56. During the anisotropic etching process, horizontal portions of the continuous layer stack may be removed from the bottom of each line trench 49 and from above the insulating cap layer 70. The top surface of the semiconductor material layer 10 may be physically exposed at the bottom of each line trench 49. Each layer in the continuous layer stack of the blocking dielectric layer 52, the charge storage material layer 54L, and the tunneling dielectric layer 56 is divided into a plurality of discrete portions. The layer stack of the blocking dielectric layer 52, the charge storage material layer 54L, and the tunneling dielectric layer 56 located on the longitudinal sidewalls of the line trench 49 is referred to herein as a memory film 50.

[0223] See also FIG. 36A to FIG. 36C, a semiconductor channel material layer 60L may be optionally formed on the memory film 50. The semiconductor channel material layer 60L may directly contact the physically exposed top surface of the semiconductor material layer 10. The semiconductor channel material layer 60L includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. In one embodiment, the semiconductor channel material layer 60L may have a first conductivity type doping that is the same as the conductivity type of the doping of the semiconductor material layer 10. In one embodiment, the semiconductor channel material layer 60L may include a semiconductor material that includes an atomic concentration of 1.0×10 14 / cm to 1.0×10 18 / cm 3 range of electrical dopants.

[0224] See also FIG. 37A to FIG. 37C , a mask material may be deposited in the remaining volume of the line trench 49 to form a mask material layer 226L. In one embodiment, the mask material may include a carbon-based material. In one embodiment, the mask material may include spin-on carbon that may be applied by spin coating and then dried.

[0225] See also FIG. 38A to FIG. 38C , excess portions of the mask material may be removed from above the top surface of the insulating cap layer 70. The remaining portions of the mask material in the line trenches 49 constitute the second mask material tracks 226R. The second mask material tracks 226R may have a laterally modulated horizontal cross-sectional profile in a horizontal cross-sectional view, and may have a laterally modulated vertical cross-sectional profile in a vertical cross-sectional view perpendicular to the longitudinal direction of the second mask material tracks 226R. The horizontal portions of the semiconductor channel material layer 60L overlying the insulating cap layer 70 may then be removed, for example, by recess etching.

[0226] See also FIG. 39A to FIG. 39C, a photoresist layer (not shown) may be applied over the first exemplary structure and may subsequently be patterned to form an array of openings. In one embodiment, the array of openings in the photoresist layer may be a two-dimensional periodic array of discrete openings. In one embodiment, the two-dimensional periodic array of discrete openings may include multiple rows of openings overlying a corresponding one of the linear grooves 49. The row-to-row spacing within the two-dimensional periodic array of discrete openings may be the same as the center-to-center spacing between the linear grooves 49. Each row of openings may have a periodic one-dimensional array of openings having a regular spacing P, which is the lateral distance between the center points of the two-dimensional array of lateral recesses within the sacrificial material strips 42 in the alternating stack (32, 42). In one embodiment, the positions of the openings in the photoresist layer may be the same as in FIG. 31A to FIG. 31C The positions of the openings in the photoresist layer used at the processing step are laterally offset by half the regular pitch p.

[0227] An anisotropic etching process (which selectively etches the material of the second mask material rail 222R for the material of the alternating stack (32, 42), the memory film 50, and the semiconductor channel material layer 60L) may be performed to transfer the pattern of the opening in the photoresist layer through the second mask material rail 226R. Each remaining portion of the second mask material rail 226R may have a rectangular column shape and is referred to herein as a second mask material column 226. A two-dimensional array of second mask material columns 226 may be formed. Adjacent pairs of second mask material columns 226 in the line trench 49 are laterally spaced apart by second columnar cavities 227. Each second columnar cavity 227 may have a rectangular horizontal cross-sectional shape. A row of second mask material columns 226 is formed in each line trench 49. Each row of second mask material columns 226 is staggered with a row of second columnar cavities 227 in the corresponding line trench 49. Second mask material pillars 226 may be formed in regions where a pair of recessed sidewalls of two second sacrificial material rails 42 facing the same linear trench 49 are laterally spaced apart by a maximum lateral spacing. Second pillar cavities 227 may be formed in gap regions between adjacent pairs of unrecessed sidewalls of sacrificial material strips 42.

[0228] See also FIG. 40A to FIG. 40C , an isotropic etching process is performed to etch the physically exposed portion of the semiconductor channel material layer 60L surrounding each second columnar cavity 227. For example, a wet etching process using tetramethylammonium hydroxide (TMAH) may be performed to etch the semiconductor material of the semiconductor channel material layer 60L. Each remaining portion of the semiconductor channel material layer 60L covered by the second mask material pillars 226 constitutes a vertical semiconductor channel 60. A row of vertical semiconductor channels 60 is formed above each tunnel dielectric layer 56. A two-dimensional array of lateral protrusion regions 510 is disposed on each longitudinal sidewall of the line trench 49.

[0229] At least one isotropic etching process is performed to etch the unmasked portion of the memory film 50. For example, a series of wet etching processes may be used to sequentially etch the unmasked portions of the tunneling dielectric layer 56, the charge storage material layer 54L, and the blocking dielectric layer 52 around each second pillar-shaped cavity 227. The portions of the memory film 50 that are not masked by the second mask material pillars 226 are isotropically etched. The remaining portions of the tunneling dielectric layer 56, the charge storage material layer 54L, and the blocking dielectric layer 52 have corresponding stripe shapes and are positioned adjacent to corresponding ones of the vertical semiconductor channels 60.

[0230] The remaining portions of the memory film 50 and the vertical semiconductor channel 60 constitute a material stack strip that extends into the sacrificial material strip 42 above the vertical stack of lateral recesses. Each of the material stack strips includes a blocking dielectric layer 52 that contacts the insulating strip 32 within a corresponding one of the alternating stacks (32, 42), a charge storage material layer 54L, a tunneling dielectric layer 56, and a vertical semiconductor channel 60, the blocking dielectric layer contacts the insulating strip 32 within a corresponding one of the alternating stacks (32, 42), the charge storage material layer contacts the blocking dielectric layer 52 and includes a vertical stack of charge storage elements, the tunneling dielectric layer contacts the charge storage material layer 54L, and the vertical semiconductor channel contacts the tunneling dielectric layer 56. Each material stack strip is referred to herein as a memory stack structure 55, which includes a memory film 50 (as patterned into a stripe shape) and a vertical semiconductor channel 60.

[0231] Each memory film 50 within the line groove 49 is divided into a row of memory films 50 spaced apart laterally. Each combination of the vertical semiconductor channel 60 and the memory film 50 constitutes a memory stack structure 55. Each memory stack structure 55 includes a vertical stack of memory elements, which is embodied as a portion of the charge storage material layer 54L located at the level of the sacrificial material strip 42. Each vertical semiconductor channel 60 laterally covers a corresponding vertical stack of the charge storage material layer 54L. Each line groove 49 may include two rows of material stack strips (including the memory stack structure 55), which extend vertically and laterally over the sidewalls of a corresponding one of the alternating stacks (32, 42). Each row of material stack strips includes a corresponding plurality of material stack strips spaced apart laterally along the first horizontal direction hd1. Each of the material stack strips includes a corresponding charge storage material layer 54L, which includes a charge storage element in each corresponding vertical stack of a lateral recess selected from a two-dimensional array of lateral recesses.

[0232] Each charge storage element is embodied as a portion of a charge storage material layer 54L at the level of a sacrificial material strip 42 and has a pair of concave inner sidewall segments connected by straight inner sidewall segments, such as Fig.40CAs shown. A pair of concave inner sidewall segments of each charge storage element contacts a pair of convex outer sidewall segments of the vertical semiconductor channel 60. A straight inner sidewall segment of each charge storage element contacts a straight outer sidewall segment of the vertical semiconductor channel 60, as shown. Fig.40C As shown. Each charge storage element has a pair of convex outer sidewall segments, which have corresponding horizontal convex profiles in a horizontal cross-sectional view. The pair of convex outer sidewall segments can be connected to each other by straight outer sidewall segments. The pair of convex outer sidewall segments of each charge storage element contact a pair of concave inner sidewall segments of the blocking dielectric layer 52. The straight outer sidewall segments of each charge storage element contact the straight inner sidewall segments of the blocking dielectric layer 52, as shown. Fig.40C shown.

[0233] See also FIG. 41A to FIG. 41C , the second mask material pillars 226 may be removed selectively to the vertical semiconductor channels 60 and the memory film 50. For example, the second mask material pillars 226 may be removed by ashing.

[0234] See also FIG. 42A to FIG. 42C , a dielectric material such as undoped silicate glass or doped silicate glass may be deposited in the remaining volume of the line trenches 49. Excess portions of the dielectric material located above the horizontal plane including the insulating cap layer 70 may be removed by a planarization process such as recess etching or chemical mechanical planarization. Each remaining portion of the dielectric material constitutes a dielectric core 62. In one embodiment, each dielectric core 62 contacts two rows of vertical semiconductor channels 60 and two tunneling dielectric layers 56.

[0235] In one embodiment, the dielectric core 62 may be formed in the unfilled volume of the line trench 49 after forming the material stack strips. The dielectric core 62 may be formed on physically exposed sidewall surfaces of the insulating strips 32 and the sacrificial material strips 42, which are located outside the two-dimensional array of lateral recesses. The dielectric core 62 contacts the secondary surfaces of the blocking dielectric layer 52, the charge storage material layer 54L, the tunneling dielectric layer 56, and the vertical semiconductor channel 60. As used herein, the secondary surface of an element refers to a surface that includes less than 25% of the entire surface area of ​​the element. In contrast, the primary surface of an element refers to a surface that includes more than 25% of the entire surface area of ​​the element. The dielectric core 62 contacts the primary surface of each vertical semiconductor channel 60 and does not contact the primary surfaces of the blocking dielectric layer 52, the charge storage material layer 54L, and the tunneling dielectric layer 56. The primary surface of each blocking dielectric layer 52 contacts a corresponding one of the alternating stacks (32, 42) of insulating strips 32 and sacrificial material strips 42.

[0236] See also FIG. 43A to FIG. 43D , Fig.44A and Fig.44BThe upper end of each dielectric core 62 may be vertically recessed, for example, by applying a photoresist layer over the first exemplary structure and patterning it to form an opening covering the dielectric core 62 and vertically recessing by performing an etching process, which may be an anisotropic etching process or an isotropic etching process. The photoresist layer may be removed, and a doped semiconductor material having a second conductivity type may be deposited in the recessed portion to form a drain region 63. The second conductivity type may be opposite to the first conductivity type, and the atomic concentration of the second conductivity type dopant in the drain region 63 may be between 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 range, but smaller and larger atomic concentrations may also be used.

[0237] See also Fig.45A and 45B , backside via cavities 79 may be formed through the isolation regions of the dielectric core 62 such that the remaining material portion within each line trench 49 includes at least one memory stack assembly 509. Each memory stack assembly 509 includes two rows of vertical semiconductor channels 60 connected to a row of drain regions 63. The positions of the backside via cavities 79 may be selected such that each sacrificial material strip 42 contacts at least one of the backside via cavities 79. Additionally, the positions of the backside via cavities 79 may be selected such that each point within the sacrificial material strip 42 is laterally spaced apart from the nearest backside via cavity in the backside via cavities 79 by a lateral distance that does not exceed a lateral etching distance during a subsequent isotropic etching process.

[0238] The memory stack assemblies 509 are formed in each volume, each of which includes a combination of the volume of the initially formed line trenches 49 and the volume of the two adjacent two-dimensional arrays of lateral recesses formed above the sidewalls of the sacrificial material strips 42. Each of the memory stack assemblies 509 includes two two-dimensional arrays of lateral protrusions 510, and each of the lateral protrusions 510 includes a corresponding charge storage element, i.e., a discrete charge storage element 54. Each of the memory stack assemblies 509 includes two rows of vertical semiconductor channels 60.

[0239] See also Fig.46, an etchant may be introduced into the backside via cavity 79, for example, using an isotropic etching process, which selectively etches the material of the sacrificial material strip 42 relative to the material of the insulating strip 32, the blocking dielectric layer 52, and the dielectric core 62. The backside recess 43 is formed in the volume from which the sacrificial material strip 42 was removed. In one embodiment, the sacrificial material strip 42 may include silicon nitride, and the material of the insulating strip 32 may include silicon oxide. In this case, the isotropic etching process may include a wet etching process using hot phosphoric acid.

[0240] The duration of the isotropic etching process may be selected so that the sacrificial material strips 42 are completely removed from each alternating stack (32, 42) of insulating strips 32 and sacrificial material strips 42. Each backside recess 43 may be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 may be greater than the height of the backside recess 43.

[0241] In one embodiment, the memory array area 100 includes a single three-dimensional NAND string array having a plurality of device levels disposed above the substrate (9, 10). In this case, each backside recess 43 may define a space for receiving a corresponding word line of the single three-dimensional NAND string array. Each backside recess in the plurality of backside recesses 43 may extend substantially parallel to the top surface of the substrate (9, 10). The backside recess 43 may be vertically defined by the top surface of the underlying insulating strip 32 and the bottom surface of the overlying insulating strip 32. In one embodiment, each backside recess 43 may have a uniform height throughout. The memory stack assembly 509 provides structural support for the first exemplary structure during the formation of the backside recess 43.

[0242] See also Fig.47 and FIG. 48A to FIG. 48C , a backside blocking dielectric layer (not shown) may optionally be formed in the backside recess 43 by a conformal deposition process. For example, the backside blocking dielectric layer may include a dielectric metal oxide (such as aluminum oxide). The conformal deposition process may include, for example, an atomic layer deposition (ALD) process. The thickness of the backside blocking dielectric layer may be in the range of 1 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0243] At least one conductive material may be deposited in the remaining volume of the backside recess 43. For example, without using a backside blocking dielectric layer, a metal barrier layer may be deposited directly on the physically exposed surface of the backside blocking dielectric layer in the backside recess 43, or on the physically exposed surfaces of the blocking dielectric 52 and the insulating strip 32. The metal barrier layer includes a conductive metal material that can be used as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited metal filler material. The metal barrier layer may include a conductive metal nitride material such as TaN, WN, or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer may be in the range of 2nm to 8nm, such as 3nm to 6nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier layer may be substantially composed of a conductive metal nitride such as TiN.

[0244] The metal filling material is deposited in the remaining volume of the backside recess 43 on the sidewalls of at least one backside through-hole cavity 79, and is deposited above the insulating cap layer 70. The metal filling material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filling material can be substantially composed of at least one elemental metal. At least one elemental metal of the metal filling material can be selected from, for example, tungsten, cobalt, ruthenium, molybdenum, titanium, and tantalum. In one embodiment, the metal filling material can be substantially composed of a single elemental metal. In one embodiment, the metal filling material can be deposited using a fluorine-containing precursor gas such as WF6. In one embodiment, the metal filling material may include tungsten, which includes a residual level of boron, fluorine, or silicon atoms as impurities.

[0245] A plurality of conductive strips 46 (i.e., conductive strips having a strip shape) may be formed in the plurality of backside recesses 43, and a continuous metal material layer may be formed on the sidewalls of each backside via cavity 79 and over the insulating capping layer 70. Each conductive strip 46 includes a portion of the metal barrier layer between vertically adjacent pairs of insulating strips 32 and a metal filling material.

[0246] The deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each backside via cavity 79 and from above the insulating cap layer 70, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive strip 46. Each conductive strip 46 can be a conductive line structure. Thus, the sacrificial material strip 42 is replaced with a conductive strip 46.

[0247] Each conductive strip 46 can be used as a combination of a plurality of control gate electrodes at the same level and a word line electrically interconnected (i.e., electrically shorted) with the plurality of control gate electrodes at the same level. The plurality of control gate electrodes within each conductive strip 46 are control gate electrodes for the NAND strings in the line trench 49. In other words, each conductive strip 46 can be a word line used as a common control gate electrode for the plurality of vertical memory devices. Each vertical semiconductor channel 60 has a laterally undulating vertical cross-sectional profile and includes a vertical stack of lateral bump portions located at the level of the conductive strip 46 within the lateral recess, into the concave surface of the conductive strip 46.

[0248] See also Fig.49A and Fig.49B , a dielectric material such as silicon oxide is anisotropically deposited within the backside via cavity 79. The anisotropic deposition of the dielectric material can be performed by plasma enhanced chemical vapor deposition (PECVD), in which the dielectric material is directionally deposited. Excess portions of the deposited dielectric material can be removed from above a horizontal plane including the top surface of the rear stepped dielectric material portion 65. Each portion of the deposited dielectric material in the backside via cavity 79 forms a dielectric pillar 176. Optionally, the dielectric pillar 176 can be an air gap pillar including a corresponding void therein. The curvature of the elements shown in the foregoing close-up figures is not shown in FIG. Fig.49B It is shown in Fig.49B The figure is an unfolded top view, in which the curvature is not visible given the scale of the figure.

[0249] Referring to all the drawings related to the second embodiment, a three-dimensional memory device is provided, the three-dimensional memory device comprising: alternating stacks of conductive strips 46 and insulating strips 32, the alternating stacks being located above a substrate (9, 10) and being laterally spaced apart from each other by memory stack assemblies 509, wherein the memory stack assemblies 509 extend laterally along a first horizontal direction hd1 and are spaced apart from each other along a second horizontal direction hd2, wherein: each of the memory stack assemblies 509 comprises two two-dimensional arrays of lateral protrusion areas 510; the lateral protrusion areas 510 Each of the two two-dimensional arrays includes a corresponding two-dimensional array of lateral protrusion areas 510, which protrude laterally outward from a corresponding vertical plane including an interface between the memory stack assembly 509 and a subset of the insulating strips 32; and each of the lateral protrusion areas 510 includes a corresponding charge storage element, which has a pair of concave inner wall segments and a pair of convex outer wall segments, the pair of concave inner wall segments have corresponding horizontal concave profiles in a horizontal cross-sectional view, and the pair of convex outer wall segments have corresponding horizontal convex profiles in a horizontal cross-sectional view.

[0250] In one embodiment, the pair of concave inner sidewall segments are connected to each other by a straight inner sidewall segment, and the pair of convex outer sidewall segments are connected to each other by a straight outer sidewall segment.

[0251] In one embodiment, each of the memory stack assemblies 509 includes two rows of charge storage material layers extending over the side walls of a corresponding one of the alternating stacks (32, 42); and each of the charge storage material layers 54L includes a corresponding vertical stack of charge storage elements, which is a portion of the corresponding charge storage material layer 54L located within a corresponding one of the two-dimensional array of lateral protrusion regions 510.

[0252] In one embodiment, each of the memory stack assemblies 509 includes two rows of vertical semiconductor channels 60; and each vertical semiconductor channel within the two rows of vertical semiconductor channels 60 laterally overlies a corresponding vertical stack of charge storage elements. In one embodiment, each of the memory stack assemblies 509 includes two tunneling dielectric layers 56; and each of the two tunneling dielectric layers 56 contacts the vertical semiconductor channels 60 of the corresponding row.

[0253] In one embodiment, each of the memory stack assemblies 509 includes a dielectric core 62 extending laterally along a first horizontal direction hd1 and contacting inner sidewalls of each vertical semiconductor channel 60 within two rows of vertical semiconductor channels 60 of the corresponding memory stack assembly 509 .

[0254] In one embodiment, the vertical semiconductor channels 60 within each row of vertical semiconductor channels 60 are laterally spaced apart along the first horizontal direction hd1 by vertically extending regions where the dielectric core 62 contacts the insulating strips 32 of one of the alternating stacks.

[0255] In one embodiment, each charge storage material layer 54L within the two rows of charge storage material layers 54L has: a first major surface contacting a corresponding vertical semiconductor channel 60; a second major surface contacting a corresponding blocking dielectric layer 52; and a pair of minor surfaces contacting a dielectric core 62. In one embodiment, the dielectric core 62 contacts the two rows of vertical semiconductor channels 60 of the corresponding memory stack assembly 509.

[0256] In one embodiment, each memory stack assembly in the memory stack assembly 509 includes two rows of material stack strips that extend vertically and laterally over the side walls of a corresponding one of the alternating stacks (32, 46); and each material stack strip in the two rows of material stack strips includes: a blocking dielectric layer 52 that contacts the insulating strip 32 within a corresponding one of the alternating stacks (32, 46); a charge storage material layer 54L or a floating gate that contacts the blocking dielectric layer 52; a tunneling dielectric layer 56 that contacts the charge storage material layer 54L or the floating gate; and a vertical semiconductor channel 60 that contacts the tunneling dielectric layer 56.

[0257] In one embodiment, each of the blocking dielectric layer 52, the charge storage material layer 54L, the tunneling dielectric layer 56, and the vertical semiconductor channel 60 contacts the dielectric core 62. In one embodiment, each of the blocking dielectric layer 52, the charge storage material layer 54L, the tunneling dielectric layer 56, and the vertical semiconductor channel 60 has a laterally undulating vertical cross-sectional profile, so that the sidewalls of the blocking dielectric layer 52, the charge storage material layer 54L, the tunneling dielectric layer 56, and the vertical semiconductor channel 60 include vertical straight segments at the level of the alternating stacks (32, 46) of insulating strips 32 and curved laterally protruding segments at the level of the alternating stacks (32, 46) of conductive strips 46.

[0258] The lateral recessed region with curvature provides a geometry with increased local electric field strength. The curvature in the memory film 50 enhances the electric field concentration during programming and erasing, thereby reducing the operating voltage of the three-dimensional memory device. The three-dimensional memory device of various embodiments can provide a lower programming voltage and a lower erase voltage by local enhancement of the electric field line density and thus by enhanced local electric field strength. The power consumption of the three-dimensional memory device can be reduced by using low voltage programming. The present invention discloses various embodiments of providing a lateral recessed region with curvature in multiple planes (such as an xy plane and a zx plane). By providing a lateral recessed region with curvature in multiple planes, the resulting structure can enhance control gate performance and provide an improved channel corner effect. In addition, the stacked layer can be minimized to reduce production costs.

[0259] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising: alternating stacks of conductive strips and air gap strips, the alternating stacks being located above the substrate and laterally spaced apart from each other by a memory stack assembly, wherein the memory stack assembly extends laterally in a first horizontal direction and is spaced apart from each other in a second horizontal direction, wherein: Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion areas; The lateral protrusion regions protrude laterally outward from respective vertical planes including interfaces between the memory stack assembly and a subset of the air gap stripes; Each of the lateral protrusion regions comprises a respective curved charge storage element; Each of the memory stack assemblies includes two rows of vertical semiconductor channels; and Each vertical semiconductor channel within the two rows of vertical semiconductor channels laterally overlies a corresponding vertical stack of charge storage elements.

2. The three-dimensional memory device according to claim 1, wherein: Each of the memory stack assemblies comprises two tunneling dielectric layers; and Each of the two tunneling dielectric layers contacts a corresponding row of vertical semiconductor channels selected from the two rows of vertical semiconductor channels.

3. The three-dimensional memory device of claim 2 , wherein each of the memory stack assemblies comprises a dielectric core extending laterally along the first horizontal direction and contacting an inner sidewall of each vertical semiconductor channel within the two rows of vertical semiconductor channels.

4. The three-dimensional memory device of claim 3 , wherein the vertical semiconductor channels within each row of vertical semiconductor channels are laterally spaced apart along the first horizontal direction by vertically extending regions in which the dielectric core contacts one of the two tunneling dielectric layers.

5. The three-dimensional memory device of claim 2, wherein each of the two tunneling dielectric layers contacts a two-dimensional array of charge storage elements located in a two-dimensional array of lateral protrusion regions. 6 . The three-dimensional memory device of claim 2 , wherein each vertical semiconductor channel within the two rows of vertical semiconductor channels comprises a vertical stack of lateral bump portions at the level of the conductive strips.

7. The three-dimensional memory device according to claim 2, wherein: Each of the memory stack assemblies comprises two blocking dielectric layers; and Each of the two blocking dielectric layers contacts a respective one of the two tunneling dielectric layers at each level of the air gap strips and between each adjacent pair of vertical stacks of charge storage elements.

8. The three-dimensional memory device according to claim 7, wherein: Each of the conductive strips includes a respective metal barrier layer and a respective portion of a metal fill material formed within the respective metal barrier layer; and Each of the two blocking dielectric layers contacts a sidewall of a subset of the metal barrier layers.

9. The three-dimensional memory device of claim 1, wherein the charge storage element comprises discrete floating gate or dielectric charge trapping material portions that are not in direct contact with each other.

10. The three-dimensional memory device of claim 9, wherein each of the charge storage elements comprises: a concave inner sidewall having a horizontal concave profile in a horizontal cross-sectional view; and A convex outer side wall has a horizontal convex profile in the horizontal cross-sectional view.

11. The three-dimensional memory device according to claim 10, wherein: In a vertical cross-sectional view, the concave inner sidewall has a vertical concave profile at an upper edge region and a lower edge region of the corresponding charge storage element; and In the vertical cross-sectional view, the convex outer sidewall has a vertical convex profile at the upper edge region and at the lower edge region of the corresponding charge storage element.

12. The three-dimensional memory device of claim 9 , wherein each of the charge storage elements is located between a first horizontal plane including a top surface of a corresponding one of the conductive strips and a second horizontal plane including a bottom surface of the corresponding one of the conductive strips.

13. A method of forming a three-dimensional memory device, comprising: forming an alternating stack of first and second sacrificial material strips over a substrate, wherein the alternating stacks are laterally spaced apart from one another by line trenches extending laterally in a first horizontal direction; modifying the line trench to provide a two-dimensional array of transverse recesses on each sidewall of the line trench, wherein each two-dimensional array of transverse recesses is laterally bounded by a corresponding two-dimensional array of transverse recessed surfaces of the second sacrificial material strip; forming a memory stack assembly in each volume, each volume comprising a combination of a volume of linear trenches and a volume of two contiguous two-dimensional arrays of lateral recesses, wherein each of the memory stack assemblies comprises two two-dimensional arrays of lateral protrusion areas, and each of the lateral protrusion areas comprises a respective charge storage element; replacing a remaining portion of the second strip of sacrificial material with a conductive strip; as well as An air gap strip is formed by removing the first sacrificial material strip.

14. The method according to claim 13, further comprising: forming diffusion barrier strips extending vertically and laterally on each sidewall of the line trench at intervals from each other; oxidizing a surface portion of the second strip of sacrificial material at a faster rate than a surface portion of the first strip of sacrificial material; as well as The diffusion barrier strip, the oxidized portion of the second strip of sacrificial material, and the oxidized portion of the first strip of sacrificial material are removed, wherein a two-dimensional array of the laterally recessed surfaces of the second strip of sacrificial material is provided.

15. The method according to claim 14, wherein: The diffusion barrier strips include silicon nitride; The first strip of sacrificial material comprises silicon; and The second strip of sacrificial material includes a silicon-germanium alloy including a higher atomic concentration of germanium than the first strip of sacrificial material.

16. The method according to claim 15, further comprising: forming a diffusion barrier layer on each sidewall of the linear trench; After forming the diffusion barrier layer, forming a two-dimensional array of pillars of mask material within the linear trenches; as well as Physically exposed portions of the diffusion barrier layer not masked by the two-dimensional array of pillars of mask material are isotropically etched, wherein remaining portions of the diffusion barrier layer constitute the diffusion barrier strips.

17. The method according to claim 13, further comprising: After forming the two-dimensional array of lateral recesses, depositing a layer of charge storage material over the remainder of the alternating strips; as well as An anisotropic etching process is used to remove portions of the layer of charge storage material outside the two-dimensional array of lateral recesses, wherein the remaining portions of the layer of charge storage material within the two-dimensional array of lateral recesses constitute the charge storage element.

18. The method according to claim 17, further comprising: forming a tunneling dielectric layer over each set of charge storage elements within a corresponding two-dimensional array of lateral recesses; as well as A row of vertical semiconductor channels is formed above each tunneling dielectric layer.

19. The method of claim 18, wherein: Each of the memory stack assemblies includes two rows of vertical semiconductor channels; and Each vertical semiconductor channel within the two rows of vertical semiconductor channels laterally overlies a corresponding vertical stack of charge storage elements. 20 . The method of claim 19 , further comprising forming a dielectric core in each remaining volume of the line trenches after forming the vertical semiconductor channels, wherein each dielectric core contacts two rows of vertical semiconductor channels and two tunneling dielectric layers.

21. A three-dimensional memory device, comprising: an alternating stack of conductive strips and insulating strips, the alternating stacks being located above the substrate and laterally spaced apart from each other by a memory stack assembly, wherein the memory stack assembly extends laterally in a first horizontal direction and is spaced apart from each other in a second horizontal direction, wherein: Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion areas; each lateral projection region projects laterally outwardly from a respective vertical plane including an interface between an insulating strip within a respective one of the memory stack assemblies and a respective one of the alternating stacks; and Each of the lateral protrusion areas includes a corresponding charge storage element, and the corresponding charge storage element has a pair of concave inner wall segments and a pair of convex outer wall segments, the pair of concave inner wall segments have corresponding horizontal concave profiles in the horizontal cross-sectional view, and the pair of convex outer wall segments have corresponding horizontal convex profiles in the horizontal cross-sectional view.

22. The three-dimensional memory device according to claim 21, wherein: The pair of concave inner side wall segments are connected to each other by a straight inner side wall segment; and The pair of convex outer side wall segments are connected to each other by a straight outer side wall segment.

23. The three-dimensional memory device of claim 21, wherein: Each of the memory stack assemblies includes two rows of charge storage material layers extending over a sidewall of a respective one of the alternating stacks; and Each of the charge storage material layers comprises a respective vertical stack of charge storage elements, the respective vertical stack being a portion of the respective charge storage material layer located within a respective one of the two-dimensional arrays of lateral protruding regions.

24. The three-dimensional memory device according to claim 23, wherein: Each of the memory stack assemblies includes two rows of vertical semiconductor channels; and Each vertical semiconductor channel within the two rows of vertical semiconductor channels laterally overlies a corresponding vertical stack of charge storage elements.

25. The three-dimensional memory device of claim 24, wherein: Each of the memory stack assemblies comprises two tunneling dielectric layers; and Each of the two tunneling dielectric layers contacts a corresponding row of vertical semiconductor channels.

26. The three-dimensional memory device of claim 24, wherein each of the memory stack assemblies comprises a dielectric core extending laterally along the first horizontal direction and contacting an inner sidewall of each vertical semiconductor channel within two rows of vertical semiconductor channels of the corresponding memory stack assembly.

27. The three-dimensional memory device of claim 24, wherein the vertical semiconductor channels within each row of vertical semiconductor channels are laterally spaced apart along the first horizontal direction by vertically extending regions in which the dielectric core contacts the insulating strips of one of the alternating stacks.

28. The three-dimensional memory device of claim 23, wherein each charge storage material layer within the two rows of charge storage material layers has: a first major surface, the first major surface contacting a corresponding vertical semiconductor channel; a second major surface, the second major surface contacting a corresponding blocking dielectric layer; and A pair of sub-surfaces contact the dielectric core.

29. The three-dimensional memory device of claim 28, wherein the dielectric core contacts two rows of vertical semiconductor channels of a corresponding memory stack assembly.

30. The three-dimensional memory device of claim 21, wherein: Each of the memory stack assemblies comprises two rows of material stack strips extending vertically and laterally overlying sidewalls of a respective one of the alternating stacks; and Each of the two rows of stacked strips of material comprises: a blocking dielectric layer contacting the insulating strips within the corresponding one of the alternating stacks; a charge storage material layer or a floating gate, wherein the charge storage material layer or the floating gate contacts the blocking dielectric layer; a tunneling dielectric layer, the tunneling dielectric layer contacting the charge storage material layer; and A vertical semiconductor channel contacts the tunneling dielectric layer.

31. The three-dimensional memory device of claim 30, wherein each of the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer, and the vertical semiconductor channel contacts a dielectric core.

32. A three-dimensional memory device according to claim 31, wherein each of the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer and the vertical semiconductor channel has a laterally undulating vertical cross-sectional profile, so that the sidewalls of the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer and the vertical semiconductor channel include vertical straight segments at the level of the alternatingly stacked insulating strips and curved laterally protruding segments at the level of the alternatingly stacked conductive strips.

33. A method of forming a three-dimensional memory device, comprising: forming an alternating stack of insulating strips and sacrificial material strips over a substrate, wherein the alternating stacks are laterally spaced apart from one another by linear trenches extending laterally in a first horizontal direction; selectively to the insulating strip, laterally etching a surface portion of the strip of sacrificial material exposed in the wire trench to provide a two-dimensional array of lateral recesses on each sidewall of the wire trench, wherein each two-dimensional array of lateral recesses is laterally bounded by a corresponding two-dimensional array of lateral recessed surfaces of the strip of sacrificial material; forming a memory stack assembly in each volume, each volume comprising a combination of a volume of the linear trenches and a volume of two adjacent two-dimensional arrays of lateral recesses, wherein each of the memory stack assemblies comprises two rows of material stack strips extending vertically and laterally overlying a sidewall of a corresponding one of the alternating stacks, and each row of material stack strips comprises a respective plurality of material stack strips laterally spaced apart along the first horizontal direction, and each of the material stack strips comprises a respective charge storage material layer comprising a charge storage element within a respective vertical stack of lateral recesses selected from the two-dimensional array of lateral recesses; as well as The strip of sacrificial material is replaced with a conductive strip.

34. The method of claim 33, wherein each of the material stack strips comprises: a blocking dielectric layer contacting the insulating strips within the corresponding one of the alternating stacks; a layer of charge storage material contacting the blocking dielectric layer and comprising a vertical stack of charge storage elements; a tunneling dielectric layer, the tunneling dielectric layer contacting the charge storage material layer; and A vertical semiconductor channel contacts the tunneling dielectric layer.

35. The method of claim 34, further comprising forming a dielectric core in the unfilled volume of the line trench after forming the material stack strip, wherein each of the memory stack assemblies includes a respective one of the dielectric cores.

36. A method according to claim 35, wherein the dielectric core is directly formed on the physically exposed sidewall surfaces of the insulating strips and the sacrificial material strips located outside the two-dimensional array of the lateral recesses, wherein the dielectric core contacts the sub-surfaces of the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer and the vertical semiconductor channel.

37. The method of claim 34, further comprising: After forming the two-dimensional array of lateral recesses, forming a continuous layer stack of blocking dielectric layers, charge storage material layers, and tunneling dielectric layers over the alternatingly stacked physically exposed surfaces; as well as The continuous layer stack is anisotropically etched, wherein the semiconductor surface of the substrate is physically exposed at the bottom of each of the line-trench lines.

38. The method of claim 37, further comprising: After anisotropically etching the continuous layer stack, forming a semiconductor channel material layer over a remaining vertical portion of the continuous layer stack; After forming the semiconductor channel material layer, forming a two-dimensional array of pillars of mask material within the unfilled volume of the linear trench; as well as Portions of the continuous layer stack not masked by the pillars of mask material are isotropically etched, wherein the continuous layer stack and remaining portions of the semiconductor channel material layer constitute the material stack stripes.

39. The method of claim 33, further comprising: forming a two-dimensional array of pillars of mask material in the linear trenches; Wherein the step of laterally etching a surface portion of the strip of sacrificial material occurs while the two-dimensional array of pillars of masking material is present within the linear trenches, wherein the two-dimensional array of lateral recesses is formed.

40. The method of claim 33, further comprising: forming a backside via cavity after forming the memory stack assembly such that sidewalls of the insulating strip and the sacrificial material strip are physically exposed to the backside via cavity; forming a backside recess by selectively removing the sacrificial material strip with respect to the insulating strip; and At least one conductive material is deposited in the backside recess to form the conductive strip.

41. The method of claim 33, wherein laterally etching a surface portion of the strip of sacrificial material comprises performing an isotropic etching process that etches the material of the strip of sacrificial material selective to the material of the insulating strip.

42. The method of claim 41 further comprises forming a two-dimensional array of first mask material pillars within the line grooves prior to performing the isotropic etching process, wherein the isotropic etching process is performed while the two-dimensional array of first mask material pillars are present within the line grooves.

43. The method of claim 42, further comprising removing the two-dimensional array of first mask material pillars prior to forming the stack assembly.

44. The method of claim 33, wherein: The linear groove is formed with straight sidewalls parallel to the first horizontal direction; and The sidewalls of the two-dimensional array of lateral recesses comprise straight segments parallel to the first horizontal direction in a horizontal cross-sectional view at the level of one of the sacrificial material layers.

45. The method of claim 35, further comprising: forming a backside through-hole cavity through a portion of the dielectric core; forming a backside recess by introducing an etchant that selectively etches a sacrificial material layer selective to the insulating layer into the backside via cavity; as well as A conductive layer is formed by depositing at least one conductive material in the backside recess.

46. ​​The method of claim 45, wherein an interface between the conductive layer and the memory stack assembly comprises a straight segment parallel to the first horizontal direction in a horizontal cross-sectional view.

47. The method of claim 45, wherein in forming the backside via cavity, sidewalls of the insulating layer, sidewalls of the sacrificial material layer, and sidewalls of the dielectric core are physically exposed to the backside via cavity.

48. The method of claim 45, further comprising forming a dielectric post in the backside via cavity, wherein the dielectric post contacts a sidewall of the conductive layer and a sidewall of the dielectric core.

49. The method of claim 33, wherein each of the memory stack components comprises a respective layer stack of a blocking dielectric layer, a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel.

50. The method of claim 49, wherein each of the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer, and the vertical semiconductor channel has a laterally undulating vertical cross-sectional profile in a vertical cross-sectional view.

51. A method according to claim 49, wherein the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer and the sidewalls of the vertical semiconductor channel within each memory stack assembly include vertical straight segments at the level of the insulating strips and curved lateral protrusion segments at the level of the conductive strips.

52. The method of claim 51, wherein: The curved lateral protrusion sections of the blocking dielectric layer adjoin the vertical straight sections of the blocking dielectric layer via horizontal extensions of the vertical straight sections contacting the horizontal surface of the insulating layer.

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