Photoelectric conversion element, solid-state imaging device, and electronic device

Abstract

The present invention provides a photoelectric conversion element that occupies a smaller area and has adjustable conversion efficiency and dynamic range. The photoelectric conversion element according to the present invention is provided with: a photoelectric conversion unit that converts a light signal into a signal charge; a transmission gate structure that is connected to the photoelectric conversion unit and transmits the signal charge; a charge storage region to which the signal charge is transmitted by the transmission gate structure; a charge retention unit that is electrically connected to the charge storage region and has a capacitor structure for storing the signal charge; and an amplifier transistor that has a control electrode electrically connected to the charge storage region. The photoelectric conversion unit, the transmission gate structure, and the charge storage region are provided on a first substrate, and the amplifier transistor is provided on a second substrate; and the first substrate and the second substrate are stacked on each other.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion element, a solid-state imaging device, and an electronic device, and particularly relates to a back-illuminated photoelectric conversion element using CMOS, a solid-state imaging device in which the photoelectric conversion elements are arranged as pixels, and an electronic device using the solid-state imaging device. Background Art

[0002] A CMOS image sensor (CIS), a solid-state imaging device, consists of a pixel array in which a plurality of pixels are arranged and a logic circuit arranged on the periphery of the pixel array and performing signal processing. Each pixel constituting the pixel array includes a light receiving unit made of a photodiode (PD) and an active element such as an amplifier transistor (hereinafter referred to as a "pixel transistor") arranged adjacent to the PD in the pixel. As the unit size decreases, individual functional units such as pixel arrays and logic circuits are being miniaturized. The so-called miniaturization of semiconductor devices enables pixel transistors, logic circuits, etc. to be reduced to a certain extent.

[0003] However, for the light receiving unit, the miniaturization of the area (or volume) used to capture light has greatly impaired the characteristics of the solid-state imaging device. From this perspective, the miniaturization of the pixel size in the pixel array is promoted in the following manner: while reducing the pixel transistors arranged in the pixels, etc., the PD size is ensured to be as large as possible. Other functional elements that are difficult to miniaturize as the PD include the amplifying transistors arranged in the pixels. For the amplifying transistors, similarly, there is a trade-off between size miniaturization and noise reduction. As described above, the miniaturization of the pixel size poses a major obstacle to the two-dimensional arrangement of the various functional units.

[0004] To address this issue, a stacked structure has recently been proposed, in which a semiconductor substrate having integrated PDs, pixel transistors, and the like, and a semiconductor substrate having integrated logic circuits are separated and stacked (see Patent Document 1). In Patent Document 1, a back-illuminated solid-state imaging device is constructed by bonding a semiconductor substrate having pixel regions and a semiconductor substrate having logic circuits to each other.

[0005] By stacking semiconductor substrates in this manner, functional units to be formed in the semiconductor region of the semiconductor substrate can be formed in an area approximately twice as large as a conventional area. The expansion of the semiconductor region increases the area for mounting other functions.

[0006] Effective utilization of semiconductor areas contributes to the expanded application of solid-state imaging devices and promotes the advancement of key technologies for advanced technologies related to solid-state imaging devices.

[0007] List of citations

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Publication No. 2010-245506 Summary of the Invention

[0010] Technical problem to be solved by the invention

[0011] The present invention has been made in order to solve such problems existing in conventional technologies, and an object of the present invention is to provide a photoelectric conversion element that can reduce the occupied area and can adjust the conversion efficiency and dynamic range, a high-resolution solid-state imaging device in which the photoelectric conversion elements are arranged as pixels and the area resources of the semiconductor substrate are effectively utilized, and an electronic device using the solid-state imaging device.

[0012] Solutions to technical problems

[0013] A first aspect of the present invention is a photoelectric conversion element, comprising: a photoelectric conversion unit for converting a light signal into a signal charge; a transfer gate structure connected to the photoelectric conversion unit and for transferring the signal charge; a charge storage region to which the signal charge is transferred by the transfer gate structure; a charge retention unit electrically connected to the charge storage region and for storing the signal charge; and an amplifier transistor, wherein the control electrode of the amplifier transistor is electrically connected to the charge storage region, wherein the photoelectric conversion unit, the transfer gate structure and the charge storage region are arranged on a first substrate, the amplifier transistor is arranged on a second substrate, and the first substrate and the second substrate are stacked.

[0014] A second aspect of the present invention is a solid-state imaging device, in which a plurality of pixels are arranged, each pixel including: a photoelectric conversion unit for converting a light signal into a signal charge; a transfer gate structure connected to the photoelectric conversion unit and for transferring the signal charge; a charge storage region to which the signal charge is transferred by the transfer gate structure; a charge retention unit electrically connected to the charge storage region and for storing the signal charge; and an amplifier transistor, a control electrode of the amplifier transistor electrically connected to the charge storage region, wherein the photoelectric conversion unit, the transfer gate structure and the charge storage region are arranged on a first substrate, the amplifier transistor is arranged on a second substrate, and the first substrate and the second substrate are stacked.

[0015] The third aspect of the present invention is an electronic device including a solid-state imaging device, wherein the solid-state imaging device is arranged with a plurality of pixels, each pixel including: a photoelectric conversion unit for converting a light signal into a signal charge; a transfer gate structure connected to the photoelectric conversion unit and for transferring the signal charge; a charge storage area, to which the signal charge is transferred by the transfer gate structure; a charge retention unit electrically connected to the charge storage area and for storing the signal charge; and an amplifying transistor, the control electrode of the amplifying transistor being electrically connected to the charge storage area, wherein the photoelectric conversion unit, the transfer gate structure and the charge storage area are arranged on a first substrate, the amplifying transistor is arranged on a second substrate, and the first substrate and the second substrate are stacked. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] [ Figure 1 ]

[0017] Figure 1 It is a schematic diagram for explaining the configuration of a CMOS image sensor as a solid-state imaging element to which the present invention is applied.

[0018] [ Figure 2 ]

[0019] Figure 2 is a diagram showing an example of an equivalent circuit of a pixel of the solid-state imaging device according to the first embodiment of the present invention.

[0020] [ Figure 3A ]

[0021] Figure 3A is a schematic cross-sectional view showing an example of the solid-state imaging device according to the first embodiment of the present invention.

[0022] [ Figure 3B ]

[0023] Figure 3B is a schematic cross-sectional view showing another example of the charge holding unit used in the solid-state imaging device according to the first embodiment of the present invention.

[0024] [ Figure 3C ]

[0025] Figure 3C : is a schematic cross-sectional view showing an example of connection electrode wiring used in the solid-state imaging device according to the first embodiment of the present invention.

[0026] [ Figure 4 ]

[0027] Figure 4Schematic cross-sectional views for explaining an example of steps of a method of manufacturing the solid-state imaging device according to the first embodiment of the present invention.

[0028] [ Figure 5 ]

[0029] Figure 5 is an example for explaining the steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. Figure 4 Schematic cross-sectional view of the subsequent part.

[0030] [ Figure 6 ]

[0031] Figure 6 is an example for explaining the steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. Figure 5 Schematic cross-sectional view of the subsequent part.

[0032] [ Figure 7 ]

[0033] Figure 7 is an example for explaining the steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. Figure 6 Schematic cross-sectional view of the subsequent part.

[0034] [ Figure 8 ]

[0035] Figure 8 is an example for explaining the steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. Figure 7 Schematic cross-sectional view of the subsequent part.

[0036] [ Figure 9 ]

[0037] Figure 9 is an example for explaining the steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. Figure 8 Schematic cross-sectional view of the subsequent part.

[0038] [ Figure 10A ]

[0039] Figure 10A is an example for explaining the steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. Figure 9 Schematic cross-sectional view of the subsequent part.

[0040] [ Figure 10B ]

[0041] Figure 10Bis another example for explaining the steps of the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention. Figure 9 Schematic cross-sectional view of the subsequent part.

[0042] [ Figure 11 ]

[0043] Figure 11 is a schematic cross-sectional view showing another example of the solid-state imaging device according to the first embodiment of the present invention.

[0044] [ Figure 12 ]

[0045] Figure 12 is a schematic cross-sectional view showing another example of the solid-state imaging device according to the first embodiment of the present invention.

[0046] [ Figure 13 ]

[0047] Figure 13 is a schematic cross-sectional view showing another example of the solid-state imaging device according to the first embodiment of the present invention.

[0048] [ Figure 14 ]

[0049] Figure 14 : is a schematic cross-sectional view showing an example corresponding to 2 pixels shared by 2×2 pixels of the solid-state imaging device according to the second modification example of the first embodiment of the present invention.

[0050] [ Figure 15 ]

[0051] Figure 15 It shows Figure 14 A diagram showing an example of an equivalent circuit of a pixel of a solid-state imaging device is shown.

[0052] [ Figure 16 ]

[0053] Figure 16 It shows Figure 14 A diagram showing an example of a layout of pixels of a solid-state imaging device.

[0054] [ Figure 17 ]

[0055] Figure 17 It shows Figure 14 A diagram showing an example of a layout of pixel transistors of a solid-state imaging device.

[0056] [ Figure 18 ]

[0057] Figure 18 It shows Figure 16 and Figure 17 Figure 1. Overlay of the layout shown.

[0058] [ Figure 19 ]

[0059] Figure 19 It shows that when using Figure 12 The structure of the solid-state imaging device shown is a diagram showing an example of the layout of pixels corresponding to two pixels when a charge accumulation region is shared in a 2×2 pixel sharing manner.

[0060] [ Figure 20 ]

[0061] Figure 20 Is shown when using Figure 12 The structure of the solid-state imaging device shown is a diagram showing an example of the layout of pixel transistors corresponding to two pixels when a charge storage region is shared in a 2×2 pixel sharing manner.

[0062] [ Figure 21 ]

[0063] Figure 21 It shows Figure 19 and Figure 20 Figure 1. Overlay of the layout shown.

[0064] [ Figure 22 ]

[0065] Figure 22 is a schematic cross-sectional view showing an example of a solid-state imaging device according to a second embodiment of the present invention.

[0066] [ Figure 23 ]

[0067] Figure 23 is a schematic cross-sectional view showing another example of the solid-state imaging device according to the second embodiment of the present invention.

[0068] [ Figure 24 ]

[0069] Figure 24 Is used to illustrate Figure 23 Schematic cross-sectional views showing examples of steps of a method for manufacturing a solid-state imaging device.

[0070] [ Figure 25 ]

[0071] Figure 25 Is used to illustrate Figure 23 An example of the steps of the method for manufacturing a solid-state imaging device is shown as follows Figure 24 Schematic cross-sectional view of the subsequent part.

[0072] [ Figure 26 ]

[0073] Figure 26 Is used to illustrate Figure 23 An example of the steps of the method for manufacturing a solid-state imaging device is shown as follows Figure 25 Schematic cross-sectional view of the subsequent part.

[0074] [ Figure 27 ]

[0075] Figure 27 is a diagram showing an example of an equivalent circuit of a pixel of a solid-state imaging device according to a second embodiment of the present invention.

[0076] [ Figure 28 ]

[0077] Figure 28 is a schematic cross-sectional view showing an example of a solid-state imaging device according to a first modification example of the second embodiment of the present invention.

[0078] [ Figure 29 ]

[0079] Figure 29 is a schematic cross-sectional view showing an example of a solid-state imaging device according to a second modification of the second embodiment of the present invention.

[0080] [ Figure 30 ]

[0081] Figure 30 is a diagram showing an example of an equivalent circuit of a pixel of a solid-state imaging device according to a second modification example of the second embodiment of the present invention.

[0082] [ Figure 31 ]

[0083] Figure 31 : is a diagram showing an example of the layout of pixels of a solid-state imaging device according to a second modification example of the second embodiment of the present invention.

[0084] [ Figure 32 ]

[0085] Figure 32 Schematic configuration diagrams showing examples of electronic equipment using the solid-state imaging devices according to the first and second embodiments of the present invention. DETAILED DESCRIPTION

[0086] In the description of the drawings used to illustrate the first embodiment and the second embodiment of the present invention, the same or similar parts are represented by the same or similar reference numerals and repeated descriptions will be omitted. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plan view size, the thickness ratio of each layer, etc. may be different from the actual ones. In addition, the drawings may include parts with different dimensional relationships and proportions from those in the drawings. In addition, the embodiments given below only provide examples of devices and methods for realizing the technical ideas of the present invention. Therefore, the technical ideas of the present invention are not intended to limit the materials, shapes, arrangements, etc. of the components to the examples described below.

[0087] In addition, it should be understood that in the following description of the first and second embodiments, the definitions of directions such as up and down relative to the photoelectric conversion substrate are selected only for the purpose of simplicity and are not intended to limit the technical ideas of the present invention. For example, it is obvious that when an object is rotated 90 degrees and then observed, up and down are converted into and understood as left and right, and when the object is rotated 180 degrees and then observed, up and down are understood to be inverted. In addition, the following will exemplify the case where the first conductivity type is p-type and the second conductivity type is n-type. However, the conductivity type can be selected in an opposite relationship so that n-type is adopted as the first conductivity type and p-type is adopted as the second conductivity type. In addition, + and - added to p and n respectively represent semiconductor regions with higher or lower impurity densities relative to semiconductor regions to which + and - are not added. However, the fact that p is added to semiconductor regions in a similar manner does not mean that the impurity densities of the semiconductor regions are exactly the same.

[0088] (First embodiment)

[0089] <Configuration of Solid-State Imaging Device>

[0090] like Figure 1 As shown, the solid-state imaging device includes a pixel array unit 91 and a drive unit 93 that drives the pixel array unit 91. The drive unit 93 includes a column processing unit 94, a horizontal drive unit 95, and a vertical drive unit 97. The operation of the drive unit 93 is controlled by a control circuit (not shown). The pixel array unit 91, the column processing unit 94, the horizontal drive unit 95, and the vertical drive unit 97 are formed on a semiconductor substrate (not shown). The solid-state imaging device also includes a signal processing unit 99.

[0091] The pixel array unit 91 is formed by arranging pixels 92 in a matrix pattern. The pixels 92 include a photoelectric conversion unit and a floating diffusion region (charge storage region) to which the photoelectrically converted charge is transferred. Each pixel 92 is connected to a vertical drive unit 97 in units of rows via a control line 98. In addition, each pixel 92 is connected to a column processing unit 94 in units of columns via a vertical signal line (VSL) 96.

[0092] Light collected by an optical system (not shown) enters the pixel array unit 91. The pixels 92 output pixel signals having a level corresponding to the light intensity of the received light. The pixel signals constitute an image of the subject.

[0093] Pixel 92 includes a photoelectric conversion unit made of a photodiode (PD) or the like, a floating diffusion region (charge storage region) to which charge from the photoelectric conversion unit is transferred, and a pixel transistor for driving the pixel. For example, a configuration can be employed in which these components are formed within a p-type well provided in an n-type semiconductor substrate. In the present invention, transfer transistors, amplifier transistors, reset transistors, select transistors, and the like are defined as pixel transistors.

[0094] In the pixel array unit 91, a control line 98 is formed corresponding to each pixel row. The vertical driving unit 97 provides a driving signal for sequentially driving the pixels 92 in each row to the pixels 92 of the pixel array unit 91 via the control line 98. For the convenience of explanation, Figure 1 One control line 98 is shown for each pixel row. In practice, a plurality of control lines are arranged corresponding to a single pixel row.

[0095] Furthermore, in the pixel array unit 91, a VSL 96 is formed corresponding to each pixel column. The signal (signal level or reset level) output from the pixel 92 is sent to the column processing unit 94 via the VSL 96. The column processing unit 94 applies double data sampling (DDS) based on the signal output from the pixel 92, and then performs A / D conversion. The column processing unit 94 can be configured to perform DDS processing in parallel in units of pixel rows.

[0096] The column processing unit 94 is operated by a drive signal from the horizontal driving unit 95. The horizontal driving unit 95 includes a logic circuit such as a shift register or an address decoder. The pixel signal from the column processing unit 94 is sequentially output to the signal processing unit 99 for each of the plurality of pixel columns arranged in the pixel array unit 91.

[0097] For example, the signal processing unit 99 performs various signal processing on the pixel signals from the column processing unit 94 and outputs the processed pixel signals as image output. For example, the signal processing unit 99 may be integrally formed in the semiconductor substrate on which the pixel array unit 91 is formed, or may be provided on a separate substrate. Alternatively, the signal processing unit 99 may perform processing using a DSP or software.

[0098] The vertical drive unit 97 includes a logic circuit such as a shift register or an address decoder, and drives the respective pixels 92 of the pixel array unit 91 simultaneously or in row units. Specifically, the pixels 92 are driven so that resetting, exposure, and charge transfer of the pixels 92 are performed simultaneously for all pixels 92, but reading is performed in row units.

[0099] The so-called global exposure is performed by batch resetting and batch exposure. In addition, reading and scanning involve sequentially selecting and scanning the pixels 92 of the pixel array unit 91 in units of rows. In the present invention, global exposure is performed by the following steps: while the pixels 92 of the pixel array unit 91 are sequentially scanned in units of rows and all pixels are read, the photoelectric conversion units of all pixels are initialized, and then the signal charge is stored in the photoelectric conversion units at the same time in all pixels. The time period from the initialization of the photoelectric conversion unit and the new start of exposure to the execution of transfer is considered to be the exposure period (photoelectric charge storage period).

[0100] <Structure of Solid-State Imaging Device>

[0101] Figure 2 An example of an equivalent circuit of the pixel 92 of the solid-state imaging device according to the first embodiment is shown. Figure 2 As shown, the photoelectric conversion unit (PD) 10 having a grounded anode is connected to the charge retention unit 23 via the transfer gate structure 16 serving as a transfer transistor. The charge retention unit 23 is connected to the charge storage region (floating diffusion region) 15. The charge storage region 15 is connected to the source of the reset transistor 32c and the gate of the amplifier transistor 32a. The source of the amplifier transistor 32a is connected to the drain of the select transistor 32b. The source of the select transistor 32b is connected to the vertical signal line (VSL) 96. The drains of the amplifier transistor 32a and the reset transistor 32c are each connected to the power supply Vdd.

[0102] like Figure 3AAs shown, the solid-state imaging device according to the first embodiment includes a charge retention unit 23 having a capacitor structure on a first substrate 1. The charge retention unit 23 includes a MOS type capacitor. The charge retention unit 23 as a capacitive element has: a buried capacitor region 24 having a pn junction provided in a well region 11; a capacitor insulating film 230 provided on the upper surface of the buried capacitor region 24; and a capacitor electrode 231 provided on the upper surface of the capacitor insulating film 230. The buried capacitor region 24 has an n-type first buried region 24A provided on the lower surface of the capacitor insulating film 230 and a p-type first buried region 24A buried in the first buried region 24A. + The first buried region 24A, the second buried region 24B and the well region 11 constitute the main part of the capacitor. Figure 3A The equivalent circuit of the charge holding unit 23 shown in FIG is composed of Figure 2 , but the signal charge read by the transfer gate structure 16 passes through the semiconductor layer of the well region 11 and is temporarily held by the charge holding unit 23. The signal charge held by the charge holding unit 23 is guided from the charge holding unit 23 to the charge storage region 15. In addition, the signal charge is transmitted to the gate electrode 34 of the pixel transistor such as the amplifier transistor 32a of the second substrate 3 through the through-connection conductor (through via plug) 21. The charge holding unit 23 is provided with a capacitor electrode 231, and the capacitor electrode 231 is turned on and off at the required time so that the transmission time can be measured. Therefore, the signal charges held by the charge holding unit 23 in each pixel can be simultaneously and collectively transmitted to each charge storage region 15 so that the global shutter function can be realized.

[0103] In the first embodiment, by including a charge holding unit 23 having a function of storing signal charges, the amount of signal charges stored in the charge storage region 15 can be increased. Therefore, even in the case of very strong light incidence, the dynamic range can be expanded by using the charge holding unit 23 as an auxiliary storage region of the charge storage region 15. In addition, since the charges that may cause dark current and the excess signal charges stored in the charge holding unit 23 can be released via the reset transistor 32c, a global shutter function can be provided for the solid-state imaging device. Therefore, the skew (skewing) of the image observed in the rolling shutter adopted by the ordinary CMOS solid-state imaging device can be suppressed and image formation can be performed with high precision. With Figure 3A The structure of the charge holding unit 23 of the buried capacitor region 24, the capacitor insulating film 230, and the capacitor electrode 231 shown can have a variable capacitance capacitor according to the magnitude of the voltage to be applied to the capacitor electrode 231. For example, Figure 3BAs shown, p can be omitted + The n-type second buried region 24B is buried while only the n-type buried capacitor region 24 remains. Therefore, it is possible to operate in a mode in which the conversion efficiency of the charge storage region 15 to voltage is adjusted by changing the capacitance of the buried capacitor region 24. In addition, the charge retention unit 23 having an amplification function similar to that of a MOS transistor (more conventionally, an MIS transistor) is provided to achieve a mode in which the amount of signal charge to be transferred from the charge retention unit 23 to the charge storage region 15 is adjusted by the amount of voltage applied to the capacitor electrode 231. Although in Figure 3A A single pixel is shown in FIG, but a shared pixel may be used. In addition, a structure may be adopted in which the transfer gate structure of the solid-state imaging device according to the first embodiment is provided with the charge holding unit 23 and the vertical gate 17 is omitted.

[0104] In addition, if Figure 3A As shown, the solid-state imaging device according to the first embodiment has three stacked substrates: a first substrate 1, a second substrate 3 and a third substrate 5. The first substrate 1 is provided with a plurality of photoelectric conversion units 10 arranged in a matrix pattern, and generates signal charges by photoelectric conversion. The second substrate 3 integrates a pixel circuit that processes the signal charges from the photoelectric conversion unit 10 and outputs a pixel signal. The third substrate 5 integrates a logic circuit having functions such as image processing and signal processing, and processes pixel signals and outputs images. The first substrate 1 and the second substrate 3 are bonded to each other via an interlayer insulating film 20, and the second substrate 3 and the third substrate 5 are bonded to each other via an interlayer insulating film 57. The first substrate 1 is a substrate for receiving a signal from the back side ( Figure 3A The logic circuit can be provided on the third substrate at a position overlapping with the pixel area or in a peripheral area other than the pixel area. In addition, the logic circuit can be provided in the peripheral area other than the pixel area on the first substrate and the second substrate. Although the three substrates are described using serial numbers for convenience, the serial numbers do not limit the order of the substrates, and the substrates can be described in a different order when necessary.

[0105] In the composition Figure 3A A large number of photoelectric conversion units 10 constituting photodiodes (PDs) are arranged in a matrix pattern on the topmost first substrate 1. The photoelectric conversion units 10 constitute a major portion of the region defining each pixel of the solid-state imaging device. A semiconductor substrate such as a silicon (Si) wafer can be used as the semiconductor layer (first semiconductor layer) (11 and 12) of the first substrate 1. Figure 3A One of the photoelectric conversion units 10 arranged continuously is shown as a cross-sectional view of a portion of the first substrate 1. Figure 3AIn the illustrated arrangement, a planarization film 18 and an incident light unit 7 composed of a color filter (CF) 71, a microlens 72, and the like are provided above the photoelectric conversion unit 10. Incident light L incident sequentially via the microlens 72, the color filter 71, and the planarization film 18 is received by the photoelectric conversion unit 10 and subjected to photoelectric conversion.

[0106] exist Figure 3A In the structure shown, the photoelectric conversion unit 10 includes a pn junction formed using a well region 11 of a first conductivity type (p-type) and a charge generation region 12 of a second conductivity type (n-type) provided on top of the well region 11 and in contact with the well region 11. The photoelectric conversion unit 10 also includes a p-type charge generation region 12 provided on top of the charge generation region 12 and in contact with the charge generation region 12. + Type bottom pinning layer 13, and p-type bottom pinning layer 13 surrounding charge generation region 12 + The charge generation region 12 of the photoelectric conversion unit 10 functions as a portion of a PD that generates charge (electrons). In other words, the photoelectric conversion unit 10 has a hole accumulation diode (HAD (registered trademark)) structure and is capable of suppressing the generation of dark current at the interface with the bottom pinning layer 13 on the upper surface side of the charge generation region 12, at the interface with the side pinning layer 14 on the side surface side, and at the interface with the well region 11.

[0107] A pixel separation unit 19 that electrically separates a plurality of pixels arranged in a matrix pattern into individual pixels is provided inside the first substrate 1. The photoelectric conversion unit 10 is provided in each of a plurality of areas divided by the pixel separation unit 19. Figure 3A In the direction shown, when viewing the solid-state imaging device from the top side, the pixel separation unit 19 is formed, for example, in a grid pattern so as to be interposed between the plurality of pixels. The shape of the grid forming the pixel separation unit 19 is not limited to a rectangular grid, and other topological structures such as a hexagonal honeycomb grid may be employed instead. The photoelectric conversion units 10 constituting the pixels are arranged in the respective areas divided by the pixel separation unit 19 in a grid pattern.

[0108] Each pixel of the solid-state imaging device according to the first embodiment of the present invention further includes a T-type transfer gate structure 16 including a vertical gate 17 that transfers signal charges from the photoelectric conversion unit 10 of each pixel. Figure 3AIn the illustrated orientation, the transfer gate structure 16 includes a gate insulating film 160 in contact with the lower surface of the well region 11 and a planar gate electrode 161 in contact with the gate insulating film 160 from below. In the vertical gate 17, a gate insulating film 170 extending from the gate insulating film 160 is provided on the bottom and side surfaces of a trench that penetrates the well region 11 and reaches the charge generation region 12. A vertical gate electrode 171 is embedded to extend from the planar gate electrode 161 via the gate insulating film 170. An insulating film such as a silicon dioxide (SiO2) film is used as the gate insulating films 160 and 170. A conductor such as impurity-added polycrystalline (poly) silicon (p-Si) or a high-melting-point metal is used as the planar gate electrode 161 and the vertical gate electrode 171. On the lower surface side of the well region 11 in the lower portion of the photoelectric conversion unit 10, a charge storage region 15 for temporarily storing signal charge transferred from the photoelectric conversion unit 10 of each pixel is embedded in the lower portion of the well region 11 via the transfer gate structure 16. The charge storage region 15 includes a semiconductor region in an electrically floating state such as a floating diffusion region. In addition, an interlayer insulating film 20 is formed to cover a portion of the lower surface of the well region 11 , a portion of the lower surface of the charge storage region 15 , and the lower surface of the transfer gate structure 16 .

[0109] exist Figure 3A In the embodiment, a planarization film 18 in contact with the bottom pinning layer 13 is provided on top of the bottom pinning layer 13. Since the solid-state imaging device according to the present invention is a back-illuminated solid-state imaging device, the planarization film 18 is formed using an insulating material that transmits light, such as SiO2. The pixel separation unit 19 is provided by coating the inner side of the engraved pixel separation groove with an insulating film and burying a light-shielding metal such as tungsten (W) in the pixel separation groove via the insulating film. The pixel separation unit 19 can be formed by using a "fixed charge film" such as a hafnium oxide film (HfO2 film) as an insulating film for coating the inner side of the pixel separation groove and filling the pixel separation groove with the insulating film. When the pixel separation unit 19 is formed using a fixed charge film, the side pinning layer 14 that constitutes the side interface with the side surface of the charge generation region 12 of the photoelectric conversion unit 10 can be omitted.

[0110] A high dielectric having negative fixed charges is used to form the fixed charge film constituting the pixel separation unit 19, thereby forming a positive charge (hole) storage region and suppressing the generation of dark current at the interface portion with the charge generation region 12. The negative fixed charges distributed in the fixed charge film generate an electric field to be applied to the interface with the charge generation region 12 and form a positive charge (hole) storage region in the charge generation region 12. As the fixed charge film constituting the pixel separation unit 19, in addition to HfO2, an insulating film including at least one of oxides of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), magnesium (Mg), yttrium (Y), and lanthanide elements can also be used.

[0111] In the photoelectric conversion unit 10 of each pixel of the solid-state imaging device according to the first embodiment, the well region 11 constituting the anode of the PD is connected via p + The type well contact region 22 is grounded. In the solid-state imaging device, the signal charge (e.g., electron) generated by the photoelectric conversion unit 10 is stored in the charge storage region 15 via the transfer gate structure 16 and the like. The amplifier transistor 32a reads the stored signal charge as a charge from the charge storage region 15 in a floating state via the through-connection conductor (through-hole plug) 21, the wiring of the first wiring layer 38a, and the connection conductor (contact plug) 36, and outputs it to the Figure 1 or Figure 2 A vertical signal line (VSL) 96 is shown.

[0112] In the solid-state imaging device according to the first embodiment, the interlayer insulating film 20 is provided on the front surface ( Figure 3A The front surface is located on the opposite side of the rear surface (the upper surface in FIG. 3 ) where the incident unit 7 and the like are provided. The second substrate 3 including the pixel transistor is provided on the upper surface ( Figure 3A ), and the first substrate 1 and the second substrate 3 are bonded to each other via the interlayer insulating film 20.

[0113] For example, a semiconductor layer (second semiconductor layer) 31 of the second substrate 3 is provided with a Figure 2 The three pixel transistors of the pixel circuit (signal readout circuit) shown in FIG. 3 include an amplifier transistor (signal readout transistor) 32 a, a selection transistor (switching transistor) 32 b, and a reset transistor 32 c. Although all three pixel transistors are provided on the second substrate 3 in the first embodiment, this structure is not restrictive. For example, only the amplifier transistor 32 a may be provided on the second substrate 3, and one or both of the selection transistor 32 b and the reset transistor 32 c may be provided on the first substrate 1 or the third substrate 5.

[0114] like Figure 2As shown, the drain of the amplifier transistor 32a is connected to the power supply Vdd, and the source of the amplifier transistor 32a is connected to the drain of the selection transistor 32b for pixel selection. The gate of the amplifier transistor 32a is connected to the charge storage area 15 in a floating state, and the signal charge is read from the charge storage area 15. The drain of the reset transistor 32c is connected to the power supply Vdd, and the source of the reset transistor 32c is connected to the gate of the amplifier transistor 32a. By setting the reset control signal applied to the gate electrode of the reset transistor 32c to a high (H) level, the reset transistor 32c becomes conductive and resets the charge stored in the charge storage area 15. The source of the selection transistor 32b for pixel selection, which is another circuit element for reading the signal charge from the pixel storage area 15, is connected to the vertical signal line 96, and the gate electrode of the selection transistor 32b is supplied with a control signal for horizontal line selection from the vertical shift register. Setting the selection control signal to a high (H) level causes the selection transistor 32 b to become conductive, and a current corresponding to the potential of the charge storage region 15 that has been amplified by the signal read amplifier transistor 32 a flows through the vertical signal line 96 .

[0115] The interlayer insulating film 35 is provided to cover the front surface ( Figure 3A The lower surface of the interlayer insulating film 20 is exposed. The interlayer insulating film 37 is provided on the front surface of the interlayer insulating film 35. The interlayer insulating film 37 has a plurality of wiring layers including a first wiring layer 38a, a second wiring layer 38b, a third wiring layer 38c and a fourth wiring layer 38d. In other words, although the interlayer insulating film 37, the first wiring layer 38a, the second wiring layer 38b, the third wiring layer 38c and the fourth wiring layer 38d constitute a multilayer wiring layer, the multilayer wiring layer is not limited to Figure 3A The four-layer structure shown.

[0116] Although the details are not shown, in the interlayer insulating film 37, multiple wiring layers including a first wiring layer 38a, a second wiring layer 38b, a third wiring layer 38c and a fourth wiring layer 38d are electrically connected to each element of the pixel circuit formed in the second semiconductor layer 31 of the second substrate 3. Figure 3A Schematically shows the Figure 2 The cross-sectional structure of the amplifier transistor 32a in the signal readout circuit is shown, and the source region 33a and the drain region 33b of the amplifier transistor 32a are arranged so that they are separated from each other on the lower surface of the second semiconductor layer 31 of the second substrate 3. In addition, between the source region 33a and the drain region 33b, the gate electrode 34 is arranged on the lower surface of the second semiconductor layer 31 with a gate insulating film (not shown) interposed therebetween to constitute the amplifier transistor 32a. It should be noted that Figure 2 It is only a schematic diagram and Figure 3AThe positions of the source region 33a and the drain region 33b in the cross-sectional view of the embodiment can be interchanged. In addition, the end portion of the wiring of the first wiring layer 38a in contact with the interlayer insulating film 35 is electrically connected to the through-connection conductor (through-hole plug) 21, and the through-connection conductor (through-hole plug) 21 penetrates the interlayer insulating film 35 and the interlayer insulating film 20 to be electrically connected to the charge storage region 15. In addition, the other end of the wiring portion of the first wiring layer 38a (i.e., Figure 3A The portion exposed as a long horizontal wiring in the cross section shown is electrically connected to a connecting conductor (contact plug) 36, which passes through the interlayer insulating film 35 to be electrically connected to the gate electrode 34 of the amplifier transistor 32a. In a similar manner, another pixel transistor, a signal line such as VSL, a power supply line, a ground line, and the like are electrically connected to the wiring of the second wiring layer 38b, the wiring of the third wiring layer 38c, and the wiring of the fourth wiring layer 38d via a through-hole plug 39 or the like.

[0117] constitute Figure 3A The third substrate 5, the lowest layer of the three-layer stacked structure shown, is bonded to the front surface of the interlayer insulating film 37 of the second substrate 3 via the interlayer insulating film 57 ( Figure 3A The lower surface of the substrate). The third substrate 5 is provided with a semiconductor layer (third semiconductor layer) 51 made of Si semiconductor with a thickness of several hundred μm as a supporting substrate. The third semiconductor layer 51 is provided with a logic circuit transistor 52 composed of a plurality of logic transistors having a first main electrode region 53a, a second main electrode region 53b and a control electrode 54. In this case, the "first main electrode region" and the "second main electrode region" refer to semiconductor regions that become one of the source region and the drain region in a MOS field effect transistor (MOSFET) or a MOS electrostatic induction transistor (MOSSIT). Therefore, when the "first main electrode region" refers to the source region, the "second main electrode region" refers to the drain region. In addition, the "control electrode" refers to an electrode for controlling the main current flowing between the first main electrode region and the second main electrode region. For example, in the case of a MOSFET, the gate electrode for controlling the main current flowing between the source region and the drain region corresponds to the control electrode. An interlayer insulating film 55 is provided between the third semiconductor layer 51 and the interlayer insulating film 57 to cover the surface of the logic transistor and the third semiconductor layer 51. The first wiring layer 58a, the second wiring layer 58b, and the third wiring layer 58c are provided as multilayer wiring inside the interlayer insulating film 57. Figure 3ASchematically illustrating a multilayer wiring structure consisting of a three-layer structure, it is needless to say that the multilayer wiring structure used in the third substrate 5 is not limited to a three-layer structure. The control electrode 54 of the logic circuit transistor 52 and the contact plugs 56 in each of the first main electrode region 53a and the second main electrode region 53b are electrically connected to the wiring of the first wiring layer 58a through the interlayer insulating film 55. In addition, the logic circuit transistor 52, signal lines, power lines, ground lines, etc. are electrically connected to the wiring of the first wiring layer 58a, the wiring of the second wiring layer 58b, and the wiring of the third wiring layer 58c via the contact plugs 56 and the through-hole plugs 59.

[0118] although Figure 3A Although not shown, an opening is provided for a pad serving as an input / output electrode for connecting a signal line, a power line, a ground line, etc. to an external wiring. Metals such as Al that enable wiring bonding are ideal pads. The pads only need to be formed in any one wiring layer of the third substrate 5 and the second substrate 3. In addition, a chip scale package (CSP) structure can be used as an input / output electrode for external wiring. Figure 3C As shown, an insulating film 505 is provided on the lower surface of the third semiconductor layer 51. Wiring 506 provided on the lower surface of the insulating film 505 is electrically connected to any wiring layer of the second substrate 3 and the third substrate 5 (such as the second wiring layer 58b of the third substrate 5) via a through-hole plug 504. Bumps 507 such as solder are provided on the lower surface of the wiring 506. Signal lines, power lines, etc. can be connected to external wiring via the bumps 507.

[0119] <Method for Manufacturing Solid-State Imaging Device>

[0120] Next, refer to Figures 4 to 10A The process cross-sectional views shown here will explain the method for manufacturing a solid-state imaging device according to the first embodiment, focusing primarily on the structure corresponding to two pixels. It should be noted that the method for manufacturing a solid-state imaging device described below is merely an example, and that a solid-state imaging device can be implemented using various other manufacturing methods within the scope of the claims, including variations of the manufacturing method described below.

[0121] First, on the p-type substrate having a bottom pinning layer 13, +An n-type epitaxial growth layer that will become the n-type charge generation region 12 is grown on the semiconductor substrate of the n-type layer. Next, in order to form the pattern of the side pinning layer 14, a mask for selective ion implantation is formed by photolithography, and ion implantation of p-type impurity ions such as boron (B) is performed in multiple stages by adjusting the acceleration voltage to change the projection range, so that the charge generation region 12 remains in a portion of the n-type epitaxial growth layer. After removing the selective ion implantation mask for forming the side pinning layer 14, p-type impurities such as B are thermally diffused on the surface of the n-type epitaxial growth layer to form the well region 11. Due to the heat treatment when forming the well region 11, the ions implanted in multiple stages along the pattern of the side pinning layer 14 are also activated, and a well region 11 is formed. Figure 3A The side pinning layer 14 is shown.

[0122] Next, a thermal oxide film is formed on the upper surface of the well region 11. In addition, using a photolithography method, an etching mask for forming a pixel separation groove for forming the pixel separation unit 19 is formed by aligning the mask with the pattern of the side pinning layer 14. Using the etching mask, holes are selectively opened at specific positions of the thermal oxide film on the upper surface of the well region 11 by reactive ion etching (RIE) or the like to form an oxide film mask for forming the pixel separation groove for forming the pixel separation unit 19. After the oxide film mask is formed, the etching mask for forming the oxide film mask is removed. In addition, using the oxide film mask, a pixel separation groove is formed by dry etching such as RIE. After the pixel separation groove is dug out, a fixed charge film such as an HfO2 film is formed on the side wall of the pixel separation groove by chemical vapor deposition (CVD) or the like. Next, a pixel separation insulating film such as an SiO2 film is buried in the pixel separation groove in which the fixed charge film has been formed by CVD or the like. By planarizing and removing the fixed charge film and the pixel separation insulating film protruding from the pixel separation groove through etch-back, chemical mechanical polishing (CMP), etc., a pixel separation film is formed in the first semiconductor layer (11 and 12). Figure 3A Alternatively, the side pinning layer 14 may be formed after forming the pixel separation unit 19. For example, after epitaxially growing the charge generation region 12, the pixel separation groove may be formed first. The p-type impurity ions may be injected through the sidewalls of the pixel separation groove, and the p-type impurity ions may be formed using active thermal treatment. + Alternatively, a p-type side pinning layer 14 may be formed by depositing a Si layer to which p-type impurities have been added on the sidewalls of the pixel separation grooves and using solid phase diffusion of impurities. + Type side pinning layer 14.

[0123] Next, a mask for selective ion implantation having an opening in a region where the charge storage region 15 is to be formed is formed on the upper surface of the first semiconductor layer (11 and 12) by photolithography, and ions exhibiting n-type ions such as phosphorus (p) are implanted. By performing heat treatment after removing the photoresist film of the mask for n-type ion implantation, as shown in FIG. Figure 4 As shown, the charge storage region 15 is formed in the upper portion of the well region 11 on the upper surface side of the first semiconductor layer (11 and 12). + type extension region 116. In addition, a mask for selective ion implantation having an opening in the region where the first buried region 24A of the buried capacitor region 24 will be formed is formed by photolithography, and ions exhibiting n-type such as As are implanted in a projection range shallower than the extension region 116. After removing the photoresist film of the mask for n-type ion implantation, a mask for selective ion implantation having an opening in the region where the second buried region 24B of the buried capacitor region 24 and the well contact region 22 will be formed is formed by photolithography, and ions exhibiting n-type such as B are implanted in a projection range shallower than the extension region 116, so that the second buried region 24B becomes buried in the first buried region 24A. After removing the photoresist film of the mask for p-type ion implantation, by performing heat treatment, as Figure 4 As shown, a layer with n is formed on the upper portion of the well region 11. - Type first buried region 24A and p + The embedded capacitor region 24 and the p-type second embedded region 24B + Type well contact region 22.

[0124] Next, a vertical gate trench is dug between the embedded capacitor region 24 and the well contact region 22, penetrating the well region 11 and reaching the upper portion of the charge generation region 12, using photolithography and dry etching such as RIE. After the vertical gate trench is formed, the photoresist film used as an etching mask is removed and a thermal oxide film is formed to cover the upper surface of the well region 11 and the inner wall of the vertical gate trench. In addition, an impurity-added polysilicon (Si) film (DOPOS film) to which impurities have been added by CVD or the like is buried in the vertical gate trench and simultaneously deposited on the upper surface of the well region 11 to a thickness of 200 to 1000 nm. The DOPOS film is patterned by using photolithography and dry etching such as RIE, as shown in FIG. Figure 5As shown, a vertical gate 17 is formed inside the vertical gate trench, and at the same time, a pattern of a planar gate 16 and a charge retention unit 23 is formed on the upper surface of the well region 11. Although the formation of the vertical gate 17 has been described using a DOPOS film, the formation of the vertical gate 17 is not limited thereto. For example, after an impurity-free, non-doped polysilicon film is buried in the trench, impurities can be added by ion implantation or the like. Next, an interlayer insulating film 20 is formed on the upper surface of the well region 11 where the planar gate 16 and the charge retention unit 23 are formed by CVD or the like. In the first semiconductor layer (11 and 12) formed in this manner, an example of a gate electrode is polysilicon. When a functional element such as a pixel transistor is formed on a second substrate provided with a pixel circuit, since a heat treatment of nearly 1000°C is applied, a gate electrode material that can withstand such a temperature is required. For example, the gate electrode can be formed of a stack of a high melting point metal such as tungsten (W) or molybdenum (Mo) and polysilicon, or can be formed of only a high melting point metal. As Figure 5 As shown, the surface of the interlayer insulating film 20 is planarized by CMP or the like.

[0125] like Figure 6 As shown, the first semiconductor layer (11 and 12) and the semiconductor layer 31s composed of a silicon substrate are bonded via an interlayer insulating film 20 using a wafer direct bonding technique. Next, the semiconductor layer 31s is thinned from the upper surface of the semiconductor layer 31s to a desired thickness by grinding, polishing such as CMP, etching, etc. to form a second semiconductor layer 31. In this way, the second semiconductor layer 31 is given the film thickness required for the first main electrode region and the second main electrode region of the pixel transistor. The film thickness of the second semiconductor layer 31 varies depending on the concept of the pixel transistor. For example, when the film thickness of the first semiconductor layer (11 and 12) is approximately 1 μm to 10 μm, the film thickness of the second semiconductor layer 31 is in the range of several nm to several tens of μm, and more desirably, it is several tens of nm to several μm.

[0126] Figure 7 There are two types of pixel circuit separation regions: a deep pixel circuit separation region 351a that penetrates the second semiconductor layer 31 and a shallow pixel circuit separation region 351b that has a depth that does not penetrate the second semiconductor layer 31. Therefore, first, a pixel circuit separation region 351a is formed using photolithography. Figure 7The etching mask for forming the first pixel separation groove of the deep pixel circuit separation area 351a is shown. Using the etching mask, the first pixel separation groove is formed until it reaches the interlayer insulation 20 by dry etching such as RIE. The photoresist film used as the mask for forming the first pixel separation groove is removed and an etching mask for forming the second pixel separation groove of the shallow pixel circuit separation area 351b is formed. Using the etching mask, a shallow second pixel separation groove that does not reach the interlayer insulation film 20 is formed by dry etching such as RIE. Although the combined use of two types of element separation is described as a typical example, only shallow element separation or only deep element separation can be selectively used according to the application. After the first and second pixel separation grooves are dug out, an insulating film is buried in the first and second pixel separation grooves by CVD or the like. The insulating film protruding from the first and second pixel separation grooves is flattened and removed by etching back, CMP or the like. Figure 7 As shown, a pattern of a deep pixel circuit separation region 351a and a shallow pixel circuit separation region 351b is formed. The deep pixel circuit separation region 351a penetrating the second semiconductor layer 31 is formed so as to contact the underlying first semiconductor layer (11, 12).

[0127] The DOPOS film is patterned by using photolithography and dry etching such as RIE, as shown in Figure 7 As shown, patterns are formed for the gate electrodes 34 of pixel transistors such as the amplifier transistor, reset transistor, and select transistor. Next, using the opening pattern created by photolithography and the ends of the gate electrodes 34 as self-aligned masks, n-type impurity ions are implanted to form the first and second main electrode regions 33a and 33b. Heat treatment is then performed to activate the impurity ions, forming the first and second main electrode regions 33a and 33b at positions sandwiching the respective gate electrodes 34.

[0128] like Figure 8As shown, an interlayer insulating film 352 is formed by CVD or the like to cover the gate electrode 34 of the pixel transistor, thereby performing flattening. The interlayer insulating film 35 is formed by the pixel circuit separation regions 351a and 351b and the interlayer insulating film 352. Next, contact openings 311, 331, 341, 151, 221, etc. are formed by RIE or the like. The opening 341 is set to penetrate the interlayer insulating film 352 and reach the gate electrode 34. The openings 151 and 221 form contact vias (contact vias) that expose a portion of the upper surface of the extension region 116 and the well contact region 22 of the first semiconductor layer (11 and 12), and the contact vias pass through the area inside the pixel circuit separation region 351a that penetrates the second semiconductor layer 31, thereby preventing the side walls of the second semiconductor layer 31 and the contact vias from contacting each other. In addition, a high dose of n-type impurity ions is injected through the openings 151 and 331 by photolithography, ion implantation, etc. Next, the photoresist film used as the mask for ion implantation is removed and heat treatment is performed. By performing heat treatment, as shown in FIG. Figure 8 As shown, the charge storage region 15 is formed deeper than the extension region 116 and has a higher impurity density than the extension region 116, so as to overlap with the end of the extension region 116 at the upper portion of the well region 11 of the first semiconductor layer (11 and 12). Although the example of introducing impurities into the semiconductor layer of the opening has been described, this step can be omitted by controlling the impurities of the first semiconductor layer and the second semiconductor layer and depending on the damage state of the semiconductor layer during the etching of the opening.

[0129] At the same time, in the first main electrode region 33a and the second main electrode region 33b of the second semiconductor layer 31, the contact region 330 having a higher impurity density than the first main electrode region 33a and the second main electrode region 33b is formed deeper than the first main electrode region 33a and the second main electrode region 33b, respectively. Next, a high dose of p-type impurity ions is injected through the openings 311 and 221 using photolithography, ion implantation, etc. Next, by removing the photoresist film used for the mask for ion implantation and performing heat treatment, as shown in FIG. Figure 8 As shown, the contact region 310 is formed in the second semiconductor layer 31 and the contact region 220 is formed in the well contact region 22 of the first semiconductor layer ( 11 and 12 ).

[0130] Next, a metal such as W or copper (Cu) is buried in the openings 311, 331, 341, 151, and 221 by CVD, electroplating, or the like. The metal film protruding from the openings 311, 331, 341, 151, and 221 and remaining on the interlayer insulating film 35 is planarized and removed by etch-back, CMP, or the like, and Figure 9As shown, through-hole plugs 312 and 332, contact plug 36, and through-hole plugs 21 and 222 are formed. Through-hole plug 312 is electrically connected to contact region 310 of second semiconductor layer 31. Through-hole plug 332 is electrically connected to contact region 330 of first main electrode region 33a and second main electrode region 33b. Contact plug 36 is electrically connected to gate electrode 34. Through-hole plug 21 is electrically connected to charge storage region 15. Through-hole plug 222 is electrically connected to contact region 220 of well contact region 22.

[0131] Next, a first interlayer insulating film, in which the first wiring layer will be formed, is deposited on the interlayer insulating film 35 by CVD or the like. Furthermore, a groove (trench) that will become the first wiring layer is formed in the interlayer insulating film using photolithography and dry etching. Next, after a barrier metal and a metal film such as a seed Cu are formed on the inner wall of the trench by sputtering or the like, Cu is deposited by electrolytic plating or the like to completely bury it in the trench. Next, the Cu on the first interlayer insulating film is removed by electropolishing, CMP or the like so that the Cu remains only in the trench, thereby forming the wiring pattern of the first wiring layer 38a. CVD is used to deposit a second interlayer insulating film on the wiring pattern of the first wiring layer 38a. A SiO2 film-based material, a SiO2 film-based material generated by tetraethoxysilane (TEOS) gas, or a low dielectric constant material is applied to the second interlayer insulating film. In particular, applying a low dielectric constant material is advantageous from the perspective of accelerating processing. In addition, the interlayer insulating film of the second layer is selectively opened using photolithography and dry etching, and a via plug opening (for via plug 39a) is formed until just before a portion of the wiring layer of the first wiring layer 38a is exposed. After separating the photoresist of this step, a wiring groove (trench) that will become the second wiring layer is formed in the interlayer insulating film of the second layer using photolithography, dry etching, etc. During the processing of the trench that will become the second wiring layer, the interlayer insulating film that did not reach the first wiring layer 38a when forming the above-mentioned via mark opening is also etched simultaneously. As a result, the via plug opening is completely opened and the upper surface of the first wiring layer 38a is exposed inside the via plug opening. Although not shown, a SiC-based layer such as silicon carbide (SiC), silicon oxycarbide (SiCO), or silicon carbonitride (SiCN) is formed in the upper portion of the first wiring layer 38a as a Cu diffusion prevention layer. The SiC-based layer serves as an etch stop layer during the processing of the interlayer insulating film of the second layer. Furthermore, the SiC-based layer serving as an etching stopper is etched to form an opening into which the second wiring layer 38b and the via plug 39a will be buried. Next, by depositing a metal such as Cu to fill the opening using CVD and electroplating methods, and flattening the metal using CMP, etc., the via plug 39a and the second wiring layer 38b, which will be electrically connected to the first layer of the first wiring layer 38a, are formed. Although copper (Cu) is generally used as the metal, the metal is not limited to Cu.

[0132] Next, a third layer of interlayer insulating film is deposited on the wiring pattern of the second wiring layer 38b formed in the above step using CVD. Furthermore, photolithography and dry etching are used to selectively open the third layer of interlayer insulating film and form a via plug opening (for via plug 39b) until just before a portion of the wiring layer of the second wiring layer 38b is exposed. After separating the photoresist of this step, photolithography, dry etching, etc. are used to form wiring grooves (trench) that will become the third wiring layer in the third layer of interlayer insulating film. During the processing of the third layer of interlayer insulating film, the interlayer insulating film that did not reach the second wiring layer 38b when forming the above-mentioned via mark opening is also etched simultaneously. As a result, the via plug opening is fully opened and the upper surface of the second wiring layer 38b is exposed inside the via plug opening. Next, by depositing metal such as Cu to fill the opening using CVD, plating, etc. and planarizing the metal using CMP, etc., a via plug 39b and a third wiring layer 38c to be electrically connected to the second layer of the second wiring layer 38b are formed.

[0133] In a similar manner, an interlayer insulating film of the fourth layer is deposited on the wiring pattern of the formed third wiring layer 38c, the interlayer insulating film of the fourth layer is selectively opened, and a through-hole plug opening (for the through-hole plug 39c) is formed until just before a portion of the wiring pattern of the third wiring layer 38c is exposed. After separating the photoresist, a wiring groove (groove) that will become the fourth wiring layer is formed in the interlayer insulating film of the fourth layer using photolithography, dry etching, etc. During the processing of the interlayer insulating film of the fourth layer, the interlayer insulating film that did not reach the third wiring layer 38c when forming the above-mentioned through-hole mark opening is also etched at the same time. Therefore, the through-hole plug opening is completely opened and the upper surface of the third wiring layer 38c is exposed inside the through-hole plug opening. Next, by depositing a metal such as Cu to fill the opening using CVD, electroplating, etc. and flattening the metal using CMP, etc., a through-hole plug 39c and the fourth wiring layer 38d of the third layer that will be electrically connected to the third wiring layer 38c are formed. Thus, a multilayer wiring structure is formed, in which, as shown in FIG. Figure 9 As shown, the wiring pattern of the second wiring layer 38b, the wiring pattern of the third wiring layer 38c, and the wiring pattern of the fourth wiring layer 38d are sequentially embedded on top of the wiring pattern of the first wiring layer 38a. Although the formation of the multilayer wiring structure has been described using a method in which metal is buried at once after forming an opening for a via plug and an opening for wiring, alternatively, a method in which an opening for wiring is formed after burying metal in the opening for a via plug may be adopted.

[0134] like Figure 9As shown, the charge storage region 15 of the first semiconductor layer (11 and 12), the amplifier transistor (33a, 33b and 34) of the second semiconductor layer 31, and the reset transistor (not shown) are electrically connected to each other through the through-hole plug 21, the wiring pattern of the first wiring layer 38a, and the contact plug 36, thereby constructing a source follower (SF) circuit. One of the first main electrode region 33a and the second main electrode region 33b of the amplifier transistor (33a, 33b and 34) is connected to the power line. In addition, the contact region 330 of the second semiconductor layer 31 and the contact region 220 of the well contact region 22 are connected to the ground line. For convenience, in the present invention, Figure 9 The illustrated first semiconductor layer ( 11 and 12 ) and second semiconductor layer 31 including the pixel transistor and the wiring layer are referred to as a “photoelectric conversion element unit”.

[0135] Next, prepare Figure 9 The third semiconductor layer 51 for logic circuit of the photoelectric conversion element unit shown is made of a new Si substrate. In addition, the logic circuit is constructed on the third semiconductor layer 51 by a conventional CMOS manufacturing step. Figure 10A In a similar manner to the two transistors constituting a part of the logic circuit schematically shown in FIG, a large number of transistors constituting the logic circuit (hereinafter referred to as “logic circuit transistors”) are formed in the third semiconductor layer 51 constituting the third substrate 5. The first main electrode region 53a and the second main electrode region 53b are arranged so that they are Figure 10A The upper portion of the third semiconductor layer 51 of the third substrate 5 shown is separated from each other, and a gate electrode 54 is arranged on the third semiconductor layer 51 between the first main electrode region 53a and the second main electrode region 53b, with a gate insulating film (not shown) interposed therebetween. The logic circuit transistor 52 is composed of the gate electrode 54, the first main electrode region 53a, and the second main electrode region 53b. The gate electrode 54 is covered by an interlayer insulating film 55. The upper surface of the interlayer insulating film 55 is flattened.

[0136] Next, by CVD, etc., Figure 10AA first interlayer insulating film in which the first wiring layer will be formed is deposited on the interlayer insulating film 55 shown. In addition, a groove (trench) that will become the first wiring layer is formed in the interlayer insulating film using photolithography and dry etching. Then, after forming a barrier metal and a metal film such as a seed Cu on the inner wall of the trench by sputtering, Cu is deposited by electrolytic plating to completely bury it in the trench. Next, the Cu on the first layer of the interlayer insulating film is removed by electrolytic polishing, CMP, etc., so that the Cu remains only in the trench to form the wiring pattern of the first wiring layer 58a. A second layer of interlayer insulating film is deposited on the wiring pattern of the first wiring layer 58a using CVD. In addition, the second layer of interlayer insulating film is selectively opened using photolithography and dry etching, and a through-hole plug opening (for through-hole plug 59a) is formed until just before a portion of the wiring layer of the first wiring layer 58a is exposed. After removing the photoresist of this step, the interlayer insulating film of the second layer is processed and a wiring groove (trench) is formed using photolithography, dry etching, etc., in which the metal of the second wiring layer 58b will be buried. During the processing of the interlayer insulating film of the second layer, the interlayer insulating film that does not reach the first wiring layer 58a when forming the above-mentioned through-hole mark opening is also etched simultaneously. As a result, the upper surface of the first wiring layer 58a is exposed inside the through-hole plug opening. Next, by depositing a metal such as Cu to fill the opening using CVD, electroplating, etc., and flattening the metal using CMP, etc., a through-hole plug 59a that will be electrically connected to the first layer of the second wiring layer 58b and the second wiring layer 58b is formed.

[0137] In a similar manner, an interlayer insulating film of a third layer is deposited on the wiring pattern of the formed second wiring layer 58b, the interlayer insulating film of the third layer is selectively opened, and a through-hole plug opening (for the through-hole plug 59b) is formed until just before a portion of the wiring layer of the second wiring layer 58b is exposed. After separating the photoresist, a wiring groove (groove) that will become the third wiring layer is formed in the interlayer insulating film of the third layer using photolithography, dry etching, etc. During the processing of the interlayer insulating film of the third layer, the interlayer insulating film that did not reach the second wiring layer 58b when forming the above-mentioned through-hole mark opening is also etched at the same time. Therefore, the through-hole plug opening is completely opened and the upper surface of the second wiring layer 58b is exposed inside the through-hole plug opening. Next, by depositing metal to fill the opening using CVD, electroplating, etc., and flattening the metal using CMP, etc., a through-hole plug 59b and the third wiring layer 58c that will be electrically connected to the second layer of the second wiring layer 58b are formed. Thus, a multi-layer wiring structure is completed, in which, as shown in FIG. Figure 10A As shown, a first wiring layer 58 a , a second wiring layer 58 b , and a third wiring layer 58 c are sequentially stacked on the interlayer insulating film 57 and the upper surface of the interlayer insulating film 57 is planarized.

[0138] exist Figure 10AA contact region using silicide or the like is formed in the third semiconductor layer 51 shown and connected to wiring of the logic circuit. In this way, the third substrate 5 in which the logic circuit is integrated in the third semiconductor layer 51 is prepared. Next, as shown in FIG. Figure 10A As shown, the third substrate 5 is bonded to the second substrate 3 via the interlayer insulating film 37 and the interlayer insulating film 57 using a wafer direct bonding technique. This bonding is performed by reversing the photoelectric conversion element unit so that the positional relationship between the third semiconductor layer 51, the second semiconductor layer 31, and the first semiconductor layer (11 and 12) is arranged in the following order: the third semiconductor layer 51, the second semiconductor layer 31, and the first semiconductor layer (11 and 12). In this case, the following example is shown: in which the third substrate 5 and the photoelectric conversion element unit are connected by Cu-Cu connection and Cu-Cu bonding is performed through the respective uppermost wiring layers. Although in Figure 10A Direct Cu-Cu bonding is performed through the respective wirings of the fourth wiring layer 38d of the second substrate 3 and the third wiring layer 58c of the third substrate 5, but alternatively, a structure in which a wiring layer for Cu-Cu bonding is separately provided may be employed. For example, Figure 10B As shown, a new interlayer insulating film 300 is deposited on the uppermost wiring layer of the second substrate 3 to form a fourth-layer via plug 39d and a fifth wiring layer 38e. The via plug 39d and the fifth wiring layer 38e are made of Cu and electrically connect the interlayer insulating film 300 to the fourth wiring layer 38d. Furthermore, a new interlayer insulating film 500 is deposited on the uppermost wiring layer of the third substrate 5 to form a third-layer via plug 59c and a fourth wiring layer 58d. The via plug 59c and the fourth wiring layer 58d are made of Cu and electrically connect to the third wiring layer 58c. Furthermore, Cu-Cu bonding can be performed between the fifth wiring layer 38e of the second substrate 3 and the fourth wiring layer 58d of the third substrate 5. Alternatively, oxide film bonding can be performed, in which the interlayer insulating film 57 of the third substrate 5 and the interlayer insulating film 37 of the second substrate 3 are bonded to each other. In this case, through-silicon vias (TSVs) are formed in a step that will be performed after thinning the first substrate 1, and the wiring of the third substrate 5 and the second substrate 3 will be connected through the TSVs. Next, the first semiconductor layer (11 and 12) is thinned by grinding, polishing, and etching until the bottom pinning layer 13 remains with the required thickness to form a light-receiving surface. Although the film thickness of the first semiconductor layer (11 and 12) varies depending on the application and material, when considering the transmission distance of visible light of commonly used Si, the thickness is about 1 μm to 10 μm.

[0139] A planarization film 18 is formed on top of the bottom pinning layer 13 of the thinned first semiconductor layer (11 and 12) to become a light receiving surface, and then a color filter 71, a micro lens 72, etc. are formed to complete the Figure 10AThe solid-state imaging device shown. If necessary, light shielding portions may be provided between pixels. Finally, openings are formed for pads, which serve as input / output electrodes for connecting signal lines, power lines, ground lines, and the like to external wiring. Although not shown, pads only need to be formed in either the third substrate 5 or the second substrate 3.

[0140] Although the description of the solid-state imaging device according to the first embodiment shows an example in which three substrates (i.e., a first substrate 1, a second substrate 3, and a third substrate 5) are bonded to each other, silicide is formed in the third substrate 5, and the substrates are stacked, the stacking is not limited to bonding three layers. For example, two substrates may be bonded to each other. In this case, a logic circuit in which silicide is formed will be formed in the second substrate 3. Alternatively, four or more layers may be stacked. In addition, although the circuit to be mounted on the third substrate 5 has been described using the general name "logic circuit", the third substrate 5 can be configured to include a logic circuit, DRAM, non-volatile memory, MEMS, etc. and is not particularly limited.

[0141] Although the T-shaped transfer gate structure 16 having the vertical gate 17 is exemplified in the description of the solid-state imaging device according to the first embodiment, this component is not restrictive. For example, although the T-shaped transfer gate structure 16 is exemplified in the first embodiment, the vertical gate 17 may be the only transfer gate structure, or may be only the vertical gate 17 as shown in FIG. Figure 11 Alternatively, the planar gate 16h and the vertical gate 17 may be separately provided and formed so that the mutual transmission paths are connected to each other. Figure 11 When only the planar gate 16h is used as shown, it is desirable to form a p-type pinning layer. + The type well contact region 22 is formed to make the well region 11 shallower, thereby preventing the storage of charge from decreasing. In addition, the pixel separation unit 19 does not need to completely separate the pixels. For example, Figure 12 As shown, a terminal may be provided in the charge generation region 12 separately from the well region 11 .

[0142] Although a single charge holding unit 23 has been described above, this configuration is not restrictive. Figure 13 As shown, multiple charge retention units are provided by providing a separate charge retention unit 23c between the charge retention unit 23 and the charge storage region 15. For example, the charge retention unit 23 temporarily retains the signal charge stored by the incident light, and then the signal charge is transferred to the charge retention unit 23c and temporarily retained by the charge retention unit 23c. In this way, a signal charge transfer operation similar to that of a charge coupled device can be performed.

[0143] also, Figure 142 shows two horizontal columns of pixels in the case where the pixels according to the first embodiment are constituted by 2×2 pixels. Figure 14 As shown, in a first pixel, a first photoelectric conversion unit 10a, consisting of a first well region 11a and a first charge generation region 12a, is provided so as to be surrounded by a first bottom pinning layer 13a, a first side pinning layer 14a, and the first well region 11a. A first transfer gate structure 16a is provided on the upper surface of the first well region 11a, and a first vertical gate 17a is provided so as to pass through the first well region 11a and reach the first charge generation region 12a. A first charge retention unit 23a is provided between the first transfer gate structure 16a and the first charge storage region 15a. A pixel transistor, such as an amplifying transistor 32aa having a first main electrode region 33aa, a second main electrode region 33ba, and a first gate electrode 34a, is provided in the second semiconductor layer 31 of the second substrate 3. The first charge storage region 15a is electrically connected to the first gate electrode 34a via a first through-hole plug 21a, a wiring pattern of a first wiring layer 38a of the second substrate 3, and a contact plug 36a.

[0144] like Figure 14 As shown, in the second pixel, a second photoelectric conversion unit 10b consisting of a second well region 11b and a second charge generation region 12b is provided, surrounded by a second bottom pinning layer 13b, a second side pinning layer 14b, and the second well region 11b. A second transfer gate structure 16b is provided on the upper surface of the second well region 11b, and a second vertical gate 17b is provided so as to pass through the second well region 11b and reach the second charge generation region 12b. A second charge retention unit 23b is provided between the second transfer gate structure 16b and the second charge storage region 15b. A pixel transistor, such as an amplifier transistor 32ab having a first main electrode region 33ab, a second main electrode region 33bb, and a second gate electrode 34b, is provided in the second semiconductor layer 31 of the second substrate 3. The second charge storage region 15b is electrically connected to the first gate electrode 34a of the amplifier transistor 32aa via a second through-hole plug 21b, a wiring pattern of a first wiring layer 38a, and a contact plug 36a. It should be noted that the first pixel, the second pixel, the third pixel (not shown), and the fourth pixel (not shown) are separated by the pixel separation unit 19 .

[0145] Figure 15 Shown Figure 14 The equivalent circuit of the solid-state imaging device shown in FIG. Figure 15As shown, within the first substrate 1, the signal charges stored by the first, second, third, and fourth photoelectric conversion units 10a, 10b, 10c, and 10d are temporarily retained by the first, second, third, and fourth charge retention units 23a, 23b, 23c, and 23d, respectively, via the first, second, third, and fourth transfer gate structures 16a, 16b, 16c, and 16d. The retained charges are then transferred to the first, second, third, and fourth charge storage regions 15a, 15b, 15c, and 15d, respectively, at predetermined timings to be converted into electrical signals. In the second substrate 3, the converted electrical signals are collectively transferred to the amplifier transistor 32a and the reset transistor 32c. The electrical signals are then sent to VSL via the select transistor 32b at predetermined timings.

[0146] Figure 16 1 is a plan view showing the layout of the first substrate 1 in a 4-pixel common area of ​​2×2 pixels. Figure 16 Also shown are connecting conductors for wiring. Figure 16 As shown, the first through-hole plug 222a, the second through-hole plug 222b, the third through-hole plug 222c, and the fourth through-hole plug 222d are respectively connected to the first well region 11a, the second well region 11b, the third well region 11c, and the fourth well region 11d separated by the pixel separation unit 19. The first contact plug 316a, the second contact plug 316b, the third contact plug 316c, and the fourth contact plug 316d are respectively connected to the first transfer gate structure 16a, the second transfer gate structure 16b, the third transfer gate structure 16c, and the fourth transfer gate structure 16d. The first contact plug 323a, the second contact plug 323b, the third contact plug 323c, and the fourth contact plug 323d are respectively connected to the first charge retention unit 23a, the second charge retention unit 23b, the third charge retention unit 23c, and the fourth charge retention unit 23d. The first through-hole plug 21a, the second through-hole plug 21b, the third through-hole plug 21c and the fourth through-hole plug 21d are connected to the first charge storage region 15a, the second charge storage region 15b, the third charge storage region 15c and the fourth charge storage region 15d, respectively.

[0147] Figure 17 1 is a plan view showing the layout of the second substrate 3 and also showing connection conductors for wiring. Figure 17As shown, in the amplifier transistor 32a, the contact plug 333a is connected to two regions (i.e., the first main electrode region 33aa and the second main electrode region 33ba) and the contact plug 36a is connected to the first gate electrode 34a. In the selection transistor 32b, the contact plug 333b is connected to the first main electrode region 33ab and the second main electrode region 33bb and the contact plug 36b is connected to the second gate electrode 34b. In the reset transistor 32c, the contact plug 333c is connected to the first main electrode region 33ac and the second main electrode region 33bc and the contact plug 36c is connected to the gate electrode 34c. The contact plug 333d is a node for connecting the amplifier transistor 32a and the selection transistor 32b to each other. In practice, the pixel transistors (32a, 32b and 32c) are covered by the interlayer insulating film 35. Figure 18 The layout of the through hole plug, contact plug and pixel transistor is shown, wherein Figure 16 The first substrate 1 and Figure 17 The second substrates 3 are shown stacked on top of each other.

[0148] exist Figures 16 to 18 In the description of the solid-state imaging device according to the first embodiment, each pixel is separated by the pixel separation unit 19. Figure 12 The pixel separation unit 19 shown enables the charge storage region to be shared without separating the first to fourth well regions 11 a to 11 d . Figure 19 1 shows the layout of the first substrate 1 when the charge storage region 15A is shared. Figure 19 As shown, the first to fourth well regions 11a to 11d are not separated by the pixel separation unit 19. The charge storage region 15A is provided in the center portion of the four intersecting pixels. A through-hole plug 21A is connected to the charge storage region 15A in the center portion. The first to fourth contact plugs 316a to 316d are connected to the first to fourth transfer gate structures 16a to 16d, respectively, and the first to fourth contact plugs 323a to 323d are connected to the first to fourth charge retention units 23a to 23d, respectively. Charge transferred from the first to fourth transfer gate structures 16a to 16d to the first to fourth charge retention units 23a to 23d and retained therein is transferred to the charge storage region 15A in the center portion.

[0149] Figure 20 and Figure 21 Indicates that when shared Figure 19 The charge storage area 15A shown is the layout of the second substrate 3 and the superimposed layout of the first substrate 1 and the second substrate 3. Figure 20 As shown, the layout of the second substrate 3 is similar to Figure 17 In addition, as Figure 21 As shown, the layout of the superposition of the first substrate 1 and the second substrate 3 is similar to Figure 18The illustrated layout differs only in that only one through-hole plug 21A is connected to the charge storage region 15 A. In this way, by sharing the charge storage region 15A, the layout can be simplified and the connection conductor can be easily formed.

[0150] (Second embodiment)

[0151] like Figure 22 As shown, the solid-state imaging device according to the second embodiment of the present invention includes a through-connection conductor 43 made of a metal such as Cu or W to be electrically connected to the charge storage region 15, and a charge holding unit 41 having a capacitor structure and having an insulating film 42 made of a dielectric film and covering the surface of the through-connection conductor 43. The through-connection conductor 43 is a through-hole plug, which is connected to the gate electrode 34 of the pixel transistor 32 such as an amplifier transistor through the contact plug 36 and the wiring pattern of the first wiring layer 38a formed in the interlayer insulating film 37 of the second substrate 3. The charge holding unit 41 is formed in the second semiconductor layer 31 of the second substrate 3 so as to be in contact with the insulating film 42. In this case, the wiring capacitance C of the charge holding unit 41 is V By C V =ε·S / d, where ε represents the dielectric constant of the insulating film 42, S represents the surface area of ​​the through-connection conductor 43 as a metal, and d represents the distance between the through-connection conductor 43 and the second semiconductor layer 31. Figure 22 In the example shown, the distance d between the through-hole connection conductor 43, which serves as a through-hole plug, and the second semiconductor layer 31 is the film thickness of the insulating film 42. Furthermore, the surface area S can be adjusted by changing the shape of the through-hole connection conductor 43. Furthermore, the surface area S can also be adjusted by the dielectric constant of the dielectric material. The capacitance of the portion of the insulating film 42 where the charge retention unit 41 contacts the interlayer insulating film 20 and the interlayer insulating film 35 becomes very small. Therefore, the wiring capacitance C of the charge retention unit 41 is reduced. V It is determined by the portion where the charge holding unit 41 is in contact with the second semiconductor layer 31 .

[0152] Alternatively, as Figure 23 As shown, the charge holding unit 41 may be configured to penetrate the interlayer insulating film 35 and not be in contact with the second semiconductor layer 31. In this case, the wiring capacitance C of the charge holding unit 41 is given by the series connection of the capacitance caused by the insulating film 42 in the region where the through-connecting conductor 43 faces the second semiconductor layer 31 and the capacitance caused by the interlayer insulating film 35. V Therefore, the wiring capacitance C of the charge holding unit 41 is adjusted by selecting the dielectric constant or thickness of the insulating film 42. V .

[0153] In solid-state imaging devices, the parameters that control the photoelectric conversion efficiency include the parasitic capacitance C of the charge storage region. FD The photoelectric conversion efficiency of the charge storage region to voltage depends on the parasitic capacitance C of the charge storage region. FD Generally, the conversion efficiency is related to the parasitic capacitance C FD Inversely proportional. Reduce the parasitic capacitance C FD This enables improved conversion efficiency, increased sensitivity, and a high SN ratio. FD The conversion efficiency is reduced, and the operation can be performed under high illumination and the dynamic range is increased. Therefore, the parasitic capacitance C of the charge storage area 15 is used. FD and the wiring capacitance C of the charge holding unit 41 V The effective capacitance C of the charge storage region 15 can be adjusted over a wide range. EFF Therefore, the conversion efficiency can be adjusted in a wide range, and at the same time, the dynamic range can also be adjusted. In addition, in a manner similar to the solid-state imaging device according to the first embodiment, providing a capacitor electrode in a part of the charge holding unit 41 can make the wiring capacitance C of the charge holding unit 41 V Varies depending on the magnitude of the voltage applied to the capacitor electrodes.

[0154] Next, refer to Figures 24 to 26 The following describes a method for manufacturing a solid-state imaging device according to the second embodiment, focusing primarily on an example of the steps for forming the charge retention unit 41. It should be noted that the method for forming the charge retention unit 41 described below is merely an example, and that the charge retention unit 41 can be formed using various other manufacturing methods within the scope of the claims, including the modified examples of the manufacturing method described below.

[0155] like Figure 24 As shown, an opening 241 is formed by photolithography, RIE, or the like so as to penetrate the interlayer insulating film 35 and the interlayer insulating film 20 without contacting the second semiconductor layer 31 and reach the storage area 15 in the well region 11. At the same time, an opening 341 is formed that penetrates the interlayer insulating film 35 and reaches the gate electrode 34 of the pixel transistor 32. Next, an insulating film 42s is deposited on the bottom surface and side surfaces of the openings 241 and 341 and on the surface of the interlayer insulating film 35. Next, the insulating film 42s formed in the bottom of the openings 241 and 341 is removed by etching back.

[0156] like Figure 25 As shown, a through-connection conductor 43 made of a conductor such as W is embedded in the opening 241 via the insulating film 42 by CVD, chemical mechanical polishing (CMP), etc. A contact plug 36 as a conductor is embedded in the opening 341 and electrically connected to the gate electrode 34.

[0157] like Figure 26 As shown, the wiring pattern of the first wiring layer 38A embedded in the opening provided in the interlayer insulating film 37s is provided so as to be electrically connected to the through-connection conductor 43 of the charge holding portion 41 and the gate electrode 34 of the pixel transistor 32. In this way, the parasitic capacitance C of the charge storage region 15 can be formed. FD and the wiring capacitance C of the charge holding unit 41 V .

[0158] Figure 27 FIG. 2 shows an equivalent circuit of a solid-state imaging device according to the second embodiment. Figure 27 As shown, the parasitic capacitance C of the charge storage region 15 FD and the wiring capacitance C of the charge holding unit 41 V The charge storage region 15 is connected in parallel. By adjusting the wiring capacitance C V For example, the effective capacitance C can be adjusted by using a high dielectric constant material and a low dielectric constant material based on the SiO2 film as the insulating film 42 of the charge holding unit 41. EFF Alternatively, the effective capacitance C EFF It can also be adjusted by appropriately selecting the film thickness of the insulating film 42 .

[0159] Although a single charge holding unit 41 is used to adjust the effective capacitance C in the above description EFF , but the effective capacitance C EFF It cannot be changed after manufacture. For example, Figure 28 As shown, each of the plurality of charge holding units 41A, 41B, and 41C electrically connected to the charge storage region 15 may be given a different effective capacitance C EFF . For example, an insulating film 42A made of a high dielectric constant material is used in the charge holding unit 41A, an insulating film 42B which is a standard SiO2 film is used in the charge holding unit 41B, and an insulating film 42C made of a low dielectric constant material is used in the charge holding unit 41C. The through-connection conductor 43A of the charge holding unit 41A is connected to the gate electrode 34A of the pixel transistor 32A via the wiring pattern of the first wiring layer 38A and the contact plug 36A. The through-connection conductor 43B of the charge holding unit 41B is connected to the gate electrode 34B of the pixel transistor 32B via the wiring pattern of the second wiring layer 38B and the contact plug 36B. The through-connection conductor 43C of the charge holding unit 41C is connected to the gate electrode 34C of the pixel transistor 32C via the wiring pattern of the third wiring layer 38C and the contact plug 36C. By appropriately selecting the pixel transistors 32A, 32B and 32C according to the control of the logic circuit, the effective capacitance C EFFAlternatively, the film thickness of the insulating films 42A, 42B, and 42C may be changed instead of the dielectric constant.

[0160] Figure 29 The use of switching transistors 45A, 45B, and 45C to adjust the effective capacitance C is shown. EFF structure. Figure 30 Shown Figure 29 The equivalent circuit of the solid-state imaging device shown in FIG. The insulating films 42A, 42B, and 42C of the charge holding units 41A, 41B, and 41C have wiring capacitances C that are differentiated by changing the dielectric material or film thickness. VA , C VB and C VC . The charge holding unit 41A is electrically connected to one main electrode region of the switching transistor 45A through the wiring pattern of the first wiring layer 38A and is electrically connected to the other main electrode region through the wiring 47. The charge holding unit 41B is electrically connected to one main electrode region of the switching transistor 45B through the wiring pattern of the second wiring layer 38B and is electrically connected to the other main electrode region through the wiring 47. The charge holding unit 41C is electrically connected to one main electrode region of the switching transistor 45C through the wiring pattern of the third wiring layer 38C and is electrically connected to the other main electrode region through the wiring 47. The wiring 47 is electrically connected to the gate electrode of the pixel transistor 32. By appropriately switching the switching transistors 45A, 45B and 45C, the effective capacitance C can be adjusted. EFF .

[0161] Figure 31 1 shows the layout of the first substrate 1 when the charge storage region 15 is shared. Figure 31 As shown, the charge storage region 15 is provided in the central portion of four intersecting pixels. Charge retention units 41A, 41B, and 41C are connected to the charge storage region 15. First to fourth contact plugs 316a to 316d are connected to first to fourth transfer gate structures 16a to 16d, respectively. Charge transferred from the first to fourth transfer gate structures 16a to 16d to the charge storage region 15 is transferred from the charge storage region 15 to the pixel transistor 32.

[0162] Despite Figure 28 and Figure 29 Three charge holding units 41A, 41B, and 41C are used in FIG. However, two capacitors or four or more capacitors may be used instead.

[0163] (Electronic equipment)

[0164] like Figure 32As shown, an imaging device 101 to be mounted on an electronic device using the solid-state imaging device according to the first and second embodiments of the present invention includes an optical system 102, an imaging element 103, a logic circuit 104, a monitor 105, and a memory 106. The imaging device 101 can image both still images and moving images.

[0165] The optical system 102 includes one or more lenses. The optical system 102 guides incident light from a subject to the imaging element 103 and forms an image on the light-receiving surface of the imaging element 103. The imaging element 103 can be a solid-state imaging device according to the first and second embodiments. The imaging element 103 stores charge for a certain period of time based on the image formed on the light-receiving surface via the optical system 102. The signal charge stored in the imaging element 103 is converted into an electrical signal. The converted electrical signal is output to the logic circuit 104.

[0166] The logic circuit 104 performs various signal processing on the image signal output from the imaging element 103 and generates image data. The image data generated by the logic circuit 104 can be displayed on the monitor 105. In addition, the image data can also be stored in the memory 106.

[0167] As described above, using the solid-state imaging device according to the first or second embodiment as the imaging element 103 enables realization of a global shutter function, and adjustment of sensitivity or dynamic range by switching conversion efficiency.

[0168] (Other implementation plans)

[0169] Although the present invention has been described above in the form of the first embodiment and the second embodiment, it should be understood that the description and the accompanying drawings, which constitute a part of the present invention, do not limit the present invention. It should be understood that various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art based on this disclosure.

[0170] Although the photoelectric conversion unit 10 using Si semiconductors has been described in the first and second embodiments, the photoelectric conversion unit is not limited thereto. For example, a compound semiconductor can also be applied as a photoelectric conversion unit. For example, III-V compound semiconductors such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs) and indium antimonide (InSb) can be used as photoelectric conversion units in the infrared region. In addition, II-VI compound semiconductors such as mercury cadmium telluride (HgCdTe) can be used as photoelectric conversion units in the infrared region. In addition, II-VI compound semiconductors such as cadmium telluride (CdTe) can be used as photoelectric conversion units in the X-ray region.

[0171] As described above, it should be understood that the present invention includes various embodiments etc. not described herein. Therefore, the present invention is limited only by matters specifying the present invention according to the scope of the claims that are reasonable from the invention disclosed above.

[0172] The present invention can also be constructed as follows. (1)

[0174] A photoelectric conversion element, comprising:

[0175] A photoelectric conversion unit, used for converting an optical signal into a signal charge;

[0176] a transfer gate structure connected to the photoelectric conversion unit and configured to transfer the signal charge;

[0177] a charge storage region, to which the signal charge is transferred by the transfer gate structure;

[0178] a charge holding unit having a capacitor structure, electrically connected to the charge storage region and configured to store the signal charge; and

[0179] an amplifying transistor, a control electrode of the amplifying transistor being electrically connected to the charge storage region, wherein

[0180] The photoelectric conversion unit, the transfer gate structure and the charge storage region are arranged on a first substrate,

[0181] The amplifying transistor is provided on the second substrate, and

[0182] The first substrate and the second substrate are stacked. (2)

[0184] The photoelectric conversion element according to (1) above, wherein the charge holding unit connected to the input side of the charge storage region is provided on the first substrate. (3)

[0186] The photoelectric conversion element according to (2) above, wherein

[0187] The photoelectric conversion unit includes a well region of a first conductivity type and a charge generation region of a second conductivity type for forming a pn junction with the well region, and

[0188] The charge retention unit includes: a buried capacitor region including a pn junction provided on a surface of the well region opposite to a surface in contact with the charge generation region; an insulating film provided on a surface of the buried capacitor region; and an electrode provided on the insulating film. (4)

[0190] The photoelectric conversion element according to (1) above, wherein the charge holding unit connected to the output side of the charge storage region is provided in a part of an electrical path from the first substrate to the second substrate. (5)

[0192] The photoelectric conversion element according to (4) above, wherein

[0193] The photoelectric conversion unit includes a well region of a first conductivity type and a charge generation region of a second conductivity type for forming a pn junction with the well region.

[0194] The charge storage region is provided on a surface of the well region opposite to a surface in contact with the charge generation region, and

[0195] The photoelectric conversion element further includes a through-connection conductor that penetrates a bonding interface between the first substrate and the second substrate and serves to electrically connect the control electrode of the amplifying transistor and the charge storage region to each other. (6)

[0197] The photoelectric conversion element according to (5) above, wherein the charge retention unit includes: the through-connection conductor; an insulating film arranged around the through-connection conductor; and a semiconductor layer of the second substrate, the semiconductor layer of the second substrate being opposite to the through-connection conductor via the insulating film. (7)

[0199] The photoelectric conversion element according to (6) above, wherein the charge holding unit has a plurality of the through-connection conductors. (8)

[0201] The photoelectric conversion element according to (7) above, wherein one or more dielectric materials are provided as the insulating film around each of the plurality of through-connector conductors. (9)

[0203] A solid-state imaging device having a plurality of pixels arranged therein, each pixel comprising:

[0204] A photoelectric conversion unit, used for converting an optical signal into a signal charge;

[0205] a transfer gate structure connected to the photoelectric conversion unit and configured to transfer the signal charge;

[0206] a charge storage region, to which the signal charge is transferred by the transfer gate structure;

[0207] a charge holding unit having a capacitor structure, electrically connected to the charge storage region and configured to store the signal charge; and

[0208] an amplifying transistor, a control electrode of the amplifying transistor being electrically connected to the charge storage region, wherein

[0209] The photoelectric conversion unit, the transfer gate structure and the charge storage region are arranged on a first substrate,

[0210] The amplifying transistor is provided on the second substrate, and

[0211] The first substrate and the second substrate are stacked. (10)

[0213] The solid-state imaging device according to (9) above, wherein the charge holding unit connected to the input side of the charge storage region is provided on the first substrate. (11)

[0215] The solid-state imaging device according to (10) above, wherein the photoelectric conversion unit includes a well region of the first conductivity type and a charge generation region of the second conductivity type for forming a pn junction with the well region, and

[0216] The charge retention unit includes: a buried capacitor region including a pn junction provided on a surface of the well region opposite to a surface in contact with the charge generation region; an insulating film provided on a surface of the buried capacitor region; and an electrode provided on the insulating film. (12)

[0218] The solid-state imaging device according to (9) above, wherein the charge holding unit connected to the output side of the charge storage region is provided in a part of an electrical path from the first substrate to the second substrate. (13)

[0220] The solid-state imaging device according to (12) above, wherein

[0221] The photoelectric conversion unit includes a well region of a first conductivity type and a charge generation region of a second conductivity type for forming a pn junction with the well region.

[0222] The charge storage region is provided on a surface of the well region opposite to a surface in contact with the charge generation region, and

[0223] The solid-state imaging device further includes a through-connection conductor that penetrates a bonding interface between the first substrate and the second substrate and serves to electrically connect the control electrode of the amplifying transistor and the charge storage region to each other. (14)

[0225] A solid-state imaging device according to (13) above, wherein the charge retention unit includes: the through-connection conductor; an insulating film arranged around the through-connection conductor; and a semiconductor layer of the second substrate, the semiconductor layer of the second substrate being opposite to the through-connection conductor via the insulating film. (15)

[0227] The solid-state imaging device according to any one of (9) to (14) above, wherein

[0228] A third substrate is bonded to the second substrate so that the main surface facing the second substrate is located on the opposite side of the main surface facing the first substrate, the third substrate has a logic circuit for performing signal processing of the electrical signal output from the second substrate, and the first substrate, the second substrate and the third substrate electrically connected to each other constitute a three-layer stacked structure. (16)

[0230] An electronic device including a solid-state imaging device, wherein the solid-state imaging device is arranged with a plurality of pixels, each of the pixels including:

[0231] A photoelectric conversion unit, used for converting an optical signal into a signal charge;

[0232] a transfer gate structure connected to the photoelectric conversion unit and configured to transfer the signal charge;

[0233] a charge storage region, to which the signal charge is transferred by the transfer gate structure;

[0234] a charge holding unit having a capacitor structure, electrically connected to the charge storage region and configured to store the signal charge; and

[0235] an amplifying transistor, a control electrode of the amplifying transistor being electrically connected to the charge storage region, wherein

[0236] The photoelectric conversion unit, the transfer gate structure and the charge storage region are arranged on a first substrate,

[0237] The amplifying transistor is provided on the second substrate, and

[0238] The first substrate and the second substrate are stacked.

[0239] [Reference Signs List]

[0240] 1. First substrate

[0241] 3 Second substrate

[0242] 5. Third substrate

[0243] 7 Incident unit

[0244] 10 Photoelectric conversion unit (PD)

[0245] 11, 12 first semiconductor layer

[0246] 11-well region

[0247] 12 Charge generation region

[0248] 13 Bottom pinning layer

[0249] 14 Side pinning layer

[0250] 15 Charge storage area (floating diffusion area)

[0251] 16 Transmission Gate Structure

[0252] 17 Vertical Gate

[0253] 18 planarization film

[0254] 19 pixel separation unit

[0255] 20, 35, 37, 55, 57 interlayer insulation film

[0256] 21, 43 through-hole conductor (through-hole plug)

[0257] 22-well contact area

[0258] 23, 41 Charge retention unit

[0259] 24 Embedded capacitor area

[0260] 31 Second semiconductor layer

[0261] 32 pixel transistors

[0262] 32a amplifier transistor

[0263] 33a, 53a First main electrode region (source region)

[0264] 33b, 53b Second main electrode region (drain region)

[0265] 34, 54 control electrode (gate electrode)

[0266] 36, 56 connecting conductor (contact plug)

[0267] 38a, 38A, 58a first wiring layer

[0268] 38b, 38B, 58b second wiring layer

[0269] 38c, 38C, 58c third wiring layer

[0270] 38d fourth wiring layer

[0271] 39, 59 through-hole plug

[0272] 42 Insulation film

[0273] 51 third semiconductor layer

[0274] 52 logic circuit transistors

[0275] 71 Color Filters

[0276] 72 microlenses

[0277] 91 pixel array unit

[0278] 92 pixels

[0279] 93 drive unit

[0280] 94 columns of processing units

[0281] 95 horizontal drive unit

[0282] 96 vertical signal lines

[0283] 97 vertical drive unit

[0284] 98 control line

[0285] 99 signal processing unit

[0286] 101 Imaging Device

[0287] 102 Optical System

[0288] 103 Imaging Element

[0289] 104 Logic Circuits

[0290] 105 Monitor

[0291] 106 Memory

[0292] 230 Capacitor insulation film

[0293] 231 capacitor electrode

[0294] C FD Diffusion layer capacitance

[0295] C V Wiring capacitance

Claims

1. A photoelectric conversion element, comprising: A photoelectric conversion unit, used for converting an optical signal into a signal charge; a transfer gate structure connected to the photoelectric conversion unit and configured to transfer the signal charge; a charge storage region, to which the signal charge is transferred by the transfer gate structure; a charge holding unit having a capacitor structure, electrically connected to the charge storage region and configured to store the signal charge; and an amplifying transistor, a control electrode of the amplifying transistor being electrically connected to the charge storage region, wherein The photoelectric conversion unit, the transfer gate structure and the charge storage region are arranged on a first substrate, The amplifying transistor is provided on the second substrate, and The first substrate and the second substrate are stacked, wherein the charge retention unit has a plurality of through-connection conductors, the through-connection conductors penetrating the bonding interface between the first substrate and the second substrate and used to electrically connect the control electrode of the amplifying transistor and the charge storage region to each other; Here, one or more dielectric materials are provided as insulating films around each of the plurality of through-hole connection conductors.

2. The photoelectric conversion element according to claim 1, wherein The charge holding unit connected to the output side of the charge storage region is provided in a portion of an electrical path from the first substrate to the second substrate.

3. The photoelectric conversion element according to claim 2, wherein The photoelectric conversion unit includes a well region of a first conductivity type and a charge generation region of a second conductivity type for forming a pn junction with the well region. The charge storage region is provided on a surface of the well region opposite to a surface in contact with the charge generation region.

4. The photoelectric conversion element according to claim 3, wherein The charge retention unit includes: the through-connection conductor; the insulating film provided around the through-connection conductor; and a semiconductor layer of the second substrate, the semiconductor layer of the second substrate facing the through-connection conductor with the insulating film interposed therebetween.

5. A solid-state imaging device, wherein a plurality of pixels are arranged, each of the pixels comprising: A photoelectric conversion unit, used for converting an optical signal into a signal charge; a transfer gate structure connected to the photoelectric conversion unit and configured to transfer the signal charge; a charge storage region, to which the signal charge is transferred by the transfer gate structure; a charge holding unit having a capacitor structure, electrically connected to the charge storage region and configured to store the signal charge; and an amplifying transistor, a control electrode of the amplifying transistor being electrically connected to the charge storage region, wherein The photoelectric conversion unit, the transfer gate structure and the charge storage region are arranged on a first substrate, The amplifying transistor is provided on the second substrate, and The first substrate and the second substrate are stacked, wherein the charge retention unit has a plurality of through-connection conductors, the through-connection conductors penetrating the bonding interface between the first substrate and the second substrate and used to electrically connect the control electrode of the amplifying transistor and the charge storage region to each other; Here, one or more dielectric materials are provided as insulating films around each of the plurality of through-hole connection conductors.

6. The solid-state imaging device according to claim 5, wherein The charge holding unit connected to the output side of the charge storage region is provided in a portion of an electrical path from the first substrate to the second substrate.

7. The solid-state imaging device according to claim 6, wherein The photoelectric conversion unit includes a well region of a first conductivity type and a charge generation region of a second conductivity type for forming a pn junction with the well region. The charge storage region is provided on a surface of the well region opposite to a surface in contact with the charge generation region.

8. The solid-state imaging device according to claim 7, wherein The charge retention unit includes: the through-connection conductor; the insulating film provided around the through-connection conductor; and a semiconductor layer of the second substrate, the semiconductor layer of the second substrate facing the through-connection conductor with the insulating film interposed therebetween.

9. The solid-state imaging device according to any one of claims 5 to 8, wherein A third substrate is bonded to the second substrate so that the main surface facing the second substrate is located on the opposite side of the main surface facing the first substrate, the third substrate has a logic circuit for performing signal processing of the electrical signal output from the second substrate, and the first substrate, the second substrate and the third substrate electrically connected to each other constitute a three-layer stacked structure.

10. An electronic device including a solid-state imaging device, wherein: The solid-state imaging device is the solid-state imaging device according to any one of claims 5 to 9.

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