Light emitting device and display device having the same

Abstract

A light emitting device according to an embodiment of the present invention includes: a light emitting area; an insulating pattern arranged in the light emitting area and including at least one recess and a protrusion surrounding the recess; a first electrode arranged on the insulating pattern and overlapping with a first area of ​​the recess and a protrusion adjacent to the first area; a second electrode arranged on the insulating pattern to be separated from the first electrode by a predetermined distance in a first direction and overlapping with a second area of ​​the recess and a protrusion adjacent to the second area; and a light emitting diode arranged inside the recess and electrically connected between the first electrode and the second electrode.

Description

Technical Field

[0001] Various embodiments of the present disclosure are directed to a light emitting device and a display apparatus including the same. Background Art

[0002] Recently, a technology for manufacturing an ultra-small light-emitting diode using a material having a reliable inorganic crystal structure and manufacturing a light-emitting device using the light-emitting diode has been developed. For example, a technology for manufacturing an ultra-small light-emitting diode having a small size corresponding to a range from a nanometer level to a micrometer level and forming a light source of a light-emitting device using the ultra-small light-emitting diode has been developed. Such a light-emitting device can be provided in various electronic devices such as display devices and lighting devices. Summary of the invention

[0003] Technical issues

[0004] Various embodiments of the present disclosure are directed to a light emitting device including a light emitting diode and a display apparatus including the light emitting device.

[0005] Technical Solution

[0006] According to the present disclosure, a light-emitting device may include: a light-emitting area; an insulating pattern, which is arranged in the light-emitting area and includes at least one recess and a protrusion configured to surround the recess; a first electrode, which is arranged on the insulating pattern and is configured to overlap with a first area of ​​the recess and a protrusion in a periphery of the first area; a second electrode, which is arranged on the insulating pattern and is spaced apart from the first electrode by a predetermined distance in a first direction and is configured to overlap with a second area of ​​the recess and a protrusion in a periphery of the second area; and a light-emitting diode, which is arranged in the recess and is electrically connected between the first electrode and the second electrode.

[0007] In an embodiment, the recess may include an inclined surface having an inclination within a predetermined angle range in a peripheral region thereof adjacent to the protrusion.

[0008] In an embodiment, each of the first electrode and the second electrode may include a bent portion having a bent shape at each of an upper end and a lower end of the inclined surface.

[0009] In an embodiment, the recess may have a circular shape, an elliptical shape, a polygonal shape, or a combination thereof in a plan view.

[0010] In an embodiment, the recess may include an opening.

[0011] In an embodiment, the recess may have a width in the first direction that is greater than a length of the light emitting diode.

[0012] In an embodiment, the recess may have the same width in a first direction and in a second direction perpendicular to the first direction.

[0013] In an embodiment, the light emitting diode may include a rod-type light emitting diode including a first end and a second end disposed at opposite ends thereof in a longitudinal direction.

[0014] In an embodiment, the light emitting device may further include: a first contact electrode, disposed on a first end of the light emitting diode and a region of the first electrode, and configured to electrically connect the first end to the first electrode; and a second contact electrode, disposed on a second end of the light emitting diode and a region of the second electrode, and configured to electrically connect the second end to the second electrode.

[0015] In an embodiment, the light emitting device may further include a first insulating layer interposed between the light emitting diode and the first electrode and the second electrode and configured to expose the one region of each of the first electrode and the second electrode.

[0016] In an embodiment, the light emitting device may further include a reflective electrode disposed on the first insulating layer at a position adjacent to the light emitting diode and including an opening corresponding to the light emitting diode.

[0017] In an embodiment, each of the first electrode and the second electrode may extend in a second direction intersecting the first direction, and the reflective electrode may include at least one first direction pattern extending in the first direction to intersect the first electrode and the second electrode.

[0018] In an embodiment, the insulating layer pattern may include a plurality of recesses dispersed at predetermined intervals. At least one light emitting diode may be disposed in each of the plurality of recesses.

[0019] A display device according to an embodiment of the present disclosure may include: a display area; and a pixel, which is arranged in the display area and includes a light-emitting area. The pixel may include: an insulating pattern, which is arranged in the light-emitting area and includes at least one recess and a protrusion configured to surround the recess; a first electrode, which is arranged on the insulating pattern and is configured to overlap with a first area of ​​the recess and a protrusion in the periphery of the first area; a second electrode, which is arranged on the insulating pattern and is spaced a predetermined distance from the first electrode in the first direction, and is configured to overlap with a second area of ​​the recess and a protrusion in the periphery of the second area; and a light-emitting diode, which is arranged in the recess and is electrically connected between the first electrode and the second electrode.

[0020] In an embodiment, the recess may include an inclined surface having an inclination within a predetermined angle range in a peripheral region thereof adjacent to the protrusion. Each of the first electrode and the second electrode may include a bent portion having a bent shape at each of an upper end and a lower end of the inclined surface.

[0021] In an embodiment, the recess may have a circular shape, an elliptical shape, a polygonal shape, or a combination thereof in a plan view.

[0022] In an embodiment, the recess may include an opening.

[0023] In an embodiment, the recess may have a width in the first direction that is greater than a length of the light emitting diode.

[0024] In an embodiment, the pixel may include at least one of the following: a first insulating layer disposed between the light emitting diode and the first electrode and the second electrode, and including an opening formed to expose an area of ​​each of the first electrode and the second electrode; and a reflective electrode disposed on the first insulating layer at a position adjacent to the light emitting diode, and including an opening corresponding to the light emitting diode.

[0025] In an embodiment, the insulating pattern may include a plurality of recesses dispersed at predetermined intervals in the light emitting region. At least one light emitting diode may be disposed in each of the plurality of recesses.

[0026] Beneficial Effects

[0027] In the light emitting device and the display apparatus including the same according to various embodiments of the present disclosure, the efficiency of light emitted from each light emitting region may be improved, and the degree of alignment of light emitting diodes may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a and Figure 1b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting diode according to an embodiment of the present disclosure.

[0029] Figure 2a and Figure 2b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting diode according to an embodiment of the present disclosure.

[0030] Figure 3a and Figure 3b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting diode according to an embodiment of the present disclosure.

[0031] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0032] Figure 5a to Figure 5cEach is a circuit diagram showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, different embodiments of active pixels including the light emitting device.

[0033] Figure 6a and Figure 6b Each is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, different embodiments of a pixel including a light source unit formed of the light emitting device.

[0034] Figure 7 It shows that according to Figure 6a and Figure 6b A plan view of an insulating pattern of an embodiment.

[0035] Figure 8a and Figure 8b Each of them is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Figure 6b Line II' corresponds to different embodiments of the cross section.

[0036] Fig. 9 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Figure 6b An embodiment of a cross section corresponding to line II-II'.

[0037] Fig.10 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Figure 6b The line III-III' corresponds to an embodiment of a cross section.

[0038] Fig.11 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel including a light source unit formed of the light emitting device.

[0039] Fig.12 It shows that according to Fig.11 A plan view of an insulating pattern of an embodiment.

[0040] Fig.13a and Fig.13b Each of them is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Fig.11 Line IV-IV' corresponds to different embodiments of the cross section.

[0041] Fig.14 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Fig.11 An embodiment of a cross section corresponding to line V-V'.

[0042] Fig.15is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Fig.11 An embodiment of a cross section corresponding to line VI-VI'.

[0043] Fig.16 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel including a light source unit formed of the light emitting device.

[0044] Fig.17 It shows that according to Fig.16 A plan view of an insulating pattern of an embodiment.

[0045] Fig.18 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, Fig.16 and Fig.17 Modifications related to the insulation pattern.

[0046] Fig.19 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel including a light source unit formed of the light emitting device.

[0047] Fig. 20 It shows that according to Fig.19 A plan view of an insulating pattern of an embodiment.

[0048] Fig.21 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, Fig.19 and Fig. 20 Modifications related to the insulation pattern.

[0049] Fig. 22 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel including a light source unit formed of the light emitting device.

[0050] Fig.23 It shows that according to Fig. 22 A plan view of a reflective electrode of an embodiment.

[0051] Fig.24 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Fig. 22 An embodiment of a cross section corresponding to line VII-VII'. DETAILED DESCRIPTION

[0052] Since the embodiments of the present disclosure can be variously modified in many different forms, reference will now be made in detail to the various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below. However, the present disclosure is not limited to the following embodiments and can be modified in various forms.

[0053] Some elements that are not directly related to the features of the present disclosure in the drawings may be omitted to clearly explain the present disclosure. In addition, the sizes, proportions, etc. of some elements in the drawings may be slightly exaggerated. It should be noted that throughout the drawings, the same reference numerals are used to represent the same or similar elements, and repeated descriptions will be omitted.

[0054] It will be understood that, although the terms "first", "second", etc. can be used here to describe various elements, these elements should not be limited by these terms. It will also be understood that when the terms "including", "comprising", "having", etc. are used in the present disclosure, it is explained that there are stated features, wholes, steps, operations, elements, components and / or combinations thereof, but it is not excluded that there are or add one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, when a first component or part is arranged on a second component or part, the first component or part can not only be directly on the second component or part, but a third component or part can be between the first component or part and the second component or part. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they can be changed to opposite positions or directions according to the viewing angle or direction.

[0055] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings to describe the present disclosure in detail so that those skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

[0056] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 is a perspective view and a cross-sectional view showing a light emitting diode LD according to an embodiment of the present disclosure. Figures 1a to 3b A cylindrical rod-type light emitting diode LD is illustrated, but the type and / or shape of the light emitting diode LD according to the present disclosure is not limited thereto.

[0057] Reference Figure 1a and Figure 1b , the light emitting diode LD according to the embodiment of the present disclosure may include a first conductive type semiconductor layer (also referred to as "first semiconductor layer") 11, a second conductive type semiconductor layer (also referred to as "second semiconductor layer") 13, and an active layer 12 disposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. For example, the light emitting diode LD may be composed of a stacked body formed by sequentially stacking the first conductive type semiconductor layer 11, the active layer 12, and the second conductive type semiconductor layer 13.

[0058] In an embodiment, the light emitting diode LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting diode LD extends is defined as a longitudinal direction, the light emitting diode LD may have a first end and a second end with respect to the longitudinal direction.

[0059] In an embodiment, one of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a first end of the light emitting diode LD, and the other of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a second end of the light emitting diode LD.

[0060] In an embodiment, the light emitting diode LD may be a rod-type light emitting diode manufactured in the form of a rod. In the present disclosure, the term "rod-type" includes rod-like shapes and strip-like shapes such as cylindrical and prismatic shapes extending in the longitudinal direction (i.e., having an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting diode LD may be greater than its diameter D (or the width of its cross section).

[0061] In an embodiment, the light emitting diode LD may have a small size corresponding to a size ranging from a nanometer size to a micrometer size, for example, a diameter D and / or a length L in the range of nanometer to micrometer. However, in the present disclosure, the size of the light emitting diode LD is not limited thereto. For example, the size of the light emitting diode LD may be changed in various ways according to the design conditions of various devices (for example, display devices) each of which adopts a light emitting device using the light emitting diode LD as a light source.

[0062] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material used to form the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0063] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0064] If an electric field of a predetermined voltage or higher is applied to opposite ends of the light emitting diode LD, the light emitting diode LD emits light by a combination of electron-hole pairs in the active layer 12. Since the light emission of the light emitting diode LD can be controlled based on the aforementioned principle, the light emitting diode LD can be used as a light source for various light emitting devices and pixels of a display device.

[0065] The second conductive type semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive type semiconductor layer 11. For example, the second conductive type semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive type semiconductor layer 13 may include a p-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials and doped with a second conductive dopant such as Mg. However, the material for forming the second conductive type semiconductor layer 13 is not limited thereto, and the second conductive type semiconductor layer 13 may be formed of various other materials.

[0066] In an embodiment, the light emitting diode LD may further include an insulating film INF disposed on the surface of the light emitting diode LD. In an embodiment, the insulating film INF may be formed on the surface of the light emitting diode LD to surround at least the outer peripheral surface of the active layer 12. In addition, the insulating film INF may also surround a region of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light emitting diode LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 disposed on the corresponding opposite ends relative to the longitudinal direction of the light emitting diode LD, for example, the two bottom surfaces of the cylinder (at Figure 1a and Figure 1b In the embodiment, the top surface and the bottom surface of the light emitting diode LD are covered instead of covering the two bottom surfaces.

[0067] In an embodiment, the insulating film INF may include SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various well-known insulating materials.

[0068] In an embodiment, the light emitting diode LD may further include additional components in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13 and / or the insulating film INF. For example, the light emitting diode LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer and / or at least one electrode layer disposed on one end of the first conductive semiconductor layer 11, the active layer 12 and / or the second conductive semiconductor layer 13.

[0069] For example, Figure 2a and Figure 2b As shown in , the light emitting diode LD may further include at least one electrode layer 14 disposed on one end of the second conductive type semiconductor layer 13. In an embodiment, as shown in Figure 3a and Figure 3b As shown in , the light emitting diode LD may further include at least one electrode layer 15 disposed on one end of the first conductive type semiconductor layer 11 .

[0070] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, Cr, Ti, Al, Au, Ni, an oxide or alloy thereof, and ITO, IZO, ITZO may be used alone or in combination with one another. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Therefore, the light generated from the light emitting diode LD may be emitted from the light emitting diode LD after passing through the electrode layers 14 and 15.

[0071] In an embodiment, the insulating film INF may at least partially surround the peripheral surface of the electrode layers 14 and 15, or may not surround the peripheral surface. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to allow the opposite ends of the light emitting diode LD having different polarities to be exposed, for example, to allow at least one region of each of the electrode layers 14 and 15 to be exposed. Alternatively, in an embodiment, the insulating film INF may not be provided.

[0072] If the insulating film INF is provided on the surface of the light emitting diode LD (specifically, on the surface of the active layer 12), the active layer 12 can be prevented from being short-circuited with at least one electrode not shown (for example, at least one of the contact electrodes connected to the opposite ends of the light emitting diode LD). Therefore, the electrical stability of the light emitting diode LD can be ensured.

[0073] In addition, due to the insulating film INF formed on the surface of the light emitting diode LD, the occurrence of defects on the surface of the light emitting diode LD can be minimized, so that the life and efficiency of the light emitting diode LD can be improved. In addition, if the insulating film INF is formed on each light emitting diode LD, even when a plurality of light emitting diodes LD are arranged adjacent to each other, the light emitting diode LD can be prevented from being unexpectedly short-circuited.

[0074] In an embodiment of the present disclosure, the light emitting diode LD may be manufactured by a surface treatment process. For example, each light emitting diode LD may be surface treated so that when a plurality of light emitting diodes LD are mixed with a fluid solution and then supplied to each light emitting region (e.g., the light emitting region of each pixel), the light emitting diodes LD may be uniformly dispersed rather than unevenly aggregated in the solution. For example, the surface of the light emitting diode LD may be coated with a predetermined material.

[0075] The light emitting device including the above-mentioned light emitting diode LD can be used in various devices including a display device requiring a light source. For example, at least one ultra-small light emitting diode LD (for example, a plurality of ultra-small light emitting diodes LD each having a size ranging from nanometers to micrometers) can be arranged in each pixel area of ​​the display panel to form a light source (or light source unit) of the corresponding pixel. In addition, the application field of the light emitting diode LD according to the present disclosure is not limited to display devices. For example, the light emitting diode LD can also be used in various devices such as lighting devices requiring a light source.

[0076] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device (specifically, a display panel PNL provided in the display device) is shown as a reference device that can be used. Figures 1a to 3b The light emitting diode LD is described as an example of a device of a light source. For example, each pixel PXL of the display panel PNL may include a light emitting device. The light emitting device may include at least one light emitting diode LD.

[0077] For illustration purposes, Figure 4 The structure of the display panel PNL according to the embodiment is simply shown focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided on the display panel PNL.

[0078] Reference Figure 4, the display panel PNL according to an embodiment of the present disclosure may include a base layer BSL and a plurality of pixels PXL disposed on the base layer BSL. In detail, the display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA formed in a predetermined area other than the display area DA. The pixels PXL may be disposed in the display area DA on the base layer BSL.

[0079] In an embodiment, the display area DA may be disposed in the central area of ​​the display panel PNL, and the non-display area NDA may be disposed in the peripheral area of ​​the display panel PNL in a manner of surrounding the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0080] The base layer BSL may form a base of the display panel PNL. In an embodiment, the base layer BSL may be a rigid or flexible substrate or film, and its material or properties are not specifically limited. For example, the base layer BSL may be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and its material and / or properties are not specifically limited.

[0081] In addition, the base layer BSL may be transparent, but the present disclosure is not limited thereto. For example, the base layer BSL may be a transparent base, a semi-transparent base, an opaque base, or a reflective base.

[0082] One area on the base layer BSL is defined as a display area DA in which the pixels PXL are disposed, and another area thereof is defined as a non-display area NDA. For example, the base layer BSL may include a display area DA including a plurality of pixel areas in which corresponding pixels PXL are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or internal circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0083] In an embodiment, the pixels PXL may be distributed and arranged in the display area DA. In an embodiment, the pixels PXL may be arranged in stripes or The arrangement structure is arranged in the display area DA. However, the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in the display area DA in various known arrangement manners.

[0084] Each pixel PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and / or a power voltage (eg, a first power voltage and a second power voltage), for example, according to Figures 1a to 3bThe light emitting diode LD of any one of the embodiments of the present invention. For example, each pixel PXL may include at least one light emitting diode LD having a small size ranging from nanometer level to micrometer level. For example, each pixel PXL may include a plurality of rod-type light emitting diodes connected in parallel between the pixel electrodes and / or the power lines. A plurality of rod-type light emitting diodes may form a light emitting device of each pixel PXL (e.g., a light source or a light source unit of each pixel PXL).

[0085] In an embodiment, each pixel PXL may be formed by an active pixel. However, the type, structure and / or driving scheme of the pixel PXL applicable to the display device according to the present disclosure is not specifically limited. For example, each pixel PXL may have the same structure as that of a pixel of various known passive light-emitting display devices or active light-emitting display devices.

[0086] Figure 5a to Figure 5c is a circuit diagram showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, different embodiments of an active pixel PXL including a light emitting device. In the embodiment, Figure 5a to Figure 5c Each pixel PXL shown in FIG. 1 may be set to Figure 4 The pixels PXL may have substantially the same or similar structures.

[0087] Reference Figure 5a The pixel PXL according to an embodiment of the present disclosure may include a light source unit LSU configured to generate light having brightness corresponding to a data signal and a pixel circuit PXC configured to drive the light source unit LSU. The light source unit LSU may form a light emitting device according to an embodiment of the present disclosure.

[0088] In an embodiment, the light source unit LSU may include a plurality of light emitting diodes LD electrically connected between a first power source VDD and a second power source VSS. In an embodiment, the light emitting diodes LD may be connected in parallel with each other, but the present disclosure is not limited thereto. For example, in an embodiment, the plurality of light emitting diodes LD may be connected between the first power source VDD and the second power source VSS in a series / parallel combination structure.

[0089] In an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light emitting diode LD can emit light. For example, the first power supply VDD may be set to a high potential power supply, and the second power supply VSS may be set to a low potential power supply. Here, at least during the light emitting period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting diode LD or greater.

[0090] although Figure 5aAn embodiment is shown in which the light emitting diodes LD of the light source unit LSU forming each pixel PXL are connected in parallel to each other in the same direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS, but the present disclosure is not limited thereto. For example, in an embodiment, some light emitting diodes LD may be connected to each other in a first direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS, while other light emitting diodes LD may be connected to each other in a second direction (e.g., in the reverse direction). Alternatively, in an embodiment, at least one pixel PXL may include only a single light emitting diode LD (e.g., a single effective light emitting diode connected in the forward direction between the first power supply VDD and the second power supply VSS).

[0091] In an embodiment, a first end of the light emitting diode LD forming each light source unit LSU may be commonly connected to a pixel circuit PXC through a first electrode (also referred to as a "first pixel electrode" or a "first alignment electrode") of the light source unit LSU, and may be commonly connected to a first power source VDD through the pixel circuit PXC and a first power line PL1. A second end of the light emitting diode LD may be commonly connected to a second power source VSS through a second electrode (also referred to as a "second pixel electrode" or a "second alignment electrode") of the light source unit LSU and a second power line PL2.

[0092] Each light source unit LSU may emit light having brightness corresponding to a driving current supplied thereto through a corresponding pixel circuit PXC. Thus, a predetermined image may be displayed in the display area DA.

[0093] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed on the i-th row (i is a natural number) and the j-th column (j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0094] The first transistor (also referred to as a "driving transistor") T1 is connected between the first power source VDD and the first electrode of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0095] The second transistor (also referred to as a "switching transistor") T2 may be connected between the data line Dj and the first node N1. The gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal of a gate-on voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj.

[0096] During each frame period, a data signal of a corresponding frame is supplied to the data line Dj. The data signal is transmitted to the first node N1 via the second transistor T2. Therefore, a voltage corresponding to the data signal is charged to the storage capacitor Cst.

[0097] One electrode of the storage capacitor Cst is connected to the first power source VDD, and the other electrode of the storage capacitor Cst is connected to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal to be supplied to the first node N1 during each frame period.

[0098] Despite Figure 5a In the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, any one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0099] For example, Figure 5b As shown in FIG. 1 , both the first transistor T1 and the second transistor T2 can be formed by N-type transistors. In addition to the fact that the connection positions of some circuit elements change according to the change of the type of transistor, Figure 5b The construction and operation of the pixel PXL shown in FIG. Figure 5a The structure and operation of the pixel PXL are basically similar. Therefore, Figure 5b A detailed description of the pixel PXL.

[0100] The structure of the pixel circuit PXC is not limited to Figure 5a and Figure 5b In other words, the pixel circuit PXC may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. For example, the pixel circuit PXC may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. Figure 5c The embodiment shown in FIG. 1 is constructed in the same manner.

[0101] Reference Figure 5c, the pixel circuit PXC can be connected not only to the scan line Si of the corresponding horizontal row, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL arranged in the i-th row of the display area DA can also be connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to the third power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0102] The first transistor T1 is connected between the first power source VDD and the first electrode of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0103] The second transistor T2 is connected between the data line Dj and one electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal of a gate-on voltage is supplied from the scan line Si, the second transistor T2 can be turned on so that the data line Dj is electrically connected to the one electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line Dj can be transmitted to the first transistor T1.

[0104] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal of a gate-on voltage is supplied from the scan line Si, the third transistor T3 can be turned on to electrically connect the first transistor T1 in the form of a diode.

[0105] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. When the scan signal of the gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint may be the minimum voltage of the data signal or less.

[0106] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 can be turned off when the emission control signal of the gate cut-off voltage (for example, a high voltage) is supplied to the emission control line Ei, and can be turned on in other cases.

[0107] The sixth transistor T6 is connected between the first transistor T1 and the second node N2 connected to the first electrode of the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 can be turned off when the emission control signal of the gate-off voltage is supplied to the emission control line Ei, and can be turned on in other cases.

[0108] The seventh transistor T7 is connected between the second node N2 and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal of a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU.

[0109] The storage capacitor Cst may be connected between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal applied to the first node N1 during each frame period and a threshold voltage of the first transistor T1.

[0110] Despite Figure 5c The transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0111] The structure of the pixel PXL applicable to the present disclosure is not limited to Figure 5a to Figure 5c The embodiment shown in , and each pixel PXL may have various well-known structures. For example, the pixel circuit PXC included in each pixel PXL may be formed by a well-known pixel circuit that may have various structures and / or operate through various driving schemes. In an embodiment of the present disclosure, each pixel PXL may be constructed in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first pixel electrode and the second pixel electrode of the light source unit LSU may be directly connected to the scan line Si, the data line Dj, the power line and / or the control line.

[0112] Figure 6a and Figure 6b1 and 2 are plan views showing a light emitting device according to an embodiment of the present disclosure, and for example show different embodiments of a pixel PXL including a light source unit LSU formed by a light emitting device. In the embodiment, the pixel PXL may be Figure 5a to Figure 5c Any one pixel PXL shown in FIG. 1 may be used, but the present disclosure is not limited thereto. Figure 7 It shows that according to Figure 6a and Figure 6b A plan view of an insulation pattern INP of an embodiment.

[0113] Although for illustrative purposes, Figure 6a and Figure 6b Only the display element layer on which the light source unit LSU is disposed is shown, but each pixel PXL may further selectively include a circuit element configured to control the light source unit LSU (eg, a circuit element for forming a Figure 5a to Figure 5c At least one circuit element of the pixel circuit PXC). In addition, in an embodiment, Figure 6a and Figure 6b An embodiment in which the light source unit LSU is connected to a predetermined power line (e.g., a first power line PL1 and / or a second power line PL2), a circuit element (e.g., at least one circuit element forming a pixel circuit PXC), and / or a signal line (e.g., a scan line Si and / or a data line Dj) through a first contact hole CH1 and a second contact hole CH2 is shown, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one of the first electrode ELT1 and the second electrode ELT2 provided in the light emitting device may be directly connected to a predetermined power line and / or a signal line without passing through a contact hole and / or an intermediate line.

[0114] Reference Figures 6a to 7 , the light emitting device and the pixel PXL including the light emitting device according to the embodiment of the present disclosure may include a predetermined light emitting area EMA, at least one first electrode ELT1 and at least one second electrode ELT2 disposed in the light emitting area EMA, and at least one light emitting diode LD connected between the first electrode ELT1 and the second electrode ELT2. For example, the pixel PXL may include a plurality of light emitting diodes LD connected in series and / or in parallel to each other between the first electrode ELT1 and the second electrode ELT2. In addition, the pixel PXL may further include an insulating pattern INP disposed in the light emitting area EMA and disposed to overlap the first electrode ELT1 and the second electrode ELT2. In an embodiment, the insulating pattern INP may be disposed under the first electrode ELT1 and the second electrode ELT2 and the light emitting diode LD.

[0115] In addition, the pixel PXL may further selectively include at least one first contact electrode CNE1 disposed to overlap each first electrode ELT1 and / or at least one second contact electrode CNE2 disposed to overlap each second electrode ELT2. Figure 6a As shown in FIG. 1 , the pixel PXL according to the embodiment may not include the first contact electrode CNE1 and the second contact electrode CNE2. In this case, the light emitting diode LD may be directly connected to the first electrode ELT1 and the second electrode ELT2. Figure 6b As shown in , the pixel PXL according to the embodiment may include the first contact electrode CNE1 and the second contact electrode CNE2. In this case, the light emitting diode LD may be connected to the first electrode ELT1 and the second electrode ELT2 through the first contact electrode CNE1 and the second contact electrode CNE2, or directly connected to the first contact electrode CNE1 and the second contact electrode CNE2 and the first electrode ELT1 and the second electrode ELT2.

[0116] The light emitting area EMA may be an area in which a light emitting diode LD of a light source unit LSU forming a pixel PXL (specifically, an effective light emitting diode effectively connected between the first electrode ELT1 and the second electrode ELT2) is disposed. The light emitting area EMA may be surrounded by a light shielding bank or a reflective bank (also referred to as a "pixel defining layer") not shown.

[0117] The insulating pattern INP may include at least one recess RCS and a protrusion PTS protruding from the recess RCS. For example, the insulating pattern INP may include a plurality of recess RCSs dispersed at predetermined intervals in the light emitting area EMA in the first direction DR1 and the second direction DR2. In an embodiment, the recess RCS may be uniformly dispersed in the light emitting area EMA. For example, the recess RCS may be uniformly distributed in the first direction DR1 and / or the second direction DR2 at predetermined intervals. In an embodiment, a plurality of recess RCSs may be unevenly dispersed in the insulating pattern INP.

[0118] In an embodiment, each recessed RCS may be disposed in an area including an area formed between the first electrode ELT1 and the second electrode ELT2. In addition, when at least one light emitting diode LD is oriented in a first direction DR1 (e.g., a horizontal direction) intersecting the first electrode ELT1 and the second electrode ELT2 and connected between a pair of first electrodes ELT1 and the second electrode ELT2 corresponding to each other, each recessed RCS may have a first width W1 greater than the length of each light emitting diode LD in at least the first direction DR1. In addition, in an embodiment, each recessed RCS may have a second width W2 equal to the first width W1 in a second direction DR2 (e.g., a vertical direction) intersecting the first direction DR1 (e.g., perpendicular to the first direction DR1). For example, each recessed RCS may have a circular shape in a plan view. However, the shape of the recessed RCS may be changed in various ways. For example, in a plan view, each recessed RCS may have a circular shape, an elliptical shape, a polygonal shape, or a combination thereof.

[0119] The surface of the insulating pattern INP may have an uneven profile by the recesses RCS and the protrusions PTS. The first and second electrodes ELT1 and ELT2 and the light emitting diode LD may be disposed on the insulating pattern INP.

[0120] The first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other and disposed such that at least portions thereof face each other. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed on a base layer ( Figure 4 The first electrode ELT1 and the second electrode ELT2 may be arranged in parallel at positions spaced apart from each other by a predetermined distance in the first direction DR1. For example, the first electrode ELT1 and the second electrode ELT2 may be arranged in the light emitting area EMA at positions spaced apart from each other by a predetermined distance in the first direction DR1, and each electrode may have a strip shape extending in a second direction DR2 intersecting with the first direction DR1 (perpendicular to the first direction DR1). However, the present disclosure is not limited thereto, and the shapes and / or relative arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0121] Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure. For example, each first electrode ELT1 may include at least one reflective electrode layer, and optionally further include at least one transparent electrode layer and / or a conductive cover layer. Similarly, each second electrode ELT2 may include at least one reflective electrode layer, and optionally further include at least one transparent electrode layer and / or a conductive cover layer.

[0122] In an embodiment, the first electrode ELT1 may be electrically connected to a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., a first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line) through the first connection electrode CNL1 and the first contact hole CH1. For example, the first electrode ELT1 may be electrically connected to a predetermined circuit element disposed thereunder through the first connection electrode CNL1 and the first contact hole CH1. Alternatively, in an embodiment, the first electrode ELT1 may be directly connected to a predetermined power line or signal line without passing through the first connection electrode CNL1, the first contact hole CH1, and / or the circuit element. In this case, the first electrode ELT1 may be connected to the predetermined power line or signal line integrally or non-integrally.

[0123] In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may extend in different directions. For example, when the first connection electrode CNL1 extends in the first direction DR1, the first electrode ELT1 may extend in the second direction DR2 intersecting the first direction DR1.

[0124] In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may be integrally connected to each other. For example, the first electrode ELT1 may be branched from the first connection electrode CNL1 in at least one manner. In the case where the first electrode ELT1 and the first connection electrode CNL1 are integrally connected to each other, the first connection electrode CNL1 may be considered as a region of the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may be formed separately and electrically connected to each other through at least one contact hole or through hole, etc.

[0125] In an embodiment, the second electrode ELT2 may be electrically connected to a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., a second power line PL2) and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line) through the second connection electrode CNL2 and the second contact hole CH2. For example, the second electrode ELT2 may be electrically connected to a second power line PL2 disposed thereunder through the second connection electrode CNL2 and the second contact hole CH2. Optionally, in an embodiment, the second electrode ELT2 may be directly connected to a predetermined power line or signal line without passing through the second connection electrode CNL2 and / or the second contact hole CH2. In this case, the second electrode ELT2 may be connected to the predetermined power line or signal line integrally or non-integrally.

[0126] In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may extend in different directions. For example, when the second connection electrode CNL2 extends in the first direction DR1, the second electrode ELT2 may extend in the second direction DR2 intersecting the first direction DR1.

[0127] In an embodiment, the second electrode ELT2 may be integrally connected to the second connection electrode CNL2. For example, the second electrode ELT2 may branch from the second connection electrode CNL2 in at least one manner. In the case where the second electrode ELT2 and the second connection electrode CNL2 are integrally connected to each other, the second connection electrode CNL2 may be considered as a region of the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may be formed separately and electrically connected to each other through at least one contact hole or through hole, etc.

[0128] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed on the insulating pattern INP and arranged to overlap different regions of at least one recessed RCS formed in the insulating pattern INP. For example, each first electrode ELT1 may overlap a first region AR1 of at least one recessed RCS from among a plurality of recessed RCSs formed in the insulating pattern INP and a protrusion PTS in the periphery of the first region AR1. Each second electrode ELT2 may overlap a second region AR of at least one recessed RCS and a protrusion PTS in the periphery of the second region AR2. In an embodiment, each second region AR2 may be an area facing away from the corresponding first region AR1. For example, each recessed RCS may include a first region AR1 and a second region AR2, the first region AR1 overlapping the first electrode ELT1, and the second region AR2 being disposed at a position opposite to the first region AR1 and overlapping the second electrode ELT2 corresponding to the first electrode ELT1.

[0129] The first electrode ELT1 and the second electrode ELT2 may each have an uneven portion corresponding to the shape of the insulating pattern INP. For example, the first electrode ELT1 and the second electrode ELT2 may each be recessed downward in a region corresponding to the recess RCS of the insulating pattern INP and protrude upward in a region corresponding to the protrusion PTS of the insulating pattern INP. The first electrode ELT1 and the second electrode ELT2 may each have an inclined surface or a curved surface corresponding to the contour of the insulating pattern INP in a boundary region between the recess RCS and the protrusion PTS of the insulating pattern INP.

[0130] At least one light emitting diode LD may be disposed in each light emitting area EMA in which the insulating pattern INP and the first and second electrodes ELT1 and ELT2 are disposed. For example, at least one light emitting diode LD may be disposed in each recess RCS. For example, at least one light emitting diode LD may be disposed in the recess RCS so that at least one light emitting diode LD is surrounded by any one recess RCS.

[0131] In an embodiment, when the insulating pattern INP includes a plurality of recessed RCSs, at least one light emitting diode LD may be disposed in each of the recessed RCSs. However, the present disclosure is not limited thereto. For example, in an embodiment, at least one light emitting diode LD may be disposed only in some of the plurality of recessed RCSs.

[0132] Each light emitting diode LD may be electrically connected between the first electrode ELT1 and the second electrode ELT2 corresponding to each other. For example, each light emitting diode LD may be a rod-type light emitting diode having a longitudinal direction. In addition, the light emitting diode LD may include a first end EP1 and a second end EP2, the first end EP1 being disposed on one end of the light emitting diode LD in the longitudinal direction and being electrically connected to the first electrode ELT1, and the second end EP2 being disposed on the other end of the light emitting diode LD in the longitudinal direction and being electrically connected to the second electrode ELT2. For example, in a region in which the first electrode ELT1 and the second electrode ELT2 corresponding to each other are disposed to face each other (for example, in each recess RCS), each light emitting diode LD may be arranged between the first electrode ELT1 and the second electrode ELT2 in a horizontal direction along the first direction DR1.

[0133] although Figure 6a and Figure 6b The light emitting diodes LD are shown to be uniformly oriented in any one direction (e.g., in the first direction DR1), but the present disclosure is not limited thereto. For example, at least one of the light emitting diodes LD may be oriented in a diagonal direction between the first electrode ELT1 and the second electrode ELT2. Figure 6a and Figure 6b Not shown, but at least one ineffective light emitting diode that is not completely connected between the first electrode ELT1 and the second electrode ELT2 may be further provided in each light emitting area EMA and / or in a peripheral area of ​​the light emitting area EMA.

[0134] In an embodiment, each light emitting diode LD may be a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size (eg, ranging from nanometer to micrometer). Figures 1a to 3bAs shown in , each light emitting diode LD may be an ultra-small rod-type light emitting diode having a diameter D and / or a length L ranging from nanometer level to micrometer level. However, the size of the light emitting diode LD may be changed in various ways according to the design conditions of each light emitting device (e.g., pixel PXL), etc.

[0135] In an embodiment, a first end EP1 of a light emitting diode LD (e.g., an effective light emitting diode completely connected between the first electrode ELT1 and the second electrode ELT2) may be electrically connected to the first electrode ELT1 via a first contact electrode CNE1. A second end EP2 of the light emitting diode LD may be connected to the second electrode ELT2 via a second contact electrode CNE2. In an embodiment, at least one of the first end EP1 and the second end EP2 of each light emitting diode LD may be in direct contact with the first electrode ELT1 and / or the second electrode ELT2, and may be electrically connected to the first electrode ELT1 and / or the second electrode ELT2.

[0136] In an embodiment, the light emitting diode LD may be prepared in a diffused form in a predetermined solution and then supplied to the light emitting area EMA by an inkjet scheme or the like. For example, the light emitting diode LD may be mixed with a volatile solvent and supplied to each light emitting area EMA. Here, if a predetermined alignment voltage (or alignment signal) is applied to the first electrode ELT1 and the second electrode ELT2, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting diode LD may be aligned between the first electrode ELT1 and the second electrode ELT2. After the light emitting diode LD has been aligned, the solvent may be removed by a volatilization scheme or other schemes. In this way, the light emitting diode LD may be reliably arranged between the first electrode ELT1 and the second electrode ELT2. In addition, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed on opposite ends (i.e., the first end EP1 and the second end EP2) of the light emitting diode LD, respectively. Therefore, the light emitting diode LD may be more reliably connected between the first electrode ELT1 and the second electrode ELT2.

[0137] In an embodiment, the first contact electrode CNE1 may be formed on the first end EP1 of the light emitting diode LD and at least one region of the first electrode ELT1, whereby the first end EP1 of the light emitting diode LD may be electrically connected to the first electrode ELT1. Similarly, the second contact electrode CNE2 may be formed on the second end EP2 of the light emitting diode LD and at least one region of the second electrode ELT2, whereby the second end EP2 of the light emitting diode LD may be electrically connected to the second electrode ELT2. In addition, the first contact electrode CNE1 and the second contact electrode CNE2 fix the first end EP1 and the second end EP2 of each light emitting diode LD, so that the light emitting diode LD may be prevented from being removed from its aligned position.

[0138] If the first end EP1 of the light emitting diode LD is connected to the first power source VDD via the first electrode ELT1 and / or the pixel circuit PXC, etc., and the second end EP2 of the light emitting diode LD is connected to the second power source VSS via the second electrode ELT2 and / or the second power line PL2, etc., at least one light emitting diode LD connected in the forward direction between the first electrode ELT1 and the second electrode ELT2 may emit light with brightness corresponding to the driving current supplied from the pixel circuit PXC, etc. Therefore, the pixel PXL may emit light.

[0139] Figure 8a and Figure 8b Each of them is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Figure 6b Line II' corresponds to different embodiments of the cross section. Fig. 9 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Figure 6b An embodiment of a cross section corresponding to line II-II'.

[0140] Reference Figures 6a to 9 According to an embodiment of the present disclosure, a light emitting device (e.g., a pixel PXL including a light source unit LSU formed by the light emitting device) may include a base layer BSL, an insulating pattern INP, first and second electrodes ELT1 and ELT2, a first insulating layer INS1, at least one light emitting diode LD, a second insulating layer INS2, first and second contact electrodes CNE1 and CNE2, and a third insulating layer INS3. In an embodiment, the light emitting device may further selectively include a pixel circuit layer PCL between the base layer BSL and the insulating pattern INP.

[0141] The pixel circuit layer PCL may include at least one circuit element (e.g., at least one transistor and / or capacitor) forming the pixel circuit PXC and at least one power line and / or signal line, etc. Here, in the case where the light emitting device is directly connected to the first power line PL1 and the second power line PL2 (or a predetermined signal line), the pixel circuit layer PCL may be omitted.

[0142] The insulating pattern INP may include an insulating material including an inorganic material or an organic material. For example, the insulating pattern INP may include an insulating material including an inorganic material or an organic material. x or SiO x At least one inorganic layer of various known inorganic insulating materials. Optionally, the insulating pattern INP may include at least one organic layer and / or a photoresist layer including various known organic insulating materials, or a single-layer insulator or a multi-layer insulator including an organic material / inorganic material combination may be formed. In the embodiments of the present disclosure, the constituent materials in the insulating pattern INP may be changed in various ways.

[0143] In an embodiment, the insulating pattern INP may function as a reflector. For example, the insulating pattern INP and the first and second electrodes ELT1 and ELT2 disposed thereon may function as a reflector to guide light emitted from each light emitting diode LD in a desired direction, thereby improving optical efficiency of the pixel PXL.

[0144] In an embodiment, the insulating pattern INP may include at least one recessed RCS in which a light emitting diode LD or the like is disposed and a protrusion PTS surrounding the recessed RCS. The recessed RCS may include an inclined surface having an inclination within a predetermined angle (θ) range in a peripheral region BOR adjacent to the protrusion PTS. In an embodiment, the insulating pattern INP may include a recessed RCS having an angle (θ) ranging from 40° to 50°. In this case, light emitted from opposite ends (i.e., the first end EP1 and the second end EP2) of the light emitting diode LD may be guided to travel in a forward direction (e.g., toward the front surface of the display panel PNL). Therefore, the optical efficiency of each light emitting device and the pixel PXL including the light emitting device may be improved.

[0145] However, the present disclosure is not limited to the aforementioned structure, and the shape of the insulating pattern INP may be changed in various ways. For example, in an embodiment of the present disclosure, the inclination range of the inclined surface may be changed, or a recessed RCS may be formed by recessing the insulating pattern INP so that at least one region of the insulating pattern INP has a smooth curved surface.

[0146] In an embodiment, in order to form a bend on the surface of the insulating pattern INP, during the process of forming the insulating pattern INP, the insulating pattern INP may be patterned at different heights in the region by at least two mask processes, or the insulating pattern INP may be patterned at different heights in the region by a single mask process using a halftone mask. In this way, the recess RCS and the protrusion PTS may be formed in the surface of the insulating pattern INP. In other words, the process of forming the insulating pattern INP is not specifically limited and may be changed in various ways according to the embodiment.

[0147] In an embodiment, a height difference between the recess RCS and the protrusion PTS may be set to a value sufficient to accommodate each light emitting diode LD in the recess RCS. In this case, the insulating pattern INP may surround all sides of the light emitting diode LD disposed in the recess RCS.

[0148] The first electrode ELT1 and the second electrode ELT2 may be disposed on the insulating pattern INP at positions spaced apart from each other. Figure 6a and Figure 6bAs shown in , the first electrode ELT1 and the second electrode ELT2 may be formed of strip-shaped electrodes arranged parallel to each other at positions spaced apart from each other by a predetermined distance in the first direction DR1. In this case, the manufacturing process may be easily performed. Here, the shapes of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways according to the embodiment.

[0149] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof), a conductive oxide (such as ITO, IZO, ZnO, or ITZO), and a conductive polymer (such as PEDOT); however, each of the first electrode ELT1 and the second electrode ELT2 is not limited thereto.

[0150] Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one reflective electrode layer. Each of the first electrode ELT1 and the second electrode ELT2 may also selectively include at least one of at least one transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive cover layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0151] In an embodiment, the reflective electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be formed of a conductive material having a constant reflectivity. For example, the reflective electrode layer may include at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and alloys thereof; however, the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various reflective conductive materials. Each of the first electrode ELT1 and the second electrode ELT2 including the reflective electrode layer may enable light emitted from opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting diodes LD to travel in a direction in which an image is displayed (e.g., in a forward direction). Specifically, if the first and second electrodes ELT1 and ELT2 have inclined surfaces or curved surfaces corresponding to the shape of the insulating pattern INP and are disposed to face the first and second ends EP1 and EP2 of the light emitting diodes LD, light emitted from the first and second ends EP1 and EP2 of each of the light emitting diodes LD may be reflected by the first and second electrodes ELT1 and ELT2 and thus further reliably travel in the forward direction of the display panel PNL (e.g., in the upward direction of the base layer BSL). Therefore, the efficiency of light emitted from the light emitting diodes LD may be improved.

[0152] In addition, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be formed of various transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, if the first electrode ELT1 and the second electrode ELT2 are both formed of a multilayer structure of two or more layers, the voltage drop caused by the signal delay (RC delay) may be minimized. Therefore, the desired voltage may be effectively transmitted to the light emitting diode LD.

[0153] In addition, if each of the first electrode ELT1 and the second electrode ELT2 includes a conductive cover layer covering the reflective electrode layer and / or the transparent electrode layer, it is possible to prevent the reflective electrode layer of the first electrode ELT1 and the second electrode ELT2 from being damaged due to defects caused during the manufacturing process of the pixel PXL. However, the conductive cover layer may be selectively included in the first electrode ELT1 and the second electrode ELT2, and may be omitted according to the embodiment. In addition, the conductive cover layer may be considered as a component of each of the first electrode ELT1 and the second electrode ELT2, or as a separate component disposed on the first electrode ELT1 and the second electrode ELT2.

[0154] In an embodiment, the first electrode ELT1 and the second electrode ELT2 corresponding to each other may be arranged to face each other with at least one recess RCS interposed therebetween. In addition, the first electrode ELT1 and the second electrode ELT2 may be arranged on the insulating pattern INP so that the first electrode ELT1 and the second electrode ELT2 overlap different regions of the recess RCS.

[0155] The first electrode ELT1 and the second electrode ELT2 may each have a curve corresponding to the surface profile of the insulating pattern INP. For example, the first electrode ELT1 and the second electrode ELT2 may include a first bend BP1 and a second bend BP2 having a curved shape on the upper and lower ends of the inclined surface connecting the recess RCS and the protrusion PTS of the insulating pattern INP, respectively. In an embodiment, the first bend BP1 formed on the first electrode ELT1 may have a shape symmetrical to the shape of the second bend BP2 formed on the second electrode ELT2. In this way, if the first electrode ELT1 and the second electrode ELT2 include the first bend BP1 and the second bend BP2, respectively, in the step of aligning the light emitting diode LD, the electric field generated between the first electrode ELT1 and the second electrode ELT2 may be further concentrated on the first bend BP1 and the second bend BP2. Therefore, the number of light emitting diodes LD moved into and / or around the recess RCS may be increased, so that the light emitting diode LD may be aligned between the first electrode ELT1 and the second electrode ELT2. Therefore, the alignment efficiency of the light emitting diode LD may be improved.

[0156] The first insulating layer INS1 may be formed to cover one region of each of the first electrode ELT1 and the second electrode ELT2, and may include an opening to expose another region of each of the first electrode ELT1 and the second electrode ELT2. In an embodiment, the first insulating layer INS1 may be mainly formed to cover the entire surface of the first electrode ELT1 and the second electrode ELT2. After the light emitting diode LD is supplied and aligned on the first insulating layer INS1 (for example, on the first insulating layer INS1 on the recess RCS), the first insulating layer INS1 may be patterned in the form of a separate pattern in which, as shown in FIG. Figure 8a As shown in FIG. 1 , the first insulating layer INS1 is partially opened to expose the first electrode ELT1 and the second electrode ELT2 in the predetermined first contact portion CNT1 and the second contact portion CNT2, respectively, or as shown in FIG. Figure 8b As shown in FIG. 1 , the first insulating layer INS1 is partially disposed under the light emitting diode LD.

[0157] In other words, the first insulating layer INS1 may be disposed between the first and second electrodes ELT1 and ELT2 and the light emitting diode LD, and may expose a region of each of the first and second electrodes ELT1 and ELT2. After forming the first and second electrodes ELT1 and ELT2, the first insulating layer INS1 may be formed to cover the first and second electrodes ELT1 and ELT2, so that the first and second electrodes ELT1 and ELT2 can be prevented from being damaged or metal can be prevented from being precipitated in a subsequent process. In addition, the first insulating layer INS1 may stably support each light emitting diode LD.

[0158] A plurality of light emitting diodes LD may be supplied to and aligned on each light emitting area EMA on which the first insulating layer INS1 is formed. For example, a plurality of light emitting diodes LD may be supplied to each light emitting area EMA through an inkjet scheme, and at least some of the light emitting diodes LD may be aligned in the recess RCS.

[0159] For example, in each recess RCS, at least one light emitting diode LD may be disposed. For example, the light emitting diode LD may be disposed on the first insulating layer INS1 on the recess RCS, and thus be surrounded by the recess RCS of the insulating pattern INP and / or the inclined surfaces (or curved surfaces) of the first electrode ELT1 and the second electrode ELT2 disposed on the recess RCS. In other words, in an embodiment, the recess RCS of the insulating pattern INP and the first electrode ELT1 and the second electrode ELT2 may surround the entire side wall of the light emitting diode LD. Therefore, the light emitted from the light emitting diode LD may be reflected by the recess RCS of the insulating pattern INP and the first electrode ELT1 and the second electrode ELT2, and travel in a forward direction (e.g., toward the front surface on which an image is displayed) of the light emitting device and the display device including the light emitting device.

[0160] Specifically, among the light emitting diodes LD disposed in the recess RCS, the first end EP1 of the light emitting diode LD oriented in the first direction DR1 including the predetermined error angle range may be disposed to face the inclined surface (or curved surface) formed on the first electrode ELT1 by the insulating pattern INP. In addition, the second end EP2 of the light emitting diode LD may be disposed to face the inclined surface (or curved surface) formed on the second electrode ELT2 by the insulating pattern INP. Each light emitting diode LD may emit light through the first end EP1 and the second end EP2. Therefore, the light emitted from the light emitting diode LD may be more reliably transmitted in the forward direction (for example, in the Figures 8a to 9 In addition, even when at least one light emitting diode LD provided in each light emitting area EMA is provided in a direction such as a diagonal line between the first electrode ELT1 and the second electrode ELT2, if the light emitting diode LD is provided in the recess RCS, the light emitted from the light emitting diode LD can also travel in a forward direction more reliably. According to an embodiment of the present disclosure, the amount of light emitted from the light emitting diode LD traveling in a desired direction can be increased. Therefore, the efficiency of light emitted from each light emitting area EMA can be improved.

[0161] The second insulating layer INS2 may be disposed on the light emitting diode LD (specifically, at least one light emitting diode LD aligned between the first electrode ELT1 and the second electrode ELT2), and may expose the first end EP1 and the second end EP2 of the light emitting diode LD. For example, the second insulating layer INS2 may be disposed only partially on the upper portion of one region of the light emitting diode LD without covering the first end EP1 and the second end EP2 of the light emitting diode LD. The second insulating layer INS2 may be formed as an independent pattern on each light emitting region EMA; however, the present disclosure is not limited thereto.

[0162] like Figure 8a and Figure 8b As shown in , if there is a space between the first insulating layer INS1 and the light emitting diode LD before forming the second insulating layer INS2, the space can be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. For example, in the case where the first insulating layer INS1 is formed of at least one inorganic insulating layer, the first insulating layer INS1 can be formed to be recessed along the contour of the bottom surface between the first electrode ELT1 and the second electrode ELT2. In the case where the light emitting diodes LD, each having a length greater than the width of the recess formed in the first insulating layer INS1, are horizontally arranged on the first insulating layer INS1, a space can be formed between the light emitting diode LD and the first insulating layer INS1. The space can be filled with an insulating material for forming the second insulating layer INS2 in a subsequent process step (for example, in a process step of forming the second insulating layer INS2 on the light emitting diode LD). In this way, if the second insulating layer INS2 flows under the light emitting diode LD and is filled into the space under the light emitting diode LD, the light emitting diode LD can be supported more stably.

[0163] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the first electrode ELT1 and the second electrode ELT2 and the first end EP1 and the second end EP2 of the light emitting diode LD. Figure 8a As shown in , the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer. In this case, although the first contact electrode CNE1 and the second contact electrode CNE2 are formed by the same process using the same conductive material, the present disclosure is not limited thereto.

[0164] In an embodiment, Figure 8bAs shown in , the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on different layers. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed by different processes using the same conductive material or different conductive materials. In the case where the first contact electrode CNE1 and the second contact electrode CNE2 are disposed on different layers, at least one insulating layer (e.g., a fourth insulating layer INS4) may be formed on the contact electrode (e.g., the first contact electrode CNE1) disposed on the lower layer.

[0165] The first and second contact electrodes CNE1 and CNE2 may electrically connect the first and second ends EP1 and EP2 of the light emitting diode LD to the first and second electrodes ELT1 and ELT2 , respectively.

[0166] For example, the first contact electrode CNE1 may be disposed on each first electrode ELT1 to contact the first electrode ELT1. For example, the first contact electrode CNE1 may be disposed on a region (e.g., the first contact portion CNT1) of the first electrode ELT1 that is not covered by the first insulating layer INS1, so that the first contact electrode CNE1 contacts the first electrode ELT1. In addition, the first contact electrode CNE1 may be disposed on a first end EP1 of at least one light emitting diode LD that is adjacent to the first electrode ELT1, for example, disposed on the corresponding first ends EP1 of the plurality of light emitting diodes LD, so that the first contact electrode CNE1 may contact the first end EP1. In other words, the first contact electrode CNE1 may be disposed to cover the corresponding first end EP1 of the light emitting diode LD and at least one region of the corresponding first electrode ELT1. Therefore, the corresponding first end EP1 of the light emitting diode LD may be electrically connected to the first electrode ELT1.

[0167] Likewise, the second contact electrode CNE2 may be disposed on each second electrode ELT2 to contact the second electrode ELT2. For example, the second contact electrode CNE2 may be disposed on a region (e.g., the second contact portion CNT2) of the second electrode ELT2 that is not covered by the first insulating layer INS1, so that the second contact electrode CNE2 contacts the second electrode ELT2. In addition, the second contact electrode CNE2 may be disposed on a second end EP2 of at least one light emitting diode LD that is adjacent to the second electrode ELT2, for example, disposed on the corresponding second ends EP2 of a plurality of light emitting diodes LD, so that the second contact electrode CNE2 may contact the second end EP2. In other words, the second contact electrode CNE2 may be disposed to cover the corresponding second end EP2 of the light emitting diode LD and at least one region of the corresponding second electrode ELT2. Therefore, the corresponding second end EP2 of the light emitting diode LD may be electrically connected to the second electrode ELT2.

[0168] In such Figure 6a In the case where the first contact electrode CNE1 and the second contact electrode CNE2 are not provided as shown in the embodiment, the first end EP1 and the second end EP2 of the light emitting diode LD may be in direct contact with the first electrode ELT1 and the second electrode ELT2. In this case, the first insulating layer INS1 may not be disposed between the first end EP1 and the second end EP2 of the light emitting diode LD and the first electrode ELT1 and the second electrode ELT2 of the light emitting diode LD.

[0169] The third insulating layer INS3 may be formed and / or disposed on one surface of the base layer BSL on which the insulating pattern INP, the first and second electrodes ELT1 and ELT2, the light emitting diode LD, and the first and second contact electrodes CNE1 and CNE2 are formed, so that the third insulating layer INS3 may cover the first and second electrodes ELT1 and ELT2, the light emitting diode LD, and the first and second contact electrodes CNE1 and CNE2. In an embodiment, the third insulating layer INS3 may include a thin film encapsulation layer including at least one inorganic layer and / or an organic layer.

[0170] In an embodiment, each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may have a single-layer structure or a multi-layer structure, and include at least one inorganic insulating material and / or an organic insulating material. For example, each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may include a SiN x The first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may include various well-known organic insulating materials / inorganic insulating materials, and the constituent material of each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 is not particularly limited. The first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may include different insulating materials, or at least some of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may include the same insulating material.

[0171] Fig.10 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Figure 6b In the embodiment, Fig.10 Some circuit elements and / or lines disposed in the pixel circuit layer PCL and a connection structure between the pixel circuit layer PCL and a display element layer DPL disposed above the pixel circuit layer PCL (for example, a layer on which light emitting diodes LD forming the light source unit LSU are disposed) are shown. Fig.10In the drawings, the same reference numerals are used to denote Figures 6a to 9 The components of the embodiments are similar or identical components, and further description thereof will be omitted.

[0172] Reference Figures 6a to 10 According to an embodiment of the present disclosure, the light emitting device may include a pixel circuit layer PCL disposed between a base layer BSL and a display element layer DPL. For example, the pixel circuit layer PCL may be formed on a surface of the base layer BSL, and the display element layer DPL may be formed on a surface of the base layer BSL on which the pixel circuit layer PCL is formed.

[0173] The pixel circuit layer PCL may include a pixel circuit (eg, Figure 5a to Figure 5c Any one of the pixel circuits PXC shown in FIG. 1 , etc.) and / or lines connected to the pixel circuits PXC. For example, the pixel circuit layer PCL may include Figure 5a The pixel circuit layer PCL may further include a first transistor T1 and a second transistor T2. Figure 5a to Figure 5c The storage capacitor Cst shown in FIG. 1 , various signal lines (e.g., scan lines Si and data lines Dj) connected to each pixel circuit PXC, and various power lines (e.g., first power lines PL1 and second power lines PL2) connected to the pixel circuit PXC and / or the light source unit LSU.

[0174] In an embodiment, a plurality of transistors (e.g., a first transistor T1 and a second transistor T2) disposed in each pixel circuit PXC may have substantially the same or similar cross-sectional view structures. However, the present disclosure is not limited thereto. For example, in an embodiment, at least some of the plurality of transistors may have different types and / or structures.

[0175] In addition, the pixel circuit layer PCL may include a plurality of insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on one surface of the base layer BSL. The pixel circuit layer PCL may also selectively include at least one light shielding pattern (not shown) disposed under at least some of the transistors.

[0176] The buffer layer BFL can prevent impurities from diffusing into each circuit element. The buffer layer BFL can be formed of a single layer, or can be formed of a multilayer having two or more layers. In the case where the buffer layer BFL has a multilayer structure, each layer can be formed of the same material or different materials. In an embodiment, the buffer layer BFL can be omitted.

[0177] Each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, and first and second transistor electrodes ET1 and ET2. Fig.10 An embodiment in which each of the first transistor T1 and the second transistor T2 includes a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL is shown, but the present disclosure is not limited thereto. For example, in an embodiment, the first transistor electrode ET1 and / or the second transistor electrode ET2 provided in at least one transistor provided in each pixel region may be formed integrally with the corresponding semiconductor layer SCL.

[0178] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with each first transistor electrode ET1, a second region in contact with each second transistor electrode ET2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0179] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor as an undoped semiconductor pattern. Each of the first and second regions of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0180] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap at least one region of the semiconductor layer SCL.

[0181] The first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on each semiconductor layer SCL and the corresponding gate electrode GE, and at least one interlayer insulating layer ILD is disposed between the first transistor electrode ET1 and the second transistor electrode ET2 and each semiconductor layer SCL and the corresponding gate electrode GE. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be disposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be connected to the first region and the second region of each semiconductor layer SCL respectively through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0182] In an embodiment, at least one transistor provided in the pixel circuit PXC may be connected to any one of the pixel electrodes. For example, any one of the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1 may be electrically connected to the first electrode ELT1 and / or the first connection electrode CNL1 of the light source unit LSU provided on the passivation layer PSV through the first contact hole CH1 passing through the passivation layer PSV.

[0183] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be disposed on the same layer as one electrode of each circuit element forming the pixel circuit PXC. For example, a second power line PL2 for supplying a voltage of a second power source VSS may be disposed on the same layer as the gate electrode GE of the first transistor T1 and the second transistor T2, and may be electrically connected to the second electrode ELT2 and / or the second connection electrode CNL2 of the light source unit LSU disposed on the passivation layer PSV through a bridge pattern BRP disposed on the same layer as the first transistor electrode ET1 and the second transistor electrode ET2 and at least one second contact hole CH2 passing through the passivation layer PSV. However, the structure and / or position of the second power line PL2, etc. may be changed in various ways.

[0184] In an embodiment, the display element layer DPL may include a light source unit LSU for each pixel PXL. For example, the display element layer DPL may include at least one first electrode ELT1 and at least one second electrode ELT2 and at least one light emitting diode LD electrically connected between the first electrode ELT1 and the second electrode ELT2. In addition, the display element layer DPL may further include, for example, at least one conductive layer and / or insulating layer.

[0185] For example, the display element layer DPL may include an insulating pattern INP disposed in each light emitting area EMA, at least a pair of first electrodes ELT1 and second electrodes ELT2 disposed on the insulating pattern INP, and a plurality of light emitting diodes LD disposed between the first electrodes ELT1 and the second electrodes ELT2, and may also selectively include a first contact electrode CNE1 and a second contact electrode CNE2 disposed on a first end EP1 and a second end EP2 of each light emitting diode LD. In addition, the display element layer DPL may include a first insulating layer INS1, a second insulating layer INS2, and a third insulating layer INS3 disposed in sequence, and may also selectively include Figure 8b As already mentioned, the fourth insulating layer INS4 is shown in FIG. Figures 6a to 9 The structure of the display element layer DPL is described in detail, and thus a detailed description thereof will be omitted.

[0186] according to Figures 6a to 10In an embodiment, an insulating pattern INP including at least one recess RCS (e.g., a plurality of recess RCS) is disposed under the first electrode ELT1 and the second electrode ELT2. At least one light emitting diode LD is disposed in at least one of the plurality of recess RCSs. The first end EP1 and the second end EP2 of the light emitting diode LD may be electrically connected to the first electrode ELT1 and the second electrode ELT2, respectively. The sidewall of the light emitting diode LD including the first end EP1 and the second end EP2 may be surrounded by the insulating pattern INP and the first electrode ELT1 and the second electrode ELT2. Therefore, the efficiency of light emitted from each light emitting area EMA may be improved.

[0187] Since the insulating pattern INP includes the recess RCS, when the solvent supplied to the light emitting area EMA together with the light emitting diode LD during the process of supplying the light emitting diode LD is removed, the light emitting diode LD can be more centrally arranged in the recess RCS of the insulating pattern INP. Therefore, the light emitting diode LD can be more easily arranged in a desired area.

[0188] In addition, according to Figures 6a to 10 In an embodiment of the present disclosure, the first electrode ELT1 and the second electrode ELT2 may include a first bend BP1 and a second bend BP2 corresponding to the shape of the insulating pattern INP in an area corresponding to each recess RCS. In this way, if the first electrode ELT1 and the second electrode ELT2 include the first bend BP1 and the second bend BP2, when the light emitting diode LD is supplied to each light emitting area EMA and an electric field for alignment of the light emitting diode LD is formed by applying a predetermined alignment voltage to the first electrode ELT1 and the second electrode ELT2, the electric field may be significantly concentrated around the first bend BP1 and the second bend BP2. Therefore, the alignment efficiency of the light emitting diode LD may be improved. In other words, in an embodiment of the present disclosure, a larger number of light emitting diodes LD may be more efficiently aligned at a desired position. Therefore, the alignment rate of the light emitting diode LD may be improved.

[0189] Fig.11 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel PXL including a light source unit LSU formed of the light emitting device. Fig.12 It shows that according to Fig.11 A plan view of an insulation pattern INP of an embodiment. Fig.13a and Fig.13b Each of them is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Fig.11 Line IV-IV' corresponds to different embodiments of the cross section. Fig.14 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Fig.11An embodiment of a cross section corresponding to line V-V'. Fig.15 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Fig.11 The cross section of line VI-VI' corresponds to an embodiment of the present invention. Figures 11 to 15 In the embodiment of Figures 6a to 10 The components of the embodiments are the same or similar components, and their detailed description will be omitted.

[0190] Reference Figures 11 to 15 , the insulation pattern INP may include at least one opening OPN. For example, the insulation pattern INP may include a plurality of openings OPN corresponding to the corresponding recesses RCS.

[0191] For example, Figures 11 to 15 As shown in Figures 6a to 10 Each recess RCS of the embodiment of the present invention may be modified to include an opening OPN. For example, each recess RCS may include an opening OPN by opening a bottom surface of the recess RCS.

[0192] In the aforementioned embodiment, the sidewall of the light emitting diode LD connected between the first electrode ELT1 and the second electrode ELT2 may also be surrounded by the insulating pattern INP and the first and second electrodes ELT1 and ELT2. Therefore, the efficiency of light emitted from each light emitting area EMA may be improved.

[0193] Furthermore, since the insulating pattern INP includes the openings OPN corresponding to the recesses RCS, the light emitting diodes LD can be more centrally disposed in each recess RCS, and the alignment efficiency of the light emitting diodes LD can be further improved. Therefore, the alignment rate of the light emitting diodes LD can be improved.

[0194] Fig.16 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel PXL including a light source unit LSU formed of the light emitting device. Fig.17 It shows that according to Fig.16 FIG. 1 is a plan view of an insulating pattern INP′ of an embodiment. Fig.18 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, Fig.16 and Fig.17 The insulation pattern INP' is modified accordingly. Figures 16 to 18 In the description of the embodiments, the same reference numerals will be used to denote components similar to or identical to those of the previous embodiments, and their detailed description will be omitted.

[0195] Reference Figures 16 to 18, the insulating pattern INP' may include a rectangular recess RCS'. For example, the insulating pattern INP' may include a plurality of recesses RCS' each having a square shape. In an embodiment, at least one recess RCS' may selectively include an opening OPN'. In an embodiment, each opening OPN' may have a shape corresponding to each recess RCS'. For example, the opening OPN' may have a size corresponding to each recess RCS' and have a square shape.

[0196] Fig.19 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel PXL including a light source unit LSU formed of the light emitting device. Fig. 20 It shows that according to Fig.19 A plan view of an insulation pattern INP” of an embodiment. Fig.21 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, Fig.19 and Fig. 20 The insulation pattern INP" is modified. Figures 19 to 21 In the description of the embodiments, the same reference numerals will be used to denote components similar to or identical to those of the previous embodiments, and their detailed description will be omitted.

[0197] Reference Figures 19 to 21 , the insulation pattern INP" may include a recess RCS" having a diamond shape. For example, the insulation pattern INP" may include a plurality of recesses RCS" each having a diamond shape. In an embodiment, at least one recess RCS" may selectively include an opening OPN". In an embodiment, each opening OPN" may have a shape corresponding to each recess RCS". For example, the opening OPN" may have a size corresponding to each recess RCS" and have a diamond shape.

[0198] like Figures 6a to 21As shown in the embodiments of the present disclosure, the shape of each recess RCS, RCS', RCS", and / or each opening OPN, OPN', OPN", may be changed in various ways. For example, each recess RCS, RCS', RCS", and / or each opening OPN, OPN', OPN", may have a circular shape, a square shape, or a diamond shape. For example, each recess RCS, RCS', RCS", and / or each opening OPN, OPN', OPN", may have other shapes. For example, in the embodiments of the present disclosure, each recess RCS, RCS', RCS", and / or each opening OPN, OPN', OPN", may have an elliptical shape or a polygonal shape other than a square shape or a diamond shape. Optionally, in the embodiments of the present disclosure, each recess RCS, RCS', RCS", and / or each opening OPN, OPN', OPN", may have a circular shape or a combination of an elliptical shape and a polygonal shape, for example, a shape including a combination of linear edges and curved edges.

[0199] In addition, the size of each recess RCS, RCS', RCS" and / or each opening OPN, OPN', OPN" can be changed in various ways. For example, the size of each recess RCS, RCS', RCS" and / or each opening OPN, OPN', OPN" can be changed in various ways according to the size, structure, etc. of each light-emitting area EMA, the first and second electrodes ELT1 and ELT2 and / or the light-emitting diode LD.

[0200] Fig. 22 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel PXL including a light source unit LSU formed of the light emitting device. Fig.23 It shows that according to Fig. 22 A plan view of a reflective electrode REF of an embodiment. Fig.24 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows Fig. 22 The cross section of line VII-VII' corresponds to an embodiment. Figure 22 to Figure 24 In the description of the embodiments of the present invention, the same reference numerals are used to represent the same embodiments as those described above (e.g., Figures 6a to 10 ) are similar or identical components to the components of the embodiment, and their detailed description will be omitted.

[0201] Reference Figure 22 to Figure 24 The light emitting device and the pixel PXL including the light emitting device according to the embodiment of the present disclosure may further include a reflective electrode (or a reflective pattern layer) REF disposed around the light emitting diode LD.

[0202] In an embodiment, the reflective electrode REF may be disposed on the first insulating layer INS1 at a position adjacent to the light emitting diode LD and include an opening OPNr corresponding to the light emitting diode LD. For example, the reflective electrode REF may include at least one opening OPNr partially overlapping the at least one recess RCS.

[0203] For example, the reflective electrode REF may include at least one first direction pattern PAT1 extending in a direction intersecting the first electrode ELT1 and the second electrode ELT2. For example, the reflective electrode REF may include a plurality of first direction patterns PAT1 extending in a first direction DR1 perpendicular to the first electrode ELT1 and the second electrode ELT2 and arranged parallel to each other. The reflective electrode REF may include a second direction pattern PAT2 connecting the first direction patterns PAT1 to each other. In an embodiment, the first direction pattern PAT1 and the second direction pattern PAT2 may be integrally connected to each other, but the present disclosure is not limited thereto.

[0204] In an embodiment, the reflective electrode REF may be electrically isolated from the first and second electrodes ELT1 and ELT2 and the light emitting diode LD. To this end, a fifth insulating layer INS5 may be disposed on the reflective electrode REF. The reflective electrode REF may be floated to maintain electrical isolation and may be connected to a predetermined reference power supply.

[0205] according to Figure 22 to Figure 24 In the embodiment of the present invention, the additional reflective electrode REF is formed around the light emitting diode LD, so that the reflectivity of the light emitted from the light emitting diode LD can be improved. For example, with respect to the second direction DR2, the reflectivity of the light emitted from the light emitting diode LD can also be improved. Therefore, the efficiency of the light emitted from each light emitting area EMA can be further improved.

[0206] Although the scope of the present disclosure is described by detailed embodiments, it should be noted that the above embodiments are only illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and modifications can be made here without departing from the scope of the present disclosure defined by the claims.

[0207] The scope of the present disclosure is not limited by the detailed description of the present disclosure, and should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A light emitting device, comprising: Luminous area; an insulating pattern disposed in the light emitting region and including at least one recess and a protrusion configured to surround the recess; a first electrode disposed on the insulating pattern and configured to overlap the recessed first region and the protrusion in the periphery of the first region; a second electrode disposed on the insulating pattern and spaced apart from the first electrode by a predetermined distance in a first direction and configured to overlap the recessed second region and the protrusion in the periphery of the second region; a first insulating layer disposed in the recess and covering portions of the first electrode and the second electrode; a light emitting diode, disposed in the recess on the first insulating layer and electrically connected between the first electrode and the second electrode; as well as A first contact electrode and a second contact electrode are disposed on the first insulating layer.

2. The light emitting device according to claim 1, wherein: The recess includes an inclined surface having an inclination within a predetermined angle range in a peripheral region of the recess adjacent to the protrusion.

3. The light emitting device according to claim 2, wherein: Each of the first electrode and the second electrode includes a bent portion having a bent shape at each of an upper end and a lower end of the inclined surface.

4. The light emitting device according to claim 1, wherein: The depression has a circular shape, an elliptical shape, a polygonal shape, or a combination thereof in a plan view.

5. The light emitting device according to claim 1, wherein: The recess includes an opening.

6. The light emitting device according to claim 1, wherein: The recess has a width in the first direction that is greater than a length of the light emitting diode.

7. The light emitting device according to claim 1, wherein: The recess has the same width in the first direction and in a second direction perpendicular to the first direction.

8. The light emitting device according to claim 1, wherein: The light emitting diode includes a rod-type light emitting diode including a first end and a second end disposed at opposite ends thereof in a longitudinal direction.

9. The light emitting device according to claim 8, wherein: The first contact electrode is disposed on the first end of the light emitting diode and a region of the first electrode and is configured to electrically connect the first end to the first electrode; as well as The second contact electrode is disposed on the second end of the light emitting diode and a region of the second electrode, and is configured to electrically connect the second end to the second electrode.

10. The light emitting device according to claim 9, wherein: The first insulating layer is interposed between the light emitting diode and the first and second electrodes, and is configured to expose the one region of each of the first and second electrodes. 11 . The light emitting device according to claim 10 , further comprising a reflective electrode disposed on the first insulating layer at a position adjacent to the light emitting diode and comprising an opening corresponding to the light emitting diode.

12. The light emitting device according to claim 11, in, Each of the first electrode and the second electrode extends in a second direction intersecting the first direction, and The reflective electrode includes at least one first direction pattern, and the first direction pattern extends in the first direction to intersect with the first electrode and the second electrode.

13. The light emitting device according to claim 1, in, The insulating pattern includes a plurality of recesses dispersed at predetermined intervals, and At least one light emitting diode is disposed in each of the plurality of recesses.

14. A display device, comprising: Display area; as well as a pixel disposed in the display area and including a light emitting area, The pixel includes: an insulating pattern, which is arranged in the light-emitting area and includes at least one recess and a protrusion configured to surround the recess; a first electrode, which is arranged on the insulating pattern and is configured to overlap with a first area of ​​the recess and a protrusion in the periphery of the first area; a second electrode, which is arranged on the insulating pattern and is spaced a predetermined distance from the first electrode in a first direction, and is configured to overlap with a second area of ​​the recess and a protrusion in the periphery of the second area; a first insulating layer, which is arranged in the recess and covers parts of the first electrode and the second electrode; a light-emitting diode, which is arranged on the first insulating layer in the recess and is electrically connected between the first electrode and the second electrode; and a first contact electrode and a second contact electrode, which are arranged on the first insulating layer.

15. The display device according to claim 14, in, The recess includes an inclined surface having an inclination within a predetermined angle range in a peripheral region of the recess adjacent to the protrusion, and Each of the first electrode and the second electrode includes a bent portion having a bent shape at each of an upper end and a lower end of the inclined surface.

16. The display device according to claim 14, wherein: The depression has a circular shape, an elliptical shape, a polygonal shape, or a combination thereof in a plan view.

17. The display device according to claim 14, wherein: The recess includes an opening.

18. The display device according to claim 14, wherein: The recess has a width in the first direction that is greater than a length of the light emitting diode.

19. The display device according to claim 14, wherein: The pixel also includes a reflective electrode disposed on the first insulating layer at a position adjacent to the light emitting diode and including an opening corresponding to the light emitting diode, and The first insulating layer is interposed between the light emitting diode and the first and second electrodes, and includes an opening formed to expose one region of each of the first and second electrodes.

20. The display device according to claim 14, in, The insulating pattern includes a plurality of recesses dispersed at predetermined intervals in the light emitting region, and At least one light emitting diode is disposed in each of the plurality of recesses.

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