Systems and methods for integrating an injection locked oscillator into a transceiver array

Abstract

Systems and methods for integrating injection locked oscillators into a transceiver array are disclosed. In one aspect, an injection locked oscillator (ILO) distribution system is provided that includes a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit that includes an ILO and is configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal that indicates an operating frequency of the ILO. The ILO distribution system also includes an injection locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or an unlocked state based on the master clock signal and the output signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application 62 / 745,036, filed October 12, 2018, and the benefit of U.S. Provisional Application 62 / 745,041, filed October 12, 2018, the entire contents of each of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the technology described herein relate to electronic systems and methods, and more specifically, to systems and methods for integrating injection-locked oscillators into transceiver arrays. Background Technology

[0004] Some communication standards can be implemented via transceiver chips configured to transmit and receive radio frequency (RF) signals to / from one or more antennas. Revisions and improvements to communication standards (e.g., including the introduction of 5G standards) may require the use of multiple antennas to fully realize communication in the desired frequency band (e.g., frequencies in the 6 GHz to 30 GHz range). Therefore, transceiver chips can be designed to appropriately interface with multiple antennas at the desired frequency band. Summary of the Invention

[0005] Various aspects of this application relate to technologies and electronic systems that can be used to integrate injection-locked oscillators (ILOs) into transceiver arrays and detect whether each ILO is locked or unlocked. For example, in one aspect, an ILO distribution system is provided, including a master clock generator configured to generate a master clock signal. The system also includes ILO distribution circuitry that includes an ILO and is configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal, and the ILO distribution circuitry is further configured to generate an output signal indicating the operating frequency of the ILO. The system also includes an ILO detector configured to receive the master clock signal and the output signal, and the ILO detector is further configured to determine whether the ILO is locked or unlocked based on the master clock signal and the output signal.

[0006] According to another aspect of this application, a method for detecting an injection-locked state is provided. The method includes: generating a master clock signal by a master clock generator, and receiving the master clock signal at an injection-locked oscillator distribution circuit, the injection-locked oscillator distribution circuit including an injection-locked oscillator. The method further includes: generating a reference clock signal based on the master clock signal at the injection-locked oscillator, and generating an output signal indicating the operating frequency of the injection-locked oscillator at the injection-locked oscillator distribution circuit. The method also includes receiving the master clock signal and the output signal at an injection-lock detector, and determining whether the injection-locked oscillator is in a locked state or an unlocked state based on the master clock signal and the output signal.

[0007] According to another aspect of this application, a mobile device is provided. The mobile device includes an antenna, transceiver circuitry operatively coupled to the antenna, the transceiver including a first mixer and a master clock generator configured to generate a master clock signal. The mobile device further includes an injection-locked oscillator (ILO) distribution circuit, which includes an ILO and is configured to receive the master clock signal. The ILO is operatively coupled to the first mixer and configured to generate a reference clock signal based on the master clock signal and provide the reference clock signal to the first mixer. The ILO distribution circuit is further configured to generate an output signal indicating the operating frequency of the ILO. The mobile device also includes an injection-lock detector configured to receive the master clock signal and the output signal, and the injection-lock detector is further configured to determine whether the ILO is in a locked or unlocked state based on the master clock signal and the output signal.

[0008] According to another aspect of this application, an injection-locked oscillator (ILO) distribution system is provided. The system includes a master clock generator configured to generate a master clock signal and transceiver circuitry including a plurality of mixers. The system also includes an ILO distribution circuitry comprising a plurality of ILOs, each ILO being configured to receive the master clock signal, each ILO being configured to generate a reference clock signal based on the master clock signal, and each ILO being configured to provide the reference clock signal to one of the mixers.

[0009] According to another aspect of this application, a method for allocating a reference clock signal is provided. The method includes: generating a master clock signal by a master clock generator; and receiving the master clock signal at an injection-locked oscillator (ILO) allocation circuit, the ILO including a plurality of ILOs. The method further includes, at each ILO, generating a reference clock signal based on the master clock signal and providing the reference clock signal from each ILO to a mixer.

[0010] According to another aspect of the present invention, a mobile device is provided. The mobile device includes an antenna and transceiver circuitry operatively coupled to the antenna, the transceiver including a first mixer. The mobile device further includes a master clock generator configured to generate a master clock signal, and transceiver circuitry including a plurality of mixers. The mobile device also includes an injection-locked oscillator (ILO) distribution circuitry including a plurality of ILOs, each ILO configured to receive the master clock signal, each ILO configured to generate a reference clock signal based on the master clock signal, and each ILO configured to provide the reference clock signal to one of the mixers. Attached Figure Description

[0011] Figure 1A This is a schematic diagram of another example ILO allocation network according to one embodiment.

[0012] Figure 1B This is a schematic diagram of an example of a communication network.

[0013] Figure 2A This is a schematic diagram of an example of a communication link using carrier aggregation.

[0014] Figure 2B It shows the use of Figure 2A Various examples of uplink carrier aggregation in communication links.

[0015] Figure 2C It shows the use of Figure 2A Various examples of downlink carrier aggregation in communication links.

[0016] Figure 3A This is a schematic diagram of an example of a downlink channel using multiple-input multiple-output (MIMO) communication.

[0017] Figure 3B This is a schematic diagram of an example of an uplink channel using MIMO communication.

[0018] Figure 3C This is a schematic diagram of another example of an uplink channel using MIMO communication.

[0019] Figure 4A This is a schematic diagram of an example of a communication system that operates using beamforming.

[0020] Figure 4B This is a schematic diagram of an example of beamforming used to provide a transmit beam.

[0021] Figure 4C This is a schematic diagram of an example of beamforming used to provide a receiving beam.

[0022] Figure 5A This is a perspective view of an embodiment of a module that operates using beamforming.

[0023] Figure 5B yes Figure 6 A is the cross-section of the module taken along line 6B-6B.

[0024] Figure 6 This is a schematic diagram of one embodiment of a mobile device.

[0025] Figure 7 This is a schematic diagram of another embodiment of a mobile device.

[0026] Figure 8 This is a schematic diagram of a power amplifier system according to one embodiment.

[0027] Figure 9 This is a schematic diagram of an example transceiver according to one embodiment.

[0028] Figure 10 This is a block diagram of an example injected locked oscillator (ILO) allocation network according to one embodiment.

[0029] Figure 11 This is a schematic diagram of another example ILO allocation network according to one embodiment.

[0030] Figure 12 This is a schematic diagram of yet another example ILO allocation network according to one embodiment.

[0031] Figure 13 This is a schematic diagram of yet another exemplary ILO allocation network according to one embodiment.

[0032] Figure 14 This is a schematic diagram of another example ILO allocation network according to one embodiment.

[0033] Figure 15 This is a schematic diagram of an example injection lock detector (ILD) according to one embodiment.

[0034] Figure 16 This is a graph of example values ​​output from certain components of the ILD when the selected ILO is in an unlocked state, according to one embodiment.

[0035] Figure 17 This is a graph of example values ​​output from certain components of the ILD when the selected ILO is in a locked state, according to one embodiment.

[0036] Figure 18 This is a schematic diagram of an example multiphase clock pulse generator according to one embodiment.

[0037] Figure 19 This is a graph 600 showing example values ​​output from the delay element 515 of the multi-phase clock pulse generator 207 according to one embodiment. Detailed Implementation

[0038] The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in many different ways, for example, as defined and covered by the claims. Reference is made to the accompanying drawings in this description, wherein the same reference numerals may indicate the same or functionally similar elements. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that some embodiments may include more elements than those shown in the drawings and / or a subset of the elements shown in the drawings. In addition, some embodiments may incorporate any suitable combination of features from two or more drawings.

[0039] Overview of examples of wireless communication systems

[0040] The International Telecommunication Union (ITU) is a specialized agency of the United Nations (UN) responsible for global issues related to information and communication technologies, including the global sharing of radio spectrum.

[0041] The 3rd Generation Partnership Project (3GPP) is a collaboration among various telecommunications standards bodies worldwide, such as the Radio Engineering Business Association (ARIB), the Telecommunication Technology Committee (TTC), the China Communications Standards Association (CCSA), the Telecommunication Industry Solutions Alliance (ATIS), the Telecommunication Technology Association (TTA), the European Telecommunications Standards Institute (ETSI), and the Telecommunication Standards Development Institute of India (TSDSI).

[0042] By operating within the ITU, 3GPP develops and maintains technical specifications for a variety of mobile communication technologies, including, for example, second-generation (2G) technologies (e.g., Global System for Mobile Communications (GSM) and Enhanced Data Rate GSM Evolution (EDGE)), third-generation (3G) technologies (e.g., Universal Mobile Telecommunications System (UMTS) and High-Speed ​​Packet Access (HSPA)), and fourth-generation (4G) technologies (e.g., Long Term Evolution (LTE) and LTE-Advanced).

[0043] Technical specifications controlled by 3GPP can be extended and modified through specification versions, which can span multiple years and specify new features and the breadth of evolution.

[0044] In one example, 3GPP introduced carrier aggregation (CA) for LTE in Release 10. While the initial introduction included two downlink carriers, 3GPP expanded carrier aggregation in Release 14 to include up to five downlink carriers and up to three uplink carriers. Other examples of new features and evolutions provided by 3GPP releases include, but are not limited to, Licensed Assisted Access (LAA), Enhanced LAA (eLAA), Narrowband Internet of Things (NB-IoT), Vehicle-to-Everything (V2X), and High Power User Equipment (HPUE).

[0045] 3GPP introduced Phase 1 of 5G technology in Release 15 and plans to introduce Phase 2 of 5G technology in Release 16 (target 2019). Release 15 at least partially addressed 5G communication below 6 GHz, while Release 16 is expected to address communication above 6 GHz. Subsequent 3GPP releases will further evolve and expand 5G technology. 5G technology is also referred to as 5G New Radio (NR) in this document.

[0046] The initial specifications for 5G NR support various features such as millimeter-wave spectrum communication, beamforming capabilities, high spectral efficiency waveforms, low-latency communication, multiple radio digitization, and / or non-orthogonal multiple access (NOMA). While such RF capabilities provide network flexibility and enhance user data rates, supporting these features presents numerous technical challenges.

[0047] The teachings in this article are applicable to a wide variety of communication systems, including but not limited to those using advanced cellular technologies such as Advanced LTE, Advanced LTE Pro, and / or 5G NR.

[0048] Figure 1A This is a schematic diagram of an example ILO allocation network 200 according to one embodiment. Figure 1A As shown, the ILO distribution network 200 includes four ILO distribution circuits, each configured to receive a master clock signal from a master clock generator. The ILO distribution circuits can be configured to provide reference clocks to the respective mixers of the transceiver. Further details regarding embodiments of the ILO distribution network 200 are incorporated herein by reference. Figure 11 The description of the accompanying drawings is provided.

[0049] Figure 1B This is a schematic diagram of an example of a communication network 10. The communication network 10 includes a macro cell base station 1, a small cell base station 3, and various examples of user equipment (UE), including a first mobile device 2a, a wirelessly connected car 2b, a laptop computer 2c, a fixed wireless device 2d, a wirelessly connected train 2e, and a second mobile device 2f.

[0050] Despite Figure 1BThe illustration shows specific examples of base stations and user equipment, but communication networks can include various types and / or numbers of base stations and user equipment.

[0051] For example, in the illustrated example, communication network 10 includes a macrocell base station 1 and a small cell base station 3. Compared to macrocell base station 1, small cell base station 3 can operate with relatively lower power, shorter range, and / or fewer concurrent users. Small cell base station 3 may also be referred to as a femtocell, picocell, or microcell. Although communication network 10 is illustrated as including two base stations, communication network 10 can be implemented to include more or fewer base stations and / or other types of base stations.

[0052] While various examples of user equipment are shown, the teachings herein apply to a wide variety of user equipment, including, but not limited to, mobile phones, tablets, laptops, IoT devices, wearable electronic devices, customer premises equipment (CPE), wirelessly connected vehicles, wireless repeaters, and / or a wide variety of other communication devices. Furthermore, user equipment includes not only existing communication devices operating in cellular networks, but also communication devices subsequently developed that are easily implemented in conjunction with the inventive systems, processes, methods, and devices described and claimed herein.

[0053] Figure 1B The example communication network 10 supports communication using various technologies, including, for example, 4G LTE, 5G NR, and wireless local area networks (WLANs) such as Wi-Fi. While various examples of communication technologies have been provided, the communication network 10 can be adapted to support a wide range of communication technologies.

[0054] Figure 1B Various communication links of the communication network 10 are depicted. These communication links can be duplexed in a wide variety of ways, including, for example, using Frequency Division Duplex (FDD) and / or Time Division Duplex (TDD). FDD is a type of radio frequency communication that uses different frequencies to transmit and receive signals. FDD offers many advantages, such as high data rates and low latency. Conversely, TDD is a type of radio frequency communication that uses approximately the same frequency to transmit and receive signals, and in which transmit and receive communications are switched in time. TDD offers many advantages, such as efficient use of the spectrum and variable allocation of the amount of transmission between the transmit and receive directions.

[0055] In some implementations, the user equipment may communicate with the base station using one or more of 4G LTE, 5G NR, and Wi-Fi technologies. In some implementations, enhanced licensed assisted access (eLAA) is used to aggregate one or more licensed frequency carriers (e.g., licensed 4G LTE and / or 5G NR frequencies) with one or more unlicensed carriers (e.g., unlicensed Wi-Fi frequencies).

[0056] Communication links can operate at various frequencies. In some implementations, 5G NR technology is used to support communication on one or more frequency bands below 6 GHz and / or on one or more frequency bands above 6 GHz. In one embodiment, one or more mobile devices support the HPUE power class specification.

[0057] In some implementations, base stations and / or user equipment use beamforming for communication. For example, beamforming can be used to focus signal strength to overcome path loss, such as the high loss associated with communication at high signal frequencies. In some embodiments, user equipment (such as one or more mobile phones) uses beamforming to communicate in the millimeter-wave band of 30 GHz to 300 GHz and / or in the centimeter-wave frequency of 6 GHz to 30 GHz (or more specifically, 24 GHz to 30 GHz).

[0058] Different users of communication network 10 can share available network resources, such as available spectrum, in a wide variety of ways.

[0059] Figure 2A This is a schematic diagram illustrating an example of a communication link using carrier aggregation. Carrier aggregation can be used to widen the bandwidth of a communication link by supporting communication on multiple frequency carriers, thereby increasing user data rates and enhancing network capacity by utilizing segmented spectrum allocation.

[0060] In the example shown, a communication link is provided between base station 21 and mobile device 22. Figure 2A As shown, the communication link includes a downlink channel for RF communication from base station 21 to mobile device 22, and an uplink channel for RF communication from mobile device 22 to base station 21.

[0061] although Figure 2A Carrier aggregation is shown in the FDD communication scenario, but carrier aggregation can also be used in TDD communication.

[0062] In some implementations, the communication link can provide asymmetric data rates for downlink and uplink channels. For example, the communication link can be used to support relatively high downlink data rates for high-speed streaming of multimedia content to mobile devices, while providing relatively slow data rates for uploading data from mobile devices to the cloud.

[0063] In the example shown, base station 21 and mobile device 22 communicate via carrier aggregation, which can be used to selectively increase the bandwidth of the communication link. Carrier aggregation includes contiguous aggregation, where consecutive carriers within the same operating frequency band are aggregated. Carrier aggregation can also be discontinuous and can include carriers separated by frequency within a common frequency band or in different frequency bands.

[0064] exist Figure 2A In the example shown, the uplink channel includes three aggregated component carriers f UL1 f UL2 and f UL3 Additionally, the downlink channel includes five aggregated component carriers f. DL1 f DL2 f DL3 f DL4 and f DL5 Although an example of component carrier aggregation is shown, more or fewer carriers can be aggregated for uplink and / or downlink. Furthermore, the number of aggregated carriers can vary over time to achieve the desired uplink and downlink data rates.

[0065] For example, the number of aggregated carriers for uplink and / or downlink communication of a specific mobile device can change over time. For instance, the number of aggregated carriers can change as the device moves within the communication network and / or as network usage changes over time.

[0066] Figure 2B It shows the use of Figure 2A Various examples of uplink carrier aggregation in communication links. Figure 2B The diagram includes a first carrier aggregation scenario 31, a second carrier aggregation scenario 32, and a third carrier aggregation scenario 33, which schematically depict three types of carrier aggregation.

[0067] Carrier aggregation scenarios 31-33 illustrate the first component carrier f UL1 Second component carrier f UL2 and the third component carrier f UL3 Different spectral allocations. Although Figure 2BThis is illustrated with the aggregation of three component carriers, but carrier aggregation can be used to aggregate more or fewer carriers. Furthermore, although illustrated in the uplink scenario, these aggregation scenarios also apply to the downlink.

[0068] First carrier aggregation scenario 31 illustrates intra-band contiguous carrier aggregation, wherein adjacent component carriers in both frequency and common frequency band are aggregated. For example, first carrier aggregation scenario 31 depicts contiguous component carriers f located within the first frequency band BAND1. UL1 f UL2 and f UL3 The aggregation of.

[0069] Continue to refer to Figure 2B The second carrier aggregation scenario 32 illustrates intra-band discontinuous carrier aggregation, wherein two or more component carriers that are not adjacent in frequency and are within a common frequency band are aggregated. For example, the second carrier aggregation scenario 32 depicts discontinuous component carriers f located within the first frequency band BAND1. UL1 f UL2 and f UL3 The aggregation of.

[0070] Third carrier aggregation scenario 33 illustrates the aggregation of discontinuous carriers across frequency bands, wherein component carriers that are not adjacent in frequency and exist in multiple frequency bands are aggregated. For example, third carrier aggregation scenario 33 depicts component carrier f of the first frequency band BAND1. UL1 and f UL2 The component carrier f of the second frequency band BAND2 UL3 The aggregation of.

[0071] Figure 2C It shows the use of Figure 2A Various examples of downlink carrier aggregation in communication links. These examples depict the first component carrier f DL1 Second component carrier f DL2 Third component carrier f DL3 The fourth component carrier f DL4 and the fifth component carrier f DL5 Various carrier aggregation scenarios with different spectrum allocations 34-38. Although Figure 2C This is illustrated with the aggregation of five component carriers; carrier aggregation can be used to aggregate more or fewer carriers. Furthermore, although illustrated in the downlink scenario, these aggregation scenarios also apply to the uplink.

[0072] The first carrier aggregation scenario 34 depicts the aggregation of consecutive component carriers located within the same frequency band. Furthermore, the second carrier aggregation scenario 35 and the third carrier aggregation scenario 36 illustrate two aggregation examples that are discontinuous but located within the same frequency band. Additionally, the fourth carrier aggregation scenario 37 and the fifth carrier aggregation scenario 38 illustrate two aggregation examples where component carriers that are not frequency-adjacent and exist in multiple frequency bands are aggregated. As the number of aggregated component carriers increases, the complexity of the possible carrier aggregation scenarios also increases.

[0073] Reference Figures 2A-2C In carrier aggregation, the component carriers can have different frequencies, including frequency carriers in the same or multiple frequency bands. Furthermore, carrier aggregation is applicable to implementations where the component carriers have approximately the same bandwidth and implementations where the component carriers have different bandwidths.

[0074] Some communication networks allocate primary component carriers (PCCs) or anchor carriers for uplink and PCCs for downlink to specific user equipment (UEs). Additionally, UEs use PCCs for communication when mobile devices use single-frequency carriers for uplink or downlink. To increase uplink communication bandwidth, uplink PCCs can be aggregated with one or more uplink secondary component carriers (SCCs). Similarly, to increase downlink communication bandwidth, downlink PCCs can be aggregated with one or more downlink SCCs.

[0075] In some implementations, the communication network provides a network cell for each component carrier. Additionally, the primary cell may operate using a PCC (Precision PCC), while the secondary cell may operate using a SCC (Specialized Cell CC). For example, due to differences in carrier and / or network environment frequencies, the primary and secondary cells may have different coverage areas.

[0076] Licensed Assisted Access (LAA) refers to downlink carrier aggregation, where licensed frequency carriers associated with the mobile operator are aggregated with frequency carriers in unlicensed spectrum (such as WiFi). LAA uses downlink PCC (Control and Signaling Code) in the licensed spectrum to carry control and signaling information associated with the communication link, while unlicensed spectrum is aggregated for wider downlink bandwidth when available. LAA can operate with dynamic adjustment of secondary carriers to avoid coexistence with WiFi users. Enhanced Licensed Assisted Access (eLAA) is an evolution of LAA that aggregates licensed and unlicensed spectrum for both downlink and uplink.

[0077] Figure 3A This is a schematic diagram of an example of a downlink channel using multiple-input multiple-output (MIMO) communication. Figure 3BThis is a schematic diagram of an example of an uplink channel using MIMO communication.

[0078] MIMO communication uses multiple antennas to simultaneously transmit multiple data streams on a common spectrum. In some implementations, the data streams operate with different reference signals to enhance data reception at the receiver. MIMO communication benefits from higher SNR, improved coding, and / or reduced signal interference due to spatial multiplexing differences in the radio environment.

[0079] MIMO order refers to the number of separate data streams transmitted or received. For example, the MIMO order used for downlink communication can be described by the number of transmit antennas at the base station and the number of receive antennas for the UE (such as a mobile device). For example, 2x2 DL MIMO refers to MIMO downlink communication using two base station antennas and two UE antennas. Similarly, 4x4 DL MIMO refers to MIMO downlink communication using four base station antennas and four UE antennas.

[0080] exist Figure 3A In the example shown, downlink MIMO communication is provided by transmitting using M antennas 43a, 43b, 43c, ... 43m of base station 41 and receiving using N antennas 44a, 44b, 44c, ... 44n of mobile device 42. Therefore, Figure 3A An example of mxn DL MIMO is shown.

[0081] Similarly, the MIMO order used for uplink communication can be described by the number of transmit antennas of the UE (such as a mobile device) and the number of receive antennas of the base station. For example, 2x2 UL MIMO refers to MIMO uplink communication using two UE antennas and two base station antennas. Conversely, 4x4 UL MIMO refers to MIMO uplink communication using four UE antennas and four base station antennas.

[0082] exist Figure 3B In the example shown, uplink MIMO communication is provided by transmitting using N antennas 44a, 44b, 44c, ... 44n of mobile device 42 and receiving using M antennas 43a, 43b, 43c, ... 43m of base station 41. Therefore, Figure 3B An example of nxm UL MIMO is shown.

[0083] By increasing the level or order of MIMO, the bandwidth of the uplink channel and / or downlink channel can be increased.

[0084] MIMO communication is suitable for various types of communication links, such as FDD and TDD communication links.

[0085] Figure 3C This is a schematic diagram of another example of an uplink channel using MIMO communication. Figure 3C In the example shown, uplink MIMO communication is provided by transmitting using N antennas 44a, 44b, 44c, ... 44n of the mobile device 42. Furthermore, the first portion of the uplink transmission is received using M antennas 43a1, 43b1, 43c1, ... 43m1 of the first base station 41a, and the second portion of the uplink transmission is received using M antennas 43a2, 43b2, 43c2, ... 43m2 of the second base station 41b. Additionally, the first base station 41a and the second base station 41b communicate with each other via wired, optical, and / or wireless links.

[0086] Figure 3C The MIMO scenario illustrates an example of multiple base stations cooperating to facilitate MIMO communication.

[0087] Figure 5A This is a schematic diagram of an example of a communication system 110 that operates using beamforming. The communication system 110 includes a transceiver 105, signal conditioning circuits 104a1, 104a2…104an, 104b1, 104b2…104bn, 104m1, 104m2…104mn, and an antenna array 102, which includes antenna elements 103a1, 103a2…103an, 103b1, 103b2…103bn, 103m1, 103m2…103mn.

[0088] Communication systems that use millimeter-wave carriers (e.g., 30 GHz to 300 GHz), centimeter-wave carriers (e.g., 3 GHz to 30 GHz), and / or other frequency carriers for communication can employ antenna arrays to provide beamforming and directivity for signal transmission and / or reception.

[0089] For example, in the illustrated embodiment, the communication system 110 includes an array 102 of m x n antenna elements, each of which is controlled by a separate signal conditioning circuit. As indicated by the ellipsis, the communication system 110 can be implemented with any suitable number of antenna elements and signal conditioning circuits.

[0090] Regarding signal transmission, the signal conditioning circuit can provide a transmit signal to the antenna array 102, such that the signals radiated from the antenna elements are combined using constructive and destructive interference to generate a converged transmit signal, which exhibits beamforming qualities with greater signal strength propagating away from the antenna array 102 in a given direction.

[0091] In the case of signal reception, the signal conditioning circuit processes the received signal (e.g., by controlling the phase of the received signal separately) so that more signal energy is received when the signal arrives at the antenna array 102 from a specific direction. Therefore, the communication system 110 also provides directionality for receiving signals.

[0092] The relative concentration of signal energy entering a transmit or receive beam can be enhanced by increasing the size of the array. For example, with more signal energy focused into the transmit beam, the signal can propagate over a longer distance while providing a sufficient signal level for RF communication. For instance, a signal with a large amount of signal energy focused into the transmit beam can exhibit highly efficient isotropic radiated power (EIRP).

[0093] In the illustrated embodiment, transceiver 105 provides a transmit signal to the signal conditioning circuit and processes the signal received from the signal conditioning circuit. For example... Figure 4A As shown, transceiver 105 generates control signals for the signal conditioning circuit. These control signals can be used for various functions, such as controlling the gain and phase of the transmitted and / or received signals to control beamforming.

[0094] Figure 4B This is a schematic diagram of an example of beamforming to provide a transmission beam. Figure 4B A portion of a communication system is shown, which includes a first signal conditioning circuit 114a, a second signal conditioning circuit 114b, a first antenna element 113a, and a second antenna element 113b.

[0095] Although shown as including two antenna elements and two signal conditioning circuits, the communication system may include additional antenna elements and / or signal conditioning circuits. For example, Figure 4B It shows Figure 4A An embodiment of a partial communication system.

[0096] The first signal conditioning circuit 114a includes a first phase shifter 130a, a first power amplifier 131a, a first low-noise amplifier (LNA) 132a, and a switch for controlling the selection of power amplifier 131a or LNA 132a. The second signal conditioning circuit 114b includes a second phase shifter 130b, a second power amplifier 131b, a second LNA 132b, and a switch for controlling the selection of power amplifier 131b or LNA 132b.

[0097] Although one embodiment of the signal conditioning circuit has been shown, other implementations of the signal conditioning circuit are possible. For example, in one example, the signal conditioning circuit includes one or more band filters, duplexers, and / or other components.

[0098] In the illustrated embodiment, the first antenna element 113a and the second antenna element 113b are separated by a distance d. Additionally, Figure 4B The angle θ is labeled. In this example, when the direction of the transmitted beam is substantially perpendicular to the plane of the antenna array, the angle θ is approximately 90°, and when the direction of the transmitted beam is substantially parallel to the plane of the antenna array, the angle θ is approximately 0°.

[0099] The desired transmit beam angle θ can be achieved by controlling the relative phase of the transmit signals supplied to antenna elements 113a and 113b. For example, when the first phase shifter 130a has a reference value of 0°, the second phase shifter 130b can be controlled to provide a phase shift of approximately -2πf(d / ν)cosθ radians, where f is the fundamental frequency of the transmit signal, d is the distance between the antenna elements, v is the velocity of the radiated wave, and π is the mathematical constant "π".

[0100] In some implementations, the distance d is realized as approximately 1 / 2λ, where λ is the wavelength of the fundamental component of the transmitted signal. In such an implementation, the second phase shifter 130b can be controlled to provide a phase shift of approximately -πcosθ radians to achieve the transmitted beam angle θ.

[0101] Therefore, the relative phase of phase shifters 130a and 130b can be controlled to provide transmit beamforming. In some embodiments, the baseband processor and / or transceiver (e.g., Figure 4A The transceiver 105 controls the phase value of one or more phase shifters and the gain value of one or more controllable amplifiers, thereby controlling beamforming.

[0102] Figure 4C This is a schematic diagram of an example of beamforming to provide a receiving beam. Figure 4C Similar to Figure 4B The difference is Figure 4C The diagram illustrates beamforming in the case of receiving a beam instead of transmitting a beam.

[0103] like Figure 4C As shown, the relative phase difference between the first phase shifter 130a and the second phase shifter 130b can be selected to be approximately equal to -2πf(d / ν)cosθ radians to achieve the desired receiving beam angle θ. In the case where the distance d corresponds to approximately 1 / 2λ, the phase difference can be selected to be approximately equal to -πcosθ radians to achieve the receiving beam angle θ.

[0104] Although various formulas have been provided for providing phase values ​​for beamforming, other phase selection values ​​are also possible, such as those based on the implementation of the antenna array, the implementation of the signal conditioning circuit, and / or the radio environment.

[0105] Figure 5A This is a perspective view of an embodiment of module 140 that operates using beamforming. Figure 5B It is a cross-section of module 140 in Figure 5, taken along line 6B-6B.

[0106] Module 140 includes a laminated substrate or laminate 141, a semiconductor die or IC 142 (in which...). Figure 5A (Not visible in the middle), Surface mount device (SMD) 143 (in) Figure 5A (Not visible in the image), and an antenna array containing antenna elements 151a1, 151a2, 151a3…151an, 151b1, 151b2, 151b3…151bn, 151c1, 151c2, 151c3…151cn, 151m1, 151m2, 151m3…151mn.

[0107] Despite Figure 5A and 5B The illustration shows one embodiment of the module, but the teachings herein apply to modules implemented in a wide variety of ways. For example, a module may include antenna elements, wafers, and / or surface mount devices in different arrangements and / or numbers. Additionally, module 140 may include other structures and components, including but not limited to package structures, shielding structures, and / or wire bonding.

[0108] Antenna elements 151a1, 151a2, 151a3…151an, 151b1, 151b2, 151b3…151bn, 151c1, 151c2, 151c3…151cn, 151m1, 151m2, 151m3…151mn are formed on the first surface of the laminate 141 and can be used to receive and / or transmit signals according to embodiments. Although a 4x4 array of antenna elements is shown, more or fewer antenna elements are also possible, as indicated by ellipses. Furthermore, the antenna elements can be arranged in other patterns or configurations, including, for example, arrays using non-uniformly arranged antenna elements. Additionally, in another embodiment, multiple antenna arrays are provided, such as antenna arrays for transmission and reception and / or for separation of different communication frequency bands.

[0109] In the illustrated embodiment, IC142 is on the second surface of the laminate 141 opposite to the first surface. However, other implementations are also possible. In one example, IC142 is internally integrated into the laminate 141.

[0110] In some embodiments, IC142 includes signal conditioning circuitry associated with antenna elements 151a1, 151a2, 151a3…151an, 151b1, 151b2, 151b3…151bn, 151c1, 151c2, 151c3…151cn, 151m1, 151m2, 151m3…151mn. In one embodiment, IC142 includes a serial interface, such as a Mobile Industrial Processor Interface Radio Front End (MIPIRFFE) bus and / or an Inter-Integrated Circuit (I2C) bus, which receives data for controlling the signal conditioning circuitry, such as phase shift amounts provided by a phase shifter. In another embodiment, IC142 includes signal conditioning circuitry associated with antenna elements 151a1, 151a2, 151a3…151an, 151b1, 151b2, 151b3…151bn, 151c1, 151c2, 151c3…151cn, 151m1, 151m2, 151m3…151mn and an integrated transceiver.

[0111] Laminate 141 may include various structures, including, for example, conductive layers, dielectric layers, and / or solder masks. The number of layers, layer thickness, and materials used to form these layers can be selected based on a wide range of factors and may vary depending on the application and / or implementation. Laminate 141 may include vias for providing electrical connections to signal feeds and / or ground feeds of antenna elements. For example, in some implementations, vias may help provide electrical connections between the signal conditioning circuitry of IC 142 and the corresponding antenna element.

[0112] Antenna elements 151a1, 151a2, 151a3…151an, 151b1, 151b2, 151b3…151bn, 151c1, 151c2, 151c3…151cn, 151m1, 151m2, 151m3…151mn can correspond to antenna elements implemented in a wide variety of ways. In one example, the array of antenna elements includes patch antenna elements formed by a patterned conductive layer on a first side of the laminate 141, and a ground plane formed by a conductive layer on the opposite side of the laminate 141 or inside the laminate 141. Other examples of antenna elements include, but are not limited to, dipole antenna elements, ceramic resonators, stamped metal antennas, and / or laser-guided structured antennas.

[0113] Module 140 may include a communication system, such as a mobile phone or a base station. In one example, module 140 is attached to the telephone board of a mobile phone.

[0114] Figure 6This is a schematic diagram of a mobile device 800. The mobile device 800 includes a baseband system 801, a submillimeter-wave (mmW) transceiver 802, a submmW front-end system 803, a submmW antenna 804, a power management system 805, a memory 806, a user interface 807, an mmW baseband (BB) / intermediate frequency (IF) transceiver 812, an mmW front-end system 813, and an mmW antenna 814.

[0115] Mobile devices 800 can communicate using a wide range of communication technologies, including but not limited to 2G, 3G, 4G (including LTE, Advanced LTE and Advanced LTE Pro), 5G NR, WLAN (e.g., WiFi), WPAN (e.g., Bluetooth and ZigBee), WMAN (e.g., WiMax), and / or GPS technologies.

[0116] In the illustrated embodiment, the sub-mmW transceiver 802, sub-mmW front-end system 803, and sub-mmW antenna 804 are used to transmit and receive centimeter waves and other radio frequency signals at frequencies below millimeter waves. Additionally, the mmWBB / IF transceiver 812, mmW front-end system 813, and mmW antenna 814 are used to transmit and receive millimeter waves. Although a specific example is shown, other implementations are possible, including, but not limited to, mobile devices operating using circuitry running on different frequency ranges and wavelengths.

[0117] The sub-mmW transceiver 802 generates RF signals for transmission and processes incoming RF signals received from the sub-mmW antenna 804. It should be understood that various functions associated with transmitting and receiving RF signals can be implemented through... Figure 6 The overall implementation is shown as one or more components of a sub-mmW transceiver 802. In one example, separate components (e.g., separate circuits or wafers) may be provided to handle certain types of RF signals.

[0118] The sub-mmW front-end system 803 assists in regulating signals transmitted to and / or received from antenna 804. In the illustrated embodiment, the front-end system 803 includes a power amplifier (PA) 821, a low-noise amplifier (LNA) 822, a filter 823, a switch 824, and a signal splitting / combining circuit 825. However, other implementations are also possible.

[0119] For example, the sub-mmW front-end system 803 can provide a number of functions, including but not limited to, amplifying signals for transmission, amplifying received signals, filtering signals, switching between different frequency bands, switching between different power modes, switching between transmit and receive modes, signal duplexing, signal multiplexing (e.g., duplex or triplex), or some combination thereof.

[0120] In some implementations, the mobile device 800 supports carrier aggregation, thereby providing flexibility to increase peak data rates. Carrier aggregation can be used for both frequency division duplex (FDD) and time division duplex (TDD), and can be used to aggregate multiple carriers or channels. Carrier aggregation includes contiguous aggregation, where consecutive carriers within the same operating frequency band are aggregated. Carrier aggregation can also be discontinuous and can include carriers that are frequency-separated within a common frequency band or in different frequency bands.

[0121] The sub-mmW antenna 804 may include antennas for a wide variety of types of communication. For example, the sub-mmW antenna 804 may include antennas for transmitting and / or receiving signals associated with a wide variety of frequencies and communication standards.

[0122] The mmW BB / IF transceiver 812 generates millimeter-wave signals for transmission and processes incoming millimeter-wave signals received from the mmW antenna 814. It should be understood that various functions associated with the transmission and reception of RF signals can be achieved through… Figure 6 The overall implementation is shown as one or more components of the mmWBB / IF transceiver 812. The mmWBB / IF transceiver 812 can operate at baseband or intermediate frequency depending on the implementation.

[0123] The mmW front-end system 813 assists in regulating signals transmitted to and / or received from the mmW antenna 814. In the illustrated embodiment, the front-end system 803 includes a power amplifier 831, a low-noise amplifier 832, a switch 833, an up-converter 834, a down-converter 835, and a phase shifter 836. However, other implementations are possible. In one example, the mobile device 800 works with a BBmmW transceiver, and the up-converter and down-converter are omitted from the mmW front-end system. In another example, the mmW front-end system also includes a filter for filtering millimeter-wave signals.

[0124] The mmW antenna 814 may include antennas for a wide variety of types of communication. The mmW antenna 814 may include antenna elements implemented in a wide variety of ways, and in some configurations, the antenna elements are arranged to form one or more antenna arrays. Examples of antenna elements for millimeter-wave antenna arrays include, but are not limited to, patch antennas, dipole antenna elements, ceramic resonators, stamped metal antennas, and / or laser-guided structured antennas.

[0125] In some implementations, the mobile device 800 supports MIMO communication and / or switchable diversity communication. For example, MIMO communication uses multiple antennas to transmit multiple data streams on a single radio frequency channel. MIMO communication benefits from a higher signal-to-noise ratio, improved coding, and / or reduced signal interference due to spatial multiplexing differences in the radio environment. Switchable diversity refers to communication in which a specific antenna is selected for operation at a specific time. For example, a switch can be used to select a specific antenna from a set of antennas based on various factors, such as observed bit error rate and / or signal strength indicators.

[0126] In some implementations, the mobile device 800 operates with beamforming. For example, the mmW front-end system 803 includes an amplifier with controllable gain and a phase shifter with controllable phase to provide beamforming and directivity for transmitting and / or receiving signals using the mmW antenna 814. For example, in the case of signal transmission, the amplitude and phase of the transmitted signal provided to the antenna array for transmission are controlled such that the radiated signals are combined using constructive and destructive interference to generate a converged transmitted signal that exhibits beamforming qualities, propagating more signal strength in a given direction. In the case of signal reception, the amplitude and phase are controlled such that more signal energy is received when the signal arrives at the antenna array from a specific direction.

[0127] The baseband system 801 is coupled to the user interface 807 to handle various user inputs and outputs (I / O), such as voice and data. The baseband system 801 provides a digital representation of the transmitted signals to sub-mmW and mmW transceivers, which are processed by the transceivers to generate RF signals for transmission. The baseband system 801 also processes a digital representation of the received signals provided by the transceivers. Figure 6 As shown, the baseband system 801 is coupled to the memory 806 to facilitate the operation of the mobile device 800.

[0128] The memory 806 can be used for a wide range of purposes, such as storing data and / or instructions to facilitate the operation of the mobile device 800 and / or providing storage for user information.

[0129] The power management system 805 provides multiple power management functions for the mobile device 800. In some embodiments, the power management system 805 includes PA power supply control circuitry that controls the supply voltage of the power amplifiers in the front-end system. For example, the power management system 805 may be configured to change the supply voltage supplied to one or more power amplifiers to improve efficiency, such as power-added efficiency (PAE).

[0130] In some implementations, the power management system 805 receives battery voltage from the battery. The battery can be any suitable battery for the mobile device 800, including, for example, a lithium-ion battery.

[0131] Figure 7 This is a schematic diagram of another mobile device 800. The mobile device 800 includes one or more baseband systems 801, one or more transceivers 802, one or more front-end systems 803, one or more antennas 804, a power management system 805, a memory 806, a user interface 807, and a battery 808. The mobile device 800 also includes a master clock generator 809 and an injection lock detector (ILD) 817.

[0132] Mobile devices 800 can communicate using a wide range of communication technologies, including but not limited to 2G, 3G, 4G (including LTE, Advanced LTE and Advanced LTE Pro), 5G NR, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth and ZigBee), WMAN (e.g., WiMax), and / or GPS technology.

[0133] Transceiver 802 generates RF signals for transmission and processes input RF signals received from antenna 804. It should be understood that various functions associated with the transmission and reception of RF signals can be achieved through… Figure 7 The transceiver 802 is implemented by one or more components. In one example, separate components (e.g., separate circuits or chips) may be provided to handle certain types of RF signals.

[0134] The front-end system 803 assists in regulating signals transmitted to and / or received from the antenna 804. In the illustrated embodiment, the front-end system 803 includes a power amplifier (PA) 811, a low-noise amplifier (LNA) 812, a filter 813, a switch 814, and a duplexer 8153. However, other implementations are also possible.

[0135] For example, the front-end system 803 may provide multiple functions, including but not limited to, amplifying the signal for transmission, amplifying the received signal, filtering the signal, switching between different frequency bands, switching between different power modes, switching between transmission and reception modes, signal duplexing, signal multiplexing (e.g., duplex or triplex), or some combination thereof.

[0136] In some implementations, the mobile device 800 supports carrier aggregation, thereby providing flexibility to increase peak data rates. Carrier aggregation can be used for both frequency division duplex (FDD) and time division duplex (TDD), and can be used to aggregate multiple carriers or channels. Carrier aggregation includes contiguous aggregation, where consecutive carriers within the same operating frequency band are aggregated. Carrier aggregation can also be discontinuous and can include carriers that are frequency-separated within a common frequency band or in different frequency bands.

[0137] Antenna 804 may include antennas for a wide variety of types of communication. For example, antenna 804 may include antennas for transmitting and / or receiving signals associated with a wide variety of frequencies and communication standards.

[0138] In some implementations, antenna 804 supports MIMO communication and / or switchable diversity communication. For example, MIMO communication uses multiple antennas to transmit multiple data streams on a single radio frequency channel. MIMO communication benefits from a higher signal-to-noise ratio, improved coding, and / or reduced signal interference due to spatial multiplexing differences in the radio environment. Switchable diversity refers to communication in which a specific antenna is selected for operation at a specific time. For example, a switch can be used to select a specific antenna from a set of antennas based on various factors, such as observed bit error rate and / or signal strength indicators.

[0139] The mobile device 800 may operate using beamforming in some embodiments. For example, the front-end system 803 may include a phase shifter with a variable phase controlled by a transceiver 802. Furthermore, the phase shifter is controlled to provide beamforming and directivity for transmitting and / or receiving signals using an antenna 804. For example, in the case of signal transmission, the phase of the transmitted signal supplied to the antenna 804 is controlled such that the signal radiated from the antenna 804 is combined using constructive and destructive interference to generate a converged transmitted signal that exhibits beamforming qualities, propagating more signal strength in a given direction. In the case of signal reception, the phase is controlled such that more signal energy is received when the signal arrives at the antenna 804 from a specific direction. In some embodiments, the antenna 804 includes one or more arrays of antenna elements to enhance beamforming.

[0140] The baseband system (also simply referred to as baseband) 801 is coupled to the user interface 807 to handle various user inputs and outputs (I / O), such as voice and data. The baseband system 801 provides a digital representation of the transmitted signal to the transceiver 802, which is processed by the transceiver 802 to generate an RF signal for transmission. The baseband system 801 also processes the digital representation of the received signal provided by the transceiver 802. For example... Figure 7 As shown, the baseband system 801 is coupled to the memory 806 to facilitate the operation of the mobile device 800.

[0141] The memory 806 can be used for a wide range of purposes, such as storing data and / or instructions to facilitate the operation of the mobile device 800 and / or to provide storage for user information.

[0142] The power management system 805 provides multiple power management functions for the mobile device 800. In some embodiments, the power management system 805 includes PA power supply control circuitry that controls the supply voltage of the power amplifier 811. For example, the power management system 805 may be configured to change the supply voltage supplied to one or more power amplifiers 811 to improve efficiency, such as power-added efficiency (PAE).

[0143] like Figure 7 As shown, the power management system 805 receives battery voltage from the battery 808. The battery 808 can be any battery suitable for the mobile device 800, including, for example, a lithium-ion battery.

[0144] Master clock generator 809 generates a master clock signal provided to transceiver 802. As described in more detail below, the master clock signal can be used by components of transceiver 802 to generate a clock signal, which can be used as the clock input to the mixer of the modulator and / or demodulator of transceiver 802. In some embodiments, transceiver 802 may include one or more injection-locked oscillators (ILOs) (e.g., such as...). Figure 10 As shown in the figure, it generates clock signals based on the master clock signal.

[0145] The injection lock detector 817 receives a clock signal generated based on the master clock signal from the transceiver 802. The injection lock detector 817 can also be configured to determine whether the ILO is operating within the injection lock region. Further details regarding the functionality of the injection lock detector 817 are provided below.

[0146] Figure 8 This is a schematic diagram of a power amplifier system 840 according to one embodiment. The power amplifier system 840 shown includes a baseband 801, a transceiver 802, a front-end 803, an antenna 804, a power management system 805, a master clock generator 809, and an injection lock detector 817. The front-end 803 includes one or more power amplifiers (PAs) 811, a directional coupler 824, front-end circuitry 825, and a low-noise amplifier (LNA) 812. The power management system 805 includes PA bias control circuitry 827 and PA power supply control circuitry 828.

[0147] Figure 9This is a schematic diagram of an example transceiver 802 according to one embodiment. The transceiver 802 shown includes a pair of digital-to-analog converters (DACs) 835, a pair of analog-to-digital converters (ADCs) 836, an I / Q modulator 837, an I / Q mixer 838, and a local oscillator (LO) distribution network 200, which may include one or more LO distribution circuits (also referred to as LO distribution units). The I / Q modulator 837 includes a pair of mixers 839 configured to receive I and Q signals from the DACs, and a signal combiner 841 configured to receive the output from the mixers 839. The I / Q mixer 838 includes a pair of mixers 839 configured to receive the output from the front end 802.

[0148] Referring again to Figures 3 and 4, the baseband system 801 can be used to generate in-phase (I) and quadrature-phase (Q) signals, which can be used to represent sine waves or signals with desired amplitude, frequency, and phase. For example, the I signal can be used to represent the in-phase component of a sine wave, and the Q signal can be used to represent the quadrature-phase component of a sine wave, which can be an equivalent representation of the sine wave. Figure 9 As shown, the I and Q signals can be provided in digital format to the I / Q modulator 837 by the DAC 835. The baseband system 801 can be implemented as any suitable processor configured to process baseband signals. For example, the baseband system 801 may include a digital signal processor, a microprocessor, a programmable core, or any combination thereof. Furthermore, in some embodiments, two or more baseband processors may be included in the baseband system 801.

[0149] I / Q modulator 837 may be configured to receive I and Q signals from baseband processor 821, process the I and Q signals to generate an RF signal, and then provide the RF signal to front end 902. For example, I / Q modulator 837 may include mixer 839 and signal combiner 841, the mixer being used to up-convert the I and Q signals to RF, and the signal combiner 841 being used to combine the up-converted I and Q signals into an RF signal suitable for amplification by power amplifier 811 of front end 803. In some embodiments, I / Q modulator 837 may include one or more filters (not shown) configured to filter the frequency content of the signals processed therein.

[0150] Power amplifier 823 can receive RF signals from I / Q modulator 837 and, when enabled, can provide amplified RF signals to antenna 804 via front-end circuitry 825. Front-end circuitry 825 can be implemented in a wide variety of ways. In one example, front-end circuitry 825 includes one or more switches, multiple filters, multiple duplexers, multiple multiplexers, and / or other components. In another example, front-end circuitry 825 is omitted to allow power amplifier 811 to directly provide amplified RF signals to antenna 804.

[0151] A directional coupler 824 is configured to sense the output signal of the power amplifier 811. Furthermore, the sensed output signal from the directional coupler 824 is provided to an I / Q mixer 838, which is configured to multiply the sensed output signal by a reference clock signal having a controlled frequency, received at the I / Q mixer 838 from the LO distribution network 200. As will be described in more detail later, one or more local oscillators (LOs) may be included in the LO distribution network 200 to provide a controlled frequency to each of the I / Q modulator 837 and the I / Q mixer 838. The I / Q mixer 838 is configured to generate a down-shifted signal by down-shifting the frequency content of the sensed output signal (received from the front end 803). The down-shifted signal may be provided to an ADC 836, which may convert the down-shifted signal into a digital format suitable for processing by the baseband system 801. Including a feedback path from the output of power amplifier 811 to baseband system 801 can provide several advantages. For example, implementing baseband system 801 in this way can help provide power control, compensate for transmitter losses, and / or perform digital predistortion (DPD). Although an example of a sensing path for the power amplifier is shown, other implementations are possible.

[0152] PA power supply control circuit 828 receives power control signals from baseband system 801 and controls the supply voltage of power amplifier 811. In the illustrated configuration, PA power supply control circuit 828 generates a first supply voltage V. CC1 This powers the input stage power amplifier 811 and provides a second supply voltage V. CC2 This supplies power to the output stage power amplifier 811. The PA power supply control circuit 828 can control the first supply voltage V. CC1 and / or second supply voltage V CC2 The voltage level is adjusted to enhance the power increase efficiency (PAE) of the power amplifier system. The PA power supply control circuit 828 can employ various power management techniques to change the voltage level of one or more supply voltages over time, thereby improving the PAE of the power amplifier and thus reducing power dissipation.

[0153] One technique for improving the efficiency of power amplifiers is Average Power Tracking (APT), where a DC-to-DC converter generates the supply voltage for the power amplifier based on the amplifier's average output power. Another technique for improving power amplifier efficiency is Envelope Tracking (ET), where the power amplifier's supply voltage is controlled relative to the envelope of an RF signal. Therefore, when the voltage level of the RF signal envelope increases, the supply voltage level of the power amplifier can increase. Similarly, when the voltage level of the RF signal envelope decreases, the supply voltage level of the power amplifier can decrease to reduce power consumption.

[0154] In some configurations, the PA power supply control circuit 828 is a multi-mode power supply control circuit that can operate in multiple power supply control modes, including APT mode and ET mode. For example, a power control signal from the baseband system 801 can instruct the PA power supply control circuit 828 to operate in a specific power supply control mode.

[0155] like Figure 8 As shown, the PA bias control circuit 827 receives a bias control signal from the baseband system 801 and generates a bias control signal for the power amplifier 811. In the illustrated configuration, the bias control circuit 827 generates bias control signals for both the input stage and the output stage of the power amplifier 811. However, other implementations are also possible.

[0156] Introduction to the use of injection-locked oscillators in transceiver arrays

[0157] In some cellular communication technologies (such as the 5G standard), multiple antennas 804 can be used to transmit signals to / from a cell base station (e.g., Figure 1B The user equipment (UE) transmits and receives signals via a large cell base station 1 and / or a small cell base station 3. In some embodiments, the UE may include 64 individual element antennas 804, each operatively coupled to a single transceiver path. Each transceiver path may include a corresponding front end 803 and transceiver 802. However, in other embodiments, the UE may be implemented to include more or fewer antennas 804 and / or transceiver paths. The use of multiple antennas 804 can be an important aspect of enabling RF communication at higher frequencies (e.g., frequencies above 6 GHz). For example, the use of multiple antennas 804 can be used to enable communication at 6 GHz or higher frequencies, and some embodiments may use 64 antennas 804 for communication at 28 GHz.

[0158] As discussed above in conjunction with Figures 3 and 4, the transceiver path between the baseband system 801 and the front-end 803 can involve mixing the transmitted / received RF signal with a reference clock signal. In embodiments with multiple antennas, each RF signal received / transmitted via one of the antennas is mixed with a reference signal separately. Therefore, to implement multiple antenna signals, a reference clock signal is allocated to each one to be provided to the mixer (e.g., Figure 9 The transceiver path of the mixer 839 shown is illustrated. In systems with multiple transceiver paths, the generation and routing of the reference clock signal can be complex and may present challenges, such as reducing / minimizing the delay along the reference clock signal path. Furthermore, using multiple separate clock generators can increase the size and complexity of the transceiver path implementation within the user equipment.

[0159] Various aspects of this application relate to systems and techniques that can be used to address one or more challenges in multi-antenna RF communication systems. In some embodiments, the LO allocation network 200 may include one or more injection-locked oscillators (ILOs) to generate a reference clock signal. Compared to other oscillator circuits, ILOs can have a relatively simple architecture, thereby reducing the space required to generate the reference clock signal.

[0160] A potential design consideration for ILO is that when the ILO is not operating in the injection-locked region, it may not generate a reference clock signal with the desired frequency. Additionally, in some applications, undesirable out-of-band emissions may occur in the transceiver path if injection lock is not maintained. The free-running frequency of the ILO (e.g., the ILO frequency without a control voltage applied) can be affected by external environmental changes (e.g., temperature variations), leading to undesirable frequency variations. Other external circuitry conditions (such as frequency pushes caused by load changes and / or frequency pulls caused by supply voltage changes) can also cause unstable behavior in the ILO. In some implementations, the oscillator used for injection lock may utilize low-Q circuitry to maximize the lockout range, which can increase the chance of ILO drift and loss of lock.

[0161] One aspect of this application includes systems and methods for detecting whether an ILO is injected and locked (e.g., whether the ILO is operating in an injected-locked region). Therefore, various aspects of this application relate to ILO lock detection circuitry (also called an injected-lock detector), which can be used to detect whether an ILO is injected and locked. In some embodiments, the injected-lock detector has a relatively simple architecture compared to more complex injected-lock detectors, thereby reducing the overall complexity of the transceiver path.

[0162] Some techniques used to determine whether an ILO is injected-locked include examining the ILO's spectrum. Using these techniques, an asymmetric sideband distribution can indicate that the ILO has lost lock (e.g., left the injected-lock region). While these techniques are suitable for laboratory testing, they may be too complex to be implemented in some RF communication devices, such as sensors, due to the space and circuitry required to implement them.

[0163] Other methods for lock detection may include feeding an injected lock-in oscillator signal (e.g., the output clock signal from the ILO) and an injected lock signal (e.g., the master clock signal provided as input to the ILO) to a mixer circuit to determine the presence of a zero beat frequency. These methods may require additional mixer components operating at millimeter-wave frequencies and may also require both the injected lock-in oscillator signal and the injected lock signal to be available for presentation to the mixer. In some implementations, directional couplers and / or circulators may be used to provide these signals to an additional mixer. However, these methods increase complexity (e.g., due to the inclusion of directional couplers and / or circulators), negating some of the advantages gained from using an injected lock-in oscillator with a simplified architecture.

[0164] ILO clock signal allocation

[0165] Figure 10 This is a block diagram of an example ILO allocation network 200 according to one embodiment. The ILO allocation network 200 may be included within a transceiver 802, such as... Figure 9 As shown. The ILO distribution network 200 includes multiple ILO distribution circuits 201A, 201B, ..., 201D, each of which receives the master clock signal from the master clock generator 809. Although Figure 10 The diagram shows three ILO distribution circuits 201A, 201B, ..., 201D. Other embodiments may include more or fewer ILO distribution circuits 201A, 201B, ..., 201D.

[0166] Each of the ILO distribution circuits 201A, 201B, ..., 201D is also configured to distribute to one or more corresponding mixers (e.g., Figure 9 The mixer 839 provides a reference clock signal and an output signal to the injection lock detector (ILD) 817. Additionally, as... Figure 10 As shown, the master clock generator 809 can be configured to receive a reference frequency signal FREF as input, which can be used to generate the master clock signal.

[0167] Figure 11 This is a schematic diagram of another example of an ILO allocation network 200 according to one embodiment. (See diagram below.) Figure 11As shown, the ILO distribution network 200 includes four ILO distribution circuits 201A, 201B, 201C, and 201D, each configured to receive the master clock signal from the master clock generator 809. Although Figure 10 The diagram shows three ILO allocation circuits 201A, 201B, 201C, and 201D. In other embodiments, more or fewer ILO allocation circuits 201A, 201B, 201C, and 201D may be included. Additionally, Figure 11 The multiple individual ILO allocation networks 200 shown can be included in a single user equipment. For example, when the user equipment includes 64 antennas, the user equipment can include 16 ILO allocation networks 200.

[0168] The master clock generator may include a master phase-locked loop (PLL) 205 and a multi-phase clock pulse generator 207. The master PLL 205 is configured to receive a reference frequency signal FREF as input and generate an output signal having a phase controlled by time with respect to the phase of the reference frequency signal FREF. The multi-phase clock pulse generator 207 receives the output signal from the master PLL 205 and generates a master signal, which is provided to each of the ILO distribution circuits 201A, 201B, 201C, and 201D.

[0169] Each of the ILO distribution circuits 201A, 201B, 201C, and 201D can have substantially similar structures; therefore, only one of the ILO distribution circuits 201A, 201B, 201C, and 201D is described as representative. Specifically, ILO distribution circuit 201A includes ILO 211, frequency tracking loop 221, multi-phase filter 223, amplifier 225, current-mode logic (CML) 227, and true single-phase clock (TSPC) divider 229. ILO 221 is configured to receive the master clock signal from master clock generator 809 and generate a reference clock signal, which is provided in the transceiver path (e.g., in...). Figure 8 The mixer 839 (used within the power amplifier system 840) can use the master clock signal as input and generate a higher frequency reference clock signal at the frequency required by the mixer 839. Since the ILO 221 is configured to use the master clock signal as an injection input, the master clock signal can also be referred to as the injection clock signal.

[0170] A frequency tracking loop (FTL) 221 is formed in a closed loop with ILO 211 and is configured to determine the frequency of ILO 211. Specifically, FTL 221 can receive the output from ILO 221 and provide a feedback signal to ILO 211 to form a closed loop. Amplifier 225 is configured to amplify the injection-locked oscillator signal output from ILO and then provide the amplified signal to multiphase filter 223 and CML divider 227. Multiphase filter 223 can first filter out certain external frequencies from the amplified injection-locked oscillator signal and then provide the resulting reference clock signal to mixer 839.

[0171] The output signal provided to the ILD817 can indicate the operating frequency of the corresponding ILO211. The ILO distribution circuit 201A can be configured to generate the output signal by down-converting the reference clock to the frequency of the master clock signal. Figure 11 In this embodiment, the CML divider 227 and the TSPC divider 229 can work together to generate an output signal. For example, the CML divider 227 and the TSPC divider 229 can divide the injection-locked oscillator signal to a frequency substantially the same as the master clock signal. The divided clock signal is then output to the ILD817.

[0172] Figure 12 This is a schematic diagram of yet another example of an ILO allocation network 200 according to one embodiment. Because... Figure 12 The embodiments are similar to Figure 11 Implementation examples, Figure 12 Zhongyu Figure 11 Some components that are identical or similar may not be described in detail. Reference Figure 12 Instead of CML divider 227 and TSPC divider 229, the ILO distribution circuit 201A includes mixer 231. Mixer 231 can be implemented as a subharmonic mixer. Mixer 231 is configured to receive both the injection-locked oscillator signal from amplifier 225 and the master clock signal from multiphase clock pulse generator 207 of master clock generator 809. Mixer 231 is also configured to generate a down-shifted signal by down-shifting the injection-locked oscillator signal with the master clock signal. Mixer 231 provides the down-shifted injection-locked oscillator signal to ILD 817.

[0173] Figure 13 This is a schematic diagram of yet another exemplary ILO allocation network 200 according to one embodiment. Figure 13In this embodiment, ILO 221 is implemented as a quadrature ILO, configured to provide quadrature ILO allocation. In the illustrated embodiment, multi-phase clock pulse generator 207 is configured to provide a master clock signal in the format of in-phase (I) and quadrature (Q) signals, each signal being provided to ILO allocation circuits 201A, 201B, 201C, and 201D. The remaining components of ILO allocation circuits 201A, 201B, 201C, and 201D can be configured to... Figure 11 The ILO distribution circuits 201A, 201B, 201C, and 201D operate in a similar manner. Figure 13 The ILO distribution circuit 201A includes and Figure 11 The implementation methods are similar to those of the CML divider 227 and TSPC divider 229 components.

[0174] Figure 14 This is a schematic diagram of another example of an ILO allocation network 200 according to one embodiment. Figure 14 In the examples, Figure 13 QILO implementation scheme and Figure 12 The subharmonic mixer 231 is combined with the implementation scheme. The remaining components can be similar to those described above. Figure 11 The components discussed.

[0175] Example ILD structure and functionality

[0176] exist Figure 6-9 In each embodiment, the output of each of the ILO allocation circuits 201A, 201B, 201C, and 201D can be provided to ILD817, which is configured to determine whether each of the ILOs 211 is operating in the injection lock region. Figure 15 This is a schematic diagram of an example ILD817 according to one embodiment. The ILD817 is configured to receive an output reference clock signal from each ILO211 of the ILO allocation network 200. Although the complete ILO allocation network 200 is not shown in... Figure 15 As shown, however, the ILO allocation network 200 may include other components, such as... Figure 6-9 As shown in the embodiments.

[0177] The ILD817 includes selection logic 315, mixer 317, multiple capacitors 319, 327, and 337, multiple resistors 321, 323, and 335, two comparators 325 and 340, and two diodes 331 and 333. Selection logic 315 can select an input received from one of the ILO211s as the output F to be provided to mixer 317. OUT In some embodiments, selection logic 315 can be implemented as a multiplexer. Mixer 317 will select the output F chosen by the selection logic.OUT With the master clock signal F INJ Combining to generate an intermediate mixed signal F BEAT The intermediate mixed signal is provided to capacitor 319. When the selection logic selects the output F... OUT With the master clock signal F INJ When they are different, the intermediate mixed signal F BEAT It can have a non-zero frequency (e.g., it can have a beat frequency signal indicating that the selected ILO 211 is in the unlocked state). Alternatively, when the selection logic selects the output F OUT With the master clock signal F INJ When they are basically the same, the intermediate mixed signal F BEAT It can have a frequency of approximately zero (e.g., to indicate that the selected ILO211 is in a locked state).

[0178] A combination of components including capacitors 319, 327, and 337, resistors 321, 323, and 335, comparator 325, and two diodes 331 and 333 can be configured to generate an intermediate voltage V. DET Its indication of the intermediate mixed signal F BEAT Does it have a non-zero frequency? For example, when a beat frequency signal is present in the output of mixer 317, the intermediate mixed signal F... BEAT The signal passes through capacitor C3 to comparator 325 and is rectified by a diode network including diodes 331 and 333. Then, a low-pass filter formed by resistor 335 and capacitor 337 filters the intermediate mixed signal F. BEAT The signal is smoothed and then fed to the inverting input of comparator 340.

[0179] Comparator 340 converts the intermediate voltage V DET With reference voltage V REF A comparison is made to provide an output value BIT, which indicates whether the selected ILO211 is in an unlocked or locked state. In this example, when the intermediate voltage V... DET Greater than the reference voltage V REF When the beat frequency signal is not present in the intermediate mixed signal F, the comparator 340 output goes low, indicating that the corresponding ILO 221 is in an unlocked state. BEAT Above, and V DET Less than the reference voltage V REF When this occurs, comparator 340 generates a high output, indicating that ILO is in a locked state.

[0180] Figure 15The illustrated embodiment of ILD817 provides a monolithically integrated solution for detecting whether one or more ILO211s are locked. Conversely, other solutions for determining whether an ILO211 is locked may use large, lumped components that are only suitable for laboratory testing and cannot be efficiently integrated into user equipment. Various aspects of this application, such as Figure 15 The ILO817 also uses low power consumption and has a compact chip area compared to the implementations tested in the lab.

[0181] The ILO 211, with its simple design, can be used across a wide operating frequency range, including frequencies used in 5G (e.g., frequencies in the 6GHz to 30GHz range). Both the ILO 221 and ILD817 have fast response times, allowing the ILD817 to set its output bit low as soon as it detects that the ILO 221 has broken out of its locked state due to a PVT change. In some implementations, the average settling time of the output bit in the ILD817 is less than 1 μs. These features, at least, make the combination of the ILD817 and the ILO allocation network 200 desirable for implementation on large array transceiver systems.

[0182] Figure 16 This is a graph 400 showing example values ​​output from certain components of the ILD817 when the selected ILO211 is in the unlocked state, according to one embodiment. Graph 400 includes the intermediate mixed signal F. BEAT Intermediate voltage V DET Reference voltage V REF And the voltage corresponding to the output value BIT of the new ILO 211 selected by the selection logic. As shown in Figure 16, when ILO 211 is in the unlocked state, the intermediate mixed signal F BEAT It has a non-zero frequency. Due to the electromagnetic coupling of the components in the ILD817, the intermediate voltage V DET Value, reference voltage V REF The value and output value BIT take a certain amount of time to stabilize to a more stable value, as shown at the end of graph 400. After a certain amount of time, the output value stabilizes to 0, indicating that the selected ILO211 is unlocked.

[0183] Figure 17 This is a graph 450 showing example values ​​output from certain components of the ILD817 when the selected ILO211 is in a locked state, according to one embodiment. Graph 450 includes the intermediate mixed signal F. BEAT Intermediate voltage V DET Reference voltage V REF The voltage of the output value BIT in response to the new ILO 211 selected by the selection logic. As shown in Figure 17, when ILO 211 is in the locked state, the intermediate mixed signal FBEAT It has a frequency of approximately zero. After a certain amount of time, the output value stabilizes at 1, indicating that the selected ILO211 is locked.

[0184] Example Multiphase Clock Pulse Generator

[0185] Figure 18 This is a schematic diagram of an example multi-phase clock pulse generator 207 according to one embodiment. The multi-phase clock pulse generator 207 can be configured to generate a master clock signal having a frequency substantially the same as the input clock (e.g., received from the master PLL 205) and having an adjustable phase. In some embodiments, the multi-phase clock pulse generator 207 can select the phase of the master clock signal based on the signal delay between the ILO distribution network 200 and the mixer 839. For example, when the user equipment includes multiple ILO distribution networks 200, the delay between the ILO distribution network 200 and the corresponding mixer 839 can vary, and therefore, the phase of the master clock signal selected by the multi-phase clock pulse generator 207 can compensate for said delay variation.

[0186] Continue to refer to Figure 18 The multi-phase clock pulse generator 207 includes a mixer 505, a low-pass filter 510, a set of delay elements 515, and selection logic 520. The mixer 505 receives the input clock from the main PLL 205 and the output from the last delay element 510. The low-pass filter 510 receives the output signal from the mixer 505 and outputs the filtered signal to each delay element 515. The selection logic 520 selects the output D0, D1, ... D from one of the delay elements 515. N And select the outputs D0, D1, ... D N As the output F of the multi-phase clock pulse generator 207 out Therefore, the multiphase clock pulse generator 207 can select the amount to be added to the output of the input clock signal by selecting the number of delay elements 515 that the clock signal Clock is routed through before being output by the multiphase clock pulse generator 207.

[0187] Figure 19 This is a graph 600 showing example values ​​output from the delay elements 515 of a multiphase clock pulse generator 207 according to one embodiment. Specifically, in the illustrated embodiment, the multiphase clock pulse generator 207 may include eight delay elements 515, each having eight delayed outputs D0, D1, ... D7. Figure 19The phase difference between adjacent delayed outputs is also shown; for example, delayed outputs D0 and D1 are phase-differential by a time period T0. When each delay element 515 is configured to include the same amount of clock signal delay, the phase difference between each of the adjacent delayed outputs D0, D1, ... D7 can be substantially the same. Selection logic 520 is configured to select any one of the delayed outputs D0, D1, ... D7 as the output F of the multi-phase clock pulse generator 207. out .

[0188] Numbered Examples

[0189] Several numbered embodiments of the subject matter described in this application are given below.

[0190] 1. An injection-locked oscillator distribution system, comprising:

[0191] The master clock generator is configured to generate the master clock signal;

[0192] An injection-locked oscillator (ILO) distribution circuit includes an ILO configured to receive a master clock signal, the ILO being configured to generate a reference clock signal based on the master clock signal, and the ILO distribution circuit is further configured to generate an output signal indicating the operating frequency of the ILO; and

[0193] An injection lock detector is configured to receive a master clock signal and an output signal, and the injection lock detector is further configured to determine whether the injection lock oscillator is in a locked or unlocked state based on the master clock signal and the output signal.

[0194] 2. The injection-locked oscillator distribution system according to Embodiment 1, wherein the injection-locked oscillator is further configured to generate a reference clock signal having a higher frequency than the master clock signal, and the injection-locked oscillator distribution circuit is further configured to generate an output signal by down-converting the reference clock signal to the frequency of the master clock signal.

[0195] 3. The injection-locked oscillator distribution system according to Embodiment 2, wherein the injection-locked oscillator distribution circuit further includes a mixer configured to generate an output signal.

[0196] 4. The injection-locked oscillator distribution system according to Embodiment 2, wherein the injection-locked oscillator distribution circuit further includes a frequency divider circuit configured to generate an output signal.

[0197] 5. The injection-locked oscillator distribution system according to Embodiment 1, wherein the injection-locked detector includes a mixer configured to mix an output signal with a master clock signal to generate an intermediate mixed signal, and the injection-locked detector is further configured to determine whether the injection-locked oscillator is in a locked state or an unlocked state based on the intermediate mixed signal.

[0198] 6. The injection-locked oscillator distribution system according to Embodiment 5, wherein the injection-locked detector includes a low-pass filter configured to receive an intermediate mixed signal and generate an intermediate voltage, and the injection-locked detector further includes a comparator configured to compare the intermediate voltage with a reference voltage and output a signal indicating whether the injection-locked oscillator is in a locked state or an unlocked state based on the comparison between the intermediate voltage and the reference voltage.

[0199] 7. The injection-locked oscillator distribution system according to Embodiment 1 further includes an additional injection-locked oscillator distribution circuit, wherein the injection-locked detector further includes selection logic configured to select one of an output signal and an additional output signal from the additional injection-locked oscillator.

[0200] 8. The injection-locked oscillator distribution system according to Embodiment 1, wherein the injection-locked oscillator distribution circuit is operatively coupled to a mixer of a transceiver circuit, and the injection-locked oscillator distribution circuit is further configured to provide a reference clock signal to the mixer.

[0201] 9. A method for detecting an injected lock state, comprising:

[0202] The master clock signal is generated by the master clock generator;

[0203] The master clock signal is received at the injection-locked oscillator distribution circuit, which includes an injection-locked oscillator;

[0204] A reference clock signal is generated at the injection-locked oscillator based on the master clock signal;

[0205] An output signal is generated at the injection-locked oscillator distribution circuit, the output signal indicating the operating frequency of the injection-locked oscillator;

[0206] The master clock signal and the output signal are received at the injection lock detector; and

[0207] The injection lock detector determines whether the injection lock oscillator is in a locked or unlocked state based on the master clock signal and the output signal.

[0208] 10. The method according to embodiment 9 further includes:

[0209] A reference clock signal with a higher frequency than the master clock signal is generated at the injection-locked oscillator; and

[0210] The output signal is generated at the injection-locked oscillator distribution circuit by down-converting the reference clock signal to the frequency of the master clock signal.

[0211] 11. The method according to embodiment 10 further includes generating an output signal at the mixer of the injection-locked oscillator distribution circuit.

[0212] 12. The method according to embodiment 10 further includes generating an output signal at the frequency divider circuit of the injection-locked oscillator distribution circuit.

[0213] 13. The method according to embodiment 9 further includes:

[0214] The output signal is mixed with the master clock signal at a mixer included in the injection lock detector to generate an intermediate mixed signal; and

[0215] At the injection lock detector, it is determined whether the injection lock oscillator is in a locked or unlocked state based on the intermediate mixed signal.

[0216] 14. The method according to embodiment 13 further includes:

[0217] An intermediate voltage is generated at the low-pass filter of the injection lock detector based on the intermediate mixed signal;

[0218] The intermediate voltage is compared with a reference voltage at the comparator of the injection lock detector; and

[0219] At the comparator, a signal is output based on a comparison between the intermediate voltage and the reference voltage, indicating whether the injection-locked oscillator is in a locked or unlocked state.

[0220] 15. The method according to embodiment 9 further includes: at the selection logic, selecting one of the output signal and an additional output signal received from the additional injection-locked oscillator.

[0221] 16. The method according to embodiment 9 further includes a mixer for providing a reference clock signal to the transceiver circuit.

[0222] 17. A mobile device, comprising:

[0223] antenna;

[0224] A transceiver circuit operatively coupled to the antenna, the transceiver including a first mixer;

[0225] The master clock generator is configured to generate the master clock signal;

[0226] An injection-locked oscillator (ILO) distribution circuit includes an ILO and is configured to receive the master clock signal, the ILO being operatively coupled to the first mixer and configured to generate a reference clock signal based on the master clock signal and provide the reference clock signal to the first mixer. The ILO distribution circuit is further configured to generate an output signal indicating the operating frequency of the ILO.

[0227] An injection lock detector is configured to receive a master clock signal and an output signal, and the injection lock detector is further configured to determine whether the injection lock oscillator is in a locked state or an unlocked state based on the master clock signal and the output signal.

[0228] 18. The mobile device according to embodiment 17, wherein the injection-locked oscillator is further configured to generate a reference clock signal having a frequency higher than that of the master clock signal, and the injection-locked oscillator distribution circuit is further configured to generate an output signal by down-converting the reference clock signal to the frequency of the master clock signal.

[0229] 19. The mobile device according to embodiment 18, wherein the injection-locked oscillator distribution circuit further includes a second mixer configured to generate an output signal.

[0230] 20. The mobile device according to embodiment 18, wherein the injection-locked oscillator distribution circuit further includes a frequency divider circuit configured to generate an output signal.

[0231] 21. An injection-locked oscillator distribution system, comprising:

[0232] The master clock generator is configured to generate the master clock signal;

[0233] Transceiver circuitry, including multiple mixers;

[0234] An injection-locked oscillator distribution circuit includes multiple injection-locked oscillators, each configured to receive a master clock signal, each configured to generate a reference clock signal based on the master clock signal, and each configured to provide the reference clock signal to one of the mixers.

[0235] 22. The injection-locked oscillator distribution system according to embodiment 21 further includes an additional injection-locked oscillator distribution circuit, the circuit including a plurality of additional injection-locked oscillators, each additional injection-locked oscillator being configured to generate a reference clock signal and provide the reference clock signal to one of the mixers.

[0236] 23. The injection-locked oscillator distribution system according to embodiment 21, wherein the master clock generator includes a master phase-locked loop and a multi-phase clock pulse generator, the master phase-locked loop is configured to receive a reference frequency signal as input and generate an output signal having a phase controlled by the phase of the reference frequency signal, and the multi-phase clock pulse generator is configured to receive the output signal from the master phase-locked loop, generate a master signal, and provide the master signal to the injection-locked oscillator distribution circuit.

[0237] 24. The injection-locked oscillator distribution system according to embodiment 21, wherein the injection-locked oscillator distribution circuit is further configured to generate an output signal indicating the operating frequency of the injection-locked oscillator, the injection-locked oscillator distribution system further includes an injection-lock detector, the injection-lock detector being configured to receive a master clock signal and an output signal, and the injection-lock detector being further configured to determine whether the injection-locked oscillator is in a locked state or an unlocked state based on the master clock signal and the output signal.

[0238] 25. The injection-locked oscillator distribution system according to embodiment 24, wherein the injection-locked oscillator is further configured to generate a reference clock signal having a higher frequency than the master clock signal, and the injection-locked oscillator distribution circuit is further configured to generate an output signal by down-converting the reference clock signal to the frequency of the master clock signal.

[0239] 26. The injection-locked oscillator distribution system according to embodiment 25, wherein the injection-locked oscillator distribution circuit further includes a mixer configured to generate an output signal.

[0240] 27. The injection-locked oscillator distribution system according to embodiment 25, wherein the injection-locked oscillator distribution circuit further includes a frequency divider circuit configured to generate an output signal.

[0241] 28. The injection-locked oscillator distribution system according to embodiment 24, wherein the injection-locked detector includes a mixer configured to mix an output signal with a master clock signal to generate an intermediate mixed signal, and the injection-locked detector is further configured to determine whether the injection-locked oscillator is in a locked state or an unlocked state based on the intermediate mixed signal.

[0242] 29. A method for allocating a reference clock signal, comprising:

[0243] The master clock signal is generated by the master clock generator;

[0244] The master clock signal is received at the injection-locked oscillator distribution circuit, which includes multiple injection-locked oscillators;

[0245] At each injection-locked oscillator, a reference clock signal is generated based on the master clock signal; and the reference clock signal from each injection-locked oscillator is provided to the mixer.

[0246] 30. The method according to embodiment 29 further includes:

[0247] Generate a reference clock signal at each additional injection-locked oscillator; and

[0248] The reference clock signal from each additional injection-locked oscillator is provided to the mixer.

[0249] 31. The method according to embodiment 29 further includes:

[0250] The reference frequency signal is received as input at the main phase-locked loop of the master clock generator;

[0251] An output signal is generated at the main phase-locked loop, the output signal having a phase that is time-controlled to the phase of the reference frequency signal;

[0252] The multi-phase clock pulse generator of the master clock generator receives the output signal from the master phase-locked loop;

[0253] The main signal is generated at the multi-phase clock pulse generator; and

[0254] The main signal is supplied from the multi-phase clock pulse generator to the injection-locked oscillator distribution circuit.

[0255] 32. The method according to embodiment 29 further includes:

[0256] At the injection-locked oscillator distribution circuit, an output signal indicating the operating frequency of the injection-locked oscillator is generated.

[0257] The master clock signal and output signal are received at the injection lock detector of the injection lock oscillator distribution system.

[0258] At the injection lock detector, it is determined whether the injection lock oscillator is in a locked state or an unlocked state based on the master clock signal and the output signal.

[0259] 33. The method according to embodiment 32 further includes:

[0260] At the injection-locked oscillator, a reference clock signal with a higher frequency than the master clock signal is generated; and

[0261] At the injection-locked oscillator distribution circuit, the output signal is generated by down-converting the reference clock signal to the frequency of the master clock signal.

[0262] 34. The method according to embodiment 33 further includes generating an output signal at the mixer of the injection-locked oscillator distribution circuit.

[0263] 35. The method according to embodiment 33 further includes generating the output signal at the frequency divider circuit of the injection-locked oscillator distribution circuit.

[0264] 36. The method according to embodiment 32 further includes:

[0265] At the mixer included in the injection lock detector, the output signal is mixed with the master clock signal to generate an intermediate mixed signal; and

[0266] At the injection lock detector, the state of whether the injection lock oscillator is locked or unlocked is determined based on the intermediate mixed signal.

[0267] 37. A mobile device, comprising:

[0268] antenna;

[0269] A transceiver circuit operatively coupled to the antenna, the transceiver including a first mixer;

[0270] The master clock generator is configured to generate the master clock signal;

[0271] Transceiver circuitry, including multiple mixers; and

[0272] An injection-locked oscillator distribution circuit includes multiple injection-locked oscillators, each configured to receive a master clock signal, each configured to generate a reference clock signal based on the master clock signal, and each configured to provide the reference clock signal to one of the mixers.

[0273] 38. The mobile device according to embodiment 37 further includes an additional injection-locked oscillator distribution circuit, the additional injection-locked oscillator distribution circuit including a plurality of additional injection-locked oscillators, each additional injection-locked oscillator being configured to generate a reference clock signal and provide the reference clock signal to one of the mixers.

[0274] 39. The mobile device according to embodiment 37, wherein the master clock generator includes a master phase-locked loop and a multi-phase clock pulse generator, the master phase-locked loop being configured to receive a reference frequency signal as input and generate an output signal having a phase controlled by the phase of the reference frequency signal, and the multi-phase clock pulse generator being configured to receive the output signal from the master phase-locked loop, generate a master signal, and provide the master signal to the injection-locked oscillator distribution circuit.

[0275] 40. The mobile device according to embodiment 37, wherein the injection-locked oscillator allocation circuit is further configured to generate an output signal indicating the operating frequency of the injection-locked oscillator, the injection-locked oscillator allocation system further includes an injection-lock detector configured to receive a master clock signal and an output signal, and the injection-lock detector is further configured to determine whether the injection-locked oscillator is in a locked state or an unlocked state based on the master clock signal and the output signal.

[0276] in conclusion

[0277] Unless the context clearly requires otherwise, throughout the specification and claims, the words “comprising,” “including,” etc., shall be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, meaning “including but not limited to.” The word “coupled,” as commonly used herein, means that two or more elements can be directly connected or connected via one or more intermediate elements. Similarly, the word “connected,” as commonly used herein, means that two or more elements can be directly connected or connected via one or more intermediate elements. Furthermore, the words “this,” “above,” “below,” and words of similar importance, when used in this application, should refer to the entire application, not any particular part of it. Where the context permits, the singular or plural forms used in the preceding detailed description section may also include the plural or singular, respectively. The word “or” refers to a list of two or more items, and this word covers all of the following interpretations: any item in the list, all items in the list, and any combination of items in the list.

[0278] Furthermore, the conditional language used herein, such as “can,” “could,” “might,” “e.g.,” “for example,” “such as,” etc., unless specifically stated or otherwise understood according to the context, is generally intended to indicate that some embodiments include certain features, elements, and / or states, while other embodiments do not include certain features, elements, and / or states. Therefore, such conditional language is not generally intended to imply that these features, elements, and / or states are required in any way by one or more embodiments, or that one or more embodiments must include logic for determining, with or without author input or prompting, whether to include or perform these features, elements, and / or states in any particular embodiment.

[0279] The above detailed description of embodiments of the present invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed above. While specific embodiments and examples of the invention have been described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as will be recognized by those skilled in the art. For example, although processes or blocks are presented in a given order, alternative embodiments may execute routines having steps in a different order, or employ a system having blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these processes or blocks can be implemented in various different ways. Furthermore, although processes or blocks are sometimes represented as being executed serially, these processes or blocks may also be executed in parallel, or may be executed at different times.

[0280] The teachings of this invention provided herein can be applied to other systems, not necessarily those described above. Elements and actions of the various embodiments described above can be combined to provide other embodiments.

[0281] While certain embodiments of the invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. An injection-locked oscillator distribution system, comprising: The master clock generator is configured to generate the master clock signal; An injection-locked oscillator (ILO) distribution circuit includes an ILO and is configured to receive a master clock signal. The ILO is configured to generate a reference clock signal with a higher frequency than the master clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicating the operating frequency of the ILO by down-converting the reference clock signal to the frequency of the master clock signal. as well as An injection lock detector is configured to receive a master clock signal and an output signal, and the injection lock detector is further configured to determine whether the injection lock oscillator is in a locked or unlocked state based on the master clock signal and the output signal.

2. The injection-locked oscillator distribution system of claim 1, wherein the injection-locked oscillator distribution circuit further includes a mixer configured to generate an output signal.

3. The injection-locked oscillator distribution system according to claim 1, wherein the injection-locked oscillator distribution circuit further includes a frequency divider circuit configured to generate an output signal.

4. An injection-locked oscillator distribution system, comprising: The master clock generator is configured to generate the master clock signal; An injection-locked oscillator (ILO) distribution circuit includes an ILO and is configured to receive a master clock signal, the ILO being configured to generate a reference clock signal based on the master clock signal, the ILO distribution circuit being further configured to generate an output signal indicating the operating frequency of the ILO, the ILO distribution circuit being operatively coupled to a mixer of a transceiver circuit, and the ILO distribution circuit being further configured to provide the reference clock signal to the mixer of the transceiver circuit. as well as An injection lock detector is configured to receive a master clock signal and an output signal, and the injection lock detector is further configured to determine whether the injection lock oscillator is in a locked or unlocked state based on the master clock signal and the output signal.

5. The injection-locked oscillator distribution system of claim 4, wherein the injection-lock detector includes a mixer configured to mix an output signal with a master clock signal to generate an intermediate mixed signal, and the injection-lock detector is further configured to determine whether the injection-locked oscillator is in a locked state or an unlocked state based on the intermediate mixed signal.

6. The injection-locked oscillator distribution system of claim 5, wherein the injection-locked detector includes a low-pass filter configured to receive an intermediate mixed signal and generate an intermediate voltage, and the injection-locked detector further includes a comparator configured to compare the intermediate voltage with a reference voltage and output a signal indicating whether the injection-locked oscillator is in a locked state or an unlocked state based on the comparison between the intermediate voltage and the reference voltage.

7. The injection-locked oscillator distribution system of claim 4 further includes an additional injection-locked oscillator distribution circuit, wherein the injection-locked detector further includes selection logic configured to select one of an output signal and an additional output signal from the additional injection-locked oscillator.

8. The injection-locked oscillator distribution system according to claim 4, wherein, The injection-locked oscillator is also configured to generate a reference clock signal with a higher frequency than the master clock signal, and the injection-locked oscillator distribution circuit is also configured to generate an output signal by down-converting the reference clock signal to the frequency of the master clock signal.

9. A method for detecting an injected lock state, comprising: The master clock signal is generated by the master clock generator; The master clock signal is received at the injection-locked oscillator distribution circuit, which includes an injection-locked oscillator; A reference clock signal is generated at the injection-locked oscillator based on the master clock signal; An output signal is generated at the injection-locked oscillator distribution circuit, the output signal indicating the operating frequency of the injection-locked oscillator; The master clock signal and the output signal are received at the injection lock detector; The output signal is mixed with the master clock signal at the mixer included in the injection lock detector to generate an intermediate mixed signal; as well as The injection lock detector determines whether the injection lock oscillator is in a locked or unlocked state based on the intermediate mixed signal.

10. The method of claim 9, further comprising: A reference clock signal with a higher frequency than the master clock signal is generated at the injection-locked oscillator; as well as The output signal is generated at the injection-locked oscillator distribution circuit by down-converting the reference clock signal to the frequency of the master clock signal.

11. The method of claim 10, further comprising generating an output signal at the mixer of the injection-locked oscillator distribution circuit.

12. The method of claim 10, further comprising generating an output signal at the frequency divider circuit of the injection-locked oscillator distribution circuit.

13. The method of claim 9, further comprising: An intermediate voltage is generated at the low-pass filter of the injection lock detector based on the intermediate mixed signal; The intermediate voltage is compared with a reference voltage at the comparator of the injection lock detector; as well as At the comparator, a signal is output based on a comparison between the intermediate voltage and the reference voltage, indicating whether the injection-locked oscillator is in a locked or unlocked state.

14. The method of claim 9, further comprising: At the selection logic, one of the output signal and the additional output signal received from the additional injection-locked oscillator is selected.

15. The method of claim 9, further comprising a mixer for providing a reference clock signal to the transceiver circuit.

16. A mobile device, comprising: antenna; A transceiver circuit operatively coupled to the antenna, the transceiver including a first mixer; The master clock generator is configured to generate the master clock signal; An injection-locked oscillator (ILO) distribution circuit includes an ILO and is configured to receive the master clock signal, the ILO being operatively coupled to the first mixer and configured to generate a reference clock signal based on the master clock signal and provide the reference clock signal to the first mixer, the ILO distribution circuit also being configured to generate an output signal indicating the operating frequency of the ILO. An injection lock detector is configured to receive a master clock signal and an output signal, and the injection lock detector is further configured to determine whether the injection lock oscillator is in a locked state or an unlocked state based on the master clock signal and the output signal; as well as An additional injection-locked oscillator distribution circuit is provided, and the injection-locked detector further includes selection logic configured to select one of an output signal and an additional output signal from the additional injection-locked oscillator.

17. The mobile device of claim 16, wherein the injection-locked oscillator is further configured to generate a reference clock signal having a higher frequency than the master clock signal, and the injection-locked oscillator distribution circuit is further configured to generate an output signal by down-converting the reference clock signal to the frequency of the master clock signal.

18. The mobile device of claim 17, wherein the injection-locked oscillator distribution circuit further comprises a second mixer configured to generate an output signal.

19. The mobile device according to claim 17, wherein, The injection-locked oscillator distribution circuit also includes a frequency divider circuit configured to generate an output signal.

20. The mobile device according to claim 17, wherein, The injection lock detector includes a mixer configured to mix an output signal with a master clock signal to generate an intermediate mixed signal, and the injection lock detector is further configured to determine whether the injection lock oscillator is in a locked or unlocked state based on the intermediate mixed signal.

21. An injection-locked oscillator distribution system, comprising: The master clock generator is configured to generate the master clock signal; Transceiver circuitry, including multiple mixers; as well as An injection-locked oscillator (ILO) distribution circuit includes a plurality of ILOs, each ILO configured to receive a master clock signal, each ILO configured to generate a reference clock signal based on the master clock signal, and each ILO configured to provide the reference clock signal to one of the mixers. The ILO distribution circuit is further configured to generate output signals, each output signal indicating the operating frequency of a corresponding one of the ILOs. The ILO distribution circuit also includes an injection-lock detector configured to receive the master clock signal and the output signals, and to determine whether the ILO is in a locked or unlocked state based on the master clock signal and the output signals.

22. The injection-locked oscillator distribution system of claim 21 further includes an additional injection-locked oscillator distribution circuit, the circuit including a plurality of additional injection-locked oscillators, each additional injection-locked oscillator being configured to generate a reference clock signal and provide the reference clock signal to one of the mixers.

23. The injection-locked oscillator distribution system according to claim 21, wherein, The master clock generator includes a master phase-locked loop (PLL) and a multi-phase clock pulse generator. The PLL is configured to receive a reference frequency signal as input and generate an output signal having a phase controlled by the phase of the reference frequency signal. The multi-phase clock pulse generator is configured to receive the output signal from the PLL, generate a master signal, and provide the master signal to the injection-locked oscillator distribution circuit.

24. The injection-locked oscillator distribution system according to claim 21, wherein, Each of the injection-locked oscillators is further configured to generate a reference clock signal with a higher frequency than the master clock signal, and the injection-locked oscillator distribution circuit is further configured to generate an output signal of a corresponding one of the injection-locked oscillators by down-converting the reference clock signal of the corresponding one of the injection-locked oscillators to the frequency of the master clock signal.

25. The injection-locked oscillator distribution system according to claim 24, wherein, For each of the injection-locked oscillators, the injection-locked oscillator distribution circuit further includes a mixer configured to generate an output signal for a corresponding one of the injection-locked oscillators.

26. The injection-locked oscillator distribution system according to claim 24, wherein, For each of the injection-locked oscillators, the injection-locked oscillator distribution circuit further includes a frequency divider circuit configured to generate an output signal for a corresponding one of the injection-locked oscillators.

27. The injection-locked oscillator distribution system of claim 21, wherein the injection-lock detector includes a mixer configured to mix the output signal of at least one of the injection-locked oscillators with a master clock signal to generate an intermediate mixed signal, and the injection-lock detector is further configured to determine, based on the intermediate mixed signal, whether the at least one of the injection-locked oscillators is in a locked state or an unlocked state.

28. The injection-locked oscillator distribution system according to claim 21, wherein, The injection lock detector includes selection logic for providing one of the selected output signals to the mixer each time.

29. A method for allocating a reference clock signal, comprising: The master clock signal is generated by the master clock generator; The master clock signal is received at the injection-locked oscillator distribution circuit, which includes multiple injection-locked oscillators; A reference clock signal is generated based on the master clock signal at each injection-locked oscillator; The reference clock signal from each injection-locked oscillator is provided to multiple mixers; At the injection-locked oscillator distribution circuit, output signals are generated, each of which indicates the operating frequency of the corresponding one of the injection-locked oscillators. At the injection lock detector, based on the master clock signal and the output signal, it is determined whether the injection lock oscillator is in a locked state or an unlocked state.

30. The method of claim 29, further comprising: A reference clock signal is generated at each of the multiple additional injection-locked oscillators; as well as The reference clock signal from each additional injection-locked oscillator is provided to one of the mixers.

31. The method of claim 29, further comprising: An output signal is generated at the main phase-locked loop of the master clock generator, and the phase of the output signal is time-controlled to the phase of the reference frequency signal that is received as input. At the multi-phase clock pulse generator of the master clock generator, a master signal is generated based on the output signal from the master phase-locked loop, and the master signal is provided to the injection-locked oscillator distribution circuit.

32. The method of claim 29, further comprising: At each of the injection-locked oscillators, a reference clock signal with a higher frequency than the master clock signal is generated; as well as At the injection-locked oscillator distribution circuit, the output signal of the corresponding one of the injection-locked oscillators is generated by downconverting the reference clock signal of the corresponding one of the injection-locked oscillators to the frequency of the master clock signal.

33. The method of claim 32, further comprising: For each of the injection-locked oscillators, an output signal is generated at the mixer of the injection-locked oscillator distribution circuit for the corresponding one of the injection-locked oscillators.

34. The method of claim 32, further comprising: For each of the injection-locked oscillators, the output signal is generated for the corresponding one of the injection-locked oscillators at the frequency divider circuit of the injection-locked oscillator distribution circuit.

35. The method of claim 29, further comprising: At the mixer in the injection-lock detector, the output signal of the first injection-lock oscillator in the injection-lock oscillator is mixed with the master clock signal to generate an intermediate mixed signal; as well as At the injection lock detector, it is determined whether the first injection lock oscillator is in a locked state or an unlocked state based on the intermediate mixed signal.

36. The method of claim 35, further comprising: By selecting logic, the output signal of the first injection-locked oscillator is selected for mixing with the master clock signal.

37. A mobile device, comprising: antenna; A transceiver circuit operatively coupled to the antenna, the transceiver circuit including a plurality of mixers; The master clock generator is configured to generate the master clock signal; as well as An injection-locked oscillator (ILO) distribution circuit includes a plurality of ILOs, each configured to receive a master clock signal, each configured to generate a reference clock signal based on the master clock signal, and each configured to provide the reference clock signal to one of the plurality of mixers. The ILO distribution circuit is further configured to generate output signals, each of which indicates the operating frequency of a corresponding one of the ILOs. The ILO distribution circuit also includes an injection-lock detector configured to receive the master clock signal and the output signals, and to determine whether the ILO is in a locked or unlocked state based on the master clock signal and the output signals.

38. The mobile device of claim 37, further comprising an additional injection-locked oscillator distribution circuit, the additional injection-locked oscillator distribution circuit comprising a plurality of additional injection-locked oscillators, each additional injection-locked oscillator being configured to generate a reference clock signal and provide the reference clock signal to one of the plurality of mixers.

39. The mobile device according to claim 37, characterized in that, The master clock generator includes a master phase-locked loop (PLL) and a multi-phase clock pulse generator. The PLL is configured to receive a reference frequency signal as input and generate an output signal having a phase controlled by the phase of the reference frequency signal. The multi-phase clock pulse generator is configured to receive the output signal from the PLL, generate a master signal, and provide the master signal to the injection-locked oscillator distribution circuit.

40. The mobile device according to claim 37, wherein, The injection-locked oscillator distribution circuit includes at least four injection-locked oscillators.

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