Solid-state imaging element and imaging device

Abstract

A solid-state imaging element for detecting the presence / absence of an address event, wherein erroneous detection of the address event is minimized. Each of a plurality of pixels performs a detection process of detecting whether a change in an incident light amount exceeds a predetermined threshold value and outputting a detection result. An abnormal pixel determination evaluation evaluates the presence or absence of an abnormality for each of a plurality of pixels, and sets a pixel without an abnormality as valid and sets a pixel with an abnormality as invalid. A control unit performs control for causing a pixel set as valid to perform a detection process and a control for fixing a detection result of a pixel set as invalid to a specific value.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element and an imaging device. More specifically, the present technology relates to a solid-state imaging element and an imaging device that compare the amount of change in the amount of incident light with a threshold value. Background Art

[0002] Conventionally, a synchronous solid-state imaging element for capturing image data (frames) synchronously with a synchronization signal such as a vertical synchronization signal has been used in imaging devices and the like. Conventional synchronous solid-state imaging elements can only acquire image data in each cycle of the synchronization signal (e.g., 1 / 60 second), so it is difficult to cope with situations requiring higher-speed processing in the fields of transportation, robots, etc. Therefore, an asynchronous solid-state imaging element has been proposed, in which a detection circuit is provided for each pixel, and the detection circuit detects, in real time for each pixel address, that the amount of change in the amount of light of the pixel has exceeded a threshold as an address event (e.g., see non-patent document 1). This solid-state imaging element that detects address events for each pixel is called a dynamic vision sensor (DVS).

[0003] Prior art literature

[0004] Non-patent literature

[0005] Non-patent document 1: Jing Huang, et al., A Dynamic Vision Sensor with DirectLogarithmic Output and Full-frame Picture-On-Demand, 2017 IEEE International Symposium on Circuits and Systems (ISCAS) Summary of the invention

[0006] Problems to be solved by the present invention

[0007] The above-mentioned asynchronous solid-state imaging element (DVS) generates data at a much higher speed than the synchronous solid-state imaging element. However, in the above-mentioned DVS, pixels with abnormal behavior may appear due to various factors such as dark current noise and defective elements. For example, an address event is erroneously detected even if the incident light does not change. When such an abnormal pixel erroneously detects an address event, various adverse effects such as reduced image recognition accuracy and increased power consumption may occur.

[0008] The present technology has been made in view of such circumstances, and an object is to suppress erroneous detection of an address event in a solid-state imaging element that detects the presence or absence of an address event.

[0009] Solution to the problem

[0010] The present technology has been made to solve the above-mentioned problems, and the first aspect is a solid-state imaging element, which includes: a plurality of pixel circuits, each of which is configured to perform a detection process of detecting whether the amount of change in the amount of incident light exceeds a predetermined threshold value and outputting a detection result; an abnormal pixel determination unit, which is configured to determine whether each of the plurality of pixel circuits has an abnormality, and set the pixel circuit without an abnormality to be enabled and the pixel circuit with an abnormality to be disabled; and a control unit, which is configured to perform control of causing the pixel circuit set to be enabled to perform the detection process, and control of fixing the detection result of the pixel circuit set to be disabled to a specific value. This brings about the effect that the detection result of the abnormal pixel circuit is fixed.

[0011] Furthermore, in the first aspect, each of the plurality of pixels may include: a logarithmic response unit in which a photoelectric conversion element configured to generate a photocurrent by photoelectric conversion and a current-voltage conversion unit configured to convert the photocurrent into a voltage are arranged; a buffer configured to output a voltage; a differential circuit configured to generate a differential signal indicating a change amount of the output voltage by differential operation; a comparator configured to compare the differential signal with a threshold value; and a transmission unit configured to transmit a comparison result of the comparator as a detection result, and any one of the logarithmic response unit, the buffer, the differential circuit, and the comparator may include a switch that opens or closes a predetermined path according to the control of the control unit. This brings about an effect of fixing the detection result by the switch.

[0012] Furthermore, in the first aspect, the control unit may control the switch of the pixel circuit set to be disabled to be in an off state. This brings about an effect of fixing the detection result by the switch in the off state.

[0013] A switch may be inserted between the photoelectric conversion element and the current-voltage conversion unit. This brings about the effect that the photoelectric conversion element is switched off.

[0014] In addition, in the first aspect, the current-voltage conversion unit may include a transistor and a switch connected in series with the photoelectric conversion element, and the switch may be inserted into at least one of the path between the photoelectric conversion element and the transistor and the path between the transistor and the power supply terminal. This brings about the effect that the current is cut off.

[0015] In addition, in the first aspect, the buffer may include a first transistor and a second transistor connected in series, and a switch may be inserted between the first transistor and the second transistor, and between a connection point of the first transistor and the second transistor and the differential circuit. This brings about an effect that the output voltage of the buffer is cut off.

[0016] In addition, in the first aspect, the differential circuit may include: a capacitor configured to output a charge according to a change in voltage to a predetermined input terminal; and an inverting circuit configured to output a signal obtained by inverting the voltage of the input terminal as a differential signal, and a switch may be inserted between the capacitor and the input terminal. This brings about an effect that the differential signal is cut off.

[0017] Furthermore, in the first aspect, a switch may be inserted between the output node of the comparator and the transmission unit. This brings about an effect that the comparison result of the comparator is cut off.

[0018] Furthermore, in the first aspect, the control unit may control the switch of the pixel circuit set to be disabled to be in a closed state. This brings about an effect of fixing the detection result by the switch in the closed state.

[0019] Furthermore, in the first aspect, a switch may be inserted between a connection point of the current-voltage conversion unit and the photoelectric conversion element and a predetermined reference terminal. This brings about an effect that the input side of the current-voltage conversion unit is short-circuited.

[0020] Furthermore, in the first aspect, a switch may be inserted between a connection point of the current-voltage conversion unit and the buffer and a predetermined reference terminal. This brings about an effect that the output side of the current-voltage conversion unit is short-circuited.

[0021] Furthermore, in the first aspect, a switch may be inserted between a connection point between the buffer and the differentiating circuit and a predetermined reference terminal. This brings about the effect that the output terminal of the buffer is short-circuited.

[0022] In addition, in the first aspect, the differential circuit may include: a capacitor configured to output a charge according to a change in voltage to a predetermined input terminal, and an inverting circuit configured to output a signal obtained by inverting the voltage of the input terminal as a differential signal, and a switch may be inserted between the input terminal and the output terminal of the inverting circuit. This brings about an effect that the differential circuit is initialized.

[0023] In addition, in the first aspect, the differential circuit may include: a capacitor configured to output a charge according to a change in voltage to a predetermined input terminal; an inverting circuit configured to output a signal obtained by inverting the voltage of the input terminal as a differential signal; and a short-circuit transistor configured to short-circuit between the input terminal and the output terminal of the inverting circuit according to an auto-zero signal from a transmission unit, the auto-zero signal indicating initialization, and a switch may be inserted between the gate of the short-circuit transistor and the transmission unit. This brings about the effect that the differential circuit is initialized.

[0024] Furthermore, in the first aspect, a switch may be inserted between the output terminal of the comparator and the predetermined terminal. This brings about the effect that the output terminal of the comparator is short-circuited.

[0025] Furthermore, in the first aspect, the abnormal pixel determination unit may determine whether each of the plurality of pixel circuits has an abnormality before executing the detection process. This brings about an effect of determining the presence or absence of an abnormality due to a static factor.

[0026] Furthermore, in the first aspect, the abnormal pixel determination unit may determine whether each of the plurality of pixel circuits has an abnormality during execution of the detection process. This brings about an effect of determining the presence or absence of an abnormality due to a dynamic factor.

[0027] In addition, in the first aspect, the abnormal pixel determination unit may include a plurality of abnormal pixel determination circuits, the plurality of abnormal pixel determination circuits may be arranged in pixels different from each other, and the plurality of pixel circuits may be arranged in pixels different from each other. This brings about an effect of determining the presence or absence of an abnormality by a circuit set for each pixel.

[0028] Furthermore, in the first aspect, the above specific value may be a value indicating that the amount of change does not exceed the threshold value. This brings about the effect that the detection result is fixed to the value when no address event occurs.

[0029] In addition, a second aspect of the present technology is an imaging device, the imaging device including: a plurality of pixel circuits, each of which is configured to perform a detection process of detecting whether a change in an amount of incident light exceeds a predetermined threshold value and outputting a detection result; an abnormal pixel determination unit, configured to determine whether each of the plurality of pixel circuits has an abnormality, and set a pixel circuit without an abnormality to be enabled and a pixel circuit with an abnormality to be disabled; a control unit, configured to perform control of causing a pixel circuit set to be enabled to perform a detection process, and control of fixing a detection result of a pixel circuit set to be disabled to a specific value; and a signal processing unit, configured to process the detection result. This brings about an effect of processing the detection result of a pixel circuit without an abnormality and fixing the detection result of a pixel circuit with an abnormality. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology.

[0031] Figure 2 : is a diagram showing a stacking structure example of the solid-state imaging element according to the first embodiment of the present technology.

[0032] Figure 3 is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology.

[0033] Figure 4is a block diagram showing a configuration example of a pixel according to the first embodiment of the present technology.

[0034] Figure 5 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to the first embodiment of the present technology.

[0035] Figure 6 : is a circuit diagram showing a configuration example of a reduced capacitance logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to the first embodiment of the present technology.

[0036] Figure 7 is a block diagram showing a configuration example of a signal processing unit according to the first embodiment of the present technology.

[0037] Figure 8 is a block diagram showing a configuration example of an abnormal pixel determination unit according to the first embodiment of the present technology.

[0038] Fig. 9 : is a block diagram showing a configuration example of an abnormal pixel determination unit using a counter according to the first embodiment of the present technology.

[0039] Fig.10 is a flowchart illustrating an example of abnormality determination processing according to the first embodiment of the present technology.

[0040] Fig.11 is a flowchart illustrating an example of a detection process according to the first embodiment of the present technology.

[0041] Fig.12 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to a first modification example of the first embodiment of the present technology.

[0042] Fig.13 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to a second modification example of the first embodiment of the present technology.

[0043] Fig.14 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to a third modification example of the first embodiment of the present technology.

[0044] Fig.15 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to a fourth modification example of the first embodiment of the present technology.

[0045] Fig.16 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to a fifth modification example of the first embodiment of the present technology.

[0046] Fig.17 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to a sixth modification example of the first embodiment of the present technology.

[0047] Fig.18 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to a second embodiment of the present technology.

[0048] Fig.19 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, and a differentiating circuit according to a first modification example of the second embodiment of the present technology.

[0049] Fig. 20 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, and a differentiating circuit according to a second modification example of the second embodiment of the present technology.

[0050] Fig.21 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to a third modification example of the second embodiment of the present technology.

[0051] Fig. 22 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, a differentiation circuit, and a comparator according to a third embodiment of the present technology.

[0052] Fig.23 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, and a differentiating circuit according to a first modification example of the third embodiment of the present technology.

[0053] Fig.24 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, and a differentiating circuit according to a second modification example of the third embodiment of the present technology.

[0054] Fig.25 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, and a differentiating circuit according to a third modification example of the third embodiment of the present technology.

[0055] Fig.26 : is a circuit diagram showing a configuration example of a logarithmic response unit, a buffer, and a differentiation circuit using logic gates according to a third modification example of the third embodiment of the present technology.

[0056] Fig. 27 : is a circuit diagram showing a configuration example of a buffer, a differentiation circuit, and a comparator according to a fourth modification example of the third embodiment of the present technology.

[0057] Fig.28: is a block diagram showing a configuration example of a solid-state imaging element according to a fourth embodiment of the present technology.

[0058] Fig.29 is a block diagram showing a configuration example of a pixel according to a fourth embodiment of the present technology.

[0059] Fig.30 is a block diagram showing a configuration example of an imaging device according to a fifth embodiment of the present technology.

[0060] Fig.31 is a block diagram showing a configuration example of a solid-state imaging element according to a fifth embodiment of the present technology.

[0061] Fig.32 is a block diagram showing a schematic configuration of a vehicle control system.

[0062] Fig.33 : is an explanatory diagram showing an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0063] Hereinafter, a mode for implementing the present technology (hereinafter referred to as an embodiment) will be described. The description will be given according to the following order.

[0064] 1. First Embodiment (Example of Setting Each Pixel to Enable or Disable)

[0065] 2. Second Embodiment (Example of adding a switch and setting each pixel to enable or disable)

[0066] 3. Third Embodiment (Example of Changing the Position of a Switch and Setting Each Pixel to Enable or Disable)

[0067] 4. Fourth Embodiment (Example of Setting Each Pixel to Enable or Disable During Detection of Address Event)

[0068] 5. Fifth Embodiment (Example of Executing a Program for Determining the Presence or Absence of Abnormality and Setting Each Pixel to Enable or Disable)

[0069] 6. Application of mobile objects

[0070] <1. First Embodiment>

[0071] [Configuration Example of Imaging Device]

[0072] Figure 1 1 is a block diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and a control unit 130. As the imaging device 100, a camera mounted on an industrial robot, a vehicle-mounted camera, or the like is assumed.

[0073] The imaging lens 110 converges the incident light and guides the incident light to the solid-state imaging element 200. The solid-state imaging element 200 performs photoelectric conversion on the incident light to detect the presence or absence of an address event, and generates a detection result of the detection. Here, the address event includes an on-event and an off-event, and the detection result includes a 1-bit on-event detection result and a 1-bit off-event detection result. An on-event means that the amount of change in the amount of incident light exceeds a predetermined upper threshold. At the same time, an off-event means that the amount of change in the amount of light drops below a predetermined lower threshold. The solid-state imaging element 200 processes the detection result of the address event and outputs data indicating the processing result to the recording unit 120 via the signal line 209. Note that the solid-state imaging element 200 can detect only one of the on-event and the off-event.

[0074] The recording unit 120 records data from the solid-state imaging element 200. The control unit 130 controls the solid-state imaging element 200 to detect the presence or absence of an address event.

[0075] [Configuration example of solid-state imaging element]

[0076] Figure 2 1 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a circuit chip 202 and a light receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via a connection portion such as a through hole. Note that in addition to the through hole, Cu-Cu bonding or bumps can also be used for connection.

[0077] Figure 3 2 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a drive circuit 211, an arbitrator 213, a pixel array unit 214, a signal processing unit 220, an abnormal pixel determination unit 230, and a setting information storage unit 240. In the pixel array unit 214, a plurality of pixels 300 are arranged in a two-dimensional dot matrix.

[0078] The pixel 300 detects the presence or absence of an address event based on the setting information stored in the setting information storage unit 240. When an address event is detected, the pixel 300 supplies a request for requesting transmission of a detection signal indicating the detection result to the arbitrator 213. Then, when a response to the request is received, the pixel 300 supplies the detection signal to the signal processing unit 220.

[0079] The arbitrator 213 arbitrates requests from corresponding pixel blocks and sends responses to the pixels 300 based on the arbitration result.

[0080] The signal processing unit 220 performs predetermined signal processing such as image recognition processing on the detection signal from the pixel array unit 214. The mode signal MODE from the control unit 130 is input to the signal processing unit 220. The mode signal MODE is a signal indicating one of a plurality of modes including a detection mode and an abnormality determination mode. In the detection mode, the solid-state imaging element 200 detects the presence or absence of an address event for each pixel. At the same time, in the abnormality determination mode, it is determined whether the pixel is abnormal for each pixel.

[0081] Here, "abnormal" means that the behavior of the pixel is different from the behavior assumed in the design. For example, when a large number of address events occur even if the amount of incident light does not change, the pixel flickers in the image data in which the detection results of the address events are arranged. In addition, when the state in which the address events continue to occur even if there is a change in the amount of incident light, the pixel becomes a white dot in the image data. In addition, in the case where the pixel receives a flickering light source, the address events occur periodically regardless of the presence or absence of changes in light from an object other than the light source, and the pixel flickers. These behaviors are regarded as abnormal behaviors.

[0082] The factors that cause such abnormalities can be divided into static factors and dynamic factors. As static factors, noise such as dark current noise, quality variation of components, defective components in pixels, etc. are assumed. As dynamic factors, aging degradation, irradiation with flickering light sources, etc. are assumed.

[0083] The signal processing unit 220 performs signal processing on the detection signal in the detection mode, and supplies the processed data to the recording unit 120. Meanwhile, the signal processing unit 220 supplies the detection signal to the abnormal pixel determination unit 230 in the abnormality determination mode.

[0084] The abnormal pixel determination unit 230 determines whether the pixel is abnormal for each pixel. For example, before the address event detection process (for example, when shipped from the factory or when repaired), the abnormal determination in the abnormal determination mode is performed. In the abnormal determination mode, the abnormal pixel determination unit 230 generates setting information, which sets the pixels without abnormalities to be enabled and sets the pixels with abnormalities to be disabled, and the abnormal pixel determination unit 230 causes the setting information storage unit 240 to save the setting information. The setting information includes 1-bit enabling information indicating whether the pixel is enabled for each pixel. For example, when the number of pixels is N, the N-bit setting information is maintained.

[0085] By predetermining the presence or absence of an abnormality before the address event detection process by the abnormal pixel determination unit 230, erroneous detection of address events due to static factors such as defective elements can be suppressed. Note that a method for suppressing erroneous detection of address events due to dynamic factors such as illumination with a flickering light source will be described below.

[0086] The setting information storage unit 240 holds the setting information. The setting information storage unit 240 includes, for example, a memory that cannot be rewritten. A read-only memory (ROM), an eFuse register, or the like is used as a non-rewritable memory. In addition, the setting information storage unit 240 supplies each enabling information in the stored setting information to the corresponding pixel, thereby causing the pixel set to be enabled to perform address event detection processing, and fixing the detection signal of the pixel set to be disabled to a specific value. Note that the setting information storage unit 240 is an example of a control unit described in the claims.

[0087] The driving circuit 211 drives each pixel 300. The arbitrator 213 arbitrates requests from the pixel array unit 214 and returns a response based on the arbitration result.

[0088] [Pixel configuration example]

[0089] Figure 4 Pixel 300 is a block diagram showing a configuration example of a pixel 300 according to a first embodiment of the present technology. Pixel 300 is provided with a pixel circuit 301, and a logarithmic response unit 310, a buffer 320, a differentiation circuit 330, a comparator 340, and a transfer unit 350 are arranged in the pixel circuit 301.

[0090] The logarithmic response unit 310 converts the photocurrent into a pixel voltage Vp proportional to the logarithmic value of the photocurrent and supplies the pixel voltage Vp to the buffer 320 .

[0091] The buffer 320 outputs the pixel voltage Vp from the logarithmic response unit 310 to the differentiating circuit 330. The buffer 320 can improve the driving force for driving the subsequent stage. In addition, the buffer 320 can ensure that the noise associated with the subsequent stage switching operation is isolated.

[0092] The differential circuit 330 obtains the variation of the pixel voltage Vp by differential operation. The variation of the pixel voltage Vp indicates the variation of the light amount. The differential circuit 330 supplies the differential signal Vout indicating the variation of the light amount to the comparator 340.

[0093] The comparator 340 compares the differential signal Vout with a predetermined threshold value (an upper threshold value or a lower threshold value). The comparison result COMP of the comparator 340 indicates the detection result of the address event. The comparator 340 supplies the comparison result COMP to the transmission unit 350.

[0094] The transmission unit 350 transmits the detection signal DET and supplies the auto-zero signal XAZ to the differentiating circuit 330 for initialization after the transmission. When an address event is detected, the transmission unit 350 supplies a request for requesting the transmission of the detection signal DET to the arbiter 213. Then, when a response to the request is received, the transmission unit 350 supplies the comparison result COMP as the detection signal DET to the signal processing unit 220, and supplies the auto-zero signal XAZ to the differentiating circuit 330.

[0095] Figure 5 is a circuit diagram showing a configuration example of the logarithmic response unit 310 , the buffer 320 , the differentiation circuit 330 , and the comparator 340 according to the first embodiment of the present technology.

[0096] The logarithmic response unit 310 includes a photoelectric conversion element 311, a switch 317, and a current-voltage conversion unit 316. The photoelectric conversion element 311 generates a photocurrent by photoelectrically converting incident light.

[0097] The switch 317 opens or closes the path between the photoelectric conversion element 311 and the current-voltage conversion unit 316 according to the enable information EN from the setting information storage unit 240. The switch 317 is turned into a closed state when it is set to be enabled by the enable information EN, and is turned into an open state when it is set to be disabled by the enable information EN. For example, a metal oxide semiconductor (MOS) transistor is used as the switch 317.

[0098] The current-voltage conversion unit 316 logarithmically converts the photocurrent into a pixel voltage Vp. The current-voltage conversion unit 316 includes N-type transistors 312 and 315, a capacitor 313, and a P-type transistor 314. For example, MOS transistors are used as the N-type transistors 312, 314, and 315.

[0099] The source of the N-type transistor 312 is connected to the switch 317, and the drain of the N-type transistor 312 is connected to the power supply terminal. The P-type transistor 314 and the N-type transistor 315 are connected in series between the power supply terminal and a reference terminal having a predetermined reference potential (ground potential, etc.). In addition, the connection point between the P-type transistor 314 and the N-type transistor 315 is connected to the gate of the N-type transistor 312 and the input terminal of the buffer 320. The connection point between the N-type transistor 312 and the photoelectric conversion element 311 is connected to the gate of the N-type transistor 315. In this way, the N-type transistor 312 and the N-type transistor 315 are connected in a loop manner. Note that the circuit including the N-type transistor 312 and the N-type transistor 315 connected in a loop manner is an example of the loop circuit described in the present disclosure.

[0100] In addition, the predetermined bias voltage V blog is applied to the gate of the P-type transistor 314. The capacitor 313 is inserted between the gate of the N-type transistor 312 and the gate of the N-type transistor 315.

[0101] Furthermore, for example, the photoelectric conversion element 311 and the switch 317 are arranged on the light receiving chip 201, and the subsequent stage circuit is arranged on the circuit chip 202. Note that the circuits and elements arranged on the light receiving chip 201 and the circuit chip 202 are not limited to this configuration.

[0102] The buffer 320 includes a P-type transistor 321 and a P-type transistor 322. For example, a MOS transistor is used as the transistor.

[0103] In the buffer 320, the P-type transistor 321 and the P-type transistor 322 are connected in series between the power supply terminal and the reference potential terminal. In addition, the gate of the P-type transistor 322 is connected to the logarithmic response unit 310, and the connection point of the P-type transistor 321 and the P-type transistor 322 is connected to the differential circuit 330. The predetermined bias voltage V bsf Applied to the gate of the P-type transistor 321.

[0104] The differentiating circuit 330 includes capacitors 331 and 334, P-type transistors 332 and 333, and an N-type transistor 335. As the transistors in the differentiating circuit 330, for example, MOS transistors are used.

[0105] The P-type transistor 333 and the N-type transistor 335 are connected in series between the power supply terminal and the reference potential terminal. bdiff The gate of the N-type transistor 335 is input. These transistors function as an inverter circuit having the gate of the P-type transistor 333 as an input terminal 391 and a connection point between the P-type transistor 333 and the N-type transistor 335 as an output terminal 392.

[0106] The capacitor 331 is inserted between the buffer 320 and the input terminal 391. The capacitor 331 supplies a current according to the time derivative (in other words, the change in) of the pixel voltage Vp from the buffer 320 to the input terminal 391. In addition, the capacitor 334 is inserted between the input terminal 391 and the output terminal 392.

[0107] The P-type transistor 332 opens or closes the path between the input terminal 391 and the output terminal 392 according to the auto-zero signal XAZ from the transmission unit 350. For example, when the auto-zero signal XAZ of a low level is input, the P-type transistor 332 turns to a conductive state according to the auto-zero signal XAZ and sets the differential signal Vout to an initial value.

[0108] The comparator 340 includes P-type transistors 341 and 343 and N-type transistors 342 and 344. For example, MOS transistors are used as the transistors.

[0109] In the comparator 340, a P-type transistor 341 and an N-type transistor 342 are connected in series between a power supply terminal and a reference terminal, and a P-type transistor 343 and an N-type transistor 344 are also connected in series between the power supply terminal and the reference terminal. In addition, the gates of the P-type transistor 341 and the P-type transistor 343 are connected to the differential circuit 330. The upper limit voltage V indicating the upper limit threshold high Applied to the gate of the N-type transistor 342, the lower limit voltage V low Applied to the gate of N-type transistor 344.

[0110] The connection point of the P-type transistor 341 and the N-type transistor 342 is connected to the transmission unit 350, and the voltage at the connection point is output as the comparison result COMP+ relative to the upper threshold. The connection point of the P-type transistor 343 and the N-type transistor 344 is also connected to the transmission unit 350, and the voltage at the connection point is output as the comparison result COMP- relative to the lower threshold. Through this connection, the comparator 340 is connected to the transmission unit 350 when the differential signal Vout is higher than the upper limit voltage V high When the differential signal Vout is lower than the lower limit voltage V low In the case of , a low level comparison result COMP- is output. The comparison result COMP is a signal including these comparison results COMP+ and COMP-.

[0111] As described above, the switch 317 is turned into a closed state when it is set to be enabled by the enable information EN. Thus, the address event detection process is performed. At the same time, the switch 317 is turned into an open state when it is set to be disabled by the enable information EN. In this state, the photoelectric conversion element 311 is disconnected from the subsequent circuit, and the detection process is not performed. Then, the detection signal is fixed to a specific value indicating that the address event has not occurred (in other words, the change amount of the incident light amount does not exceed the threshold value).

[0112] Note that the switch 317 is inserted between the photoelectric conversion element 311 and the current-voltage conversion unit 316, but the insertion position of the switch 317 is not limited to this position. As will be described below, the switch 317 may be inserted in a path after the current-voltage conversion unit 316.

[0113] In addition, the comparator 340 compares both the upper threshold and the lower threshold with the differential signal Vout. However, the comparator 340 can only compare one of the upper threshold and the lower threshold with the differential signal Vout. In this case, unnecessary transistors can be removed. For example, when only the differential signal Vout is compared with the upper threshold, only the P-type transistor 341 and the N-type transistor 342 are arranged.

[0114] In addition, capacitor 334 is arranged in the differential circuit 330, but as Figure 6 As illustrated in FIG. , capacitor 334 may be subtracted.

[0115] [Configuration example of signal processing unit]

[0116] Figure 7 2 is a block diagram showing a configuration example of the signal processing unit 220 according to the first embodiment of the present technology. The signal processing unit 220 includes a selector 221 and a signal processing circuit 222 provided for each column.

[0117] The selector 221 switches the output destination of the detection signal DET from the corresponding column in the pixel array unit 214 according to the mode signal MODE. The selector 221 outputs the detection signal DET to the signal processing circuit 222 in the detection mode and outputs the detection signal DET to the abnormal pixel determination unit 230 in the abnormality determination mode.

[0118] The signal processing circuit 222 performs predetermined signal processing on the detection signal DET, and outputs the processed data to the recording unit 120 .

[0119] [Configuration Example of Abnormal Pixel Determination Unit]

[0120] Figure 82 is a block diagram showing a configuration example of the abnormal pixel determination unit 230 according to the first embodiment of the present technology. The abnormal pixel determination unit 230 includes a detection number counting unit 231 and a threshold comparison unit 232.

[0121] The detection count unit 231 counts the number of times an address event is detected for each pixel in the abnormal determination mode. In the abnormal determination mode, the solid-state imaging element 200 detects the presence or absence of an address event for each pixel within a certain period of time in a state where the amount of incident light does not change (for example, in a shadow state). The detection count unit 231 counts the number of times within the period of time and supplies the detection count for each pixel to the threshold comparison unit 232.

[0122] The threshold comparison unit 232 compares the corresponding detection count with a predetermined determination threshold for each pixel. As described above, since it is assumed that no address event occurs in a state where the amount of incident light does not change, it can be determined that a pixel whose detection count of address events exceeds the determination threshold in this state is abnormal. The threshold comparison unit 232 determines whether the detection count exceeds the determination threshold (i.e., the presence or absence of abnormality) for each pixel, and causes the setting information storage unit 240 to store information indicating the determination result for each pixel as setting information.

[0123] Note that the detection number counting unit 231 and the threshold value comparing unit 232 are provided in the abnormal pixel determining unit 230. However, a plurality of counters 233 may be arranged instead of the detection number counting unit 231 and the threshold value comparing unit 232. In this case, for example, Fig. 9 As shown in FIG. 1 , an N-bit (N is an integer) counter 233 is arranged for each pixel. In the counter 233, N-stage n-bit output units 234 and N switches 235 are arranged to output n-th (n is an integer from 0 to N-1) bits respectively. The detection signal DET+ of the corresponding pixel is input to the n-th bit output unit 234 of the lowest bit. Fig. 9 The case where only an ON event is detected is assumed. In addition, at the start of the abnormality determination mode, the N switches 235 do not output any N bits, and when a certain time has passed, any one of the N bits is output as the enable information EN of the pixel to the setting information storage unit 240 according to the control signal. In the case of a binary counter, when the count value becomes 2 n When the switch 235 outputs the nth bit, 2 n corresponds to the threshold.

[0124] [Operation Example of Solid-State Imaging Element]

[0125] Fig.101 is a flowchart showing an example of abnormality determination processing according to the first embodiment of the present technology. When a mode signal MODE indicating an abnormality determination mode is input, the abnormality determination processing is started.

[0126] In the abnormal determination mode, each pixel 300 detects the presence or absence of an address event (step S901), and the abnormal pixel determination unit 230 counts the number of detections of the address event for each pixel (step S902). Then, the solid-state imaging element 200 determines whether the time elapsed from the time when the detection of the address event starts becomes longer than a predetermined set time (step S903). In the case where the elapsed time is equal to or less than the set time (step S903: No), the solid-state imaging element 200 repeatedly performs step S901 and subsequent steps.

[0127] On the other hand, when the elapsed time is longer than the predetermined setting time (step S903: Yes), the abnormal pixel determination unit 230 focuses on a specific pixel and determines whether the count value of the pixel exceeds the determination threshold (i.e., whether the pixel is abnormal) (step S904). When the count value exceeds the determination threshold (step S904: Yes), the abnormal pixel determination unit 230 sets the focused pixel as disabled in the setting information (step S905).

[0128] On the other hand, in the case where the count value is equal to or less than the determination threshold value (step S904: No), the abnormal pixel determination unit 230 sets the pixel of interest to be enabled in the setting information (step S906). After step S905 or step S906, the abnormal pixel determination unit 230 determines whether the determination of the presence or absence of abnormality has been completed for all pixels (step S907). In the case where the determination for all pixels has not been completed (step S907: No), the abnormal pixel determination unit 230 repeats step S904 and subsequent steps. On the other hand, in the case where the determination for all pixels has been completed (step S907: Yes), the abnormal pixel determination unit 230 maintains the setting information and terminates the abnormal determination process.

[0129] Fig.11 1 is a flowchart showing an example of the detection process according to the first embodiment of the present technology. When a mode signal MODE indicating a detection mode is input, the detection process is started.

[0130] The switch 317 in the pixel 300 determines whether the enable information EN is enable (step S911). In the case where the enable information EN is disable (step S911: No), the switch 317 turns to an off state and repeats step S911 and subsequent steps.

[0131] On the other hand, in the case where the enable information EN is enabled (step S911: Yes), the switch 317 is turned to a closed state, and the logarithmic response unit 310 converts the photocurrent into a pixel voltage (step S912). The differential circuit 330 outputs the output voltage Vout according to the amount of change in brightness (step S913). The comparator 340 compares the output voltage Vout with the upper limit threshold value, and determines whether the amount of change in brightness exceeds the upper limit threshold value (step S914).

[0132] When the amount of change exceeds the upper threshold value (step S914: Yes), the comparator 340 detects an on event (step S915). On the other hand, when the amount of change is equal to or less than the upper threshold value (step S914: No), the comparator 340 compares the differential signal Vout with the lower threshold value and determines whether the amount of change in brightness falls below the lower threshold value (step S917).

[0133] If the change amount falls below the lower threshold (step S917: Yes), the comparator 340 detects an OFF event (step S918). On the other hand, if the change amount is equal to or greater than the lower threshold (step S917: No), the pixel 300 repeats step S912 and subsequent steps.

[0134] After step S915 or step S918 , the transmission unit 350 transmits the detection result (step S916 ) and repeatedly performs step S912 and subsequent steps.

[0135] In a synchronous solid-state imaging element that captures an image synchronously with a vertical synchronization signal, etc., the output of abnormal pixels such as flickering points or white points is the same as the output of normal pixels, and has no special effect on readout. However, in a DVS such as the solid-state imaging element 200, when an abnormal pixel detection signal is output, the signal occupies a part of the output interface frequency band and is output mixed with the normal pixel detection signal. In addition, the detection signal of the abnormal pixel (in other words, noise) increases the power consumption of the solid-state imaging element 200, and the increase in noise reduces the recognition accuracy in processing such as image recognition.

[0136] Assuming that the number of pixels is 1280×720 pixels (i.e., 0.9 megapixels) and 0.5% of the number of pixels are abnormal pixels, the number of abnormal pixels is 4600 pixels. In addition, it is assumed that the abnormal pixels flash twice in 1 second on average, and one flash causes ten address events. In this case, the frequency band used for 92,000 events per second is wasted. In addition, assuming that the power consumption when one address event occurs is 0.17 nanowatts (nW), the power consumption of the abnormal pixels is 0.016 milliwatts (mW). Assuming that the power consumption when one address event occurs is 270 nanowatts (nW), the power consumption of the abnormal pixels is 24.8 milliwatts (mW).

[0137] In contrast, the above-described solid-state imaging element 200 sets abnormal pixels to be disabled to suppress erroneous detection of address events, thereby reducing power consumption and widening the frequency band for transmitting detection signals of normal pixels.

[0138] As described above, according to the first embodiment of the present technology, since the value of the detection signal of the abnormal pixel is fixed to a specific value indicating that the address event has not occurred, erroneous detection of the address event due to the abnormal pixel can be suppressed.

[0139] [First Modification]

[0140] In the first embodiment described above, the photoelectric conversion element 311 and the switch 317 are provided on the light receiving chip 201, but in this configuration, the circuit scale of the circuit chip 202 increases as the number of pixels increases. The solid-state imaging element 200 of the first modification of the first embodiment is different from the solid-state imaging element 200 of the first embodiment in that a current-voltage conversion unit 316 and part of the circuit of the subsequent elements are also provided on the light receiving chip 201.

[0141] Fig.12 3 is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, a differential circuit 330, and a comparator 340 according to a first modification of the first embodiment of the present technology. The pixel 300 of the first modification of the first embodiment is different from the pixel 300 of the first embodiment in that an N-type transistor 312 and an N-type transistor 315 and a capacitor 313 are also provided on the light receiving chip 201. In the case of using an N-type MOS transistor as the switch 317, the transistor in the light receiving chip 201 can be limited to an N-type transistor. Thus, compared with the case where an N-type transistor is mixed with a P-type transistor, the number of steps for forming a transistor can be reduced, and the manufacturing cost of the light receiving chip 201 can be reduced.

[0142] As described above, according to the first modification of the first embodiment of the present technology, the N-type transistors 312 and 315 and the capacitor 313 are further provided on the light receiving chip 201. Therefore, the circuit scale of the circuit chip 202 can be reduced.

[0143] [Second Modification]

[0144] In the first embodiment described above, the photoelectric conversion element 311 and the switch 317 are provided on the light receiving chip 201, but in this configuration, the circuit scale of the circuit chip 202 increases as the number of pixels increases. The solid-state imaging element 200 of the second modification of the first embodiment is different from the solid-state imaging element 200 of the first embodiment in that a current-voltage conversion unit 316 and part of the circuit of the subsequent elements are also provided on the light receiving chip 201.

[0145] Fig.13 2 is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, a differentiating circuit 330, and a comparator 340 according to a second modification of the first embodiment of the present technology. The pixel 300 of the second modification of the first embodiment is different from the pixel 300 of the first embodiment in that a current-voltage conversion unit 316 and a P-type transistor 322 in the buffer 320 are further provided on the light receiving chip 201.

[0146] As described above, according to the second modification of the first embodiment of the present technology, the current voltage conversion unit 316 and the P-type transistor 322 in the buffer 320 are further provided on the light receiving chip 201. Therefore, the circuit scale of the circuit chip 202 can be reduced.

[0147] [Third Modification]

[0148] In the first embodiment described above, the photoelectric conversion element 311 and the switch 317 are provided on the light receiving chip 201, but in this configuration, the circuit scale of the circuit chip 202 increases as the number of pixels increases. The solid-state imaging element 200 of the third modification of the first embodiment is different from the solid-state imaging element 200 of the first embodiment in that a current-voltage conversion unit 316 and part of the circuit of the subsequent elements are also provided on the light receiving chip 201.

[0149] Fig.14 3 is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, a differentiating circuit 330, and a comparator 340 according to a third modification example of the first embodiment of the present technology. The pixel 300 of the third modification example of the first embodiment is different from the pixel 300 of the first embodiment in that a current-voltage conversion unit 316 and a buffer 320 are further provided on the light receiving chip 201.

[0150] As described above, according to the third modification example of the first embodiment of the present technology, the current-voltage conversion unit 316 and the buffer 320 are further provided on the light receiving chip 201. Therefore, the circuit scale of the circuit chip 202 can be reduced.

[0151] [Fourth Modification]

[0152] In the first embodiment described above, the photoelectric conversion element 311 and the switch 317 are provided on the light receiving chip 201, but in this configuration, the circuit scale of the circuit chip 202 increases as the number of pixels increases. The solid-state imaging element 200 of the fourth modification of the first embodiment is different from the solid-state imaging element 200 of the first embodiment in that a current-voltage conversion unit 316 and part of the circuit of the subsequent elements are also provided on the light receiving chip 201.

[0153] Fig.15 : is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, a differential circuit 330, and a comparator 340 according to a fourth modification of the first embodiment of the present technology. The pixel 300 of the fourth modification of the first embodiment is different from the pixel 300 of the first embodiment in that a current-voltage conversion unit 316 and a buffer 320 and a capacitor 331 in the differential circuit 330 are further provided on the light receiving chip 201.

[0154] As described above, according to the fourth modification of the first embodiment of the present technology, the current-voltage conversion unit 316 and the buffer 320 and the capacitor 331 are further provided on the light receiving chip 201. Therefore, the circuit scale of the circuit chip 202 can be reduced.

[0155] [Fifth Modification]

[0156] In the first embodiment described above, the photoelectric conversion element 311 and the switch 317 are provided on the light receiving chip 201, but in this configuration, the circuit scale of the circuit chip 202 increases as the number of pixels increases. The solid-state imaging element 200 of the fifth modification of the first embodiment is different from the solid-state imaging element 200 of the first embodiment in that a current-voltage conversion unit 316 and part of the circuit of the subsequent elements are also provided on the light receiving chip 201.

[0157] Fig.16 3 is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, a differential circuit 330, and a comparator 340 according to a fifth modification of the first embodiment of the present technology. The pixel 300 of the fifth modification of the first embodiment is different from the pixel 300 of the first embodiment in that a current-voltage conversion unit 316 and a buffer 320 and elements other than the N-type transistor 335 in the differential circuit 330 are further provided on the light receiving chip 201.

[0158] As described above, according to the fifth modification of the first embodiment of the present technology, the current voltage conversion unit 316 and the buffer 320 and part of the differential circuit 330 are also provided on the light receiving chip 201. Therefore, the circuit scale of the circuit chip 202 can be reduced.

[0159] [Sixth Modification]

[0160] In the first embodiment described above, the photoelectric conversion element 311 and the switch 317 are provided on the light receiving chip 201, but in this configuration, the circuit scale of the circuit chip 202 increases as the number of pixels increases. The solid-state imaging element 200 of the sixth modification of the first embodiment is different from the solid-state imaging element 200 of the first embodiment in that a current-voltage conversion unit 316 and part of the circuit of the subsequent elements are also provided on the light receiving chip 201.

[0161] Fig.17 : is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, a differential circuit 330, and a comparator 340 according to a sixth modification of the first embodiment of the present technology. The pixel 300 of the sixth modification of the first embodiment is different from the pixel 300 of the first embodiment in that a current-voltage conversion unit 316, a buffer 320, and a differential circuit 330 are further provided on the light receiving chip 201.

[0162] As described above, according to the sixth modification of the first embodiment of the present technology, the current voltage conversion unit 316, the buffer 320, and the differentiation circuit 330 are further provided on the light receiving chip 201. Therefore, the circuit scale of the circuit chip 202 can be reduced.

[0163] <2. Second Embodiment>

[0164] In the first embodiment described above, the photoelectric conversion element 311 is disconnected from the subsequent circuit by the switch 317, but there is a possibility that noise occurs in the subsequent circuit and an address event is erroneously detected. The solid-state imaging element 200 according to the second embodiment is different from the solid-state imaging element of the first embodiment in that a switch is inserted in the subsequent circuit of the photoelectric conversion element 311.

[0165] Fig.18 3 is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, a differential circuit 330, and a comparator 340 according to a second embodiment of the present technology. The pixel 300 of the second embodiment is different from the pixel 300 of the first embodiment in that a switch 318 is also provided in the current-voltage conversion unit 316. In addition, the switch 317 of the second embodiment is inserted into the path between the photoelectric conversion element 311 and the N-type transistor 312 in the loop circuit. The switch 318 is inserted between the N-type transistor 312 in the loop circuit and the power supply terminal. The switch 318 is changed to an open state when it is set to be disabled by the enable information EN, and is changed to a closed state when it is set to be enabled by the enable information EN. The transition of the switch 317 or the switch 318 to the open state cuts off the current from the power supply and reliably suppresses erroneous detection of address events.

[0166] Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element 200 of the second embodiment. In addition, although the switch 317 and the switch 318 are inserted at the same time, only one of them may be arranged. Only the switch 317 may be arranged, or only the switch 318 may be arranged.

[0167] As described above, according to the second embodiment of the present technology, since the switch 318 is further inserted between the N-type transistor 312 and the power supply terminal, the current from the power supply is further cut off and the erroneous detection of the address event is more reliably suppressed.

[0168] [First Modification]

[0169] In the second embodiment described above, the current is cut off by the switch 317 and the switch 318, but there is a possibility that noise occurs in the subsequent circuit of the buffer 320 or the subsequent element and the address event is erroneously detected. The solid-state imaging element 200 according to the first modified example of the second embodiment is different from the solid-state imaging element 200 of the second embodiment in that a switch is inserted in the circuit of the buffer 320 or the subsequent element.

[0170] Fig.19 1 is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, and a differentiating circuit 330 according to a first modification example of the second embodiment of the present technology. The pixel 300 of the first modification example of the second embodiment is different from the pixel 300 of the second embodiment in that switches 323 and 324 are provided instead of switches 317 and 318.

[0171] The switch 323 is inserted between the P-type transistor 321 and the P-type transistor 322 in the buffer 320. In addition, the switch 324 is inserted between the connection point of the P-type transistor 321 and the switch 323 and the differentiating circuit 330. Note that the P-type transistor 321 is an example of a first transistor described in the claims, and the P-type transistor 322 is an example of a second transistor described in the claims.

[0172] The switch 323 and the switch 324 are turned into an open state when they are set to be disabled by the enable information EN, and are turned into a closed state when they are set to be enabled by the enable information EN. The transition of the switch 323 and the switch 324 to the open state cuts off the pixel voltage Vp from the logarithmic response unit 310, and can suppress erroneous detection of address events.

[0173] Note that the switch 323 and the switch 324 are arranged at the same time, but only one of them may be arranged. In addition, each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element 200 of the first modification of the second embodiment.

[0174] As described above, according to the first modification of the second embodiment of the present technology, since the switches 323 and 324 are provided in the buffer 320, the pixel voltage Vp from the logarithmic response unit 310 in the preceding stage of the buffer 320 can be cut off. As a result, erroneous detection of address events can be suppressed.

[0175] [Second Modification]

[0176] In the second embodiment described above, the current is cut off by the switch 317 and the switch 318, but there is a possibility that noise occurs in the subsequent circuit of the buffer 320 or the subsequent element and the address event is erroneously detected. The solid-state imaging element 200 according to the second modification of the second embodiment is different from the solid-state imaging element 200 of the second embodiment in that a switch is inserted in the circuit of the buffer 320 or the subsequent element.

[0177] Fig. 20 1 is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, and a differentiating circuit 330 according to a second modification of the second embodiment of the present technology. The pixel 300 of the second modification of the second embodiment is different from the pixel 300 of the second embodiment in that a switch 336 is provided instead of the switch 317 and the switch 318.

[0178] The switch 336 is inserted between the capacitor 331 in the differential circuit 330 and the input terminal 391 of the inverter circuit. The switch 336 is turned into an open state when it is set to be disabled by the enable information EN, and is turned into a closed state when it is set to be enabled by the enable information EN. The transition of the switch 336 to the open state cuts off the differential signal Vout and can suppress erroneous detection of address events.

[0179] Note that each of the first to sixth modified examples of the first embodiment can be applied to the solid-state imaging element 200 of the second modified example of the second embodiment.

[0180] As described above, according to the second modification of the second embodiment of the present technology, since the switch 336 is provided in the differentiating circuit 330, the differential signal Vout can be cut off. As a result, erroneous detection of address events can be suppressed.

[0181] [Third Modification]

[0182] In the second embodiment described above, the current is cut off by the switch 317 and the switch 318, but there is a possibility that noise occurs in the subsequent circuit of the buffer 320 or the subsequent element and the address event is erroneously detected. The solid-state imaging element 200 according to the third modified example of the second embodiment is different from the solid-state imaging element 200 of the second embodiment in that a switch is inserted in the circuit of the buffer 320 or the subsequent element.

[0183] Fig.21 1 is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, a differentiating circuit 330, and a comparator 340 according to a third modification example of the second embodiment of the present technology. The pixel 300 of the third modification example of the second embodiment is different from the pixel 300 of the second embodiment in that switches 345 and 346 are provided instead of switches 317 and 318.

[0184] The switch 346 is inserted between the connection point of the P-type transistor 341 and the N-type transistor 342 (in other words, the output node of the comparator 340) and the transmission unit 350. The switch 345 is inserted between the connection point of the P-type transistor 343 and the N-type transistor 344 (the output node of the comparator 340) and the transmission unit 350.

[0185] The switch 345 and the switch 346 are turned into an open state when they are set to be disabled by the enable information EN, and are turned into a closed state when they are set to be enabled by the enable information EN. The transition of the switch 345 and the switch 346 to the open state cuts off the comparison result of the comparator 340 and can suppress erroneous detection of address events.

[0186] Note that the pixel 300 detects both the on event and the off event, but the pixel 300 can detect only one of them. In this case, the element for detecting the other of the on event and the off event is subtracted. For example, in the case of detecting only the on event, the P-type transistor 343 and the N-type transistor 344 and the switch 345 become unnecessary.

[0187] Furthermore, each of the first to sixth modified examples of the first embodiment can be applied to the solid-state imaging element 200 of the third modified example of the second embodiment.

[0188] As described above, according to the third modification of the second embodiment of the present technology, since the switches 345 and 346 are inserted on the output side of the comparator 340, the comparison result of the comparator 340 can be cut off. As a result, erroneous detection of address events can be suppressed.

[0189] <3. Third embodiment>

[0190] In the first embodiment described above, the switch 317 in the disabled pixel is set to an open state, and the value of the detection signal has been fixed. However, in this configuration, when the switch 317 in the enabled pixel is set to a closed state, the current or voltage value may drop slightly due to the on-resistance of the switch 317. The solid-state imaging element 200 according to the third embodiment is different from the solid-state imaging element 300 of the first embodiment in that a switch that is disconnected when set to enabled is inserted.

[0191] Fig. 22 3 is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, a differentiating circuit 330, and a comparator 340 according to a third embodiment of the present technology. The logarithmic response unit 310 of the third embodiment is provided with a switch 318 instead of the switch 317.

[0192] The switch 318 is inserted between the connection point of the photoelectric conversion element 311 and the current-voltage conversion unit 316 and a reference terminal (ground terminal, etc.). The switch 318 is turned into a closed state when it is set to be disabled by the enable information EN, and is turned into an open state when it is set to be enabled by the enable information EN. The transition of the switch 318 to the closed state blocks the photocurrent flowing into the input side of the current-voltage conversion unit 316, so that erroneous detection of address events can be suppressed. In addition, since the switch 318 is not inserted in the path for the photocurrent to flow, the switch 318 does not affect the current value or the voltage value when it is set to be enabled.

[0193] Note that each of the first to sixth modified examples of the first embodiment can be applied to the solid-state imaging element 200 of the third embodiment.

[0194] As described above, according to the third embodiment of the present technology, the switch 318 that is turned off when enabled is inserted between the connection point of the photoelectric conversion element 311 and the current voltage conversion unit 316 and the reference terminal. Therefore, the current reduction due to the enabled switch 318 can be suppressed.

[0195] [First Modification Example]

[0196] In the third embodiment described above, the switch 318 is provided on the input side of the current-voltage conversion unit 316, but there is a possibility that noise occurs in the subsequent circuit of the current-voltage conversion unit 316 or the subsequent element and an address event is erroneously detected. The solid-state imaging element 200 according to the first modified example of the third embodiment is different from the solid-state imaging element 200 of the third embodiment in that a switch is inserted in the circuit of the current-voltage conversion unit 316 or the subsequent element.

[0197] Fig.23310 , a buffer 320 , and a differentiating circuit 330 according to a first modification of the third embodiment of the present technology. The logarithmic response unit 310 of the first modification of the third embodiment is provided with a switch 319 instead of the switch 318 .

[0198] The switch 319 is inserted between the connection point of the current voltage conversion unit 316 and the buffer 320 and the reference terminal. The switch 319 is turned into a closed state when it is set to be disabled by the enable information EN, and is turned into an open state when it is set to be enabled by the enable information EN. Since the pixel voltage Vp input to the buffer 320 becomes a reference potential (ground potential, etc.), the transition of the switch 319 to the closed state can suppress erroneous detection of address events.

[0199] Note that each of the first to sixth modified examples of the first embodiment can be applied to the solid-state imaging element 200 of the first modified example of the third embodiment.

[0200] As described above, according to the first variant of the third embodiment of the present technology, since the switch 319 is inserted between the connection point of the current-voltage conversion unit 316 and the buffer 320 and the reference terminal, erroneous detection due to noise generated in the current-voltage conversion unit 316 can be suppressed.

[0201] [Second Modification]

[0202] In the third embodiment described above, the switch 318 is provided on the input side of the current-voltage conversion unit 316, but there is a possibility that noise occurs in the subsequent circuit of the current-voltage conversion unit 316 or the subsequent element and an address event is erroneously detected. The solid-state imaging element 200 according to the second modified example of the third embodiment is different from the solid-state imaging element 200 of the third embodiment in that a switch is inserted in the circuit of the current-voltage conversion unit 316 or the subsequent element.

[0203] Fig.24 : is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, and a differentiating circuit 330 according to a second modification of the third embodiment of the present technology. The pixel 300 of the second modification of the third embodiment is different from the pixel of the third embodiment in that a switch 323 is provided instead of the switch 318.

[0204] The switch 323 is inserted between the connection point of the buffer 320 and the differentiating circuit 330 and the reference terminal. The switch 323 is turned into a closed state when it is set to be disabled by the enable information EN, and is turned into an open state when it is set to be enabled by the enable information EN. Since the pixel voltage Vp output from the buffer 320 becomes a reference potential (ground potential, etc.), the transition of the switch 323 to the closed state can suppress erroneous detection of address events.

[0205] Note that each of the first to sixth modified examples of the first embodiment can be applied to the solid-state imaging element 200 of the second modified example of the third embodiment.

[0206] As described above, according to the second variant of the third embodiment of the present technology, since the switch 323 is inserted between the connection point of the buffer 320 and the differential circuit 330 and the reference terminal, erroneous detection due to noise generated in the current-voltage conversion unit 316 or the buffer 320 can be suppressed.

[0207] [Third Modification]

[0208] In the third embodiment described above, the switch 318 is provided on the input side of the current-voltage conversion unit 316, but there is a possibility that noise occurs in the subsequent circuit of the current-voltage conversion unit 316 or the subsequent element and an address event is erroneously detected. The solid-state imaging element 200 according to the third modification of the third embodiment is different from the solid-state imaging element 200 of the third embodiment in that a switch is inserted in the circuit of the current-voltage conversion unit 316 or the subsequent element.

[0209] Fig.25 : is a circuit diagram showing a configuration example of a logarithmic response unit 310, a buffer 320, and a differentiating circuit 330 according to a third modification of the third embodiment of the present technology. The pixel 300 of the third modification of the third embodiment is different from the pixel of the third embodiment in that a switch 336 is provided instead of the switch 318.

[0210] The switch 336 is inserted between the input terminal 391 and the output terminal 392 of the inverter circuit. The switch 336 is turned into a closed state when it is set to be disabled by the enable information EN, and is turned into an open state when it is set to be enabled by the enable information EN. Because the differential circuit 330 is initialized, the transition of the switch 336 to the closed state can suppress erroneous detection of address events.

[0211] Note that each of the first to sixth modified examples of the first embodiment can be applied to the solid-state imaging element 200 of the third modified example of the third embodiment. Fig.26As shown in FIG. 3 , an AND gate 337 may be arranged instead of the switch 336. The AND gate 337 supplies a logical product of the enable information EN and the auto-zero signal XAZ to the gate of the P-type transistor 332. The AND gate 337 is an example of a switch described in the claims, and the P-type transistor 332 is an example of a short-circuit transistor described in the claims.

[0212] As described above, according to the third modification of the third embodiment of the present technology, since the switch 336 is inserted between the input terminal 391 and the output terminal 392 of the inverter circuit, erroneous detection due to noise generated in the current-voltage conversion unit 316 or the buffer 320 can be suppressed.

[0213] [Fourth Modification]

[0214] In the third embodiment described above, the switch 318 is provided on the input side of the current-voltage conversion unit 316, but there is a possibility that noise occurs in the subsequent circuit of the current-voltage conversion unit 316 or the subsequent element and an address event is erroneously detected. The solid-state imaging element 200 according to the fourth modification of the third embodiment is different from the solid-state imaging element 200 of the third embodiment in that a switch is inserted in the circuit of the current-voltage conversion unit 316 or the subsequent element.

[0215] Fig. 27 1 is a circuit diagram showing a configuration example of a buffer 320, a differentiating circuit 330, and a comparator 340 according to a fourth modification of the third embodiment of the present technology. The pixel 300 of the fourth modification of the third embodiment is different from the pixel of the third embodiment in that a switch 345 and a switch 346 are provided instead of the switch 318.

[0216] The switch 345 is inserted between the output terminal of the output comparison result COMP+ of the comparator 340 and the reference terminal. The switch 346 is inserted between the output terminal of the output comparison result COMP- of the comparator 340 and the power supply terminal. The switch 345 and the switch 346 are turned into a closed state when they are set to be disabled by the enable information EN, and are turned into an open state when they are set to be enabled by the enable information EN. Because the comparison result COMP+ and the comparison result COMP- are fixed to a low level and a high level, the transition of the switch 345 and the switch 346 to the closed state can suppress erroneous detection of address events.

[0217] Note that the pixel 300 detects both the on event and the off event, but the pixel 300 can detect only one of them. In this case, the element for detecting the other of the on event and the off event is subtracted. For example, in the case of detecting only the on event, the N-type transistor 343 and the P-type transistor 344 and the switch 345 become unnecessary.

[0218] Note that each of the first to sixth modified examples of the first embodiment can be applied to the solid-state imaging element 200 of the fourth modified example of the third embodiment.

[0219] As described above, according to the fourth modification of the third embodiment of the present technology, since the switch 345 and the switch 346 are inserted between the output terminal of the comparator 340 and the ground terminal, erroneous detection due to noise generated in the preceding stage of the comparator 340 can be suppressed.

[0220] <4. Fourth embodiment>

[0221] In the first embodiment described above, the presence or absence of an abnormality is determined in advance by the abnormal pixel determination unit 230 before the address event detection process, and the erroneous detection of the address event due to static factors such as a defective element is suppressed. However, due to dynamic factors such as irradiation with a flickering light source, erroneous detection of the address event may occur. The solid-state imaging element 200 according to the fourth embodiment is different from the solid-state imaging element of the first embodiment in that the presence or absence of an abnormality is determined during the detection of the address event, and the erroneous detection of the address event due to the dynamic factor is suppressed.

[0222] Fig.28 2 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a fourth embodiment of the present technology. The solid-state imaging element 200 of the fourth embodiment is different from the solid-state imaging element 200 of the first embodiment in that the abnormal pixel determination unit 230 and the setting information holding unit 240 are not provided outside the pixel array unit 214. In the fourth embodiment, the circuits in the abnormal pixel determination unit 230 and the setting information holding unit 240 are distributed and arranged in the pixel 300.

[0223] In addition, the mode signal MODE is not input to the signal processing unit 220 of the fourth embodiment. In the fourth embodiment, during the address event detection process, the presence or absence of abnormality is determined. The signal processing circuit 220 performs signal processing on the detection signal and supplies the processed data to the recording unit 120.

[0224] Fig.29 3 is a block diagram showing a configuration example of a pixel 300 according to a fourth embodiment of the present technology. The pixel 300 of the fourth embodiment is different from the pixel of the first embodiment in that, in addition to the pixel circuit 301, it also includes an abnormal pixel determination circuit 360 and an enable saving circuit 370. In addition, the transmission unit 350 of the fourth embodiment also supplies the detection signal DET to the abnormal pixel determination circuit 360.

[0225] The abnormal pixel determination circuit 360 determines whether the pixel 300 is abnormal. During the address event detection process, the abnormal pixel determination circuit 360 counts the number of detections as in the first embodiment, and determines whether there is an abnormality according to whether the count value exceeds a threshold value. The abnormal pixel determination circuit 360 causes the enable saving circuit 370 to save 1 bit of enable information.

[0226] The enable saving circuit 370 saves the enable information. The enable saving circuit 370 includes, for example, a rewritable memory. A latch circuit, SRAM, or the like is used as the rewritable memory. In addition, the enable saving circuit 370 supplies the enable information to the pixel circuit 301. Note that the enable saving circuit 370 is an example of a control circuit described in the claims.

[0227] The abnormal pixel determination unit 360 determines the presence or absence of an abnormality during the address event detection process, so that erroneous detection of address events due to dynamic factors such as aging degradation and flickering light sources can be suppressed. Note that in addition to determining the presence or absence of an abnormality during the detection process, the abnormal pixel determination circuit 360 can also determine the presence or absence of an abnormality before the detection process as in the first embodiment.

[0228] Note that the abnormal pixel determination circuit 360 and the enable holding circuit 370 are arranged for each pixel, but these circuits may be commonly arranged outside the pixel array unit 214 as in the first embodiment.

[0229] Furthermore, each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element 200 of the fourth embodiment. Furthermore, each of the second and third embodiments and their modifications can be applied to the solid-state imaging element 200 of the fourth embodiment.

[0230] As described above, according to the fourth embodiment of the present technology, the abnormal pixel determination circuit 360 determines the presence or absence of abnormality during detection of an address event. Therefore, erroneous detection of an address event due to dynamic factors can be suppressed.

[0231] <5. Fifth embodiment>

[0232] In the first embodiment described above, the circuit in the solid-state imaging element 200 determines the presence or absence of an abnormality, but the function of determining the presence or absence of an abnormality can be realized by executing a program by a computer. The solid-state imaging element 200 according to the fifth embodiment is different from the solid-state imaging element 200 of the first embodiment in that a program for executing a process for determining the presence or absence of an abnormality is used.

[0233] Fig.301 is a block diagram showing a configuration example of an imaging device 100 according to a fifth embodiment of the present technology. The imaging device 100 is different from the imaging device 100 of the first embodiment in that an abnormal pixel determination unit 140 is further included.

[0234] The abnormal pixel determination unit 140 determines the presence or absence of an abnormality for each pixel. The method for determining abnormal pixels is similar to the method of the fourth embodiment for dynamically determining the presence or absence of an abnormality. Note that the abnormal pixel determination unit 140 can also determine the presence or absence of an abnormality statically as in the first embodiment.

[0235] In addition, the abnormal pixel determination unit 140 is realized by a processing device such as a CPU that executes a predetermined program. Therefore, it is not necessary to provide a circuit for determining the presence or absence of abnormality in the solid-state imaging element 200, and the circuit scale can be reduced accordingly.

[0236] Fig.31 1 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a fifth embodiment of the present technology. The solid-state imaging element 200 of the fifth embodiment is different from the solid-state imaging element 200 of the first embodiment in that the abnormal pixel determination unit 230 is not provided.

[0237] The signal processing unit 220 of the fifth embodiment supplies the detection signal to the abnormal pixel determination unit 140 in the abnormality determination mode. In addition, setting information is input from the abnormal pixel determination unit 140 to the setting information holding unit 240.

[0238] Note that each of the first to sixth modifications of the first embodiment can be applied to the solid-state imaging element 200 of the fifth embodiment. In addition, each of the second and third embodiments and their modifications can be applied to the solid-state imaging element 200 of the fifth embodiment.

[0239] As described above, according to the fifth embodiment of the present technology, since a program that executes a process for determining the presence or absence of an abnormality is used, a circuit for determining the presence or absence of an abnormality is unnecessary and the circuit scale of the solid-state imaging element 200 can be reduced.

[0240] <6. Application to mobile objects>

[0241] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body including automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, robots, etc.

[0242] Fig.32is a block diagram showing a schematic configuration example of a vehicle control system as an example to which a moving body control system according to the disclosed technology is applied.

[0243] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Fig.32 In the example shown in FIG. 1 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, an audio-visual output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0244] The drive system control unit 12010 controls operations related to devices of the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor for generating a vehicle drive force, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting a vehicle steering angle, and a braking device for generating a vehicle braking force.

[0245] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, an automatic window device, and various lights such as headlights, rear lights, brake lights, turn lights, and fog lights. In this case, a radio wave sent from a mobile device that replaces the key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives the input of the radio wave or the signal and controls the door lock device, automatic window device, lights, etc. of the vehicle.

[0246] The vehicle exterior information detection unit 12030 detects exterior information of the vehicle on which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing for a person, a vehicle, an obstacle, a sign, text on a road surface, etc. based on the received image.

[0247] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, and can output the electrical signal as information for distance measurement. In addition, the light received by the imaging unit 12031 may be visible light or may be non-visible light such as infrared light.

[0248] The vehicle interior information detection unit 12040 detects interior information of the vehicle. For example, a driver state detection unit 12041 that detects a driver state is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures the driver, and the vehicle interior information detection unit 12040 can calculate the driver's fatigue level or concentration level, or can determine whether the driver has fallen asleep based on the detection information input from the driver state detection unit 12041.

[0249] The microcomputer 12051 calculates a control target value of a driving force generation device, a steering mechanism, or a braking device based on the external information and internal information of the vehicle acquired in the vehicle external information detection unit 12030 or the vehicle internal information detection unit 12040, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for the purpose of realizing an advanced driver assistance system (ADAS) function, which includes collision avoidance or impact mitigation of a vehicle, following driving based on a distance between vehicles, vehicle speed maintenance driving, collision warning of a vehicle, lane departure warning of a vehicle, and the like.

[0250] In addition, the microcomputer 12051 controls the driving force generation device, steering mechanism, braking device, etc. based on the information near the vehicle obtained in the vehicle external information detection unit 12030 or the vehicle internal information detection unit 12040 to perform cooperative control for the purpose of autonomous driving for autonomous driving without relying on the operation of the driver, etc.

[0251] Furthermore, the microcomputer 12051 may output a control command to the body system control unit 12020 based on the external information of the vehicle acquired in the vehicle external information detection unit 12030. For example, the microcomputer 12051 may perform cooperative control for the purpose of achieving non-glare such as by controlling the headlights according to the position of the leading vehicle or the oncoming vehicle detected in the vehicle external information detection unit 12030 and switching the high beam to the low beam.

[0252] The audio-visual output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually and auditorily notify the passengers of the vehicle or the outside of the vehicle of the information. Fig.32In the example in FIG. 1 , an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplarily shown as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0253] Fig.33 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0254] exist Fig.33 In the imaging unit 12031, imaging unit 12101, imaging unit 12102, imaging unit 12103, imaging unit 12104 and imaging unit 12105 are included.

[0255] For example, the imaging unit 12101, the imaging unit 12102, the imaging unit 12103, the imaging unit 12104, and the imaging unit 12105 are arranged in the positions of the front of the vehicle 12100, the rearview mirror, the rear bumper, the rear door, the upper part of the windshield in the interior of the vehicle 12100, etc. The imaging unit 12101 arranged at the front of the vehicle and the imaging unit 12105 arranged at the upper part of the windshield in the interior of the vehicle mainly acquire the image in front of the vehicle 12100. The imaging unit 12102 and the imaging unit 12103 arranged at the rearview mirror mainly acquire the image of the side of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or the rear door mainly acquires the image behind the vehicle 12100. The imaging unit 12105 arranged at the upper part of the windshield in the interior of the vehicle is mainly used to detect leading vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0256] Note that, Fig.33 An example of the capture range of the imaging unit 12101 to the imaging unit 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front of the vehicle, the imaging range 12112 and the imaging range 12113 respectively indicate the imaging ranges of the imaging unit 12102 and the imaging unit 12103 provided at the rearview mirror, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging unit 12101 to the imaging unit 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0257] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0258] For example, the microcomputer 12051 obtains the distance to the three-dimensional object in the imaging range 12111 to the imaging range 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging unit 12101 to the imaging unit 12104, thereby specifically extracting the three-dimensional object that is closest to the vehicle 12100 on the driving road and is traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100 as the leading vehicle. In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be ensured with the leading vehicle, and perform automatic braking control (including follow-up parking control) and automatic acceleration control (including follow-up start control), etc. In this way, cooperative control for the purpose of autonomous driving for autonomous driving without relying on the operation of the driver, etc. can be performed.

[0259] For example, the microcomputer 12051 classifies the three-dimensional object data related to the three-dimensional object into two-wheeled vehicles, ordinary cars, large vehicles, pedestrians, and other three-dimensional objects such as electric poles based on the distance information obtained from the imaging unit 12101 to the imaging unit 12104, and can use the data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visually recognizable by the driver of the vehicle 12100 and obstacles that are not visually recognizable by the driver. Then, the microcomputer 12051 determines the collision risk indicating the danger of collision with each obstacle, and can perform driving assistance for avoiding collision by the following steps: outputting a warning to the driver through the audio speaker 12061 or the display unit 12062, and when the collision risk is a set value or greater and there is a collision probability, performing forced deceleration or evasive steering through the drive system control unit 12010.

[0260] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 determines whether a pedestrian exists in the image captured by the imaging units 12101 to 12104, thereby identifying the pedestrian. This identification of the pedestrian is performed by extracting feature points in the image captured by the imaging units 12101 to 12104, for example, as infrared cameras, and by performing pattern matching processing on a series of feature points indicating the outline of the object and determining whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the image captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 causes the display unit 12062 to superimpose and display a square outline to emphasize the identified pedestrian. In addition, the audio-visual output unit 12052 may cause the display unit 12062 to display an icon representing a pedestrian at a desired position, etc.

[0261] An example of a vehicle control system to which the technology according to the present disclosure is applicable has been described. The technology according to the present disclosure is applicable to the imaging unit 12031 of the above configuration. Specifically, Figure 1 The imaging device 100 in can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, erroneous detection of address events can be suppressed, thereby improving the reliability of the system.

[0262] It is noted that the above-mentioned embodiments describe examples for implementing the present technology, and the contents in the embodiments and the contents for specifying the present invention in the claims have a corresponding relationship with each other. Similarly, the contents for specifying the present invention in the claims given the same name and the contents in the embodiments of the present technology have a corresponding relationship with each other. However, the present technology is not limited to the embodiments, and can be implemented by applying various modifications to the embodiments without departing from the gist of the present technology.

[0263] In addition, the processing procedures described in the above embodiments can be regarded as methods having these series of processes, and can also be regarded as programs for causing a computer to execute these series of processes and recording media for storing the programs. As the recording media, for example, a compact disc (CD), a mini disc (MiniDisc (MD)), a digital versatile disc (DVD), a memory card, a Blu-ray (registered trademark) disc, etc. can be used.

[0264] Note that the effects described in this specification are merely examples and not limitations, and other effects may be exhibited.

[0265] Note that the present technology may also have the following configurations.

[0266] (1) A solid-state imaging element comprising:

[0267] a plurality of pixel circuits, each of the plurality of pixel circuits being configured to perform a detection process of detecting whether an amount of change in an amount of incident light exceeds a predetermined threshold value and outputting a detection result;

[0268] an abnormal pixel determination unit configured to determine whether each of the plurality of pixel circuits has an abnormality, and set the pixel circuits without the abnormality to be enabled and the pixel circuits with the abnormality to be disabled; and

[0269] The control unit is configured to perform control of causing the pixel circuit set to be enabled to perform a detection process, and control of fixing a detection result of the pixel circuit set to be disabled to a specific value.

[0270] (2) The solid-state imaging element according to (1), wherein

[0271] Each of the plurality of pixels includes:

[0272] a logarithmic response unit in which a photoelectric conversion element configured to generate a photocurrent by photoelectric conversion and a current-voltage conversion unit configured to convert the photocurrent into a voltage are arranged,

[0273] buffer, is configured as an output voltage,

[0274] a differential circuit configured to generate a differential signal indicating an amount of change in the output voltage through a differential operation,

[0275] a comparator configured to compare the differentiated signal with a threshold, and

[0276] a transmitting unit configured to transmit the comparison result of the comparator as a detection result, and

[0277] Any of the logarithmic response unit, the buffer, the differentiating circuit, and the comparator includes a switch that opens or closes a predetermined path according to control of the control unit.

[0278] (3) The solid-state imaging element according to (2), wherein

[0279] The control unit controls the switch of the pixel circuit set to be disabled to be in an off state.

[0280] (4) The solid-state imaging element according to (3), wherein

[0281] The switch is inserted between the photoelectric conversion element and the current-voltage conversion unit.

[0282] (5) The solid-state imaging element according to (3), wherein

[0283] The current-voltage conversion unit includes a transistor and a switch connected in series with the photoelectric conversion element, and

[0284] The switch is inserted into at least one of a path between the photoelectric conversion element and the transistor and a path between the transistor and the power supply terminal.

[0285] (6) The solid-state imaging element according to (3), wherein

[0286] The buffer includes a first transistor and a second transistor connected in series, and

[0287] The switch is inserted into at least one of between the first transistor and the second transistor and between a connection point between the first transistor and the second transistor and the differentiating circuit.

[0288] (7) The solid-state imaging element according to (3), wherein

[0289] The differentiator circuit includes:

[0290] a capacitor configured to output a charge according to a change in voltage to a predetermined input terminal, and

[0291] an inverting circuit configured to output a signal obtained by inverting the voltage of the input terminal as a differential signal, and

[0292] The switch is inserted between the capacitor and the input terminal.

[0293] (8) The solid-state imaging element according to (3), wherein

[0294] The switch is inserted between the output node of the comparator and the transmission unit.

[0295] (9) The solid-state imaging element according to (2), wherein

[0296] The switch controls the switch of the pixel circuit set to be disabled to be in a closed state.

[0297] (10) The solid-state imaging element according to (9), wherein

[0298] The switch is inserted between a connection point of the current-voltage conversion unit and the photoelectric conversion element and a predetermined reference terminal.

[0299] (11) The solid-state imaging element according to (9), wherein

[0300] The switch is inserted between a connection point of the current-voltage conversion unit and the buffer and a predetermined reference terminal.

[0301] (12) The solid-state imaging element according to (9), wherein

[0302] The switch is inserted between a connection point of the buffer and the differentiating circuit and a predetermined reference terminal.

[0303] (13) The solid-state imaging element according to (9), wherein

[0304] The differentiator circuit includes:

[0305] a capacitor configured to output a charge according to a change in voltage to a predetermined input terminal, and

[0306] an inverting circuit configured to output a signal obtained by inverting the voltage of the input terminal as a differential signal, and

[0307] The switch is inserted between the input terminal and the output terminal of the inverter circuit.

[0308] (14) The solid-state imaging element according to (9), wherein

[0309] The differentiator circuit includes:

[0310] a capacitor configured to output a charge according to a change in voltage to a predetermined input terminal,

[0311] an inverting circuit configured to output a signal obtained by inverting the voltage of the input terminal as a differential signal, and

[0312] a short-circuit transistor configured to short-circuit an input terminal and an output terminal of the inverter circuit according to an auto-zero signal from the transmission unit, the auto-zero signal indicating initialization, and

[0313] The switch is inserted between the gate of the short-circuit transistor and the transfer unit.

[0314] (15) The solid-state imaging element according to (9), wherein

[0315] The switch is inserted between the output terminal of the comparator and a predetermined terminal.

[0316] (16) The solid-state imaging element according to any one of (1) to (15), wherein

[0317] The abnormal pixel determination unit determines whether each of the plurality of pixel circuits has an abnormality before executing the detection process.

[0318] (17) The solid-state imaging element according to any one of (1) to (16), wherein

[0319] The abnormal pixel determination unit determines whether each of the plurality of pixel circuits has an abnormality during execution of the detection process.

[0320] (18) The solid-state imaging element according to any one of (1) to (17), wherein

[0321] The abnormal pixel determination unit includes a plurality of abnormal pixel determination circuits,

[0322] A plurality of abnormal pixel determination circuits are arranged in pixels different from each other, and

[0323] A plurality of pixel circuits are arranged in pixels different from each other.

[0324] (19) The solid-state imaging element according to any one of (1) to (18), wherein

[0325] The specific value is a value indicating that the amount of change does not exceed the threshold value.

[0326] (20) An imaging device comprising:

[0327] a plurality of pixel circuits, each of the plurality of pixel circuits being configured to perform a detection process of detecting whether a change amount of an incident light amount exceeds a predetermined threshold value and outputting a detection result;

[0328] an abnormal pixel determination unit configured to determine whether each of the plurality of pixel circuits has an abnormality, and set the pixel circuits without the abnormality to be enabled and the pixel circuits with the abnormality to be disabled;

[0329] a control unit configured to perform control of causing a pixel circuit set to be enabled to perform a detection process, and control of fixing a detection result of a pixel circuit set to be disabled to a specific value; and

[0330] The signal processing unit is configured to process the detection result.

[0331] Reference Symbols List

[0332] 100 Imaging Device

[0333] 110 Imaging lens

[0334] 120 Recording Units

[0335] 130 Control unit

[0336] 140, 230 Abnormal pixel determination unit

[0337] 200 Solid-state imaging element

[0338] 201 Optical Receiver Chip

[0339] 202 Circuit Chip

[0340] 211 drive circuit

[0341] 213 Arbitrator

[0342] 214 pixel array unit

[0343] 220 Signal Processing Unit

[0344] 221 Selector

[0345] 222 Signal Processing Circuit

[0346] 231 Detection times counting unit

[0347] 232 Threshold comparison unit

[0348] 233 Counter

[0349] 234 nth bit output unit

[0350] 235, 317, 318, 319, 323, 324, 336, 345, 346 Switches

[0351] 240 Setting information storage unit

[0352] 300 pixels

[0353] 301 Pixel Circuit

[0354] 310 Logarithmic response units

[0355] 311 Photoelectric conversion element

[0356] 312, 315, 335, 342, 344 N-type transistors

[0357] 313, 331, 334 Capacitors

[0358] 314, 321, 322, 332, 333, 341, 343 P-type transistors

[0359] 316 Current-voltage conversion unit

[0360] 320 Buffer

[0361] 330 Differential Circuits

[0362] 337 AND (logical product) gate

[0363] 340 Comparator

[0364] 350 Transmission Unit

[0365] 360 Abnormal Pixel Determination Circuit

[0366] 370 Enable save circuit

[0367] 12031 Imaging unit.

Claims

1. A solid-state imaging element, comprising: a plurality of pixel circuits, each of the plurality of pixel circuits being configured to perform a detection process of detecting whether a change amount of an incident light amount exceeds a predetermined threshold value and outputting a detection result; an abnormal pixel determination unit configured to determine whether each of the plurality of pixel circuits has an abnormality, and set the pixel circuits without the abnormality to be enabled and the pixel circuits with the abnormality to be disabled; as well as a control unit configured to execute control of causing the pixel circuit set to be enabled to execute the detection process, and control of fixing the detection result of the pixel circuit set to be disabled to a specific value, in, Each of the plurality of pixel circuits comprises: a logarithmic response unit in which a photoelectric conversion element configured to generate a photocurrent by photoelectric conversion and a current-voltage conversion unit configured to convert the photocurrent into a voltage are arranged, buffer, configured to output the voltage, a differential circuit configured to generate a differential signal indicating an amount of change in the output voltage through a differential operation, a comparator configured to compare the differentiated signal with the threshold, and a transmitting unit configured to transmit the comparison result of the comparator as the detection result, and Any one of the logarithmic response unit, the buffer, the differentiation circuit, and the comparator includes a switch that opens or closes a predetermined path according to control of the control unit.

2. The solid-state imaging element according to claim 1, wherein The control unit controls the switch of the pixel circuit set to be disabled to be in an off state.

3. The solid-state imaging element according to claim 2, wherein The switch is inserted between the photoelectric conversion element and the current-voltage conversion unit.

4. The solid-state imaging element according to claim 2, wherein The current-voltage conversion unit includes a transistor and a switch connected in series with the photoelectric conversion element, and The switch is inserted into at least one of a path between the photoelectric conversion element and the transistor and a path between the transistor and a power supply terminal.

5. The solid-state imaging element according to claim 2, wherein The buffer includes a first transistor and a second transistor connected in series, and the switch is inserted at least one between the first transistor and the second transistor and between a connection point of the first transistor and the second transistor and the differentiating circuit.

6. The solid-state imaging element according to claim 2, wherein The differentiator circuit comprises: a capacitor configured to output a charge according to the amount of change in the voltage to a predetermined input terminal, and an inverting circuit configured to output a signal obtained by inverting the voltage of the input terminal as the differential signal, and The switch is inserted between the capacitor and the input terminal.

7. The solid-state imaging element according to claim 2, wherein The switch is inserted between an output node of the comparator and the transmission unit.

8. The solid-state imaging element according to claim 1, wherein The control unit controls the switch of the pixel circuit set to be disabled to be in a closed state.

9. The solid-state imaging element according to claim 8, wherein The switch is inserted between a connection point of the current-voltage conversion unit and the photoelectric conversion element and a predetermined reference terminal.

10. The solid-state imaging element according to claim 8, wherein The switch is inserted between a connection point of the current-voltage conversion unit and the buffer and a predetermined reference terminal.

11. The solid-state imaging element according to claim 8, wherein The switch is inserted between a connection point of the buffer and the differentiating circuit and a predetermined reference terminal.

12. The solid-state imaging element according to claim 8, wherein The differentiator circuit comprises: a capacitor configured to output a charge according to the amount of change in the voltage to a predetermined input terminal, and an inverting circuit configured to output a signal obtained by inverting the voltage of the input terminal as the differential signal, and The switch is inserted between the input terminal and an output terminal of the inverter circuit.

13. The solid-state imaging element according to claim 8, wherein The differentiator circuit comprises: a capacitor configured to output a charge according to the amount of change in the voltage to a predetermined input terminal, an inverting circuit configured to output a signal obtained by inverting the voltage of the input terminal as the differential signal, and a short-circuit transistor configured to short-circuit between the input terminal and the output terminal of the inverter circuit according to an auto-zero signal from the transmission unit, the auto-zero signal indicating initialization, and The switch is inserted between the gate of the short-circuit transistor and the transfer unit.

14. The solid-state imaging element according to claim 8, wherein The switch is inserted between an output terminal of the comparator and a predetermined terminal.

15. The solid-state imaging element according to claim 1, wherein The abnormal pixel determination unit determines whether each of the plurality of pixel circuits has an abnormality before performing the detection process.

16. The solid-state imaging element according to claim 1, wherein The abnormal pixel determination unit determines whether each of the plurality of pixel circuits has an abnormality during execution of the detection process.

17. The solid-state imaging element according to claim 1, wherein The abnormal pixel determination unit includes a plurality of abnormal pixel determination circuits, The plurality of abnormal pixel determination circuits are arranged in pixels different from each other, and the plurality of pixel circuits are arranged in pixels different from each other.

18. The solid-state imaging element according to claim 1, wherein The specific value is a value indicating that the change amount does not exceed the threshold value.

19. An imaging device comprising: a plurality of pixel circuits, each of the plurality of pixel circuits being configured to perform a detection process of detecting whether a change amount of an incident light amount exceeds a predetermined threshold value and outputting a detection result; an abnormal pixel determination unit configured to determine whether each of the plurality of pixel circuits has an abnormality, and set the pixel circuits without the abnormality to be enabled and the pixel circuits with the abnormality to be disabled; a control unit configured to perform control of causing the pixel circuit set to be enabled to perform the detection process, and control of fixing a detection result of the pixel circuit set to be disabled to a specific value; as well as a signal processing unit, configured to process the detection result, in, Each of the plurality of pixel circuits comprises: a logarithmic response unit in which a photoelectric conversion element configured to generate a photocurrent by photoelectric conversion and a current-voltage conversion unit configured to convert the photocurrent into a voltage are arranged, buffer, configured to output the voltage, a differential circuit configured to generate a differential signal indicating an amount of change in the output voltage through a differential operation, a comparator configured to compare the differentiated signal with the threshold, and a transmitting unit configured to transmit the comparison result of the comparator as the detection result, and Any one of the logarithmic response unit, the buffer, the differentiation circuit, and the comparator includes a switch that opens or closes a predetermined path according to control of the control unit.

Images