Individual link and array error correction in memory systems

Abstract

Embodiments of the present disclosure relate to separate link and array error correction in a memory system. In certain embodiments, a memory device may include a link error correction code (ECC) decoder and a correction circuit. The ECC decoder and the correction circuit may be arranged in a write path and configured to detect and correct link errors in write data received via a data link. The memory device may also include a memory ECC encoder circuit. The memory ECC encoder circuit may be arranged in a write path and configured to perform memory protection on write data during storage of a memory array.

Description

[0001] This application is a divisional application of the invention patent application with the application date of September 28, 2016, application number 201680067416.2, and invention name “Separate link and array error correction in memory system”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 62 / 258,219, filed on November 20, 2015, entitled “SEPARATE LINK AND ARRAY ERROR CORRECTION IN A MEMORY SYSTEM,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The present disclosure relates generally to integrated circuits (ICs). More specifically, one aspect of the present disclosure relates to individual memory array and link error correction in a low power memory subsystem. Background Art

[0005] Semiconductor memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). A DRAM memory cell typically includes a transistor and a capacitor, which allows for a high degree of integration. The capacitor can be charged or discharged to store information as a corresponding bit value (e.g., '0' or '1'). Because the capacitor leaks charge, the stored information will eventually disappear unless the capacitor charge is periodically refreshed. Due to the refresh requirement, DRAM is referred to as a dynamic memory compared to SRAM and other static memories. The continuous refresh of DRAM generally limits its use in computer main memory.

[0006] DRAM scaling continues to increase the total number of bits per DRAM chip. Unfortunately, DRAM scaling increases the number of weakly retained cells (e.g., cells with reduced retention time). These cells involve additional refresh cycles to maintain the stored information. Due to additional refresh cycles or other process variations, advanced DRAM processes may suffer from additional random bit refresh errors within the memory cell array. Some low-power memories implement error correction codes (ECC) to improve memory yield and reliability by applying ECC to any random bit errors in the memory cell array. However, ECC decoding and error correction can degrade memory performance due to increased read access time. In addition, the memory link (e.g., interface) is not protected by ECC, and the overall memory reliability is insufficient to meet high reliability and high performance system memory requirements. Summary of the invention

[0007] The memory device may include a link error correction code (ECC) decoder and correction circuit. The ECC decoder and correction circuit may be arranged in the write path and configured to perform link error detection and correction on the write data received through the data link. The memory device may also include a memory ECC encoder circuit. The memory ECC encoder circuit may be arranged in the write path and configured to perform memory protection on the write data during storage in the memory array.

[0008] A method of memory cell array and link error correction in a low power memory subsystem may include: reading link error correction code (ECC) parity bits. The method may also include: verifying received write data based on the link ECC parity bits. The method may also include: transmitting the verified write data to a memory ECC encoder circuit, the memory ECC encoder circuit being configured to perform memory protection on the recovered write data within the memory array based on the memory ECC parity bits.

[0009] A memory subsystem may include a memory controller having an error correction code (ECC) encoder / decoder. The memory subsystem may also include a memory device coupled to the memory controller via at least a data link. The memory device may include a link ECC decoder and a correction circuit. The link ECC decoder and the correction circuit may be arranged in a write path and configured to detect and correct link errors during transmission of write data via the data link. The memory device may include a memory ECC encoder circuit. The memory ECC encoder circuit may be arranged in a write path and configured to perform memory protection on write data during storage in a memory array according to a memory ECC parity bit.

[0010] A memory device may include: a component in a write path of the memory device for link error detection and correction of write data received via a data link. The memory device may also include: a component in the write path of the memory device for protecting write data during storage in a memory array.

[0011] This has been a fairly broad overview of the features and technical advantages of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present disclosure may be easily used as a basis for modifying or designing other structures for achieving the same purpose of the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features and further objects and advantages will be better understood from the following description when considered in conjunction with the accompanying drawings, and the novel features are considered to be characteristic of the present disclosure with respect to its organization and method operation. However, it is to be expressly understood that each of the accompanying drawings is provided for illustration and description purposes only and is not intended to be a definition of limitations of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0013] Figure 1 A top view of a low power memory subsystem showing a host system on a chip (SoC) communicatively coupled to a low power memory device is shown in accordance with aspects of the present disclosure.

[0014] Figure 2 A top view of a low power memory subsystem showing a host system-on-chip communicatively coupled to a low power memory device is shown in accordance with another aspect of the present disclosure.

[0015] Figure 3A and Figure 3B is a timing diagram illustrating the communication of parity bits during a normal or mask write command in accordance with aspects of the present disclosure.

[0016] FIG. 4A to FIG. 4C is a timing diagram illustrating various options for transferring error correction code (ECC) parity bits between a host system on chip (SoC) and a low power memory device during a mask write (MWT) command in accordance with aspects of the present disclosure.

[0017] Figure 5 is a timing diagram illustrating communication of error correction code (ECC) parity bits during a read (RD) command within a bus in accordance with aspects of the present disclosure.

[0018] Figure 6 A top view of a low power memory subsystem is shown showing a host system on chip (SoC) communicatively coupled to a memory device using shared commands / addresses in accordance with aspects of the present disclosure.

[0019] Figure 7A timing diagram for transmitting error correction code (ECC) position information during a mask write (MWT) command in accordance with aspects of the present disclosure is shown.

[0020] Fig. 8A and Figure 8B is a flow chart illustrating a method for transmitting link / memory error correction code (ECC) parity bits during mask write (MWT) commands, normal write commands, and read (RD) commands in accordance with aspects of the present disclosure.

[0021] Fig. 9 is a block diagram illustrating a wireless communication system in which configurations of the present disclosure may be advantageously employed. DETAILED DESCRIPTION

[0022] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details that provide a thorough understanding of the various concepts. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, in order to avoid confusion with these concepts, well-known structures and components are shown in block diagram form. As described herein, the use of the term "and / or" is intended to represent "inclusive or", and the use of the term "or" is intended to represent "exclusive or".

[0023] Semiconductor memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). A DRAM memory cell typically includes a transistor and a capacitor, which allows for a high degree of integration. The capacitor can be charged or discharged to store information as a corresponding bit value (e.g., '0' or '1'). Because the capacitor leaks charge, the stored information will eventually disappear unless the capacitor charge is periodically refreshed. Due to the refresh requirement, DRAM is referred to as a dynamic memory compared to SRAM and other static memories. The continuous refresh of DRAM generally limits DRAM's use as computer main memory.

[0024] DRAM scaling continues to increase the total number of bits per DRAM chip. Unfortunately, DRAM scaling increases the number of weakly retained cells (e.g., cells with shortened retention times). These cells involve additional refresh cycles to maintain the stored information. Advanced DRAM processes may suffer from additional random bit refresh errors within the memory cell array due to additional refresh cycles or other process variations. Some low-power memories implement error correction codes (ECC) to improve memory yield and reliability by applying ECC to any random bit errors in the memory cell array.

[0025] For example, servers and computing systems can use wide (e.g., 72-bit input / output (IO) width) memory modules to enhance the reliability of memory links and memory cell arrays. Because memory failures in server computing systems are intolerable, the reliability of memory links is enhanced by applying ECC to memory operations. However, the storage of ECC involves additional devices. For example, in a 72-bit IO width memory module, 8-bit ECC is assigned to each 64-bit data block of 8 memory devices. Assigning 8-bit ECC to each 64-bit data block provides protection against bit errors in both the memory interface and the memory cell array.

[0026] However, in a 72-bit IO width memory module, a ninth 64-bit (ECC) memory device is used to store eight 8-bit ECCs for each 64-bit data block assigned to the eight memory devices. Unfortunately, this memory configuration increases the memory system cost and memory power. In particular, due to the ECC memory devices, this memory configuration involves additional printed circuit board (PCB) area and cost for supporting wider memory channels. The ECC memory devices also involve standby and active power, which increases the cost associated with this memory configuration.

[0027] One technique for protecting memory arrays and links includes transmitting ECC bits between a host (e.g., a system on chip (SoC)) and a low-power memory. The ECC bits can be transmitted by extending the data burst length (e.g., a 16-bit burst length is extended to an 18-bit burst length). Unfortunately, the extended burst length results in a significant loss of memory performance by reducing the net memory bandwidth. Some low-power memories implement ECC to improve memory yield and reliability by applying ECC to any random bit errors in the memory cell array. However, ECC decoding and error correction in memory devices degrade memory performance due to increased read access time. In addition, the memory link (e.g., interface) is not protected by ECC, and the overall memory reliability is insufficient to meet high reliability and high performance system memory specifications.

[0028] Aspects of the present disclosure relate to a memory subsystem including a host system on chip (SoC) and a plurality of memory devices. The memory controller includes an error correction code (ECC) encoding and decoding block to generate a link ECC bit for protecting write data from memory link errors, and to correct any data failure caused by the memory link and / or memory array of the memory device. Each memory device has a cell array for data and an ECC array for memory ECC parity bits. In various aspects of the present disclosure, link ECC parity bits are generated to protect read / write data from link errors during transmission through a memory link (e.g., a parallel bus structure), and memory ECC parity bits are generated to protect write data within the memory device from random bit errors within the memory array of the memory device. In some aspects of the present disclosure, memory ECC parity bits are generated based on a proprietary method of the memory device that is different from a non-proprietary method of the host SoC for generating link ECC parity bits.

[0029] The link ECC parity bits from the memory controller can be transmitted between the host and the memory device via the data mask pins or data bytes associated with the mask write (MWT) command. The position of the link ECC parity bits can be transmitted to the memory device using the link ECC bit position information. This process does not involve memory bandwidth loss or memory interface changes in the memory subsystem. In the case of a mask write operation, the memory device recovers the link ECC parity bits associated with the first asserted data mask (DM) bit (e.g., "H"), where the mask write command bit field indicates that DM activity is for an "m" bit data pattern. In the case of a normal write operation, the memory device recovers the link ECC bits from the DM data stream.

[0030] During a read operation, the memory controller can recover the memory / link ECC parity bits within the DM data stream from the memory device. When the command / address (CA) bus is shared between multiple memory devices, the mask write command can include additional bit field (EL) information indicating where the ECC bytes are embedded in the DM data stream. In one configuration, the host program writes the DQ byte ID to the mode register in each memory device during initialization. The storage device options (used to determine the byte ID / order) can be hardwired at the package level. If "m" = 128, then "n" is equal to or less than 16. In this aspect of the present disclosure, the mask write command is followed by a link ECC position command (e.g., EL bits) to indicate where the link ECC code is embedded in the write data burst.

[0031] Figure 1A top view of a low power memory subsystem according to aspects of the present disclosure is shown, showing a host system on chip (SoC) 100 coupled to a memory device 140 (140-1, ..., 140-N). This aspect of the present disclosure applies link error correction code (ECC) parity bits to a low power memory subsystem in a mobile or computing system to protect a memory link (e.g., a parallel bus structure) from random bit errors. More specifically, aspects of the present disclosure may relate to next generation low power double data rate (DDR) specifications (e.g., low power double data rate 4 (LPDDR4)) and memory controller implementations in mobile or computing system chipsets, where a memory device uses dedicated memory ECC parity bits to protect a memory cell array from random bit errors.

[0032] Typically, the host SoC 100 includes various processing units that support multi-threaded operations. Figure 1 In the configuration shown in FIG. 1 , the host SoC 100 includes a digital signal processor (DSP) 102, a graphics processor unit (GPU) and a multimedia engine 104, a multi-core central processing unit (CPU) 106, a system bus 108, a memory controller 110, and a memory physical layer (PHY) 130. The DSP 102, the GPU and the multimedia engine 104, and the multi-core CPU 106 support various functions, such as video, audio, graphics, games, etc. Each processor core of the multi-core CPU 106 can be a reduced instruction set computing (RISC) machine, a microprocessor, or some other type of processor.

[0033] In this aspect of the disclosure, the host SoC 100 is communicatively coupled to a memory device 140 (e.g., a low-power dynamic random access memory (DRAM)) through a memory PHY 130. In this configuration, the memory controller 110 includes an ECC encoder / decoder circuit 120 to generate link ECC parity bits 124 for data 122 (e.g., read / write data) transmitted to one of the memory devices 140 along a data link 132 (132-1, . . . , 132-N) and a command / address bus 134 (134-1, . . . , 134-N) (which may be collectively referred to as a memory link) through the memory PHY 130. The link ECC parity bits 124 generated by the ECC encoder / decoder circuit 120 enable correction of any data failure caused by the memory link (e.g., data link 132) at the memory device 140.

[0034] As the host SoC 100 increases the memory link serial data rate from, for example, three thousand two hundred (3200) megabits per second (Mbps) to six thousand four hundred (6400) Mbps, protection against memory link errors becomes more of a concern. In this configuration, the memory controller 110 generates link ECC parity bits 124 ("n" bit ECC) to protect the data 122 (e.g., "m" bit writes) from random bit errors during transmission over the data link 132. Because both the link ECC parity bits 124 and the data 122 are transmitted between the host SoC 100 and the memory device 140 during write and read operations, any memory link errors can be detected and corrected with the link ECC parity bits 124. Furthermore, any random bit errors during transmission from the memory cell array 150 can be corrected in the ECC encoder / decoder circuit 120 of the memory controller 110.

[0035] In this configuration, the memory device 140 includes a memory cell array 150 (e.g., memory banks) for storing data 122 and an ECC array 152 for storing memory ECC parity bits. In this aspect of the present disclosure, the memory device 140 includes a memory ECC encoder circuit 170 configured to generate memory ECC parity bits 172 to support detection and correction of any random bit errors caused by the memory cell array 150 of the memory device 140 during storage of the data 122. The data 122 is stored in one of the memory cell arrays 150 (e.g., memory banks), and the memory ECC parity bits 172 are stored in the ECC array 152. Moreover, in the memory ECC decoder and correction circuit 180 of the memory device 140, any random bit errors in the memory cell array 150 can be corrected based on a dedicated algorithm of the memory device manufacturer, which is different from the non-dedicated algorithm used by the host SoC to generate the link ECC parity bits 124. Although described as proprietary and non-proprietary algorithms for arrays and links, respectively, the present disclosure contemplates any combination of proprietary and non-proprietary algorithms.

[0036] The link ECC parity bits 124 from the memory controller 110 may be received by the memory device 140 via the data mask pins for the data bytes associated with the mask write command. The location of the link ECC parity bits 124 may be communicated to the memory device 140 using the ECC bit position (EL) information. This process is performed during a mask write (MWT) operation, where the memory device 140 recovers the link ECC parity bits 124 from the data 122 when the first data mask (DM) bit is asserted (e.g., "H") and the MWT command bit field indicates DM activity. During normal write operations, the memory device 140 may recover the link ECC parity bits 124 from the DM data stream.

[0037] In this configuration, the memory device 140 includes an input / output (I / O) block 146 communicatively coupled to the data link 132 and the command / address bus 134. In operation, the link ECC parity bits 124 generated by the memory controller 110 according to a non-proprietary method of the host SoC 100 can be used by the link ECC decoder and correction circuit 160 of the memory device 140 to detect and correct link errors within the data 122. That is, the link ECC decoder and correction circuit 160 enables the memory device 140 to perform memory link error correction. In this aspect of the present disclosure, the memory device 140 includes a memory ECC encoder circuit 170, which is configured to generate memory ECC parity bits 172 to enable detection and correction of any random bit errors during storage of the data 122. Thus, once the data 122 is corrected and / or verified, memory ECC parity bits 172 are generated within the memory ECC encoder circuit 170 along the write path 142 of the memory device 140 to protect the data 122 from random bit errors during storage.

[0038] During operation, data 122 is stored in one of the memory cell arrays 150 (e.g., memory banks), and memory ECC parity bits 172 are stored in the ECC array 152. In this configuration, the memory ECC parity bits 172 stored in the ECC array 152 can be used in the memory ECC decoder and correction circuit 180 of the memory device 140 based on the memory device manufacturer's proprietary algorithm to correct any random bit errors in the memory cell array 150. Therefore, once the data 122 is corrected and / or verified, link ECC parity bits 124 are generated within the link ECC encoder circuit 190 along the read path 144 of the memory device 140 to protect the data 122 from random bit errors during transmission over the data link 132.

[0039] In this aspect of the disclosure, the host SoC 100 is able to detect and correct any memory link errors using the link ECC parity bits 124, which may be caused by the increased memory link serial data rate (e.g., from 3200Mbps to 6400Mbps). In addition, any random bit errors in the memory cell array 150 can be corrected by the memory ECC decoder and correction circuit 180 of the memory device 140 using the memory ECC parity bits 172. The use of the memory ECC decoder and correction circuit 180 and the link ECC encoder circuit 190 along the read path 144 of the memory device 140 may result in undesirable read latency. In one aspect of the disclosure, for example, as Figure 2 As shown, the functionality of the memory ECC decoder and correction circuit 180 and / or the link ECC encoder circuit 190 is incorporated into the memory controller.

[0040] Figure 2 A top view of a low power memory subsystem according to another aspect of the present invention is shown, showing a host SoC 200 communicatively coupled to a low power memory device. In this aspect of the present disclosure, the host SoC 200 is communicatively coupled to a memory device 240 via a memory PHY 130. In this configuration, the memory controller 210 includes an ECC encoder / decoder circuit 220 to generate link ECC parity bits 124 for data 122 (e.g., write data) that is transmitted to one of the memory devices 140 via the memory PHY 130 along a memory link including a data link 132 and a command / address bus 134. The link ECC parity bits 124 generated by the ECC encoder / decoder circuit 220 are capable of correcting any data failures caused by the memory link (e.g., data link 132) at the memory device 140.

[0041] In this aspect of the disclosure, the functionality of the memory ECC decoder and correction circuit 180 and / or link ECC encoder circuit 190 is incorporated into the ECC encoder / decoder 220 of the memory controller 210. In this configuration, the write path 142 of the memory device 240 is connected to the memory controller 210. Figure 1 However, the read path 244 of the memory device 240 omits Figure 1The memory ECC decoder and correction circuit 180 and link ECC encoder circuit 190 of the memory device 140 are modified to avoid undesirable read delays. Instead, the ECC encoder / decoder 220 of the memory controller 210 is modified to detect and correct link errors (e.g., during transmission on a parallel bus structure) or memory errors (e.g., during storage in one of the memory cell arrays 150) of the read data 222 (e.g., data read out of the memory cell array) using the memory ECC parity bits.

[0042] In this aspect of the present disclosure, read data latency is considered to be one of the key parameters for determining memory system performance. Therefore, in order to reduce read latency, the proprietary method of the memory device manufacturer for generating the memory ECC parity bit 172 is shared with the host SoC manufacturer. In this aspect of the present disclosure, the memory controller 210 provides dual ECC support to eliminate memory ECC detection and correction within the memory device 240. During a read operation, the read data 222 and the memory ECC parity bit 272 read from one of the memory cell arrays 150 are directly transmitted to the memory controller 210, and the memory ECC detection and correction are performed by the memory controller 210. By skipping the ECC decoding and correction process within the memory device 240, the read latency is improved. As an alternative to providing a proprietary algorithm, a memory device manufacturer can provide a decoding algorithm that also considers link encoding combined with the memory array encoding. In this case, the proprietary algorithm is not disclosed and can remain proprietary.

[0043] Reference again Figure 1 , in the memory device 140, an entire memory row (e.g., a 256-bit word) is typically read from the memory array during a write operation. During a masked write operation, the memory ECC encoder circuit 170 performs a read-modify-write operation within one of the memory cell arrays 150 to perform ECC encoding with the read and write data (replacing the mask data bytes with the corresponding data bytes in one of the memory cell arrays 150). That is, the masked write operation enables the selected bytes of the memory row to be updated so that the mask data bytes are not written to the memory cell array 150. In operation, additional pins (e.g., data mask bits) are sent along with the data 122 to remove the specified write data and to limit the read-modify-write operation by specifying the write data bytes to be ignored.

[0044] Figure 3AThe timing diagram 300 of FIG. 1 shows a masked write (MWT) command for, for example, 128-bit write data having an associated 16-bit data mask with a burst length equal to 16. In the timing diagram 300, "D" represents the write data; "M" represents the data mask bit, with one data mask bit assigned to each DQ byte. In this example, the M2 bit of the DM0 pin associated with the write data D<16:23> is asserted (e.g., "high" or "H"). As a result, the masked write data 320 (e.g., write data D<16:23>) is not written into the memory cell array 150 ( Figure 1 ). In response to the mask write command, the target memory device in the memory devices 140 performs a read operation from one of the memory cell arrays 150 and replaces the mask write data 320 with the read data Q<16:23> to form write data (e.g., 128-bit write data) for memory ECC encoding using the memory ECC encoder circuit 170. The memory ECC encoder circuit 170 stores the 128-bit write data in the target memory cell array in the memory cell array 150, and the memory ECC parity bits 172 are written to the target ECC array in the ECC array 152.

[0045] In various aspects of the present disclosure, the link ECC parity bits 124 from the memory controller 110 are transmitted between the host SoC 100 and the memory device via the data mask pins or data bytes associated with the mask write command. The position of the link ECC parity bits 124 can be transmitted to the memory device 140 using the ECC bit position information. In the case of a mask write operation, the memory device 140 recovers the link ECC parity bits 124 associated with the first asserted data mask (DM) bit (e.g., "H"), where the mask write command bit field indicates DM activity for each "m" bit data pattern. In the case of a normal write operation, the memory device 140 recovers the link ECC parity bits 124 from the DM data stream.

[0046] Figure 3B The timing diagram 350 of FIG. 1 shows a normal write command for, for example, 128 bits of write data with an associated 16-bit data mask having a burst length equal to 16. A low power memory device (e.g., memory device 140 ( Figure 1)) has a normal write command that is different from the masked write command. For a normal write command, all bits (E0, ..., E15) of the DM0 pin associated with the 128-bit write data are deasserted (e.g., "low"). In contrast, for a masked write command, during a burst data stream (BL), at least one DM bit is asserted to "high". Therefore, during a normal write command, the bits of the DM0 pin are not used. In this example of a normal write command, the link ECC parity bits (E0, ..., E15) are transmitted to the memory device 140 via the unused DM bits 360, where "E" represents the link ECC parity bits. As a result, the memory device 140 can recognize the link ECC parity bits 124 generated by the memory controller 110 via the DM pins.

[0047] However, during a mask write command, the DM pin is not available for carrying the link ECC parity bits 124. In various aspects of the present disclosure, the link ECC parity bits 124 from the memory controller 110 are transmitted between the host SoC 100 and the memory device 140 via a mask write data byte associated with a mask write command. The position of the link ECC parity bits 124 can be passed to the memory device 140 using the ECC bit position information. The memory device 140 can recover the ECC bits associated with the first asserted data mask (DM) bit (e.g., "H"), where the mask write command bit field indicates DM activity for each "m" bit data pattern. In the case of a normal write operation, the memory device recovers the ECC bits from the DM data stream. In addition, during a read operation, the link ECC parity bits 124 or the memory ECC parity bits 172 are passed through the DM pin.

[0048] In aspects of the present disclosure, a total of 16 link ECC parity bits may be available from a 128-bit data block (e.g., DQ byte x 16 data beats). In alternative implementations, the 16 data beats for link ECC parity bits per 128-bit data block may include more than the link ECC parity bits. For example, the 16 data beats may include an 8-bit link ECC plus a data bus inversion (DBI) bit and other similar bits.

[0049] FIG. 4A to FIG. 4C The timing diagram of FIG. 1 shows various options for communicating link ECC parity bits 124 between the host SoC 100 and the memory device 140 during a masked write command according to aspects of the present invention. Communication of the link ECC parity bits 124 and / or memory ECC parity bits 172 from the memory device 140 / 240 to the host SoC 100 / 200 is passed via the masked write data 320 used during a read operation.

[0050] Figure 4A The timing diagram 400 shows a masked write command for 128-bit write data with an associated 16-bit data mask having a burst length equal to 16, for example. In this arrangement, the 128-bit write data is divided into a first write data 410 and a second write data 420 (e.g., a first 64-bit data portion with the first 8-bit link ECC parity bit and a second 64-bit data portion with the following 8-bit link ECC parity bit). As described above, for the masked write command, during a burst data stream (e.g., with a 64-bit burst length), at least one data mask bit (DM0) is asserted to "H". In this example, the first 8-bit link ECC (e.g., E0, ..., E7) is embedded in the first masked write data byte 412 (e.g., D<16:23>). In addition, the following 8-bit link ECC (e.g., E8, ..., E15) is embedded in the second masked write data byte 422 (e.g., D<64:71>).

[0051] Figure 4B The timing diagram 430 of FIG. 4 shows a combination of a mask write operation of the first write data 410 and a normal write operation of the second write data 420. In this arrangement, the first 8-bit link ECC (e.g., E0, ..., E7) is embedded in the first mask write data byte 412 (e.g., D<16:23>). In the second write data 420, the bits of the DM0 pin are not used for normal write operations. In this example, the next 8-bit link ECC (e.g., E8, ..., E15) is transmitted to the memory device 140 through the second unused DM bit 424. As a result, the memory device can identify the link ECC parity bit 124 generated by the memory controller 110 through the first mask write data byte 412 for the first write data 410 and the second unused DM bit 424 for the second write data 420. In this aspect of the disclosure, the host SoC 100 issues a mask write command with an extended bit field to indicate where the ECC bytes are embedded; that is, the mask writes either the data bytes or the unused DM bits, depending on the data masking activity.

[0052] Figure 4CThe timing diagram 450 shows a combination of a normal write operation of the first write data 410 and a mask write operation of the second write data 420. In this arrangement, the bits of the DM0 pin are not used for the normal write operation. In this example, the first 8-bit link ECC (e.g., E0, ..., E8) is transmitted to the memory device 140 through the first unused DM bit 414. In the second write data 420, the next 8-bit link ECC (e.g., E8, ..., E15) is embedded in the second mask write data byte 422 (e.g., D<120:127>). As a result, the memory device can identify the link ECC parity bit 124 generated by the memory controller 110 through the first unused DM bit 414 for the first write data 410 and the second mask write data byte 422 for the second write data 420. In this aspect of the disclosure, the host SoC 100 also issues a mask write command with an extended bit field to indicate where the ECC information is embedded; ie, the unused DM bits or the mask write data bytes, depending on the data mask activity.

[0053] Figure 5 The timing diagram 500 of FIG. 1 shows the transfer of link / memory ECC parity bits during a read (RD) command within a bus having, for example, a 128-bit input / output bus width in accordance with aspects of the present disclosure. The timing diagram 500 shows a clock signal 502, a command signal 504, and an address signal 506. The timing diagram 500 also shows a first data signal 510 and an associated first data mask signal 512 with an associated read latency 514 and burst data 516. For a read (RD) command, 128 bits of read data and 16 bits of link / memory ECC (e.g., E0, ..., E15) for each DQ byte (e.g., D0, ..., D15) are transferred from the memory cell array 150 to the host SoC 100 using unused DM bits 550.

[0054] In one aspect of the present disclosure, Figure 1 The low power memory subsystem configuration shown uses the link ECC parity bits 124 from the unused DM bits 550 to detect and correct memory link errors during read operations in the ECC encoder / decoder circuit 120 of the memory controller 110. Alternatively, the memory link can be configured to detect and correct memory link errors during read operations in the ECC encoder / decoder circuit 120 of the memory controller 110. Figure 2 The illustrated low power memory subsystem configuration uses memory ECC parity bits 272 to detect random bit errors and / or link errors in read data within the memory cell array. Also illustrated are a second data signal 520 and an associated second data mask signal 522 and a fourth data signal 530 and an associated fourth data mask signal 532.

[0055] Figure 6A top view of a low power memory subsystem according to aspects of the present disclosure is shown showing a host system on chip (SoC) 600 communicatively coupled to memory devices 640 (640-1, 640-2) via a shared command / address bus 634. During a read operation, unused DM bits 550 (see Figure 5 ) to recover the link ECC parity bits 124 and / or the memory ECC parity bits 272 from the memory device 640. However, in this arrangement, a shared command / address bus 634 is provided between the host SoC 600 and the memory device 640. In a configuration using a shared command / address bus 634, the mask write command may include an additional bit field (EL) indicating whether the link ECC parity bits 124 or the memory ECC parity bits 272 are embedded in the data or data mask bit stream.

[0056] In this aspect of the present disclosure where a shared command / address bus 634 supports multiple devices, the host can program a byte ID to each device to distinguish EL information. This programming can be performed using a package option or mode register set (MRS) programming. For example, when using a shared command / address bus 634, the host SOC 600 programs a byte ID to each memory device 640 (e.g., "L" is programmed to one of the memory devices 640-1, and "H" is programmed to one of the memory devices 640-2, then one of the memory devices 640-1 is assigned EL<0:3>, and one of the memory devices 640-2 is assigned EL<4:7>). Alternatively, this functionality is provided at the package level, where the device ID pin is connected to "ground" for one of the memory devices 640-1 and "power (logic high)" for one of the memory devices 640-2.

[0057] For example, Figure 7 A timing diagram 700 for communicating ECC positions during a mask write command in accordance with aspects of the present disclosure is shown. The timing diagram 700 shows a clock signal 702 and a command / address signal 704. In this aspect of the present disclosure, the mask write (MW) command is followed by an ECC position command (e.g., EL bits) to indicate where the link ECC parity bits 124 are embedded in the data 222 or where the memory ECC parity bits 272 are embedded in the read data 222. In an alternative configuration, during initialization the host SoC 600 program writes a DQ byte ID (identification) to the mode register 650 (650-1, 650-2) in each memory device 640, as shown in FIG. Figure 6 The memory device options (used to determine byte ID / order) can also be hardwired at the package level.

[0058] Fig. 8A8 is a flow chart illustrating a method of memory cell array and link error correction in a low power memory subsystem according to aspects of the present disclosure. Method 800 begins at block 802, where a memory controller generates link ECC parity bits for write data (e.g., 8-bit ECC parity bits for 64-bit write data). At block 804, a determination is made as to whether a mask write operation is being performed. When a normal write operation is being performed, at block 808, the link ECC parity bits are added to the data mask burst data. For example, if Figure 3B As shown, the link ECC parity bits (E0, ..., E15) are transmitted to the memory device 140 via the unused DM pins (e.g., 320). For a mask write command, at block 806, the link ECC parity bits replace the first mask write data byte associated with the first asserted data mask bit. Figure 4A As shown, the first 8 bits of link ECC (eg, E0, . . . , E7) are embedded within the first mask write data byte 412 (eg, D<16:23>).

[0059] Reference again Fig. 8A , at box 810, the host (e.g., SoC) sends the write data and the data mask to the target memory device. At box 812, the target memory device receives the write data and the data mask from the host. At box 820, it is determined whether a mask write operation is being performed. When a normal write operation is being performed, processing boxes 830 to 834 are executed to complete the normal write command. For a mask write command, processing boxes 822 to 828 are executed to complete the mask write command. In this aspect of the present disclosure, the memory device 140 / 240 can be configured to read a link error correction code (ECC) parity bit in an unused data mask bit during a normal write operation or in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.

[0060] Figure 8B 8 is a flowchart illustrating a method 850 for a read operation in a low-power memory subsystem according to various aspects of the present disclosure. At box 852, the memory controller issues a read command to the target memory device. At box 854, the target memory device reads the read data from the memory cell array and reads the memory ECC bits from the ECC array. In the read operation, optionally, boxes 856 and 858 for memory ECC decoding and read data error correction can be skipped to simplify the memory implementation and speed up the read speed (e.g., lower read latency from the read command) because the memory controller can use the ECC encoder / decoder at boxes 860 and 862 to recover the bit errors caused in the memory cell array. This is a trade-off between memory performance (latency) and memory subsystem reliability (memory cell array bit error + read link error).

[0061] In one configuration, the low-power memory subsystem includes a component for reading link ECC parity bits from unused data mask bits during normal write operations or from masked write data bytes corresponding to asserted data mask bits during masked write operations of received write data. The low-power memory subsystem also includes a component for detecting and correcting link errors of write data during transmission over a data link based on the link ECC parity bits. The low-power memory subsystem also includes a component for generating link ECC parity bits to protect read data during transmission over a data link. The low-power memory subsystem also includes a component for embedding link ECC parity bits within the data mask bits during transmission of read data over a data link.

[0062] In one aspect of the present disclosure, the reading component is Figure 1 and Figure 2 An input / output (IO) block 146 is configured to perform the functions described by the reading component. In one aspect of the present disclosure, the detection and correction component is Figure 1 and 2 The link ECC decoder and correction circuit 160 is configured to perform the functions described by the detection and correction components. The generating component may be the link ECC encoder circuit 190, and the embedding component may be Figure 1 The input / output (IO) block 146 is configured to embed the link ECC parity bit. On the other hand, the aforementioned components can be a device or any layer configured to perform the functions described by the aforementioned components.

[0063] Aspects of the present disclosure relate to a memory subsystem including a host system on chip (SoC) and multiple memories. The memory controller has an error correction code (ECC) encoding and decoding block to generate link ECC bits for writing data and correct any data failures caused by the memory link and / or memory core array. The memory has a cell array for data and an ECC array for memory ECC parity bits. The link ECC parity bits from the memory controller are transmitted between the host and the memory through a data mask pin or a data byte associated with a mask write (MWT) command. The position of the link ECC parity bits can be passed to the memory device using ECC bit position information. This process does not involve memory bandwidth loss or memory interface changes in the memory subsystem. In the case of a mask write operation, the memory device recovers the link ECC bits associated with the first asserted data mask (DM) bit (e.g., "H"), wherein the mask write command bit field indicates DM activity for each "m" bit data pattern. In the case of a normal write operation, the memory device recovers the link ECC bits from the DM data stream.

[0064] In one aspect of the present disclosure, read data latency is identified as one of the key parameters for determining memory system performance. Therefore, in order to reduce read latency, a proprietary method of a memory device manufacturer for generating memory ECC parity bits is shared with a host SoC manufacturer. In this aspect of the present disclosure, a memory controller provides dual ECC support to eliminate memory ECC detection and correction within a memory device. During a read operation, the read data and memory ECC parity bits read from one of the memory cell arrays are directly transmitted to the memory controller, and memory ECC detection and correction are performed by the memory controller. Therefore, read latency is improved by skipping the ECC decoding and correction process within the memory device.

[0065] Fig. 9 is a block diagram illustrating an exemplary wireless communication system 900 in which the configurations of the present disclosure may be advantageously employed. For purposes of illustration, Fig. 9 Three remote units 920, 930, and 950 and two base stations 940 are shown. It will be appreciated that the wireless communication system can have more remote units and base stations. Remote units 920, 930, and 950 include IC devices 925A, 925B, and 925C that include the disclosed low-power memory subsystem. It should be appreciated that any device containing an IC can also include the disclosed low-power memory subsystem, including base stations, switching equipment, and network equipment. Fig. 9 Forward link signals 980 from base station 940 to remote units 920, 930, and 950, and reverse link signals 990 from remote units 920, 930, and 950 to base station 940 are shown.

[0066] exist Fig. 9 , remote unit 920 is shown as a mobile phone, remote unit 930 is shown as a portable computer, and remote unit 950 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote unit may be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit such as a personal data assistant, a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed location data unit (e.g., a meter reading device), or any other device that stores or retrieves data or computer instructions, or any combination thereof. For example, a remote unit including a low power memory subsystem may be integrated within a vehicle control system, a server computing system, or other similar system where critical data integrity is specified. Although Fig. 9 IC devices 925A, 925B, and 925C are shown including the disclosed low power memory subsystem, but the disclosure is not limited to these exemplary illustrated units.Aspects of the disclosure may be suitably employed in any device including a low power memory subsystem.

[0067] For firmware and / or software implementations, the methods can be implemented with modules (e.g., processes, functions, etc.) that perform the functions described herein. Any machine-readable medium that tangibly embodies instructions can be used to implement the methods described herein. For example, software code can be stored in a memory and executed by a processor unit. The memory can be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to any type of long-term, short-term, volatile, non-volatile or other memory, and is not limited to any particular type of memory or number of memories or type of media on which the memory is stored.

[0068] If implemented in firmware and / or software, these functions may be stored as one or more instructions or codes on a computer-readable medium. Examples include computer-readable media encoded with data structures and computer-readable media encoded with computer programs. Computer-readable media include physical computer storage media. Storage media may be available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or other media that can be used to store desired program codes in the form of instructions or data structures and can be accessed by a computer; as used herein, disks and discs include compact discs (CDs), laser video discs, optical discs, digital versatile discs (DVDs), and Blu-ray discs, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. The above combinations should also be included within the scope of computer-readable media.

[0069] In addition to being stored on a computer readable medium, instructions and / or data may be provided as signals on a transmission medium included in a communication device. For example, the communication device may include a transceiver with signals indicating instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0070] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the technology of the present disclosure defined by the appended claims. For example, relational terms such as "above" and "below" are used with respect to a substrate or an electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. In addition, if positioned laterally, above and below can refer to the sides of the substrate or electronic device. In addition, the scope of the present application is not intended to be limited to the specific configurations of the processes, machines, manufactures, material compositions, components, methods and steps described in the specification. As will be readily understood by those of ordinary skill in the art from the present disclosure, processes, machines, manufactures, material compositions, components, methods or steps that currently exist or will be developed to perform substantially the same functions as the corresponding configurations described herein or to achieve substantially the same results can be used according to the present disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods or steps within their scope.

[0071] Those skilled in the art will further recognize that the various illustrative logic blocks, modules, circuits and algorithm steps disclosed herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative parts, blocks, modules, circuits and steps have been generally described above according to their functions. Such functions are implemented in hardware or software depending on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the described functions in various ways for each specific application, but such implementation decisions should not be interpreted as causing deviations from the scope of the present disclosure.

[0072] A general purpose processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components or any combination thereof designed to perform the functions described herein may implement or execute the various exemplary logic blocks, modules and circuits described in conjunction with the disclosure herein. A general purpose processor may be a microprocessor, but in an alternative embodiment, the processor may also be any conventional processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such structure.

[0073] The steps of the method or algorithm described in conjunction with the present disclosure may be directly embodied as hardware, a software module executed by a processor, or a combination of the two. The software module may reside in a RAM, flash memory, ROM, EPROM, EEPROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and the storage medium may reside in a user terminal as discrete components.

[0074] In one or more exemplary designs, the functions described can be implemented with hardware, software, firmware or any combination thereof. If implemented with software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include both computer storage media and communication media, wherein the communication media includes any medium that is convenient for transmitting a computer program from one place to another. The storage medium can be any available medium that a general-purpose computer or a special-purpose computer can access. By way of example and not limitation, this computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or can be used to carry or store a specific program code unit with an instruction or data structure form and can be accessed by a general-purpose computer or a special-purpose computer or a general-purpose processor or a special-purpose processor. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, wireless and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless and microwave are included in the definition of the medium. As used in this application, disk and disc include compact disc (CD), laser video disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically and discs use lasers to reproduce data optically. Combinations of the above should also be included in the scope of protection of computer-readable media.

[0075] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications of these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but to conform to the full scope consistent with the language of the claims, wherein the reference to an element in the singular is not intended to mean "only one", unless otherwise specified, but "one or more". Unless otherwise specifically stated, the term "some" refers to one or more. The phrase "at least one" of the referenced item list refers to any combination of these items, including a single member. For example, "at least one of a, b or c" is intended to cover: a; b; c; a and b; a and c; b and c; and a, b and c. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure (known or subsequently known to those of ordinary skill in the art) are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, no disclosure in the present invention is intended to be dedicated to the public, regardless of whether such disclosure is explicitly recorded in the claims. No constituent element of any claim should be interpreted under 35 U.S.C. §112, paragraph 6, unless the constituent element is explicitly recited using the wording of “functional means” or, in a method claim, the constituent element is recited using the wording of “functional step.”

Claims

1. A method for wireless communication, comprising: The host SoC issues a read command to the memory device; as well as receiving the read data by the host SoC via the data link and receiving the link ECC bits and the memory ECC bits via the link transmitting the mask data stream, The link ECC bits are used to protect read / write data from link errors during transmission over a memory link, and the memory ECC bits are used to protect write data within the memory device from random bit errors within a memory array of the memory device. 2 . The method of claim 1 , further comprising performing, by the host SoC, ECC decoding and read data error correction using the link ECC bits. 3 . The method of claim 2 , wherein the host SoC includes an ECC encoder / decoder circuit configured to detect and correct memory link errors using the link ECC bits. 4 . The method according to claim 1 , further comprising writing, by the host SoC, to a mode register to indicate the location of the link ECC bit.

5. The method according to claim 1, further comprising: reading the read data from a memory array by the memory device; as well as The read data is sent by the memory device over the data link and the link ECC bits and memory ECC bits are sent over the link that carries the mask data stream.

6. The method according to claim 5, further comprising: reading, by the memory device, the memory ECC bits from an ECC array; as well as The memory ECC bits are used by the memory device to perform ECC decoding and read data error correction.

7. A host SoC, comprising: a memory PHY configured to be communicatively coupled to a memory device via a memory link; as well as The ECC encoder / decoder circuit is configured to detect and correct the memory link errors during a read operation using the link ECC bits and the memory ECC bits from the data mask bits. 8 . The host SoC of claim 7 , wherein the data mask bit is configured to indicate that masked write data is not written to a memory cell in a masked write operation.

9. The host SoC according to claim 7, further comprising various processing units supporting multi-threaded operations.

10. A memory subsystem comprising: Memory devices; as well as a memory controller coupled to the memory device via a memory link, wherein the memory link includes a data link and a link that transmits a masked data stream, and wherein the memory controller has an ECC encoder / decoder circuit configured to detect and correct the memory link errors during a read operation using link ECC bits and memory ECC bits from the link that transmits the masked data stream.

11. The memory subsystem of claim 10, further comprising a memory PHY configured to be coupled to the memory controller and to be coupled to the memory device through the memory link.

12. The memory subsystem of claim 10, wherein the memory device is further configured to: issuing a read command to the memory device; and The read data is received over the data link and the link ECC bits and memory ECC bits are received over the link that transmits the mask data stream.

13. The memory subsystem of claim 10, wherein the memory controller is further configured to write to a mode register in the memory device to indicate where the link ECC bits are located.

14. The memory subsystem of claim 10, wherein the memory device is configured to: reading the read data from the memory array; and The read data is sent over the data link and the link ECC bits and memory ECC bits are sent over the link that carries the mask data stream.

15. The memory subsystem of claim 14, wherein the memory device is further configured to: reading the memory ECC bits from the ECC array; and The memory ECC bits are used to perform ECC decoding and read data error correction.

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