Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing the same. A semiconductor device includes a capacitor. The capacitor includes a first electrode and a second electrode disposed in a first metal layer. The first electrode has a first end and a second end, and the first electrode has a spiral pattern extending outward from the first end to the second end. The first electrode and the second electrode have substantially equal spacing therebetween.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Integrated chips are formed on a semiconductor die comprising millions or billions of transistors. These transistors are configured to function as switches and / or generate power gain to enable logic functions for the integrated chip (e.g., forming a processor configured to perform logic functions). Integrated chips typically also include passive components such as capacitors, resistors, inductors, transistors, etc. Passive components are widely used to control characteristics of the integrated chip (e.g., gain, time constant, etc.) and to provide a wide range of different functions for the integrated chip (e.g., fabricating analog and digital circuits on the same die). Summary of the Invention

[0003] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a first capacitor, including: a first electrode disposed in a first metal layer and having a first end and a second end, wherein the first electrode has a spiral pattern extending outward from the first end to the second end; and a second electrode disposed in the first metal layer, wherein the first electrode and the second electrode have a substantially equal spacing.

[0004] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first electrode disposed in a first metal layer and having a first end and a second end, the first electrode having a plurality of turns and extending outwardly from the first end to the second end, the first electrode comprising: a first portion extending longitudinally in a plane along a first direction; and a second portion coplanar with the first portion in the plane and extending from the first portion along a second direction not collinear with the first direction; and a second electrode disposed in the first metal layer, wherein the first electrode and the second electrode have substantially equal spacing.

[0005] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first dielectric layer on a substrate; forming a first anode and a first cathode in the first dielectric layer, wherein the first anode extends outwardly in a spiral or polygonal manner from a first end to a second end of the first anode, and the first anode and the first cathode have a substantially equal spacing; forming a second dielectric layer on the first dielectric layer; and forming a second anode and a second cathode in the second dielectric layer, wherein the second anode extends outwardly in a spiral or polygonal manner from a first end to a second end of the second anode, and the second anode and the second cathode have a substantially equal spacing. Attached Figure Description

[0006] This disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1-4 and Figure 6 This is a plan view of a semiconductor device according to various embodiments of the present disclosure.

[0008] Figure 5 and Figure 7 This is a cross-sectional view of a semiconductor device according to various embodiments of the present disclosure.

[0009] Figures 8A to 8F These are cross-sectional views of various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used in this document to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used in this document may be interpreted accordingly.

[0012] Throughout this specification, the term "MOM capacitor" is used to refer to a capacitor having an insulator between two conductive plates, wherein the insulator may include a dielectric material such as an oxide. A single-layer MOM capacitor may include a first metal plate, a second metal plate, and an insulating layer deposited between the first and second metal plates. The capacitance of a single-layer MOM capacitor is proportional to the area of ​​the metal plates and the dielectric constant of the insulating layer.

[0013] refer to Figure 1 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. The semiconductor device includes a capacitor 100, which includes a first electrode 110 and a second electrode 120, wherein the first electrode 110 and the second electrode 120 are disposed in a plane, for example, in the same metal layer. A dielectric material (not shown) is filled between the first electrode 110 and the second electrode 120. In some embodiments, the capacitor 100 may extend into other layers (e.g., interconnected via conductive vias). Figure 1 The capacitor 100 can be Figure 1 The first electrode 110 and the second electrode 120 are repeated in other layers above and / or below the given layer. Therefore, the first electrode 110 and the second electrode 120 can be repeated in multiple metal layers, and the electrodes in different metal layers are interconnected.

[0014] The capacitor 100 has a double-wrap structure. The first electrode 110 and the second electrode 120 are not directly connected to each other, and the first electrode 110 and the second electrode 120 surround each other from the center C of the capacitor 100 to the outside of the capacitor 100. For example, the capacitor 100 may be a double-helix structure, wherein both the first electrode 110 and the second electrode 120 are helical patterns.

[0015] In some embodiments, the first electrode 110 has a first end 112 and a second end 114. The first end 112 is substantially located near the center C of the capacitor 100, and the first electrode 110 extends spirally outward from the first end 112 to the second end 114. The first electrode 110 is a continuous line and has no branches between the first end 112 and the second end 114. In some embodiments, the first electrode 110 includes a plurality of curved portions, and these curved portions are connected to each other. The width of the first electrode 110 is uniform from the first end 112 to the second end 114. The first electrode 110 may comprise any suitable conductive material. In some embodiments, the first electrode 110 may comprise polycrystalline silicon. In some other embodiments, the first electrode 110 may comprise a metal.

[0016] In some embodiments, the second electrode 120 has a first end 122 and a second end 124. The first end 122 of the second electrode 120 is substantially located near the center C of the capacitor 100, and the second electrode 120 extends spirally outward from the first end 122 to the second end 124. The second electrode 120 is a solid line and has no branches between the first end 122 and the second end 124. In some embodiments, the second electrode 120 includes a plurality of curved portions, and these curved portions are connected to each other. The width of the second electrode 120 is uniform from the first end 122 to the second end 124. The second electrode 120 may comprise any suitable conductive material. In some embodiments, the second electrode 120 may comprise polycrystalline silicon. In some other embodiments, the second electrode 120 may comprise metal.

[0017] In some embodiments, the first electrode 110 and the second electrode 120 are spaced substantially equally. The first electrode 110 and the second electrode 120 are spaced substantially equally. This space can be considered as the distance between the first electrode 110 and the second electrode 120. Alternatively, this space can be considered as the width of the dielectric material between the first electrode 110 and the second electrode 120. The size of the space between the first electrode 110 and the second electrode 120 is designed according to the capacitor breakdown voltage requirements.

[0018] In some embodiments, the double-helix structure including the first electrode 110 and the second electrode 120 is a multi-turn structure. That is, the angle from the first end 112 to the second end 114 of the first electrode 110 is greater than about 720 degrees, and the angle from the first end 122 to the second end 124 of the second electrode 120 is greater than about 720 degrees.

[0019] The first electrode 110 and the second electrode 120 extend in the same direction. For example, both the first electrode 110 and the second electrode 120 extend counterclockwise or clockwise from the center C of the capacitor 100. To better utilize space, the first end 112 and the second end 114 of the first electrode 110 face the same direction, and the first end 122 and the second end 124 of the second electrode 120 face the same direction. Alternatively, the first end 112 of the first electrode 110 and the first end 122 of the second electrode 120 do not face the same direction, and the second end 114 of the first electrode 110 and the second end 124 of the second electrode 120 do not face the same direction. In some embodiments, the first end 112 of the first electrode 110 and the first end 122 of the second electrode 120 face opposite directions. In some embodiments, the second end 114 of the first electrode 110 and the second end 124 of the second electrode 120 face opposite directions.

[0020] In some embodiments, the spiral pattern of the first electrode 110 and the second electrode 120 is an Archimedes spiral. The first electrode 110 and the second electrode 120 can be connected to a power line or other metal layer through a through-hole 130. In some embodiments, the through-hole 130 is disposed adjacent to the second ends 114, 124 of the first and second electrodes 110, 120.

[0021] like Figure 1 The capacitor 100 shown can increase the effective area within the same layout area, thereby producing a larger capacitance value within the same layout area. The pattern of the double-wrap capacitor is not limited to a spiral pattern, and other suitable patterns can be used in the double-wrap capacitor. Variations of the double-wrap capacitor are discussed in the following embodiments.

[0022] refer to Figure 2 This is a plan view of an integrated circuit having a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the capacitor 200 of the semiconductor device has a quadrilateral double-wrap structure. The capacitor 200 includes a first electrode 210 and a second electrode 220. The first electrode 210 and the second electrode 220 are disposed in a plane, for example, in the same metal layer. The first electrode 210 and the second electrode 220 are not directly connected to each other, and the first electrode 210 and the second electrode 220 surround each other and extend from the center C of the capacitor 200 to the outside of the capacitor 200.

[0023] The first electrode 210 of capacitor 200 includes multiple turns. The first electrode 210 extends outward from a first end 212 to a second end 214, wherein the first end 212 of the first electrode 210 is disposed adjacent to the center C of capacitor 200. The first electrode 210 is a solid line and has any branches between the first end 212 and the second end 214. The first electrode 210 includes multiple first portions 216 and multiple second portions 218. The first portions 216 and second portions 218 are arranged coplanarly. The first portions 216 and second portions 218 are alternately arranged from the first end 212 to the second end 214 of the first electrode 210 and connected to each other. Each first portion 216 extends longitudinally along a first direction D1a. The first portions 216 are substantially parallel to each other. Each second portion 218 extends from an adjacent first portion 216 along a second direction D2a, wherein the second direction D2a is not collinear with the first direction D1a. The second portions 218 are substantially parallel to each other.

[0024] In some embodiments, the length of the first portion 216 varies. In some embodiments, the length of the first portion 216 gradually increases from the center C of the capacitor 200. For example, the first portion 216 adjacent to the center C has a first end 212 and has the shortest length of the first portion 216. Similarly, the length of the second portion 218 varies. In some embodiments, the length of the second portion 218 gradually increases from the center C of the capacitor 200. For example, the second portion 218 furthest from the center C has a second end 214 and has the longest length of the second portion 218.

[0025] The second electrode 220 of capacitor 200 includes multiple turns. The second electrode 220 extends outward from a first end 222 to a second end 224, with the first end 222 of the second electrode 220 positioned adjacent to the center C of capacitor 200. The second electrode 220 is a solid line and has no branches between the first end 222 and the second end 224. The second electrode 220 includes multiple first portions 226 and multiple second portions 228. The first portions 226 and second portions 228 are arranged coplanarly. The first portions 226 and second portions 228 are alternately arranged from the first end 222 to the second end 224 of the second electrode 220 and connected to each other. Each first portion 226 extends longitudinally along a third direction D3a. The first portions 226 are substantially parallel to each other. Each second portion 228 extends from an adjacent first portion 226 along a fourth direction D4a, wherein the fourth direction D4a is not collinear with the third direction D3a. The second portions 228 are substantially parallel to each other.

[0026] In some embodiments, the first direction D1a is substantially parallel to the third direction D3a, and the second direction D2a is substantially parallel to the fourth direction D4a. In some embodiments, the angle θ1a between the first direction D1a and the second direction D2a is greater than or approximately equal to 90 degrees, and the angle between each first portion 216 and each second portion 218 is greater than or approximately equal to 90 degrees. In some embodiments, the angle θ2a between the third direction D3a and the fourth direction D4a is greater than or approximately equal to 90 degrees, and the angle between each first portion 226 and each second portion 228 is greater than or approximately equal to 90 degrees.

[0027] In some embodiments, the first portion 226 of the second electrode 220 is substantially parallel to the first portion 216 of the first electrode 210, and the second portion 228 of the second electrode 220 is substantially parallel to the second portion 218 of the first electrode 210.

[0028] In some embodiments, the length of the first portion 226 varies. In some embodiments, the length of the first portion 226 gradually increases from the center C of the capacitor 200. For example, the first portion 226 adjacent to the center C has a first end 222 and has the shortest length of the first portion 226. Similarly, the length of the second portion 228 varies. In some embodiments, the length of the second portion 228 gradually increases from the center C of the capacitor 200. For example, the second portion 228 furthest from the center C has a second end 224 and has the longest length of the second portion 228.

[0029] The first electrode 210 and the second electrode 220 can be connected to a power line or other metal layer through a through-hole 230. In some embodiments, the through-hole 230 is disposed adjacent to the second ends 214 and 224 of the first and second electrodes 210 and 220.

[0030] refer to Figure 3 , Figure 3 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the capacitor 300 of the semiconductor device has a hexagonal double-wrap structure. The capacitor 300 includes a first electrode 310 and a second electrode 320. The first electrode 310 and the second electrode 320 are disposed in a plane, for example, in the same metal layer. The first electrode 310 and the second electrode 320 are not directly connected to each other, and the first electrode 310 and the second electrode 320 surround each other and extend from the center C of the capacitor 300 to the outside of the capacitor 300.

[0031] The first electrode 310 of the capacitor 300 includes multiple turns. The first electrode 310 extends outward from a first end 312 to a second end 314, wherein the first end 312 of the first electrode 310 is disposed adjacent to the center C of the capacitor 300. The first electrode 310 is a solid line and has no branches between the first end 312 and the second end 314. The first electrode 310 includes multiple first portions 316, multiple second portions 317, and multiple third portions 318. The first portions 316, second portions 317, and third portions 318 are arranged coplanarly. The first portions 316, second portions 317, and third portions 318 are arranged sequentially from the first end 312 to the second end 314 of the first electrode 310 and are connected to each other.

[0032] Each first portion 316 extends longitudinally along a first direction D1b. The first portions 316 are substantially parallel to each other. Each second portion 317 extends longitudinally along a second direction D2b. Each second portion 317 extends from the adjacent first portion 316 along the second direction D2b, wherein the second direction D2b is not collinear with the first direction D1b. The second portions 317 are substantially parallel to each other.

[0033] Each third portion 318 extends longitudinally along the third direction D3b. The third portions 318 are substantially parallel to each other. Each third portion 318 extends from the adjacent second portion 317 along the third direction D3b, wherein the third direction D3b is not collinear with the second direction D2b. The third portions 318 are substantially parallel to each other. Furthermore, each first portion 316 extends from the adjacent third portion 318 along the first direction D1b, wherein the first direction D1b is not collinear with the third direction D3b.

[0034] In some embodiments, the length of the first portion 316 varies. For example, the length of the first portion 316 gradually increases from the center C of the capacitor 300. For example, the first portion 316 closest to the center C has a first end 312 and is the shortest length of the first portion 316. The third portion 318 furthest from the center C has a second end 314 and is the longest length of the third portion 318. Similarly, the length of the second portion 317 varies, and the length of the second portion 317 gradually increases from the center C of the capacitor 300. For example, the second portion 317 closer to the center C has a shorter length than the second portion 317 farther from the center C.

[0035] The second electrode 320 of the capacitor 300 includes multiple turns. The second electrode 320 extends outward from a first end 322 to a second end 324, wherein the first end 322 of the second electrode 320 is located adjacent to the center C of the capacitor 300. The second electrode 320 is a solid line and has no branches between the first end 322 and the second end 324. The second electrode 320 includes multiple first portions 326, multiple second portions 327, and multiple third portions 328. The first portions 326, second portions 327, and third portions 328 are arranged coplanarly. The first portions 326, second portions 327, and third portions 328 are arranged sequentially from the first end 322 to the second end 324 of the second electrode 320 and are connected to each other.

[0036] Each first portion 326 extends longitudinally along the fourth direction D4b. The first portions 326 are substantially parallel to each other. Each second portion 327 extends longitudinally along the fifth direction D5b. Each second portion 327 extends from the adjacent first portion 326 along the fifth direction D5b, wherein the fifth direction D5b is not collinear with the fourth direction D4b. The second portions 327 are substantially parallel to each other.

[0037] Each third portion 328 extends longitudinally along the sixth direction D6b. The third portions 328 are substantially parallel to each other. Each third portion 328 extends from the adjacent second portion 327 along the sixth direction D6b, wherein the sixth direction D6b is not collinear with the fifth direction D5b. The third portions 328 are substantially parallel to each other. Furthermore, each first portion 326 extends from the adjacent third portion 328 along the fourth direction D4b, wherein the fourth direction D4b is not collinear with the sixth direction D6b.

[0038] In some embodiments, the length of the first portion 326 varies. For example, the length of the first portion 326 gradually increases from the center C of the capacitor 300. For example, the first portion 326 closest to the center C has a first end 322 and is the shortest length of the first portion 326. The third portion 328 furthest from the center C has a second end 314 and is the longest length of the third portion 328. Similarly, the length of the second portion 327 varies, and the length of the second portion 327 gradually increases from the center C of the capacitor 300. For example, the second portion 327 closer to the center C has a shorter length than the second portion 327 farther from the center C.

[0039] In some embodiments, the first direction D1b is substantially parallel to the fourth direction D4b, the second direction D2b is substantially parallel to the fifth direction D5b, and the third direction D3b is substantially parallel to the sixth direction D6b. In some embodiments, the angle θ1b between the first direction D1b and the second direction D2b is greater than or approximately equal to 120 degrees, and the angle between the first portions 316, 326 and the second portions 317, 327 is greater than or approximately equal to 120 degrees. In some embodiments, the angle θ2b between the second direction D2b and the third direction D3b is greater than or approximately equal to 120 degrees, and the angle between the second portions 317, 327 and the third portions 318, 328 is greater than or approximately equal to 120 degrees. In some embodiments, the angle θ3b between the first direction D1b and the third direction D3b is greater than or approximately equal to 120 degrees, and the angle between the first portions 316, 326 and the third portions 318, 328 is greater than or approximately equal to 120 degrees.

[0040] To better utilize space, the first end 312 and the second end 314 of the first electrode 310 do not face the same direction, and the first end 322 and the second end 324 of the second electrode 320 do not face the same direction. Furthermore, the first end 312 and the first end 322 of the first electrode 310 and the second end 324 of the second electrode 320 do not face the same direction. In some embodiments, the first end 312 of the first electrode 310 and the first end 322 of the second electrode 320 face opposite directions. In some embodiments, the second end 314 of the first electrode 310 and the second end 324 of the second electrode 320 face opposite directions.

[0041] The first electrode 310 and the second electrode 320 can be connected to a power line or other metal layer through a through-hole 330. In some embodiments, the through-hole 330 is disposed adjacent to the second ends 314 and 324 of the first and second electrodes 310 and 320.

[0042] refer to Figure 4 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the capacitor 400 of the semiconductor device has an octagonal double-wrap structure. The capacitor 400 includes a first electrode 410 and a second electrode 420. The first electrode 410 and the second electrode 420 are disposed in a plane, for example, in the same metal layer. The first electrode 410 and the second electrode 420 are not directly connected to each other, and the first electrode 410 and the second electrode 420 surround each other and extend from the center C of the capacitor 400 to the outside of the capacitor 400.

[0043] The first electrode 410 of capacitor 400 includes multiple turns. The first electrode 410 extends outward from a first end 412 to a second end 414, wherein the first end 412 of the first electrode 410 is disposed adjacent to the center C of capacitor 400. The first electrode 410 is a solid line and has no branches between the first end 412 and the second end 414. The first electrode 410 includes multiple first portions 416, multiple second portions 417, multiple third portions 418, and multiple fourth portions 419. The first portions 416, second portions 417, third portions 418, and fourth portions 419 are arranged coplanarly. The first portions 416, second portions 417, third portions 418, and fourth portions 419 are arranged sequentially from the first end 412 to the second end 414 of the first electrode 410 and are connected to each other.

[0044] Each first portion 416 extends longitudinally along a first direction D1c. The first portions 416 are substantially parallel to each other. Each second portion 417 extends longitudinally along a second direction D2c. Each second portion 417 extends from the adjacent first portion 416 along the second direction D2c, wherein the second direction D2c is not collinear with the first direction D1c. The second portions 417 are substantially parallel to each other.

[0045] Each third portion 418 extends longitudinally along the third direction D3c. The third portions 418 are substantially parallel to each other. Each third portion 418 extends from the adjacent second portion 417 along the third direction D3c, wherein the third direction D3c is not collinear with the second direction D2c. The third portions 418 are substantially parallel to each other.

[0046] Each fourth portion 419 extends longitudinally along the fourth direction D4c. The fourth portions 419 are substantially parallel to each other. Each fourth portion 419 extends from the adjacent third portion 418 along the fourth direction D4c, wherein the fourth direction D4c is not collinear with the third direction D3c. The fourth portions 419 are substantially parallel to each other. Furthermore, each first portion 416 extends from the adjacent fourth portion 419 along the first direction D1c, wherein the first direction D1c is not collinear with the fourth direction D4c.

[0047] In some embodiments, the first portion 416, the second portion 417, the third portion 418, and the fourth portion 419 have different lengths and gradually increase from the center C of the capacitor 400. For example, the first portion 416, which is closest to the center C, has a first end 412 and has the shortest length of the first portion 416. The first portion 416, which is furthest from the center C, has a second end 414 and has the longest length of the first portion 416.

[0048] The second electrode 420 of capacitor 400 includes multiple turns. The second electrode 420 extends outward from a first end 422 to a second end 424, wherein the first end 422 of the second electrode 420 is disposed adjacent to the center C of capacitor 400. The second electrode 420 is a solid line and has no branches between the first end 422 and the second end 424. The second electrode 420 includes multiple first portions 426, multiple second portions 427, multiple third portions 428, and multiple fourth portions 429. The first portions 426, second portions 427, third portions 428, and fourth portions 429 are arranged coplanarly. The first portions 426, second portions 427, third portions 428, and fourth portions 429 are arranged sequentially from the first end 422 to the second end 424 of the second electrode 420 and are connected to each other.

[0049] Each first portion 426 extends longitudinally along the fifth direction D5c. The first portions 426 are substantially parallel to each other. Each second portion 427 extends longitudinally along the sixth direction D6c. Each second portion 427 extends from the adjacent first portion 426 along the sixth direction D6c, wherein the sixth direction D6c is not collinear with the fifth direction D5c. The second portions 427 are substantially parallel to each other.

[0050] Each third portion 428 extends longitudinally along the seventh direction D7c. The third portions 428 are substantially parallel to each other. Each third portion 428 extends from the adjacent second portion 427 along the seventh direction D7c, wherein the seventh direction D7c is not collinear with the sixth direction D6c. The third portions 428 are substantially parallel to each other.

[0051] Each fourth portion 429 extends longitudinally along the eighth direction D8c. The fourth portions 429 are substantially parallel to each other. Each fourth portion 429 extends from the adjacent third portion 428 along the eighth direction D8c, wherein the eighth direction D8c is not collinear with the seventh direction D7c. The fourth portions 429 are substantially parallel to each other. Furthermore, each first portion 426 extends from the adjacent fourth portion 429 along the fifth direction D5c, wherein the fifth direction D5c is not collinear with the eighth direction D8c.

[0052] In some embodiments, the first direction D1c is substantially parallel to the fifth direction D5c, the second direction D2c is substantially parallel to the sixth direction D6c, the third direction D3c is substantially parallel to the seventh direction D7c, and the fourth direction D4c is substantially parallel to the eighth direction D8c. In some embodiments, the angle θ1c between the first direction D1c and the second direction D2c is greater than or approximately equal to 45 degrees, and the angle between the first portions 416, 426 and the second portions 417, 427 is greater than or approximately equal to 135 degrees. In some embodiments, the angle θ2c between the second direction D2c and the third direction D3c is greater than or approximately equal to 45 degrees, and the angle between the second portions 417, 427 and the third portions 418, 428 is greater than or approximately equal to 135 degrees. In some embodiments, the angle θ3c between the first direction D1c and the fourth direction D4c is greater than or approximately equal to 45 degrees, and the angle between the first portions 416, 426 and the fourth portions 419, 429 is greater than or approximately equal to 135 degrees.

[0053] In some embodiments, the first portion 426, the second portion 427, the third portion 428, and the fourth portion 429 have different lengths and gradually increase from the center C of the capacitor 400. For example, the first portion 426 adjacent to the center C has a first end 422 and has the shortest length of the first portion 426. The first portion 426 furthest from the center C has a second end 424 and has the longest length of the first portion 426.

[0054] To better utilize space, the first end 412 and the second end 414 of the first electrode 410 face the same direction, and the first end 422 and the second end 424 of the second electrode 420 also face the same direction. Alternatively, the first end 412 and the first end 422 of the first electrode 410 and the second end 424 of the second electrode 420 do not face the same direction, and the second ends 414 and 424 of the first electrode 410 and the second end 424 of the second electrode 420 do not face the same direction. In some embodiments, the first end 412 and the first end 422 of the first electrode 410 face opposite directions. In some embodiments, the second ends 414 and the second end 424 of the first electrode 410 face opposite directions.

[0055] The first electrode 410 and the second electrode 420 can be connected to a power line or other metal layer through a through-hole 430. In some embodiments, the through-hole 430 is disposed adjacent to the second ends 414 and 424 of the first and second electrodes 410 and 420.

[0056] refer to Figure 5This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. The semiconductor device 500 includes multiple metal layers. For example, the semiconductor device 500 includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4. The second metal layer M2 and the third metal layer M3 are formed between the first metal layer M1 and the fourth metal layer M4, and each has a first capacitor 510 and a second capacitor 520. The first metal layer M1 and the fourth metal layer M4 can be interconnected through a via 530.

[0057] In some embodiments, the first metal layer M1 includes a bottom metal plate 540, and the fourth metal layer M4 includes a top metal plate 542. The bottom metal plate 540 and the top metal plate 542 can be used as shielding metal plates, and a first capacitor 510 and a second capacitor 520 are disposed between the bottom metal plate 540 and the top metal plate 542.

[0058] The first capacitor 510 and the second capacitor 520 can be MOM capacitors, such as capacitors 100, 200, 300, and 400 discussed above. The first capacitor 510 is disposed in the second metal layer M2 and includes a first electrode 512 and a second electrode 514. The second capacitor 520 is disposed in the third metal layer M3 and includes a first electrode 522 and a second electrode 524.

[0059] In some embodiments, the first electrode 512 of the first capacitor 510 completely overlaps with the first electrode 522 of the second capacitor 520, and the second electrode 514 of the first capacitor 510 completely overlaps with the second electrode 524 of the second capacitor 520. In some embodiments, the first electrode 512 of the first capacitor 510 and the first electrode 522 of the second capacitor 520 are charged in opposite directions, and the second electrode 514 of the first capacitor 510 and the second electrode 524 of the second capacitor 520 are charged in opposite directions.

[0060] For example, the first electrode 512 is the cathode of the first capacitor 510, the second electrode 514 is the anode of the first capacitor 510, the first electrode 522 is the anode of the second capacitor 520, and the second electrode 524 is the cathode of the second capacitor 520. This arrangement introduces capacitance not only laterally between the first electrode 512 and the second electrode 514 of the first capacitor 510 and between the first electrode 522 and the second electrode 524 of the second capacitor 520, but also vertically between the first electrode 512 of the first capacitor 510 and the first electrode 522 of the second capacitor 520, and between the second electrode 514 of the first capacitor 510 and the second electrode 524 of the second capacitor 520, thereby further increasing the capacitance value of the semiconductor device 500.

[0061] refer to Figure 6This is a plan view of a semiconductor device according to some embodiments of the present disclosure. The semiconductor device 600 includes a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 and the second capacitor C2 are arranged in a plane, for example, in the same metal layer. In some embodiments, the first capacitor C1 and the second capacitor C2 are quadrilateral double-wrap structures. In some other embodiments, the first capacitor C1 and the second capacitor C2 may be a helical double-wrap structure, a hexagonal double-wrap structure, an octagonal double-wrap structure, or other polygonal double-wrap structures.

[0062] Semiconductor device 600 includes a first electrode 610 of a first capacitor C1, a second electrode 620 of a second capacitor C2, and a common electrode 630 shared by the first capacitor C1 and the second capacitor C2. The common electrode 630 is disposed between the first electrode 610 of the first capacitor C1 and the second electrode 620 of the second capacitor C2. The common electrode 630 and the first electrode 610 form the first capacitor C1, and the common electrode 630 and the second electrode 620 form the second capacitor C2. In some embodiments, the first electrode 610 is the anode of the first capacitor C1, the second electrode 620 is the anode of the second capacitor C2, and the common electrode 630 is the common cathode of the first capacitor C1 and the second capacitor C2. In some other embodiments, the first electrode 610 is the cathode of the first capacitor C1, the second electrode 620 is the cathode of the second capacitor C2, and the common electrode 630 is the common anode of the first capacitor C1 and the second capacitor C2.

[0063] In some embodiments, it can be Figure 6 The structures are stacked on the same or similar structures, such as Figure 7 As shown, this allows for the introduction of capacitance laterally between the first capacitor C1 and the second capacitor C2 in a plane, and the introduction of capacitance vertically between the first capacitor C1 and the second capacitor C2 in different planes.

[0064] refer to Figures 8A to 8F This is a cross-sectional view of various stages in the manufacture of a semiconductor device according to some embodiments of the present disclosure. Figure 8AAs shown, a dielectric layer 810 is formed on a substrate 800. The substrate 800 may include elemental semiconductors (e.g., silicon or germanium) and / or compound semiconductors (e.g., silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide). The substrate 800 may include one or more doped regions. For example, regions of the substrate 800 may be doped with p-type dopants. Suitable p-type dopants include boron, gallium, indium, other suitable p-type dopants, and / or combinations thereof. The substrate may also include one or more regions doped with n-type dopants (e.g., phosphorus, arsenic, other suitable n-type dopants, and / or combinations thereof). Doping can be achieved using processes such as ion implantation or diffusion at various steps and techniques. In some embodiments, the substrate 800 includes one or more active devices (not shown) formed on the substrate. Examples of such active devices include P-channel field-effect transistors (PFETs), N-channel FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, FinFETs, high-voltage transistors, high-frequency transistors, bipolar junction transistors, other suitable devices, and / or combinations thereof.

[0065] The dielectric layer 810 may include semiconductor oxide, semiconductor nitride, semiconductor oxynitride, TEOS oxide, or other suitable materials. In some embodiments, the dielectric layer 810 includes one or more sublayers, such as an etch stop layer and / or a contact etch stop layer (CESL).

[0066] refer to Figure 8B A patterning process is performed to pattern the dielectric layer 810, thereby forming a plurality of trenches 820 in the dielectric layer 810. In some embodiments, the number of trenches 820 may be two or three. The top view of the trenches 820 may be helical, quadrilateral, hexagonal, octagonal, or other polygonal.

[0067] refer to Figure 8C A filler layer 830 is deposited in the trench 820 and on the dielectric layer 810. The filler layer 830 comprises a conductive material, such as tungsten, copper, aluminum, aluminum / silicon / copper alloy, titanium, titanium nitride, tungsten nitride, metal silicide, combinations thereof, or another suitable conductive material.

[0068] refer to Figure 8D A planarization process is performed to expose the top surface of the dielectric layer 810, and the remaining conductive material is filled in the trench 820 (e.g., Figure 8C As shown in the figure, it is a capacitor used as electrode 840. In some embodiments, the electrode 840 of the capacitor includes a cathode and an anode, and its structure and dimensions are similar to those of a capacitor. Figures 1-4The discussion in [the document] continues. In some other embodiments, the electrodes 840 of the capacitor include a cathode, an anode, and a common electrode, and their structure and dimensions are similar to [other electrodes]. Figures 1-4 and Figure 6 The discussion in the text. In some embodiments, electrode 840 and dielectric layer 810 may be referred to as metal layers, and electrode 840 is a conductive line in the metal layer.

[0069] refer to Figure 8E An additional metal layer, including an electrode 850 and a dielectric layer 814, is formed over the metal layer including the electrode 840 and the dielectric layer 810, and the metal layer is spaced apart by the dielectric layer 812. The electrode 850 is formed in the dielectric layer 814 and has a pattern similar to that of the electrode 840.

[0070] refer to Figure 8F An interlayer dielectric layer 816 is formed on the electrode 850 and the dielectric layer 814, and a plurality of vias 860 are formed, which penetrate the interlayer dielectric layer 816 to connect to the corresponding electrode 850. In some embodiments, the electrode 840 in the dielectric layer 810 includes a first anode 840a and a first cathode 840b, wherein the first anode 840a extends outwardly spirally or polygonally from a first end to a second end, and the first anode 840a and the first cathode 840b have a substantially equal spacing. The electrode 850 in the dielectric layer 814 includes a second anode 850b and a second cathode 850a, wherein the second anode 850b extends outwardly spirally or polygonally from a first end to a second end, and the second anode 850b and the second cathode 850a have a substantially equal spacing. The second anode 850b overlaps with the first cathode 840b to generate additional capacitance therebetween. The second cathode 850a overlaps with the first anode 840a to generate additional capacitance therebetween.

[0071] According to some embodiments, the electrodes of the capacitor surround each other and are spaced at a constant distance. The electrodes of the capacitor extend spirally or polygonally from the first end to the second end without any branches, thereby increasing the capacitance value of the capacitor.

[0072] According to some embodiments, the semiconductor device includes a capacitor. The capacitor includes a first electrode and a second electrode disposed in a first metal layer. The first electrode has a first end and a second end, and the first electrode has a helical pattern extending outward from the first end to the second end. The first electrode and the second electrode have substantially equal spacing.

[0073] According to some embodiments, a semiconductor device includes a first electrode and a second electrode disposed in a metal layer. The first electrode has a first end and a second end. The first electrode has a plurality of turns and extends outward from the first end to the second end. The first electrode includes a first portion extending longitudinally in a plane along a first direction, and a second portion coplanar with the first portion in the plane and extending from the first portion along a second direction not collinear with the first direction. The first electrode and the second electrode have a substantially equal spacing.

[0074] According to some embodiments, a method includes forming a first dielectric layer on a substrate, and forming a first anode and a first cathode in the first dielectric layer, wherein the first anode extends helically or polygonally outward from a first end to a second end of the first anode, and the first anode and the first cathode have a substantially equal spacing. A second dielectric layer is formed on the first dielectric layer. A second anode and a second cathode are formed in the second dielectric layer, wherein the second anode extends helically or polygonally outward from a first end to a second end of the second anode, and the second anode and the second cathode have a substantially equal spacing.

[0075] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0076] Example 1 is a semiconductor device comprising: a first capacitor including: a first electrode disposed in a first metal layer and having a first end and a second end, wherein the first electrode has a spiral pattern extending outward from the first end to the second end; and a second electrode disposed in the first metal layer, wherein the first electrode and the second electrode have substantially equal spacing.

[0077] Example 2 is the semiconductor device described in Example 1, wherein the second electrode has a first end and a second end, wherein the second electrode extends outwardly spirally from the first end of the second electrode to the second end of the second electrode.

[0078] Example 3 is the semiconductor device described in Example 2, wherein the first end of the first electrode and the first end of the second electrode face opposite directions.

[0079] Example 4 is the semiconductor device described in Example 2, wherein the second end of the first electrode and the second end of the second electrode face opposite directions.

[0080] Example 5 is the semiconductor device described in Example 1, wherein the spiral pattern of the first electrode is an Archimedean spiral.

[0081] Example 6 is the semiconductor device described in Example 1, further comprising: a second capacitor including: a third electrode disposed in a second metal layer, wherein the third electrode overlaps with the first electrode; and a fourth electrode disposed in the second metal layer, wherein the fourth electrode overlaps with the second electrode.

[0082] Example 7 is the semiconductor device described in Example 6, wherein the first electrode and the fourth electrode are anodes, and the second electrode and the third electrode are cathodes.

[0083] Example 8 is the semiconductor device described in Example 6, further comprising: a pair of shielding plates, wherein the first capacitor and the second capacitor are disposed between the shielding plates.

[0084] Example 9 is the semiconductor device described in Example 1, further comprising: a common electrode disposed in the first metal layer and located between the first electrode and the second electrode.

[0085] Example 10 is the semiconductor device described in Example 9, wherein the common electrode is an anode, and the first electrode and the second electrode are cathodes.

[0086] Example 11 is the semiconductor device described in Example 9, wherein the common electrode is a cathode, and the first electrode and the second electrode are anodes.

[0087] Example 12 is the semiconductor device described in Example 9, wherein a first distance between the common electrode and the first electrode is equal to a second distance between the common electrode and the second electrode.

[0088] Example 13 is the semiconductor device described in Example 1, wherein the first capacitor is a metal oxide metal capacitor.

[0089] Example 14 is a semiconductor device comprising: a first electrode disposed in a first metal layer and having a first end and a second end, the first electrode having a plurality of turns and extending outwardly from the first end to the second end, the first electrode comprising: a first portion extending longitudinally in a plane along a first direction; and a second portion coplanar with the first portion in the plane and extending from the first portion along a second direction not collinear with the first direction; and a second electrode disposed in the first metal layer, wherein the first electrode and the second electrode have substantially equal spacing.

[0090] Example 15 is the semiconductor device described in Example 14, wherein the first electrode has no branches.

[0091] Example 16 is the semiconductor device described in Example 14, wherein the second electrode has no branches.

[0092] Example 17 is the semiconductor device described in Example 14, further comprising: a third electrode disposed in the first metal layer and located between the first electrode and the second electrode.

[0093] Example 18 is the semiconductor device described in Example 17, wherein the third electrode has no branches.

[0094] Example 19 is the semiconductor device described in Example 14, wherein the semiconductor device is a quadrilateral capacitor, a hexagonal capacitor, or an octagonal capacitor.

[0095] Example 20 is a method for manufacturing a semiconductor device, comprising: forming a first dielectric layer on a substrate; forming a first anode and a first cathode in the first dielectric layer, wherein the first anode extends outwardly in a spiral or polygonal manner from a first end to a second end of the first anode, and the first anode and the first cathode have a substantially equal spacing; forming a second dielectric layer on the first dielectric layer; and forming a second anode and a second cathode in the second dielectric layer, wherein the second anode extends outwardly in a spiral or polygonal manner from a first end to a second end of the second anode, and the second anode and the second cathode have a substantially equal spacing.

Claims

1. A semiconductor device comprising: a first capacitor comprising: a first electrode disposed in a first metal layer and having a first end and a second end, wherein the first electrode has a first spiral pattern extending outward from the first end to the second end; a second electrode disposed in the first metal layer and having a third end, a fourth end, and a second spiral pattern extending outward from the third end to the fourth end, wherein the first electrode and the second electrode have substantially equal spacing therebetween; and a common electrode disposed in the first metal layer and having a fifth end, a sixth end, and a third spiral pattern extending outward from the fifth end to the sixth end, wherein the fifth end of the common electrode is between the first end of the first electrode and the third end of the second electrode, wherein the first electrode, the common electrode, and the second electrode are arranged in a triple spiral pattern in order, wherein the semiconductor device further comprises: a second capacitor comprising: a third electrode disposed in a second metal layer, wherein the third electrode overlaps the first electrode; a fourth electrode disposed in the second metal layer, wherein the fourth electrode overlaps the second electrode; and a second common electrode disposed in the second metal layer, wherein the second common electrode overlaps the common electrode, wherein the third electrode, the second common electrode, and the fourth electrode are arranged in a triple spiral pattern in order.

2. The semiconductor device of claim 1, wherein, the first end of the first electrode and the third end of the second electrode face in opposite directions.

3. The semiconductor device of claim 1, wherein, the second end of the first electrode and the fourth end of the second electrode face in opposite directions.

4. The semiconductor device of claim 1, wherein, the first spiral pattern of the first electrode is an Archimedean spiral.

5. The semiconductor device of claim 1, further comprising: a pair of shielding plates, wherein the first capacitor and the second capacitor are disposed between the shielding plates.

6. The semiconductor device of claim 1, wherein, the common electrode is between the first electrode and the second electrode.

7. The semiconductor device of claim 1, wherein, the common electrode is an anode and the first electrode and the second electrode are cathodes.

8. The semiconductor device of claim 1, wherein, the common electrode is a cathode and the first electrode and the second electrode are anodes.

9. The semiconductor device of claim 1, wherein, a first distance between the common electrode and the first electrode is equal to a second distance between the common electrode and the second electrode.

10. The semiconductor device of claim 1, wherein, the first capacitor is a metal-oxide-metal capacitor.

11. A semiconductor device comprising: a first electrode disposed in a first metal layer and having a first end and a second end, the first electrode having a plurality of turns and extending outward from the first end to the second end, the first electrode comprising: a first portion extending longitudinally in a first direction in a plane; and a second portion coplanar with the first portion in the plane and extending from the first portion along a second direction that is not collinear with the first direction; a second electrode disposed in the first metal layer, wherein the first electrode and the second electrode have substantially equal spacing therebetween. a plurality of first vias on a next layer above the first metal layer and electrically coupled to the first electrode; and a plurality of second vias on the next layer above the first metal layer and electrically coupled to the second electrode, wherein the semiconductor device further comprises: a third electrode arranged in the first metal layer and between the first electrode and the second electrode, wherein the first electrode, the third electrode, and the second electrode are arranged in a triple helix pattern, wherein the semiconductor device further comprises: a fourth electrode disposed in a second metal layer, wherein the fourth electrode overlaps the first electrode; a fifth electrode disposed in the second metal layer, wherein the fifth electrode overlaps the second electrode; and a sixth electrode disposed in the second metal layer, wherein the sixth electrode overlaps the third electrode, wherein the fourth electrode, the sixth electrode, and the fifth electrode are arranged in a triple helix pattern.

12. The semiconductor device of claim 11, wherein, The first electrode has no branches.

13. The semiconductor device of claim 11, wherein, The second electrode has no branches.

14. The semiconductor device of claim 11, wherein, The third electrode has no branches.

15. The semiconductor device of claim 11, wherein, The semiconductor device is in a quadrilateral capacitor, a hexagonal capacitor, or an octagonal capacitor.

16. A method for fabricating a semiconductor device, comprising: forming a first dielectric layer on a substrate; forming a first electrode, a second electrode, and a first common electrode in the first dielectric layer, the first electrode having a first end, a second end, and a first helix pattern extending outward from the first end to the second end, the second electrode having a third end, a fourth end, and a second helix pattern extending outward from the third end to the fourth end, the first common electrode having a fifth end, a sixth end, and a third helix pattern extending outward from the fifth end to the sixth end, wherein the fifth end of the first common electrode is between the first end of the first electrode and the third end of the second electrode; forming a second dielectric layer on the first dielectric layer; and forming a third electrode and a fourth electrode and a second common electrode in the second dielectric layer, wherein the third electrode overlaps the first electrode, the fourth electrode overlaps the second electrode, and the second common electrode overlaps the first common electrode, wherein the first electrode, the first common electrode, and the second electrode are arranged in a triple helix pattern, and wherein the third electrode, the second common electrode, and the fourth electrode are arranged in a triple helix pattern.

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