Electrostatic protection

Abstract

Various embodiments of this disclosure relate to electrostatic discharge (ESD) protection. ESD protection devices and methods are provided. In at least one embodiment, the device includes a first stack forming a Zener diode. The first stack includes a substrate of a first conductivity type having a first region of a second conductivity type therein. The first region is flush with the surface of the substrate. A second stack forms the diode and is located on and in contact with the surface of the substrate. The second stack includes a first layer of a second conductivity type having a second region of the first conductivity type therein. The second region is opposite to the first stack and flush with the surface of the first layer. A third stack includes at least a second layer made of an oxygen-doped material, which is on and in contact with the second stack.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to electronic electrostatic discharge protection devices. Background Technology

[0002] Various devices are known to prevent and protect against electrostatic discharge. Summary of the Invention

[0003] The performance of current electronic electrostatic discharge protection equipment needs to be improved.

[0004] One embodiment provides an apparatus comprising:

[0005] A first stack forming a Zener diode (known by the trade name Transil) includes a substrate of a first conductivity type, the substrate having a first region therein, the first region being flush with the surface of the substrate;

[0006] A second stack, forming a diode, is located above and in contact with the aforementioned surface of the substrate, and the second stack includes a first layer of a second conductivity type, the first layer having a second layer of the first conductivity type therein, a second region opposite to the first stack and flush with the surface of the first layer; and

[0007] The third stack includes at least a second layer made of semi-insulating polycrystalline silicon, which is on top of and in contact with the second stack.

[0008] According to one embodiment, the third stack includes a third layer of field oxide, which is on top of and in contact with the second layer.

[0009] According to one embodiment, the third layer is made of undoped silicate glass.

[0010] According to one embodiment, the third layer is made of tetraethyl orthosilicate.

[0011] According to one embodiment, the third layer has a thickness in the range of 1 μm to 4 μm, preferably equal to about 2 μm, more preferably equal to 2 μm.

[0012] According to one embodiment, the second layer has a thickness in the range of 0.3 μm to 1 μm, preferably equal to about 0.8 μm, more preferably equal to 0.8 μm.

[0013] According to one embodiment, the first layer has a thickness in the range of 8 μm to 15 μm, preferably equal to about 12 μm, more preferably equal to 12 μm.

[0014] One embodiment provides a method for manufacturing the device, comprising at least the following steps:

[0015] A first region is formed in the substrate;

[0016] A first layer is formed epitaxially, the first layer being above and in contact with the aforementioned surface of the substrate, and a second region is formed within the first layer; and

[0017] A second layer is formed, which is on top of and in contact with the second stack.

[0018] According to one embodiment, the second layer is deposited by low-pressure chemical vapor deposition.

[0019] According to one embodiment, the third layer is deposited by plasma-enhanced chemical vapor deposition.

[0020] According to one embodiment, the second and third layers are etched simultaneously in a straight line perpendicular to the second region. Attached Figure Description

[0021] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings.

[0022] Figure 1 This is a simplified cross-sectional view of an electronic electrostatic discharge protection device.

[0023] Figure 2 Manufacturing process is shown Figure 1 The steps of implementing the method of the device;

[0024] Figure 3 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device;

[0025] Figure 4 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device;

[0026] Figure 5 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device;

[0027] Figure 6 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device;

[0028] Figure 7 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device;

[0029] Figure 8 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device;

[0030] Figure 9 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device; and

[0031] Figure 10 It is a diagram. Figure 1 A graphical representation of an example of the variation in stray capacitance present in the device shown; and

[0032] Figure 11 It is a diagram. Figure 1 A graphical representation of another example of the variation in stray capacitance present in the device shown. Detailed Implementation

[0033] In different figures, the same elements are designated by the same reference numerals. In particular, structural and / or functional elements common to different embodiments can be designated by the same reference numerals and can have the same structure, dimensions, and material properties.

[0034] For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, although the application of electrostatic discharge protection circuits is used as an example, the described embodiments of oxygen-doped layers that restrict charge transfer are more generally applicable to all integrated circuits that require or otherwise benefit from such a barrier to charge transfer.

[0035] Throughout this disclosure, the term "connection" is used to specify a direct electrical connection between circuit elements, while the term "coupling" is used to specify an electrical connection between circuit elements, which may be direct or may be via one or more intermediate elements.

[0036] In the following description, when a term is used to define an absolute position (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or a relative position (such as the terms “above,” “below,” “upper,” “lower,” etc.), or when a term is used to define a direction (such as the terms “horizontal,” “vertical,” etc.), it refers to the orientation of the accompanying drawings unless otherwise specified.

[0037] The terms “approximately,” “around,” “basically,” and “about” are used herein to indicate a tolerance of plus or minus 10%, preferably plus or minus 5%, for the value under discussion.

[0038] Figure 1 This is a partial simplified cross-sectional view of one embodiment of the electrostatic discharge protection device 1.

[0039] More specifically, Figure 1 An electrostatic discharge protection circuit made in an integrated form is shown.

[0040] In the following description, in Figure 1In the orientation, the upper surface of the structure or layer is considered the front, and... Figure 1 In the orientation, the lower surface of the structure or layer is considered the back side.

[0041] Device 1 includes:

[0042] The first stack 11 includes a substrate 13 having a first region 15 located in the substrate 13 and flush with the upper surface of the substrate 13;

[0043] A second stack 17 is located above and in contact with the upper surface of the first stack 11. The second stack 17 includes a first layer 19 having a second region 21 located within the first layer 19 and flush with its upper surface.

[0044] The third stack 23 is located above and in contact with the upper surface of the second stack 17, and the third stack 23 includes at least one second layer 25.

[0045] The substrate 13 is made of, for example, a heavily doped semiconductor material of the first conductivity type. The substrate 13 is made of, for example, silicon.

[0046] For example, the first region 15 extends in the plane of the front side of the substrate, above a surface area smaller than the surface of the substrate 13. The first region 15 is made of a material of a second conductivity type, different from the first conductivity type.

[0047] The first layer 19 is made of, for example, a very lightly doped material of a first conductivity type. The material of the first layer 19 has, for example, a conductivity of 20 Ω·cm. -1 Up to 100Ω·cm -1 Conductivity within a certain range.

[0048] The second region 21 is positioned, for example, opposite to the first region 15, and extends in the plane of the front side of the substrate, above a surface region smaller than that of the first region 15. The second region 21 is made of, for example, a heavily doped material of a second conductivity type.

[0049] The second layer 25 is open relative to a portion of the second region 21. In other words, layer 25 exposes a portion of the second region 21. The second layer 25 is made of SIPOS (semi-insulating polycrystalline silicon) material. SIPOS corresponds to partially oxidized silicon, i.e., silicon typically having an oxygen concentration greater than about 10%. In this description, the oxygen concentration of SIPOS is preferably in the range of 20% to 50%, and more preferably in the range of 25% to 35%.

[0050] Figure 1The third stack 23 of the device 1 illustrated in the diagram also includes a third layer 27, which is above and in contact with the second layer 25. This layer 27 is a field oxide, such as undoped silicate glass (USG) or tetraethyl orthosilicate (TEOS). The third layer 27 is open relative to the second layer 21, such that the opening in the second layer 25 is aligned with the opening in the third layer 27 (in...). Figure 1 (In the orientation, align horizontally).

[0051] The first stack 11 forms a Zener diode, such as a diode known by trade names Transil or TD, through its junction between region 15 and substrate 13. The Zener diode has a first region 15 as a cathode and a substrate 13 as an anode.

[0052] The second stack 17 forms a diode D through its junction between layer 19 and region 21. The diode D has a first layer 19 as a cathode and a second region 21 as an anode.

[0053] Device 1 is designed to be coupled to ground 29 via the back side of substrate 13 and includes input / output pads 31 (I / O) that are coupled (preferably connected to) a second region 21.

[0054] The advantage of this embodiment is the insulation provided by the second layer 25, which is made of oxygen-doped silicon. In effect, the second layer 25 enables the restriction of positive charge transport from the third field oxide layer 27 to the first layer 19. Due to the semi-insulating nature of the second layer 25, charge accumulation at the interface with the first layer 19 is prevented, thus reducing charge migration between the third layer 27 and layer 19.

[0055] Another advantage of this embodiment is that the thickness of the third layer 27 can be increased, and thus the overall capacitance is reduced by decreasing the metallization stray capacitance. Without layer 25, any increase in the layer 27 to reduce stray capacitance would adversely affect the modification of the doping of the underlying layer 19.

[0056] Figures 2 to 9 The manufacturing process is illustrated schematically and partially. Figure 1 The sequential steps of an embodiment of the method of device 1 illustrated in the figure.

[0057] For the sake of simplicity, unless otherwise specified, the manufacturing steps are specified in the same manner as the structure obtained at the end of the steps.

[0058] Figure 2 Manufacturing process is shown Figure 1 The steps of implementing the method of the device.

[0059] More specifically, Figure 2The initial structure formed from substrate 13 is shown.

[0060] Figure 3 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device.

[0061] More specifically, Figure 3 The steps for forming a first region 15 in a substrate 13 are illustrated.

[0062] A first region 15 is formed in the substrate 13 such that the front side of the first region 15 is flush with the front side of the substrate 13. The first region 15 extends, for example, in the plane of the front side of the substrate, over a surface region smaller than the surface region of the substrate 13.

[0063] exist Figure 3 At the end of the steps illustrated in the figure, the first region 15 is embedded in the substrate 13 and together with the substrate 13 forms the first stack 11.

[0064] Figure 4 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device.

[0065] More specifically, Figure 4 The illustration shows that in Figure 2 and Figure 3 The first layer 19 is formed on the front side of the structure obtained at the end of the steps.

[0066] Layer 19 is formed over the entire structure (the entire plate), that is, layer 19 is formed on the upper surface of substrate 13 and first region 15. Layer 19 has a substantially constant thickness A across its entire surface.

[0067] The thickness A of the first layer 19 is in the range of 8 μm to 15 μm, and preferably equal to about 12 μm. Thickness A is more preferably equal to 12 μm.

[0068] For example, a first layer 19 is formed on the surface of the first stack 11 by epitaxy.

[0069] Figure 5 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device.

[0070] More specifically, Figure 5 The illustration shows that in Figures 2 to 4 The step of forming the second region 21 in the first layer 19 of the structure obtained at the end of the step.

[0071] A second region 21 is formed in the first layer 19 such that the front surface of the second region 21 is flush with the front surface of the layer 19. The second region 21 is positioned, for example, opposite to and centered relative to the first region 15. The second region 21 extends in the plane of the front surface of the substrate 13, above a surface region smaller than the surface region of the first region 15.

[0072] exist Figure 5 At the end of the steps illustrated in the diagram, the second region 21 is embedded in layer 19, and the second region 21 together with layer 19 forms the second stack 17.

[0073] Figure 6 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device.

[0074] More specifically, Figure 6 The illustration shows that in Figures 2 to 5 The second layer 25 is deposited on the front side of the structure obtained at the end of the step.

[0075] Layer 25 is deposited over the entire structure as a whole plate; that is, layer 25 is deposited on the upper surface of the first layer 19 and on the front side of the second region 21. Layer 25 has a substantially constant thickness B across its entire surface.

[0076] The thickness B of the second layer 25 is in the range of 0.3 μm to 1 μm, and preferably equal to about 0.8 μm. More preferably, the thickness B is equal to 0.8 μm.

[0077] Layer 25 is formed, for example, by low-pressure chemical vapor deposition (LPCVD).

[0078] Figure 7 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device.

[0079] More specifically, Figure 7 The illustration shows that in Figures 2 to 6 The third layer 27 is deposited on the front side of the structure obtained at the end of the step.

[0080] Layer 27 is deposited over the entire structure as a whole plate; that is, layer 27 is deposited on the upper surface of layer 25. Layer 27 has a substantially constant thickness C across its entire surface.

[0081] The thickness C of the third layer 27 is in the range of 1 μm to 4 μm, preferably equal to about 2 μm. More preferably, the thickness C is equal to 2 μm.

[0082] According to one embodiment, the third layer 27 is made of USG (undoped silicate glass) and formed by plasma-enhanced chemical vapor deposition (PECVD). For example, the deposition is followed by annealing of the USG at a temperature of approximately 900 degrees Celsius.

[0083] According to another embodiment, the third layer 27 is TEOS (tetraethyl orthosilicate) and is formed by LPCVD. For example, the deposition is followed by annealing of the TEOS at a temperature of approximately 900 degrees Celsius. Stack 23 is obtained after the deposition of layer 27.

[0084] Figure 8 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device.

[0085] More specifically, Figure 8 The illustration shows that in Figures 2 to 7 The process ends with the deposition and photolithography of the fourth layer 33 of resin on the front side of the structure.

[0086] In this embodiment, the third layer 27 is covered by the fourth layer 33. The fourth layer 33 covers the third layer 27, for example, by spin coating deposition.

[0087] Then layer 33 is subjected to photolithography, that is, layer 33 is exposed to UV lines through a mask, and then developed in a solvent.

[0088] The resin is, for example, a positive resin, meaning that the portion of the resin exposed to UV rays becomes soluble in the solvent.

[0089] At the end of the photolithography step, layer 33 extends over the entire layer 27 and over a portion of the second region 21, leaving a portion of region 21 uncovered by layer 33.

[0090] Figure 9 Manufacturing process is shown Figure 1 Another step in the implementation of the method of the device.

[0091] More specifically, Figure 9 The diagram illustrates the process from... Figures 2 to 8 The step at the end of the process involves etching the second layer 25 and the third layer 27 to obtain the structure.

[0092] The portions of layers 25 and 27 that are not covered by layer 33 are removed by etching.

[0093] Etching of layers 25 and 27 enables the formation of vias in both layers 25 and 27, and thus exposes a portion of the second region 21.

[0094] according to Figure 9In the embodiment illustrated in the middle, etching is performed such that the sides of the opening are tilted and the opening narrows as it deepens. In other words, in Figure 9 At the end of the steps illustrated in the diagram, the opening on the front of region 21 is narrower than on the front of layer 27.

[0095] During this step, layer 33 is removed. Therefore, in Figure 9 When the steps shown in the diagram are completed, the structure no longer includes layer 33.

[0096] Figure 10 It is a diagram. Figure 1 A graphical representation of an example of the variation in stray capacitance present in the device shown.

[0097] More specifically, Figure 10 The figure illustrates the variation of stray capacitance in nanofarads (fF) depending on the test points and the composition of stack 23. Measurements have been performed at 20 different test points, i.e., at 20 different devices (1, Figure 1 Measurements were performed on ).

[0098] Figure 10 The graph includes two curves:

[0099] The first curve 35 shows the variation in stray capacitance, and stack 23 is formed by a single TEOS layer; and

[0100] The second curve 37 shows the variation in stray capacitance, and the stack 23 is formed by the SIPOS layer and the USG layer.

[0101] The curves show that, compared to the case without the SIPOS layer in stack 23, the presence of the SIPOS layer in stack 23 reduces stray capacitance by approximately 20%. With a single TEOS layer without SIPOS, the measured stray capacitance ranges from 440 fF to 540 fF, averaging 486 fF, depending on the measurement point. With the presence of both the SIPOS layer 25 and the USG field oxide layer, the measured stray capacitance ranges from 360 fF to 430 fF, averaging 394 fF, depending on the test point.

[0102] Figure 11 It is a diagram. Figure 1 A graphical representation of another example of the variation in stray capacitance present in the device shown.

[0103] More specifically, Figure 11 The diagram illustrates how the stray capacitance distribution varies in nanofarads (fF) depending on the composition of stack 23.

[0104] Figure 11 The graph includes three curves:

[0105] The third curve 39 shows the change in stray capacitance, and stack 23 is formed by a SIPOS layer covered with a USG layer;

[0106] The fourth curve 41 shows the variation in stray capacitance, and stack 23 is formed by SIPOS and TEOS layers; and

[0107] The fifth curve 43 shows the variation in stray capacitance. Stack 23 is formed by excluding the thermal oxide layer and TEOS layer of SIPOS.

[0108] These curves 39, 41, and 43 show that the stray capacitance of the device is smaller when stack 23 includes the SIPOS layer. The stray capacitance is also smaller when the SIPOS layer is covered by the USG layer compared to the TEOS layer.

[0109] One advantage of the described embodiments is that they enable the increase of the field oxide thickness without modifying the doping of the underlying epitaxial layer 19.

[0110] Another advantage of the described embodiments is that when the devices are used in computers or any other electronic products, they enable the reduction of metallization stray capacitance, the reduction of line capacitance, and thus the limitation of data loss.

[0111] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. The described embodiments are not limited to the examples of dimensions and materials described above.

[0112] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0113] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to these claims. Therefore, the claims are not limited by the disclosure.

Claims

1. An electronic device, comprising: A first stack is formed to form a Zener diode. The first stack includes a substrate of a first conductivity type, the substrate having a first region of a second conductivity type in the substrate, the first region having a surface flush with the surface of the substrate. A second stack forms a diode, the second stack being located on and in contact with the surface of the substrate, and the second stack including a first layer of the second conductivity type, the first layer having a second region of the first conductivity type in the first layer, the second region having a surface flush with the surface of the first layer and opposite to the first stack; as well as The third stack includes at least a second layer made of semi-insulating polycrystalline silicon, the second layer being on and in contact with the second stack; The third stack includes a third layer of field oxide that is on top of and in contact with the second layer.

2. The device according to claim 1, wherein the third layer is made of undoped silicate glass.

3. The device according to claim 1, wherein the third layer is made of tetraethyl orthosilicate.

4. The device according to claim 1, wherein the third layer has a thickness in the range of 1 μm to 4 μm.

5. The device according to claim 1, wherein the third layer has a thickness of 2 μm.

6. The device of claim 1, wherein the second layer has a thickness in the range of 0.3 μm to 1 μm.

7. The device according to claim 1, wherein the second layer has a thickness of 0.8 μm.

8. The device of claim 1, wherein the first layer has a thickness in the range of 8 μm to 15 μm.

9. The device according to claim 1, wherein the first layer has a thickness of 12 μm.

10. A method of manufacturing an electronic device, comprising: Zener diodes are formed in the following way: A first region is formed in a substrate having a first conductivity type, the first region having a second conductivity type different from the first conductivity type, and the first region having a surface flush with the surface of the substrate. as well as Diodes are formed in the following ways: A first layer is formed by epitaxy, the first layer being on and in contact with the surface of the substrate, the first layer having the second conductivity type; as well as A second region is formed in the first layer, the second region having the first conductivity type, and the surface of the second region is flush with the surface of the first layer; and a second layer of semi-insulating polysilicon is formed on the surface of the first layer and in contact with the surface of the first layer. as well as A third layer of field oxide is formed, which is on top of and in contact with the second layer.

11. The method of claim 10, wherein forming the second layer comprises forming the second layer by low-pressure chemical vapor deposition.

12. The method of claim 10, wherein forming the third layer comprises forming the third layer by plasma-enhanced chemical vapor deposition.

13. The method of claim 10 further comprises simultaneously etching the second layer and the third layer perpendicular to the second region.

14. An electronic device comprising: A substrate having a first conductivity type, the substrate having a first surface; A Zener diode includes a first region of a second conductivity type, the first region extending from a first surface of the substrate into the substrate; A diode, in the Zener diode, the diode comprising: A cathode layer of the second conductivity type is disposed on and in contact with the first surface of the substrate, the cathode layer having a second surface opposite to the first surface of the substrate; and The anode layer of the first conductivity type extends from the second surface of the cathode layer into the cathode layer; A semi-insulating polycrystalline silicon layer is disposed on and in contact with the cathode and anode layers of the diode; and, A third layer of field oxide, which is on and in contact with the semi-insulating polysilicon layer.

15. The device of claim 14, wherein the third layer is made of undoped silicate glass.

16. The device of claim 14, wherein the third layer is made of tetraethyl orthosilicate.

17. The device of claim 14, further comprising input / output pads connected to the anode layer.

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