Self-annealing chip and self-annealing system

Abstract

The present invention discloses a self-annealing chip and a self-annealing system. The self-annealing chip includes a control module and a heating module. The control module includes a PMOS total dose radiation probe. Among them, the threshold voltage of the PMOS total dose radiation probe decreases when it is exposed to external radiation. The control module is used to receive a reference voltage, and output a first control signal to control the heating module to generate heat when the threshold voltage decreases to be less than or equal to the reference voltage; during the heating process, the threshold voltage is restored after annealing; the control module is also used to output a second control signal to control the heating module to stop generating heat when the threshold voltage is restored to be greater than the reference voltage. The self-annealing chip has good anti-total dose radiation ability, and can automatically start / stop the thermal annealing treatment function according to the drift of the threshold voltage of the PMOS total dose radiation probe, effectively ensuring the real-time performance and accuracy of the thermal annealing treatment of the self-annealing chip and the chip to be protected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a self-annealing chip and a self-annealing system. Background Art

[0002] For devices that work in a radiation environment for a long time, semiconductor devices therein will have problems such as threshold voltage drift, transconductance reduction, subthreshold current increase, low-frequency noise increase, etc. under the action of continuous ionizing radiation, and may even cause the failure of semiconductor devices. This is the total dose radiation effect. The total dose radiation effect is mainly caused by charges and defects generated by ionizing radiation in the oxide layer and at the oxide layer or silicon interface.

[0003] Existing research shows that when heat treatment, i.e., annealing treatment, is performed on a radiation-damaged semiconductor device, the trapped holes in the device oxide layer will be excited to the valence band of the oxide layer and recombine with the electrons at the Si / SiO2 interface or the silicon substrate, so that the trapped charges in the device oxide layer are continuously reduced, and finally the threshold voltage of the device can be restored to the normal value. Therefore, currently, the general method is to heat-anneal the chip to be protected to reduce the impact of the total dose radiation effect on the device.

[0004] One existing heat-annealing method is to use multiple discrete devices to build a heating system, and integrate the chip to be protected and circuits such as the heating system through a PCB board to perform heat-annealing work at the board level. However, the integration degree of this solution is low, and since the heating system needs to be evenly distributed on the PCB board, a large area is occupied; at the same time, when applying this method, the heating system needs to be adaptively arranged according to different chips to be protected, resulting in low versatility.

[0005] Another existing heat-annealing method is to integrate a heater or heating wire into the active area of the chip to be protected when manufacturing the chip to be protected. When the chip to be protected works subsequently, the heating-annealing of the chip to be protected is realized by applying an external current or voltage to the heater or heating wire through a reserved contact hole. The integration degree of this solution is relatively high, but it mainly performs annealing treatment by applying an external control source, and its annealing effect depends on the external control source, resulting in its inability to ensure the real-time, accurate and reliable annealing treatment. When the total dose radiation effect occurs and is not processed in time or not processed, it is easy to cause the entire system to fail to work properly. At the same time, the available layout area of the heater or heating wire integrated in the semiconductor substrate is limited, and the versatility is poor.

[0006] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the Invention

[0007] To solve the above technical problems, the present invention provides a self-annealing chip and a self-annealing system. The self-annealing chip can automatically start / stop the thermal annealing process according to the drift of the threshold voltage of the PMOS total dose radiation probe, effectively ensuring the real-time performance and accuracy of the thermal annealing process for the self-annealing chip and the chip to be protected, and having the characteristics of high integration, small size, and simple structure.

[0008] According to a first aspect of the present disclosure, a self-annealing chip is provided, including: a control module and a heating module. The control module includes a PMOS total dose radiation probe.

[0009] Wherein, the threshold voltage of the PMOS total dose radiation probe decreases when it is exposed to external radiation; the control module is configured to receive a reference voltage, and output a first control signal to control the heating module to generate heat when the threshold voltage decreases to not exceed the reference voltage; the threshold voltage recovers during the heating process; the control module is further configured to output a second control signal to control the heating module to stop generating heat when the threshold voltage recovers to be greater than the reference voltage.

[0010] Optionally, the control module further includes: a comparator, whose non-inverting input terminal is connected to the output terminal of the PMOS total dose radiation probe to receive the above-mentioned threshold voltage, whose inverting input terminal is used to receive the above-mentioned reference voltage, and whose output terminal is used to output one of the first control signal and the second control signal.

[0011] Optionally, the heating module includes a P-type MOSFET and a heating element, wherein:

[0012] The source electrode of the P-type MOSFET is used to receive an excitation signal, the gate electrode is used to receive a control signal, and the drain electrode is connected to one end of the heating element; the other end of the heating element is used to be connected to the reference ground;

[0013] When the excitation signal is greater than the control signal, the P-type MOSFET is turned on and generates a conduction current, and the heating element generates heat when it receives the conduction current.

[0014] Optionally, the aforementioned reference voltage is less than the threshold voltage of the PMOS total dose radiation probe in the normal state; preferably, the difference between the two ranges from 0.15V to 0.35V.

[0015] Optionally, the self-annealing chip includes a substrate and a dielectric layer and a metal interconnect layer located on the substrate. The substrate includes a field region and an active region, and the heating element is located in the dielectric layer on the field region and surrounds the active region.

[0016] Optionally, the heating element is electrically connected to the drain electrode of the P-type MOSFET via the metal interconnect layer.

[0017] Optionally, an electrical connection is achieved between the heating element and the metal interconnect layer via a plurality of first contact holes; an electrical connection is achieved between the source electrode of the P-type MOSFET and the metal interconnect layer via a plurality of second contact holes.

[0018] Optionally, the heating elements are arranged in a continuous bent pattern.

[0019] Optionally, the heating element is made of polysilicon material.

[0020] Optionally, the heating element and the gate of the P-type MOSFET are fabricated synchronously.

[0021] According to a second aspect of the present disclosure, a self-annealing system is provided, including: a chip to be protected and the self-annealing chip as described above, wherein the self-annealing chip and the chip to be protected are located within the same packaging structure, or the self-annealing chip and the chip to be protected are located within the same semiconductor structure.

[0022] The beneficial effects of the present invention are as follows:

[0023] 1. For the self-annealing chip disclosed in the present invention, its control module realizes automatic switching control of the heating or stopping of the heating module based on the different changes in the threshold voltage of the PMOS total dose radiation probe under external radiation and thermal annealing treatment, thereby realizing automatic startup or shutdown of the thermal annealing treatment function of the self-annealing chip. There is no need to set an additional control source and a manually set control program, so it effectively ensures the real-time and accuracy of the thermal annealing treatment of the self-annealing chip and the chip to be protected.

[0024] 2. The self-annealing chip disclosed in the present invention can be packaged together with the chip to be protected and even fabricated based on the same semiconductor substrate. Therefore, compared with the traditional board-level heating system, it not only has a higher integration level and smaller size, but also does not require significant changes to the layout and wiring of the original circuit when applied to different chips to be protected, and has high versatility.

[0025] 3. When fabricating the self-annealing chip disclosed in the present invention, there is no need to add complex process steps, which can greatly reduce the difficulty of design and manufacturing and lower the production cost.

[0026] 4. Compared with the method of using a board-level heating system and compared with the method of controlling heating annealing by applying an external control source, for the self-annealing chip disclosed in the present invention, the radiation intensity is detected by using a PMOS total dose radiation probe, and the working state of the heating module is timely and accurately controlled according to the change of the threshold voltage, ensuring that the self-annealing chip and the chip to be protected are maintained in a normal working state. Therefore, it has higher sensitivity and reliability.

[0027] Correspondingly, the self-annealing system disclosed in the present invention has very high reliability because the above-mentioned self-annealing chip is adopted and the self-annealing chip and the chip to be protected are located in the same radiation environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features and advantages of the present invention will become more apparent.

[0029] Figure 1 FIG. shows a schematic structural diagram of a self-annealing system provided according to an embodiment of the present disclosure;

[0030] Figure 2 FIG. shows a schematic structural diagram of a control module provided according to an embodiment of the present disclosure;

[0031] Figure 3 FIG. shows a schematic structural diagram of a heating module provided according to an embodiment of the present disclosure;

[0032] Figure 4 FIG. shows a layout diagram of a heating module provided according to an embodiment of the present disclosure;

[0033] Figure 5 FIG. shows a layout diagram of heating elements in a heating module provided according to an embodiment of the present disclosure;

[0034] Figures 6a - 6k FIG. shows Figure 4 a cross-sectional view of the heating module during the manufacturing process. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0036] Figure 1 FIG. shows a schematic structural diagram of a self-annealing system provided according to an embodiment of the present disclosure. As Figure 1 shown, the self-annealing system provided by the embodiment of the present disclosure includes a self-annealing chip 100 and a chip 200 to be protected. The self-annealing chip 100 can be used to perform annealing treatment on the chip 200 to be protected, and specifically includes a control module 110 and a heating module 120.

[0037] Figure 2 FIG. shows a schematic structural diagram of a control module provided according to an embodiment of the present disclosure. As Figure 2As shown, the control module 110 specifically includes a PMOS total dose radiation probe 111 and a comparator 112. Among them, the positive input terminal of the comparator 112 is connected to the output terminal of the PMOS total dose radiation probe 111, and the negative input terminal of the comparator 112 is used to receive a reference voltage V TH(REF) , and the output terminal of the comparator 112 is used to output a control signal V P .

[0038] When the PMOS total dose radiation probe 111 is exposed to external radiation, its threshold voltage drifts negatively, and the amplitude of the threshold voltage drift shows an almost linear monotonic correspondence with the radiation dose. Therefore, it can be used to measure the total radiation dose. By performing thermal annealing on the PMOS total dose radiation probe 111, its threshold voltage can be restored. The PMOS total dose radiation probe 111 is connected to the positive input terminal of the comparator 112, so its threshold voltage can be transmitted to the comparator 112 in real time.

[0039] Those skilled in the art should understand that in this article, the positive input terminal of the comparator 112 is connected to the output terminal of the PMOS total dose radiation probe 111 to receive the threshold voltage, which means that the threshold voltage that changes with the radiation intensity in the radiation environment can be obtained through the output of the PMOS total dose radiation probe 111. This method belongs to the well-known technology in this field and will not be elaborated here.

[0040] The comparator 112 compares the received threshold voltage with the reference voltage V TH(REF) and generates a corresponding control signal V P according to the comparison result.

[0041] Specifically, when the threshold voltage of the PMOS total dose radiation probe 111 decreases to reach or be less than the reference voltage V TH(REF) , the control module 110 outputs a first control signal, such as a low-level signal; and when the threshold voltage of the PMOS total dose radiation probe 111 recovers to be greater than the reference voltage V TH(REF) , the control module 110 outputs a second control signal, such as a high-level signal.

[0042] It can be understood that the reference voltage V TH(REF) should be less than the threshold voltage of the PMOS total dose radiation probe 111 in the normal state, and by reasonably setting the value of the reference voltage V TH(REF) , the start / stop timing of the self-annealing function of the self-annealing chip 100 can be controlled, and thus different application requirements can be met. In the specific implementation process, generally, the threshold voltage of the PMOS total dose radiation probe 111 in the normal state and the reference voltage V TH(REF)The difference range is between 0.15V and 0.35V to meet multiple requirements of sensitivity, immediacy, and reliability.

[0043] In the present disclosure, the PMOS total dose radiation probe 111 can specifically adopt a P-channel LDMOS (P-channel laterally diffused metal oxide semiconductor) based on the BCD process to facilitate the manufacture of the self-annealing chip 100 and the integration with the chip 200 to be protected.

[0044] Moreover, compared with the method of adopting a board-level heating system and compared with the method of controlling heating annealing by applying an external control source, by setting the PMOS total dose radiation probe 111 in the present disclosure, the external radiation intensity can be detected in a timely manner, and the change of the threshold voltage can be fed back to the comparator 112 in real time to accurately control the working state of the heating module 120 in a timely manner. Therefore, the detection sensitivity and reliability of the self-annealing chip 100 to external radiation are relatively high.

[0045] In the present disclosure, the heating module 120 generates heat when receiving the first control signal to perform thermal annealing on the self-annealing chip 100 and the chip 200 to be protected, and stops generating heat when receiving the second control signal, thereby stopping the thermal annealing of the self-annealing chip 100 and the chip 200 to be protected. In this way, the automatic start / stop of the thermal annealing function of the self-annealing chip 100 can be realized.

[0046] Figure 3 The structural schematic diagram of the heating module provided according to an embodiment of the present disclosure is shown. As Figure 3 shown, in this embodiment, the heating module 120 specifically includes a P-type MOSFET Q1 and a heating element 121 connected in series between the excitation signal input terminal and the reference ground in sequence. Among them, the source electrode of the P-type MOSFET Q1 is used to receive excitation signals such as voltage and current, the gate electrode is used to receive the control signal V P , the drain electrode of the P-type MOSFET Q1 is electrically connected to one end of the heating element 121, and the other end of the heating element 121 is used to be electrically connected to the reference ground. When the P-type MOSFET Q1 is turned on, a conduction current is generated, and the conduction current acts on the heating element 121 to cause the heating element 121 to generate heat, so as to perform thermal annealing on the semiconductor devices including the PMOS total dose radiation probe 111 and the P-type MOSFET Q1 in the self-annealing chip 100 and the chip 200 to be protected to suppress the influence of the total dose radiation effect. Optionally, when the source electrode of the P-type MOSFET Q1 receives a voltage signal as the excitation signal, the voltage signal can be the power supply voltage VDD or the voltage of a circuit node with a high potential in the system, and can be reasonably selected according to the actual situation.

[0047] In the present disclosure, the self-annealing chip 100 includes a substrate, and a dielectric layer and a metal interconnect layer located on the substrate. Among them, the substrate includes a field region and an active region. The active region is the region where the source and drain of each semiconductor device of the self-annealing chip 100 are fabricated and the region for forming a conductive channel, and the field region is the region outside the active region; the dielectric layer can also be referred to as a pre-metal dielectric (PMD). In the self-annealing chip 100, the heating element 121 is located in the dielectric layer of the P-type MOSFET Q1 and is connected to the drain of the P-type MOSFET Q1 via the metal interconnect layer. Compared with the prior art in which a heating wire is disposed in the substrate, in the present disclosure, the heating element 121 is disposed in the dielectric layer above the substrate and corresponding to the field region. Therefore, the settable region of the heating element 121 is not limited by the active region of the P-type MOSFET Q1, that is, the arrangement manner of the heating element 121 has higher flexibility, and the self-annealing chip 100 has higher versatility. At the same time, no matter where the heating element 121 is located in the self-annealing chip 100, it can be connected to the drain of the P-type MOSFET Q1 through the metal interconnect layer, and then receive current to generate heat when the P-type MOSFET Q1 is turned on, further ensuring the flexible arrangement of the heating element 121 in the self-annealing chip 100 and improving the versatility of the self-annealing chip 100. Specifically, it can be combined with Figure 4 and Figure 6j for understanding.

[0048] Refer to Figure 6i and Figure 6j , in the present disclosure, the metal interconnect layer in the self-annealing chip 100 corresponds to the etched metal layer 127. Specifically, it corresponds to a metal lead 127' etched from the metal layer 127 for realizing the electrical connection between the drain 124 of the P-type MOSFET Q1 and one end of the heating element 121. Based on the electrical signal transmission function of the metal interconnect layer, the settable region of the heating element 121 in the self-annealing chip 100 is expanded, making the arrangement of the heating element 121 in the field region more flexible in practical applications, which helps to improve the thermal annealing efficiency.

[0049] Figure 4 shows a layout schematic diagram of a heating module according to an embodiment of the present disclosure; Figure 5 shows a layout schematic diagram of a heating element in a heating module according to an embodiment of the present disclosure. As Figure 4 and Figure 5As shown in the figure, in this embodiment, the control module 110 and the P-type MOSFET Q1 can be fabricated on the same semiconductor substrate; the heating element 121 is located on the substrate and is arranged corresponding to the field region, surrounding the active region. Since the heating element 121 is disposed above the field region, it will not cause any shielding to the radiation sensing region of the PMOS total dose radiation probe 111 in the active region, which can improve the radiation sensing ability of the PMOS total dose radiation probe 111, and thus can improve the accuracy and reliability of the thermal annealing process for the chip 200 to be protected.

[0050] It should be noted that the semiconductor substrate can have one or more active regions. The control module 110 and the heating module 120 can share the same active region, or can be fabricated based on different active regions and separated by the field region. Specific selection can be made according to the actual situation.

[0051] When the substrate of the self-annealing chip 100 includes multiple active regions, the heating element 121 located on the field region can be disposed only around the outermost field region of the self-annealing chip 100, so as to surround multiple active regions as a whole; or can surround each active region separately, or can also surround some active regions according to actual requirements.

[0052] In this embodiment, the working principle of the self-annealing chip 100 is as follows:

[0053] Under the action of external radiation, the threshold voltage (V TH ) of the PMOS total dose radiation probe 111 of the control module 110 drifts in the negative direction (i.e., the threshold voltage V TH gradually decreases), and this drift has an accumulative effect. The PMOS total dose radiation probe 111 outputs the drifted threshold voltage V TH to the positive input terminal of the comparator 112 in real time. At the same time, the reverse input terminal of the comparator 112 receives the reference voltage. When the threshold voltage V TH is greater than the reference voltage V TH(REF) , the output terminal of the comparator 112 outputs a second control signal, such as a high-level signal, and the P-type MOSFET Q1 will not conduct; when the threshold voltage V TH is less than or equal to the reference voltage V TH(REF) , the output terminal of the comparator 112 outputs a first control signal, such as a low-level signal, to control the P-type MOSFET Q1 to conduct, thereby generating a conduction current (denoted as I R ). For example, in the normal state, the designed threshold voltage of the PMOS total dose radiation probe 111 is -1.0V, and the reference voltage V TH(REF) is -1.2V. At this time, the comparator 112 outputs a high-level control signal V P, the P-type MOSFET Q1 will not conduct. Under the action of external radiation, the threshold voltage V of the PMOS total dose radiation probe 111 TH decreases. When the threshold voltage V TH decreases to reach or even be lower than -1.2V, for example, when the threshold voltage V TH decreases to -1.3V, the comparator 112 outputs a low-level control signal V P , and the P-type MOSFET Q1 automatically conducts, generating a conduction current I R .

[0054] The conduction current I generated by the conduction of the P-type MOSFET Q1 R acts on the heating element 121, and the heating element 121 generates heat. When the heat accumulates continuously and finally reaches the annealing temperature, the self-annealing chip 100 will be in a high-temperature state, and then the PMOS total dose radiation probe 111 and the chip 200 to be protected in the self-annealing chip 100 will be thermally annealed simultaneously to suppress the influence of the total dose radiation effect on the chip 200 to be protected. Among them, the calculation formula for the annealing temperature is as follows:

[0055] Q = CM(T1 - T0)..................................(1)

[0056] Among them, Q is the calorific value, C is the specific heat capacity, M is the mass, T1 is the final temperature, and T0 is the initial temperature. After converting formula (1), it can be obtained:

[0057]

[0058] Therefore, the calorific value Q of the heating element 121 can be calculated according to the resistance R of the heating element 121 and the conduction current I R , and then the annealing temperature, that is, T1, can be obtained.

[0059] Among them, the calculation formula for the calorific value Q of the heating element 121 is as follows:

[0060]

[0061]

[0062] Among them, R is the total resistance of the heating element 121, ρ is the resistivity of the material that makes up the heating element 121, L is the length of the heating element 121, S is the cross-sectional area of the heating element 121, Q is the calorific value of the heating element 121, and I R is the current value of the conduction current flowing through the heating element 121.

[0063] Based on formula (4), it can be seen that the current value I of the conduction current can be changedR and / or changing the total resistance R of the heating element 121 to control the calorific value Q of the heating element 121. Wherein, the current value I of the conduction current R can be adjusted by changing the amplitude of the excitation signal received by the source of the P-type MOSFET Q1, which is a controllable variable and can still be externally adjusted according to actual needs after the self-annealing chip 100 is manufactured. There is no need to elaborate here. And based on formula (3), the total resistance R of the heating element 121 can be adjusted by changing at least one of the material, length L, and cross-sectional area S of the heating element 121.

[0064] In a specific embodiment of the present disclosure, referring to Figure 4 , the heating element 121 is arranged around the active area of the self-annealing chip 100, so as to increase the length L of the heating element 121 to increase the total resistance R of the heating element 121, so that the heat generated by the heating element 121 during heating is sufficient to basically cover the PMOS total dose radiation probe 111, P-type MOSFET Q1, and the chip 200 to be protected in the entire self-annealing chip 100, achieving the effect of thermal annealing, and also being able to provide the generated heat to the PMOS total dose radiation probe 111, P-type MOSFET Q1, and the chip 200 to be protected in the self-annealing chip 100 as evenly as possible, improving the efficiency and accuracy of the thermal annealing process, and further better suppressing the influence of the total dose radiation effect on the chip 200 to be protected and the self-annealing chip 100. Optionally, the heating element 121 surrounds the active area at least once, and when there are multiple active areas in the self-annealing chip 100, the heating element 121 can generally surround the multiple active areas, or separately surround the multiple active areas. Specific settings should be reasonably made according to actual needs.

[0065] It should be noted that considering the actual layout design and process limitations, the so-called "surrounding the active area at least once" in this article does not mean that the heating element 121 must be a complete closed structure. For example, the heating element 121 can only surround 4 / 5, 7 / 8, 11 / 7, etc. of the active area.

[0066] In another specific embodiment of the present disclosure, referring to Figure 5 , the heating element 121 is arranged in a continuous bending pattern. In this way, the total resistance R of the heating element 121 can be further increased by further increasing the length L of the heating element 121, so that the heating element 121 can provide more heat. At the same time, the heating element 121 with such a structure can also have better uniformity during heat transfer, so that even if the conduction current I R is small, the heating element 121 can provide sufficient heat to complete the thermal annealing process of the chip 200 to be protected and the self-annealing chip 100, so it has higher reliability. However, it can be understood thatFigure 5 The continuous bending arrangement structure (continuous right-angle bends with equal amplitude) shown in is only exemplary. The heating element 121 in the present disclosure may also be a continuously bent arrangement with a curved shape having the same or different curvatures, or even a discontinuously bent arrangement with only partial bends. Specifically, the appropriate length and arrangement of the heating element may be selected according to the actual situation, and the present disclosure does not limit this.

[0067] In a specific implementation process, considering the simplification of the manufacturing process, the heating element 121 is formed synchronously with the gate 123 of the P-type MOSFET Q1. In the present disclosure, the heating element 121 is made of the same material as the gate 123 of the P-type MOSFET Q1, for example, both are polysilicon materials.

[0068] The threshold voltage V of the PMOS total dose radiation probe 111 in the self-annealing chip 100 TH will undergo a positive drift under the action of the thermal annealing treatment (i.e., the threshold voltage V TH gradually increases). When the threshold voltage V of the PMOS total dose radiation probe 111 TH is greater than the reference voltage V received by the inverting input terminal of the comparator 112 TH(REF) , the comparator 112 will output a second control signal such as a high-level signal at its output terminal, turning off the P-type MOSFET Q1, and then interrupting the conduction current I transmitted to the heating element 121 R . The heating element 121 stops heating, and stops the thermal annealing treatment of the self-annealing chip 100 and the chip 200 to be protected.

[0069] It can be understood that in the same radiation environment, the drift amount of the threshold voltage of the PMOS total dose radiation probe 111 is the same as or substantially the same as the drift amount of the threshold voltage of the chip 200 to be protected. Thus, after the heating module 120 performs heat treatment on the PMOS total dose radiation probe 111 and the chip 200 to be protected, the two can basically return to the normal working state at the same time, thereby ensuring the accuracy and reliability of the self-annealing chip 100 when performing thermal annealing treatment on the chip 200 to be protected.

[0070] Reference Figure 4 , in the present disclosure, the source 122 of the P-type MOSFET Q1 is used to receive the excitation signal. Specifically, the external electrode corresponding to the source 122 can be formed through the fourth contact hole 129 and the metal lead etched from the metal layer, realizing the electrode lead-out of the source 122. The gate 123 of the P-type MOSFET Q1 is used to receive the reference voltage V TH(REF) , and specifically, the external electrode corresponding to the gate 123 can be formed through the third contact hole 128 and the metal lead etched from the metal layer, realizing the electrode lead-out of the gate 123.

[0071] One end of the heating element 121 is electrically connected to the metal interconnection layer, i.e., the metal lead 127', via the first contact hole 125, and the drain 124 of the P-type MOSFET Q1 is electrically connected to the metal interconnection layer via the second contact hole 126. Among them, conductive materials can be filled in both the first contact hole 125 and the second contact hole 126 to form conductive plugs. In this embodiment, both the second contact hole 126 and the fourth contact hole 129 used for leading out the source / drain electrodes are multiple, and the number of the multiple second contact holes 126 and the multiple fourth contact holes 129 is the same here. In this way, when the conduction current I R flows between the drain 124 of the P-type MOSFET Q1 and the heating element 121, the distribution can be made more uniform, which can avoid the situation that the conductive plug is burned out due to local current concentration, and improve the reliability of the electrical connection relationship between the drain 124 and the heating element 121.

[0072] The other end of the heating element 121 can be led out through multiple fifth contact holes 130 and another metal lead etched from the metal layer, so as to realize the electrical connection with the reference ground.

[0073] Next, in conjunction with Figures 6a - 6k the manufacturing method of the heating module 120 provided by the present disclosure will be described.

[0074] 1) Synchronously form the gate of the P-type MOSFET Q1 located on the active region of the substrate 101 and the heating element 121 located on the field region.

[0075] As Figure 6a shown, a silicon oxide layer 102 and a silicon nitride layer 103 are sequentially formed on the P-type substrate 101. Among them, the P-type substrate 101 can be an epitaxial wafer or a single crystal wafer, and can be specifically selected according to actual situations.

[0076] As Figure 6b shown, etch and remove the silicon nitride layer 103 corresponding to the field region, and regrow or deposit silicon oxide in this part to form a field oxide layer 104.

[0077] As Figure 6c shown, etch and remove the remaining silicon nitride layer 103 and the part of the silicon oxide layer 102 located on the active region, and then regrow a thin silicon oxide layer 106 on the surfaces of the field oxide layer 104 and the active region.

[0078] As Figure 6d shown, form a polysilicon layer 107 on the surface of the silicon oxide layer 106.

[0079] As Figure 6eAs shown, the polysilicon layer 107 is etched. Through steps such as coating with photoresist, exposure, development, and etching, the polysilicon gate 123 of the P-type MOSFET Q1 located on the active region and the heating element 121 also made of polysilicon material located on the field region are fabricated synchronously.

[0080] 2) Form the source and drain of the P-type MOSFET Q1.

[0081] As Figure 6f shown, ion implantation windows are formed in the regions corresponding to the source 122 and drain 124. P-type impurities are implanted into the active region through the ion implantation windows to form the source 122 and drain 124 of the P-type MOSFET Q1 respectively. The region between the source 122 and the drain 124 is the channel region.

[0082] 3) Form an electrical connection channel between the drain 124 of the P-type MOSFET Q1 and one end of the heating element 121, and form external electrodes corresponding to the gate 123, drain 124 of the P-type MOSFET Q1 and the other end of the heating element 121 respectively.

[0083] As Figure 6g shown, a layer of SiO2 is grown on the substrate surface to form an insulating layer 108 covering the P-type MOSFET Q1 and the heating element 121. For the convenience of subsequent fabrication of the metal interconnect layer, the insulating layer 108 can generally be planarized.

[0084] As Figure 6h shown, multiple contact holes are fabricated through steps such as coating with photoresist, exposure, development, and etching. Among them, multiple fourth contact holes 129 expose a part of the source 122 in the active region; multiple second contact holes 126 expose a part of the drain 124 in the active region; multiple third contact holes 128 expose the polysilicon part on the active region, that is, the gate 123; multiple first contact holes 125 expose the polysilicon part located on the field region, that is, the heating element 121.

[0085] As Figure 6i shown, metal is sputtered on the insulating layer 108 and in the multiple contact holes to form a metal layer 127.

[0086] As Figure 6j shown, metal leads 127′ are fabricated through steps such as coating with photoresist, exposure, development, and etching, and then the photoresist is removed by a dry and wet etching process. Among them, an external electrode corresponding to the source 122 of the P-type MOSFET Q1 can be formed through the multiple fourth contact holes 129 and the metal leads 127′, thereby realizing the reception of the excitation signal. An external electrode corresponding to the gate 123 of the P-type MOSFET Q1 can be formed through the multiple third contact holes 128 and the metal leads 127′ to realize the application of the reference voltage V TH(REF)Receiving. An electrical connection channel between one end of the heating element 121 and the drain 124 of the P-type MOSFET Q1 can be realized through a plurality of first contact holes 125, metal leads 127', and a plurality of second contact holes 126. An external electrode corresponding to the other end of the heating element 121 can be formed through a plurality of fifth contact holes 130 (refer to Figure 4 ) and metal leads 127' to realize the electrical connection between the other end of the heating element 121 and the reference ground.

[0087] As Figure 6k shown, a passivation layer 112 is formed on the insulating layer 108. Among them, the deposition of the passivation layer 112 can be carried out according to the standard processes well-known in the art, which will not be elaborated here.

[0088] It can be understood that the manufacturing process of the above heating module 120 can be simply improved on the basis of the manufacturing process of traditional PMOS devices. Specifically, on the basis of the manufacturing process of traditional MOS devices, the heating element 121 is formed while forming the polysilicon gate, and the electrical connection between one end of the heating element 121 and the drain 124 is realized during the process of electrode lead-out, and the electrical connection between the other end and the reference ground is also realized.

[0089] In addition, only the manufacturing process of the heating module 120 in the self-annealing chip 100 is described in this article. Regarding the control module 110 in the self-annealing chip 100, it can be fabricated on the substrate of the self-annealing chip 110 by using the conventional semiconductor processes described in the prior art, so it will not be elaborated too much in this article.

[0090] In summary, the present invention discloses a self-annealing chip, which can realize the automatic switching control of the heating or stopping of the heating module based on the different changes of the threshold voltage of the PMOS total dose radiation probe in the control module under the action of external radiation and thermal annealing treatment, and then realize the automatic start or shutdown of the thermal annealing treatment function of the self-annealing chip. Without setting additional control sources and manually set control programs, it can effectively ensure the real-time performance and accuracy of the thermal annealing treatment of the chip to be protected.

[0091] Moreover, in the traditional solution, the heating element is arranged in the substrate, and the available layout area of the heating element is limited. While in the present disclosure, the heating element is arranged in the dielectric layer above the substrate, which has a higher design sensitivity; in particular, the heating element is arranged directly above the field region, avoiding the shielding of the PMOS total dose radiation probe by the heating element, thus ensuring that the PMOS total dose radiation probe has a very high sensitivity.

[0092] In addition, the self-annealing chip provided in the present disclosure can be easily integrated with the chip to be protected. The two can be located within the same packaging structure or fabricated based on the same semiconductor substrate. Compared with the traditional method of integrating the chip to be protected and the heating system using a PCB board, the self-annealing chip of the present disclosure not only does not require a large area on the PCB board like a board-level heating and annealing system, but also is not restricted by the circuit layout and wiring on the PCB board during integration, thus having higher versatility.

[0093] On the other hand, the manufacturing method of the self-annealing chip disclosed in the present invention is simple and has low cost.

[0094] Finally, it should be noted that: Obviously, the above embodiments are merely examples for clearly illustrating the present invention and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.

Claims

1. A self-annealing chip, comprising: A control module and a heating module, wherein the control module includes a PMOS total dose radiation probe, wherein, when the PMOS total dose radiation probe is exposed to external radiation, its threshold voltage decreases; the control module is configured to receive a reference voltage, and when the threshold voltage decreases to no more than the reference voltage, output a first control signal to control the heating module to generate heat; during the heating process, the threshold voltage recovers; the control module is further configured to output a second control signal to control the heating module to stop generating heat when the threshold voltage recovers to be greater than the reference voltage; the heating module includes a P-type MOSFET and a heating element, the source of the P-type MOSFET is configured to receive an excitation signal, the gate is configured to receive the control signal, and the drain is connected to one end of the heating element; the other end of the heating element is configured to be connected to a reference ground; when the excitation signal is greater than the control signal, the P-type MOSFET conducts and generates a conduction current, and the heating element generates heat when receiving the conduction current.

2. The self-annealing chip according to claim 1, wherein, The control module further includes: a comparator, whose non-inverting input terminal is connected to the output terminal of the PMOS total dose radiation probe to receive the threshold voltage, its inverting input terminal is configured to receive the reference voltage, and its output terminal is configured to output one of the first control signal and the second control signal.

3. The self-annealing chip according to claim 1, wherein, The self-annealing chip includes a substrate and a dielectric layer and a metal interconnect layer located on the substrate, the substrate includes a field region and an active region, and the heating element is located in the dielectric layer on the field region and surrounds the active region.

4. The self-annealing chip according to claim 3, wherein The heating element is electrically connected to the drain of the P-type MOSFET via the metal interconnect layer.

5. The self-annealing chip according to claim 4, wherein, The heating element and the metal interconnect layer are electrically connected via a plurality of first contact holes; the source of the P-type MOSFET and the metal interconnect layer are electrically connected via a plurality of second contact holes.

6. The self-annealing chip according to claim 1, wherein, The heating element is arranged in a continuous bent pattern.

7. The self-annealing chip according to claim 1, wherein, The heating element and the gate of the P-type MOSFET are formed synchronously.

8. The self-annealing chip according to any one of claims 1-7, wherein, The reference voltage is less than the threshold voltage of the PMOS total dose radiation probe in the normal state, and the difference between the two is between 0.15V and 0.35V.

9. A self-annealing system, wherein, including a chip to be protected and the self-annealing chip according to any one of claims 1-8, wherein, the self-annealing chip and the chip to be protected are located in the same packaging structure, or the self-annealing chip and the chip to be protected are located in the same semiconductor structure. When the heating module in the self-annealing chip generates heat upon receiving the first control signal, thermal annealing treatment is simultaneously performed on the self-annealing chip and the chip to be protected, and after stopping generating heat upon receiving the second control signal, the thermal annealing treatment on the self-annealing chip and the chip to be protected is stopped.

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