Structure and preparation method of an antimonide quantum well CMOS device

Abstract

The present invention discloses a structure of an antimonide quantum well CMOS device and a preparation method thereof, belonging to the field of microelectronic technology. The device structure comprises: a substrate; a buffer layer is provided on the substrate; a p-channel antimonide quantum well layer and an n-channel antimonide quantum well layer are relatively independently provided on the buffer layer; a passivation isolation layer is provided between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer. The antimonide quantum well structure provided by the present invention can, on the one hand, reduce the dislocation density caused by lattice mismatch through component regulation, and on the other hand, effectively isolate the channel from the high-k gate medium through a barrier layer, and form a two-dimensional electron / hole gas on the channel surface, thereby improving the mobility and improving the device performance. The present invention also provides a method for preparing an antimonide quantum well CMOS device, which realizes the epitaxial growth of n-channel and p-channel materials of the same system.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology and relates to semiconductor devices, in particular to the structure of an antimonide quantum well CMOS device and a preparation method thereof. Background Art

[0002] The characteristic size of traditional Si-channel MOSFET devices is shrinking in accordance with Moore's Law, and its comprehensive performance such as speed and power consumption is approaching the physical limit. Complementary metal oxide semiconductor (CMOS) devices composed of n-MOSFET and p-MOSFET are a basic unit of integrated circuits. Therefore, in order to maintain the continuous development of microelectronics technology, researchers are considering new nanoscale structure Si-channel devices, and using non-Si materials with higher mobility as n-channel and p-channel has become an important research direction for improving the performance of CMOS devices.

[0003] The electron mobility of III-V compounds is more than ten times greater than that of Si and Ge, which has driven the development of devices towards high-frequency applications. GaAs, InGaAs and InP CMOS devices prepared by a series of methods have been continuously reported, but the hole mobility of these As-containing compound materials is not high, and they need to be combined with Ge materials with higher hole mobility to prepare CMOS devices. Due to the large differences in lattice constants, polarity and thermal expansion coefficients between Ge materials and As-containing compound materials, the difficulty of epitaxial material growth and process preparation is increased. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and propose a structure of an antimonide quantum well CMOS device and a method for preparing the same. The structure effectively isolates the channel from the high-k medium through a barrier layer, and forms a two-dimensional electron / hole gas on the channel surface, thereby improving the mobility and improving the device performance. At the same time, the present invention can realize the epitaxial growth of n-channel and p-channel materials of the same system.

[0005] The first object of the present invention is to provide a structure of an antimonide quantum well CMOS device, comprising:

[0006] substrate;

[0007] A buffer layer is provided on the substrate;

[0008] A p-channel antimonide quantum well layer and an n-channel antimonide quantum well layer are relatively independently arranged on the buffer layer;

[0009] The p-channel antimonide quantum well layer comprises:

[0010] A first lower barrier layer, a first channel layer, a first isolation layer, a first upper barrier layer, a first interface control layer and a first cap layer are stacked in sequence from bottom to top on the buffer layer; a first doping layer is also provided in the first upper barrier layer;

[0011] The n-channel antimonide quantum well layer comprises:

[0012] A second lower barrier layer, a second channel layer, a second isolation layer, a second upper barrier layer, a second interface control layer and a second cap layer are stacked in sequence from bottom to top on the buffer layer; a second doping layer is also provided in the second upper barrier layer;

[0013] A passivation isolation layer is provided between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer;

[0014] A high-K gate dielectric layer is disposed on both the first interface control layer and the second interface control layer;

[0015] The first cap layer and the second cap layer are both provided with a source electrode and a drain electrode;

[0016] Gate electrodes are disposed on the two high-K gate dielectric layers.

[0017] The second object of the present invention is to provide a method for preparing the structure of an antimonide quantum well CMOS device, comprising the following steps:

[0018] Select substrate material;

[0019] growing a buffer layer on the substrate;

[0020] Preparing a p-channel antimonide quantum well layer, an n-channel antimonide quantum well layer, and a passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer on the buffer layer;

[0021] Prepare a source electrode and a drain electrode on the first cap layer and the second cap layer respectively;

[0022] Etching the first cap layer and the second cap layer to the first interface control layer and the second interface control layer respectively, and then preparing a high-K gate dielectric layer on the first interface control layer and the second interface control layer respectively;

[0023] The gate is prepared on the two high-K gate dielectric layers, thus obtaining the preparation of the antimonide CMOS device.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] In an antimonide quantum well CMOS device provided by the present invention, both the p-channel and the n-channel adopt an antimonide quantum well structure. On the one hand, the structure can reduce the dislocation density caused by lattice mismatch through component regulation, and on the other hand, the channel is effectively isolated from the high-k gate medium through a barrier layer, forming a two-dimensional electron / hole gas on the channel surface, thereby improving the mobility and improving the device performance. The mobility achieved by this antimonide n or p-channel quantum well structure is much greater than that of the existing Si, Ge channel and GaAs system materials.

[0026] The invention provides a method for preparing an antimonide quantum well CMOS device, which realizes the epitaxial growth of n-channel and p-channel materials of the same system and avoids the complex process problem of integrating n-channel InGaAs material and p-channel Ge material in the prior art.

[0027] The present invention is based on the fact that under natural environmental conditions, the surface of antimonide materials has high activity, and the trapped charges of Sb-Sb polymers, Sb single substances, etc. will cause the Fermi level pinning effect, resulting in a very high interface state density Dit>10 12 cm -2 eV -1 , forming carrier scattering centers, making it impossible to bring into play the advantage of high mobility of antimonide materials. In the insulating gate process, the introduction of an InAs thin layer as an interface control layer avoids the formation of trapped charges such as Sb elements and reduces the interface state density.

[0028] The antimonide quantum well CMOS device provided by the present invention effectively improves the stability of the CMOS device in the application of integrated circuits by adopting antimonide quantum well structures in both the p-channel and the n-channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A schematic diagram of an antimonide quantum well CMOS device structure provided in an embodiment.

[0031] Figure 2 A schematic flow chart of a method for preparing an antimonide quantum well CMOS device structure provided in Example 1.

[0032] Figure 3 A schematic flow chart of a method for preparing an antimonide quantum well CMOS device structure provided in Example 2. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] A schematic diagram of an antimonide quantum well CMOS device structure provided by the present invention is shown in FIG. Figure 1 As shown, including:

[0035] Substrate 1;

[0036] The substrate 1 is provided with a buffer layer 2, and the thickness of the buffer layer is 1 to 3 μm;

[0037] A p-channel antimonide quantum well layer 3 and an n-channel antimonide quantum well layer 4 are relatively independently arranged on the buffer layer 2;

[0038] The p-channel antimonide quantum well layer 3 comprises:

[0039] The buffer layer 2 is stacked in layers from bottom to top.

[0040] The first lower barrier layer 31 is made of AlGaSb material and has a thickness of 50-100 nm.

[0041] The first channel layer 32 is made of InGaSb material and has a thickness of 10-20 nm.

[0042] The first isolation layer 33 is made of AlGaSb material and has a thickness of 2 to 5 nm.

[0043] The first upper barrier layer 34 is made of AlGaSb material and has a thickness of 5 to 8 nm.

[0044] The first interface control layer 35 is made of InAs material and has a thickness of 1 to 2 nm.

[0045] and a first cap layer 36, made of InSb or GaSb material, with a thickness of 5 to 20 nm;

[0046] The first upper barrier layer 34 further includes a first doping layer 341, which is made of Be material with a doping concentration of 1.0×10 18 ~1.0×10 19 cm -3 ;

[0047] The first cap layer is heavily doped with Be at a concentration of 1×10 18 ~5×1019 cm -3 ;

[0048] The n-channel antimonide quantum well layer 4 comprises:

[0049] The buffer layer 2 is stacked in layers from bottom to top.

[0050] The second lower barrier layer 41 is made of AlInSb material and has a thickness of 50-100 nm.

[0051] The second channel layer 42 is made of InAsSb material and has a thickness of 10-20 nm.

[0052] The second isolation layer 43 is made of AlInSb material and has a thickness of 2 to 5 nm.

[0053] The second upper barrier layer 44 is made of AlInSb material and has a thickness of 5 to 8 nm.

[0054] The second interface control layer 45 is made of InAs material and has a thickness of 1 to 2 nm.

[0055] and a second cap layer 46, made of InSb or GaSb material, with a thickness of 5 to 20 nm;

[0056] The second upper barrier layer 44 is further provided with a second doping layer 441, which is made of Si or Te material with a doping concentration of 1.0×10 18 ~1.0×10 19 cm -3 ;

[0057] The second cap layer is heavily doped with Si at a concentration of 1×10 18 ~5×10 19 cm -3 ;

[0058] A high-K gate dielectric layer 71 is disposed on both the first interface control layer 35 and the second interface control layer 45;

[0059] The first cap layer 36 and the second cap layer 46 are both provided with a source electrode 6 and a drain electrode 5;

[0060] Gate electrodes 7 are disposed on the two high-K gate dielectric layers.

[0061] A passivation isolation layer 8 is also provided between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer;

[0062] The high-K gate dielectric layer is made of HfO2, Al2O3 or Ta2O5 materials;

[0063] The substrate is made of Si or GaAs material.

[0064] The structure and preparation method of an antimonide quantum well CMOS device provided by the present invention are described below in conjunction with specific embodiments.

[0065] Example 1

[0066] An antimonide quantum well CMOS device structure, see Figure 1 As shown, including:

[0067] GaAs is used as substrate 1;

[0068] A buffer layer 2 is provided on the substrate 1, and the thickness of the buffer layer is 1.0 μm;

[0069] A p-channel antimonide quantum well layer 3 and an n-channel antimonide quantum well layer 4 are relatively independently arranged on the buffer layer 2;

[0070] The p-channel antimonide quantum well layer 3 comprises:

[0071] The buffer layer 2 is stacked in layers from bottom to top.

[0072] The first lower barrier layer 31 is made of AlGaSb material and has a thickness of 50 nm.

[0073] The first channel layer 32 is made of InGaSb material and has a thickness of 10 nm.

[0074] The first isolation layer 33 is made of AlGaSb material and has a thickness of 2 nm.

[0075] The first upper barrier layer 34 is made of AlGaSb material and has a thickness of 5 nm.

[0076] The first interface control layer 35 is made of InAs material and has a thickness of 2 nm.

[0077] and a first cap layer 36 made of InSb material with a thickness of 5 nm;

[0078] The first upper barrier layer 34 further includes a first doping layer 341, which is made of Be material with a doping concentration of 3.3×10 18 ;

[0079] The first cap layer is heavily doped with Be at a concentration of 2×10 19 ; The n-channel antimonide quantum well layer 4 comprises:

[0080] The buffer layer 2 is stacked in layers from bottom to top.

[0081] The second lower barrier layer 41 is made of AlInSb material and has a thickness of 50 nm.

[0082] The second channel layer 42 is made of InAsSb material and has a thickness of 10 nm.

[0083] The second isolation layer 43 is made of AlInSb material and has a thickness of 2 nm.

[0084] The second upper barrier layer 44 is made of AlInSb material and has a thickness of 5 nm.

[0085] The second interface control layer 45 is made of InAs material and has a thickness of 1 nm.

[0086] and a second cap layer 46, made of InSb material, with a thickness of 5 nm;

[0087] The second upper barrier layer 44 is further provided with a second doping layer 441, which is made of Si material with a doping concentration of 5×10 18 ;

[0088] The second cap layer is heavily doped with Si at a concentration of 3×10 19 ;

[0089] A high-K gate dielectric layer 71 is disposed on both the first interface control layer 35 and the second interface control layer 45;

[0090] The first cap layer 36 and the second cap layer 46 are both provided with a source electrode 6 and a drain electrode 5;

[0091] Gate electrodes 7 are disposed on the two high-K gate dielectric layers.

[0092] A passivation isolation layer 8 is also provided between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer;

[0093] The high-K gate dielectric layer is HfO2;

[0094] The method for preparing the above antimonide quantum well CMOS device structure is shown in Figure 2 As shown, the following steps are included:

[0095] S101 selects GaAs substrate

[0096] S102 uses Molecular Beam Epitaxy (MBE) technology to grow a 1 μm buffer layer of AlGaSb on a GaAs substrate.

[0097] S103 uses molecular beam epitaxy technology to sequentially grow a p-channel antimonide quantum well layer on the buffer layer to form a heterojunction; grow a first lower barrier layer AlGaSb on the surface of the buffer layer; grow a first channel layer InGaSb on the first lower barrier layer; grow a first isolation layer AlGaSb on the first channel layer; grow a first upper barrier layer AlGaSb on the first isolation layer; perform Be doping in the first upper barrier layer; grow a first interface control layer InAs on the first upper barrier layer, and grow a first cap layer InSb on the first upper barrier layer.

[0098] S104 uses ICP etching technology to form a trench region where an n-channel antimonide quantum well layer can grow, and the thickness of the trench region is equal to the thickness of the n-channel quantum well layer.

[0099] S105: On the buffer layer, a second lower barrier layer AlInSb is grown by molecular beam epitaxy technology; a second channel layer InAsSb is grown on the second lower barrier layer; a second isolation layer AlInSb is grown on the second channel layer; a second upper barrier layer AlInSb is grown on the second isolation layer; Si-doping is performed in the second upper barrier layer to form a second doped layer; a second interface control layer InAs is grown on the second upper barrier layer, and a second cap layer InSb is grown on the second upper barrier layer, wherein the second cap layer is heavily doped with Si.

[0100] S106 Formation of passivation isolation region between n-channel antimonide quantum well layer and p-channel antimonide quantum well layer

[0101] (a) Clean the device and then blow dry it with nitrogen;

[0102] (b) The cleaned antimonide epitaxial material is subjected to photolithography and etching to complete the mesa isolation of the epitaxial material and the isolation between the n-channel and the p-channel.

[0103] (c) A SiN passivation layer is deposited on the cleaned epitaxial material using a PECVD device, and a passivation isolation region is formed on the n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer.

[0104] S107 Preparation of Ohmic Contact:

[0105] (a) performing photolithography on the source and drain ohmic regions on the surface of the cleaned antimonide epitaxial material to prepare a photoresist mask;

[0106] (b) Soak in a 37% dilute hydrochloric acid solution for 15 seconds to remove the surface oxide layer;

[0107] (c) On the heavily doped InSb cap layer of the entire n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer, Pd / Ti / Pt / Au multilayer metals are sequentially deposited and annealed at 300-350° C. for 15-30 seconds to form an ohmic contact.

[0108] S108 Preparation of high-K gate dielectric layer:

[0109] (a) performing photolithography on a dielectric layer region on the surface of the antimonide epitaxial material to prepare a photoresist mask;

[0110] (b) Immersing in a diluted citric acid (C6H8O7:H2O2 / 1:1) solution for 60 seconds to remove the cap layer under the gate and etch to the first interface control layer InAs;

[0111] (c) Atomic layer deposition (ALD) is used to deposit HfO2 to form a high-K gate dielectric layer.

[0112] S109 preparation of gate:

[0113] Perform photolithography on the gate electrode region on the surface of the high-k dielectric layer to produce a photoresist mask;

[0114] On the high-K gate dielectric layer, metal Ti / Pt / Au is deposited by electron beam evaporation;

[0115] Immerse the device in a photoresist stripping solution to strip off the metal outside the defined pattern to complete the production of the insulating gate;

[0116] S110Pad deposition:

[0117] (a) performing photolithography on the Pad region on the surface of the antimonide epitaxial material to prepare a photoresist mask;

[0118] (b) Electron beam evaporation is used to deposit metal Ti / Au to obtain the gate and drain;

[0119] (c) Immerse the device in a photoresist remover to strip off the metal outside the defined pattern, and then rinse with deionized water.

[0120] S111 secondary passivation protection device:

[0121] (a) Clean the device and then blow dry it with nitrogen;

[0122] (b) A silicon nitride passivation layer is deposited on the cleaned device using PECVD equipment, thereby completing the preparation of the antimonide quantum well CMOS device.

[0123] Example 2

[0124] An antimonide quantum well CMOS device structure is the same as that of Embodiment 1, except that:

[0125] The method for preparing the above antimonide quantum well CMOS device structure is shown in Figure 3 As shown, the following steps are included:

[0126] S201 Select GaAs substrate

[0127] S202 uses molecular beam epitaxy technology to grow a 1μm AlGaSb buffer layer on a GaAs substrate.

[0128] S203 uses molecular beam epitaxy technology on the buffer layer to sequentially grow an n-channel antimonide quantum well layer to form a heterojunction; grow a second lower barrier layer AlInSb on the surface of the buffer layer; grow a second channel layer InAsSb on the second lower barrier layer; grow a second isolation layer AlInSb on the second channel layer; grow a second upper barrier layer AlInSb on the second isolation layer; Si-dope the second upper barrier layer to form a second doped layer; grow a second interface control layer InAs on the second upper barrier layer, and grow a second cap layer InSb on the second upper barrier layer, wherein the second cap layer is heavily doped with Si.

[0129] S204 uses ICP etching technology to form a trench region where a p-channel antimonide quantum well layer can grow, and the thickness of the trench region is equal to the thickness of the p-channel quantum well layer.

[0130] S205 uses molecular beam epitaxy technology on the buffer layer to sequentially grow a p-channel antimonide quantum well layer to form a heterojunction; grow a first lower barrier layer AlGaSb on the surface of the buffer layer; grow a first channel layer InGaSb on the first lower barrier layer; grow a first isolation layer AlGaSb on the first channel layer; grow a first upper barrier layer AlGaSb on the first isolation layer; perform Be doping in the first upper barrier layer; grow a first interface control layer InAs on the first upper barrier layer, and grow a first cap layer InSb on the first upper barrier layer.

[0131] S206 Formation of passivation isolation region between n-channel antimonide quantum well layer and p-channel antimonide quantum well layer (a) Photolithography and etching are performed on the cleaned antimonide epitaxial material to complete the mesa isolation of the epitaxial material and the isolation between the n-channel and the p-channel.

[0132] (b) A SiN passivation layer is deposited on the cleaned epitaxial material using a PECVD device, and a passivation isolation region is formed on the n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer.

[0133] S207 Preparation of Ohmic Contact:

[0134] (a) performing photolithography on the source and drain ohmic regions on the surface of the cleaned antimonide epitaxial material to prepare a photoresist mask;

[0135] (b) Soak in a 37% dilute hydrochloric acid solution for 15 seconds to remove the surface oxide layer;

[0136] (c) On the heavily doped InSb cap layer of the entire n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer, Pd / Ti / Pt / Au multilayer metals are sequentially deposited and annealed at 300-350° C. for 15-30 seconds to form an ohmic contact.

[0137] S208 Preparation of high-K gate dielectric layer:

[0138] (a) performing photolithography on a dielectric layer region on the surface of the antimonide epitaxial material to prepare a photoresist mask;

[0139] (b) Immersing in a diluted citric acid (C6H8O7:H2O2 / 1:1) solution for 60 seconds to remove the cap layer under the gate and etch to the first interface control layer InAs;

[0140] (c) Atomic layer deposition (ALD) is used to deposit HfO2 to form a high-K gate dielectric layer.

[0141] S209 preparation of gate:

[0142] Perform photolithography on the gate electrode region on the surface of the high-k dielectric layer to produce a photoresist mask;

[0143] On the high-K gate dielectric layer, metal Ti / Pt / Au is deposited by electron beam evaporation;

[0144] Immerse the device in a photoresist stripping solution to strip off the metal outside the defined pattern to complete the production of the insulating gate;

[0145] S210Pad deposition:

[0146] (a) performing photolithography on the Pad region on the surface of the antimonide epitaxial material to prepare a photoresist mask;

[0147] (b) Electron beam evaporation is used to deposit metal Ti / Au to obtain the gate and drain;

[0148] (c) Immerse the device in a photoresist remover to strip off the metal outside the defined pattern, and then rinse with deionized water.

[0149] S211 secondary passivation protection device:

[0150] (a) Clean the device and then blow dry it with nitrogen;

[0151] (b) A silicon nitride passivation layer is deposited on the cleaned device using PECVD equipment, thereby completing the preparation of the antimonide quantum well CMOS device.

[0152] Example 3

[0153] Same as Example 1, except that

[0154] The p-channel antimonide quantum well layer, the n-channel antimonide quantum well layer and the passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer on the buffer layer are prepared according to the following steps:

[0155] After the p-channel antimonide quantum well layer is prepared, the p-channel antimonide quantum well layer epitaxial material is selectively etched to the buffer layer to form a groove area where the n-channel antimonide quantum well layer can grow. The etched side of the p-channel antimonide quantum well layer is passivated by PECVD, and a passivation layer SiO2 is deposited to form a passivation isolation layer. Subsequently, the n-channel antimonide quantum well layer is grown on the buffer layer, thereby realizing the passivation isolation region between the n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer.

[0156] In an antimonide quantum well CMOS device provided by the present invention, both the p-channel and the n-channel adopt an antimonide quantum well structure. On the one hand, the structure can reduce the dislocation density caused by lattice mismatch through component regulation, and on the other hand, the channel is effectively isolated from the high-k gate medium through a barrier layer, forming a two-dimensional electron / hole gas on the channel surface, thereby improving the mobility and improving the device performance. The mobility achieved by this antimonide n or p-channel quantum well structure is much greater than that of the existing Si, Ge channel and GaAs system materials.

[0157] The invention provides a method for preparing an antimonide quantum well CMOS device, which realizes the epitaxial growth of n-channel and p-channel materials of the same system and avoids the complex process problem of integrating n-channel InGaAs material and p-channel Ge material in the prior art.

[0158] The present invention is based on the fact that under natural environmental conditions, the surface of antimonide materials has high activity, and the trapped charges of Sb-Sb polymers, Sb single substances, etc. will cause the Fermi level pinning effect, resulting in a very high interface state density Dit>10 12 cm -2 eV -1 , forming carrier scattering centers, making it impossible to bring into play the advantage of high mobility of antimonide materials. In the insulating gate process, the introduction of an InAs thin layer as an interface control layer avoids the formation of trapped charges such as Sb elements and reduces the interface state density.

[0159] The antimonide quantum well CMOS device provided by the present invention effectively improves the stability of application in integrated circuits by adopting antimonide quantum well structures in both the p-channel and the n-channel.

[0160] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0161] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A structure of an antimonide quantum well CMOS device, characterized in that: include: substrate; A buffer layer is provided on the substrate; A p-channel antimonide quantum well layer and an n-channel antimonide quantum well layer are relatively independently arranged on the buffer layer; The p-channel antimonide quantum well layer comprises: A first lower barrier layer, a first channel layer, a first isolation layer, a first upper barrier layer, a first interface control layer and a first cap layer are sequentially stacked from bottom to top on the buffer layer; a first doping layer is also provided in the first upper barrier layer; The n-channel antimonide quantum well layer comprises: A second lower barrier layer, a second channel layer, a second isolation layer, a second upper barrier layer, a second interface control layer and a second cap layer are sequentially stacked on the buffer layer from bottom to top; a second doping layer is also provided in the second upper barrier layer; A passivation isolation layer is provided between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer; A high-K gate dielectric layer is disposed on both the first interface control layer and the second interface control layer; The first cap layer and the second cap layer are both provided with a source electrode and a drain electrode; Gates are provided on both of the two high-K gate dielectric layers; The first channel layer is made of InGaSb material; The second channel layer is made of InAsSb material; The first interface control layer and the second interface control layer are both made of InAs material and have a thickness of 1 to 2 nm; The first cap layer and the second cap layer are both made of GaSb or InSb material; The structure of the antimonide quantum well CMOS device is prepared by the following steps: Select substrate material; growing a buffer layer on the substrate; Preparing a p-channel antimonide quantum well layer, an n-channel antimonide quantum well layer, and a passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer on the buffer layer; Prepare a source electrode and a drain electrode on the first cap layer and the second cap layer respectively; Etching the first cap layer and the second cap layer to the first interface control layer and the second interface control layer respectively, and then preparing a high-K gate dielectric layer on the first interface control layer and the second interface control layer respectively; A gate is prepared on the two high-K gate dielectric layers, thereby preparing an antimonide CMOS device; The first lower barrier layer is made of AlGaSb material, the first isolation layer is made of AlGaSb material, the first upper barrier layer is made of AlGaSb material, and the first doping layer is made of Be material; The second lower barrier layer is made of AlInSb material, the second isolation layer is made of AlInSb material, the second upper barrier layer is made of AlInSb material, and the second doping layer is made of Si or Te material.

2. The structure of the antimonide quantum well CMOS device according to claim 1, characterized in that: The substrate is made of Si or GaAs material; the passivation isolation layer is made of SiO2 or SiNx material.

3. A method for preparing the structure of the antimonide quantum well CMOS device according to any one of claims 1 to 2, characterized in that: The following steps are involved: Select substrate material; growing a buffer layer on the substrate; Preparing a p-channel antimonide quantum well layer, an n-channel antimonide quantum well layer, and a passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer on the buffer layer; Prepare a source electrode and a drain electrode on the first cap layer and the second cap layer respectively; Etching the first cap layer and the second cap layer to the first interface control layer and the second interface control layer respectively, and then preparing a high-K gate dielectric layer on the first interface control layer and the second interface control layer respectively; The gate is prepared on the two high-K gate dielectric layers, thus obtaining the preparation of the antimonide CMOS device.

4. The method for preparing the structure of the antimonide quantum well CMOS device according to claim 3, characterized in that: The p-channel antimonide quantum well layer, the n-channel antimonide quantum well layer, and the passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are prepared on the buffer layer according to the following steps: Growing a first lower barrier layer, a first channel layer, a first isolation layer, a first upper barrier layer, a first interface control layer and a first cap layer in sequence on the buffer layer to form a p-channel antimonide quantum well layer; Etching the p-channel antimonide quantum well layer in a selected area to the buffer layer to form a groove area for growing the n-channel antimonide quantum well layer; Growing a second lower barrier layer, a second channel layer, a second isolation layer, a second upper barrier layer, a second interface control layer and a second cap layer in sequence on the buffer layer to form an n-channel antimonide quantum well layer; The p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are etched to the buffer layer, and then passivated to form a passivation isolation layer.

5. The method for preparing the structure of the antimonide quantum well CMOS device according to claim 3, characterized in that: The p-channel antimonide quantum well layer, the n-channel antimonide quantum well layer, and the passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are prepared on the buffer layer according to the following steps: Growing a second lower barrier layer, a second channel layer, a second isolation layer, a second upper barrier layer, a second interface control layer and a second cap layer in sequence on the buffer layer to form an n-channel antimonide quantum well layer; Etching the n-channel antimonide quantum well layer in a selected area to the buffer layer to form a groove area for growing the p-channel antimonide quantum well layer; A first lower barrier layer, a first channel layer, a first isolation layer, a first upper barrier layer, a first interface control layer and a first cap layer are sequentially grown on the buffer layer to form a p-channel antimonide quantum well layer; The n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer are etched to the buffer layer, and then passivated to form a passivation isolation layer.

6. The method for preparing the structure of the antimonide quantum well CMOS device according to claim 3, characterized in that: The p-channel antimonide quantum well layer, the n-channel antimonide quantum well layer, and the passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are prepared on the buffer layer according to the following steps: Growing a first lower barrier layer, a first channel layer, a first isolation layer, a first upper barrier layer, a first interface control layer and a first cap layer in sequence on the buffer layer to form a p-channel antimonide quantum well layer; Etching the p-channel antimonide quantum well layer in a selected area to the buffer layer to form a groove area for growing the n-channel antimonide quantum well layer; Then, passivation is performed on the etched side of the p-channel antimonide quantum well layer to form a passivation isolation layer; A second lower barrier layer, a second channel layer, a second isolation layer, a second upper barrier layer, a second interface control layer and a second cap layer are sequentially grown on the buffer layer to form an n-channel antimonide quantum well layer.

7. The method for preparing the structure of an antimonide quantum well CMOS device according to any one of claims 4 to 6, characterized in that: The p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are prepared on the buffer layer respectively by using molecular beam epitaxy technology.

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