Semiconductor device

Abstract

A semiconductor device includes an active pattern located on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure located on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source / drain layer located on a portion of the active pattern adjacent to the gate structure in the first direction, the source / drain layer contacting the channels; an internal spacer located between the gate structure and the source / drain layer, the internal spacer contacting the source / drain layer; and a channel connection portion located between each of the internal spacers and the gate structure, the channel connection portion connecting the channels to each other.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0004680 entitled "Semiconductor Devices", filed on January 14, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The examples involve semiconductor devices. Background Technology

[0004] When forming a multi-bridge channel field-effect transistor (MBCFET) comprising multiple channels spaced apart from each other in a vertical direction (each channel extending horizontally through the gate structure), a source / drain layer that commonly contacts the channels can be formed, and an internal spacer can be formed between the gate structure and the source / drain layer to electrically insulate the gate structure from the source / drain layer. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor device comprising: an active pattern located on a substrate and extending longitudinally in a first direction parallel to an upper surface of the substrate; a gate structure located on the active pattern and extending longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each channel extending longitudinally through the gate structure along the first direction; a source / drain layer located on a portion of the active pattern adjacent to the gate structure in the first direction, the source / drain layer contacting the channel; internal spacers located between the gate structure and the source / drain layer, the internal spacers contacting the source / drain layer; and channel connection portions located between each of the internal spacers and the gate structure, the channel connection portions connecting the channels to each other.

[0006] An embodiment can be implemented by providing a semiconductor device comprising: an active pattern located on a substrate, the active pattern extending longitudinally in a first direction parallel to an upper surface of the substrate; a gate structure located on the active pattern, the gate structure extending longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each channel extending longitudinally through the gate structure along the first direction; and a source / drain layer located on the active pattern. In the first direction, on a portion adjacent to the gate structure, the source / drain layer contacts the channel; and a channel connection portion and an internal spacer are sequentially stacked between the gate structure and the source / drain layer along the first direction, the channel connection portion comprising a semiconductor material, and the internal spacer comprising silicon nitride, wherein the gate structure comprises an interface pattern, a gate insulating pattern, and a gate electrode sequentially stacked from the channel connection portion along the first direction, the interface pattern comprising silicon oxide, the gate insulating pattern comprising a metal oxide, and the gate electrode comprising a metal.

[0007] An embodiment can be implemented by providing a semiconductor device comprising: an active pattern located on a substrate, the active pattern extending longitudinally in a first direction parallel to an upper surface of the substrate; channels located on the active pattern, the channels being spaced apart from each other along a third direction perpendicular to the upper surface of the substrate; a gate structure extending longitudinally on the active pattern in a second direction parallel to the upper surface of the substrate and intersecting the first direction, the gate structure at least partially covering each of the channels; source / drain layers located on the active pattern at respective opposite sides of the gate structure in the first direction, each of the source / drain layers contacting the channel; and internal spacers located respectively on the active pattern and the lowermost channel. The gate structure comprises, between and between the channels, internal spacers contacting the source / drain layers; gate spacers covering opposing sidewalls of the uppermost channel portion of the gate structure; and channel connection portions located between the gate structure and corresponding internal spacers, the channel connection portions connecting the active pattern and the lowermost channel and connecting the channels to each other, and the channel connection portions covering the inner sidewalls, upper surfaces, and lower surfaces of the corresponding internal spacers, wherein the gate structure includes an interface pattern, a gate insulating pattern, and a gate electrode sequentially stacked from the surface of each channel, the upper surface of the active pattern, and the inner sidewall of the channel connection portion, the interface pattern comprising silicon oxide, the gate insulating pattern comprising metal oxide, and the gate electrode comprising metal. Attached Figure Description

[0008] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figures 1 to 4 This shows a top view and a cross-sectional view of a semiconductor device according to an example embodiment.

[0010] Figures 5 to 24 These are top views and cross-sectional views of various stages in a method for manufacturing a semiconductor device according to an example embodiment.

[0011] Figures 25 to 27 These are cross-sectional views of various stages in a method for manufacturing a semiconductor device according to an example embodiment.

[0012] Figure 28 and Figure 29 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0013] Figure 30 and Figure 31 This is a cross-sectional view of a semiconductor device according to an example embodiment. Detailed Implementation

[0014] In the following text, two directions that are substantially parallel to the upper surface of the substrate and intersect each other may be referred to as the first direction and the second direction, respectively, and a direction that is substantially perpendicular to the upper surface of the substrate may be referred to as the third direction. In the example embodiment, the first direction and the second direction may be substantially perpendicular to each other.

[0015] Figures 1 to 4 This shows a top view and a cross-sectional view of a semiconductor device according to an example embodiment. Figure 1 It is a top view, and Figure 2 It is along Figure 1 The cross-sectional view taken by line A-A' in the diagram. Figure 3 It is along Figure 1 The cross-sectional view taken by line B-B' in the diagram, and Figure 4 yes Figure 3 An enlarged cross-sectional view of region X.

[0016] Reference Figures 1 to 4 The semiconductor device may include an active pattern 105, a gate structure 300, a semiconductor pattern 126, a channel connection portion 127, and a source / drain layer 230 located on a substrate 100. The semiconductor device may also include a gate spacer 185, an internal spacer 220, an isolation pattern 130, and an insulating layer 240.

[0017] The substrate 100 may include semiconductor materials such as silicon, germanium, or silicon-germanium, or III-V compounds such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs).

[0018] The active pattern 105 may protrude from the substrate 100 in a third direction and may extend in a first direction (e.g., longitudinally). In one embodiment, as shown, the device may include two active patterns 105. In one embodiment, more than two active patterns 105 may be spaced apart from each other in a second direction. The active pattern 105 may be formed by partially removing the upper portion of the substrate 100 and may comprise a material substantially the same as that of the substrate 100.

[0019] The sidewalls of the active pattern 105 facing the second direction may be covered by the isolation pattern 130. The isolation pattern 130 may include, for example, an oxide, such as silicon oxide.

[0020] In one embodiment, a plurality of semiconductor patterns 126 may be formed from the upper surface of the active pattern 105 at multiple levels, thereby being spaced apart from each other in a third-order upward direction. In one embodiment, as shown, the semiconductor patterns 126 may be located at three levels respectively.

[0021] In one embodiment, as shown, only two semiconductor patterns 126 spaced apart from each other in a first direction may be present on the active pattern 105 at each level and extend longitudinally in the first direction. In another embodiment, more than two semiconductor patterns 126 may be formed on the active pattern 105 to be spaced apart from each other in each level along the first direction.

[0022] In one embodiment, the semiconductor pattern 126 may include a first semiconductor pattern 126a at the top level (e.g., at the far end of the substrate 100 in the third-order direction), a third semiconductor pattern 126c at the bottom level (e.g., at the near end of the substrate 100 in the third-order direction), and a second semiconductor pattern 126b located between them.

[0023] In one embodiment, the semiconductor pattern 126 may be a nanosheet or nanowire comprising a semiconductor material such as silicon or germanium. In one embodiment, the semiconductor pattern 126 may be used as a channel for a transistor, and may be referred to as a channel.

[0024] The channel connection portion 127 may be located between the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c, and between the active pattern 105 and the third semiconductor pattern 126c, so that the first semiconductor pattern 126a, the second semiconductor pattern 126b, the third semiconductor pattern 126c, and the active pattern 105 can be interconnected with each other in the third direction.

[0025] The channel connection portion 127 may include a material substantially the same as the first semiconductor pattern 126a, the second semiconductor pattern 126b and the third semiconductor pattern 126c, such as monocrystalline silicon.

[0026] In one embodiment, the cross-section of the channel connection portion 127 in the first direction may have a C or inverted C shape. In one embodiment, the cross-section of the channel connection portion 127 in the first direction may have a ring shape in which a portion of it is cut off in the first direction.

[0027] A gate structure 300 may be formed on a substrate 100 and may surround the central portion of a semiconductor pattern 126 in a first direction. In one embodiment, as shown, the gate structure 300 may be formed on two active patterns 105 to cover the respective semiconductor patterns 126 thereon. In one embodiment, the gate structure 300 may extend along a second direction (e.g., longitudinally) on a substrate 100 on which an isolation pattern 130 is formed, and may be formed on more than two active patterns 105 spaced apart from each other along the second direction to cover the respective semiconductor patterns 126 thereon, or may be formed on only one active pattern 105 to cover the semiconductor pattern 126 thereon.

[0028] In one embodiment, as shown, the substrate 100 may have two gate structures 300. In another embodiment, more than two gate structures 300 may be formed on the substrate 100 and spaced apart from each other in a first direction.

[0029] The gate structure 300 may include an interface pattern 260, a gate insulating pattern 270, a work function control pattern 280, and a gate electrode 290, which are sequentially stacked from the surface of the semiconductor pattern 126, the inner sidewall of the channel connection portion 127, and / or the upper surface of the active pattern 105.

[0030] Interface pattern 260 can be located on the upper surface of active pattern 105, the upper and lower surfaces of semiconductor pattern 126, and the inner wall of channel connection portion 127. Gate insulating pattern 270 can be formed on interface pattern 260. Work function control pattern 280 can be formed on gate insulating pattern 270. Gate electrode 290 can fill the space between active pattern 105 and third semiconductor pattern 126c, the space between second semiconductor pattern 126b and third semiconductor pattern 126c, and the space between first semiconductor pattern 126a and second semiconductor pattern 126b.

[0031] In one embodiment, the interface pattern 260 may cover the entire surface of the gate insulating pattern 270 and the upper and lower surfaces of the semiconductor pattern 126, and the inner wall of the channel connection portion 127 may be spaced apart from the gate insulating pattern 270 so as not to contact the gate insulating pattern 270.

[0032] Interface pattern 260 may include, for example, oxides, such as silicon oxide. Gate insulating pattern 270 may include, for example, metal oxides having a high dielectric constant, such as hafnium oxide, tantalum oxide, zirconium oxide, etc. Work function control pattern 280 may include, for example, titanium nitride, tantalum nitride, tungsten nitride, aluminum oxide, etc. Gate electrode 290 may include, for example, metals (such as titanium and aluminum), metal alloys, or nitrides or carbides of metals.

[0033] The gate structure 300 can be electrically insulated from the source / drain layer 230 through the gate spacer 185, the internal spacer 220 and the channel connection portion 127.

[0034] In one embodiment, the channel connection portion 127 may have a convex shape that closes toward the center of the gate structure 300 along a first direction.

[0035] The gate spacer 185 may cover the opposite sidewalls of the gate structure 300 in the first direction and may include, for example, nitrides, such as silicon oxynitride.

[0036] Internal spacers 220 may be formed on the sidewalls of the channel connection portion 127 between semiconductor patterns 126 spaced apart from each other in a third direction, and may cover each opposite sidewall of the lower portion of the gate structure 300 in a first direction. The internal spacers 220 may be spaced apart from the gate structure 300 along the first direction through the channel connection portion 127, and the internal spacers 220 and the gate structure 300 may not be in contact with each other.

[0037] In one embodiment, the cross-section of the internal spacer 220 in the first direction may have a horseshoe shape, a crescent shape, or a recessed semi-circular shape on its sidewalls. In another embodiment, the cross-section of the internal spacer 220 in the first direction may have a rectangular shape with one sidewall recessed and the other sidewall rounded.

[0038] The internal spacers 220 may include, for example, nitrides, such as silicon nitride, silicon carbonitride, silicon boron nitride, or silicon carbonitride oxide. In one embodiment, the thickness of each internal spacer 220 in the third direction may gradually increase toward the source / drain layer 230 in the first direction. In another embodiment, the thickness of each internal spacer 220 in the third direction may gradually increase to a maximum thickness and then gradually decrease toward the source / drain layer 230 in the first direction, for example, as shown in the figure. Figure 28 As shown.

[0039] In one embodiment, the semiconductor pattern 126 (e.g., each of the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c) may have a first thickness T1 in the third direction, the portion of the gate structure 300 located between or between the active pattern 105 and the semiconductor pattern 126 may have a second thickness T2 in the third direction, and the internal spacer 220 may have a third thickness T3 in the third direction. The third thickness T3 may be less than the second thickness T2. In one embodiment, as shown, the first thickness T1 may be less than both the second thickness T2 and the third thickness T3. In one embodiment, the first thickness T1 may be greater than either the second thickness T2 or the third thickness T3, or it may be less than the second thickness T2 but greater than the third thickness T3. The first thickness T1 may be equal to either the second thickness T2 or the third thickness T3.

[0040] In one embodiment, the sidewalls of the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c in the first direction, the sidewalls of the channel connection portion 127 connected to the upper and / or lower portions of the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c in the first direction, and the outer sidewalls of the internal spacer 220 located between the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c in the first direction together can form an uneven surface.

[0041] The source / drain layer 230 may extend on the active pattern 105 in a third direction (e.g., upward) and may publicly contact the sidewalls of the semiconductor patterns 126, which are located at multiple levels, in a first direction, thereby connecting to them.

[0042] In one embodiment, the source / drain layer 230 may contact the semiconductor pattern 126 and the internal spacer 220 located therebetween. Corresponding to the uneven surfaces of the sidewalls of the first semiconductor pattern 126a, the second semiconductor pattern 126b, the third semiconductor pattern 126c, the channel connection portion 127, and the internal spacer 220, the sidewalls of the source / drain layer 230 may have uneven surfaces.

[0043] In one embodiment, the portion of the sidewall of the source / drain layer 230 that contacts each of the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c may be concave in a first direction, and the portion of its sidewall that contacts each internal spacer 220 may be convex in the first direction.

[0044] In one embodiment, the source / drain layer 230 may comprise single-crystal silicon carbide doped with n-type impurities or single-crystal silicon doped with n-type impurities, and therefore can be used as the source / drain of an NMOS transistor. In another embodiment, the source / drain layer 230 may comprise single-crystal silicon germanium doped with p-type impurities, and therefore can be used as the source / drain of a PMOS transistor.

[0045] In one embodiment, the source / drain layer 230 may include n-type or p-type impurities, and the gate structure 300, the source / drain layer 230, and each semiconductor pattern 126 serving as a channel may form an NMOS transistor or a PMOS transistor. The semiconductor patterns 126 may be formed in multiple layers along a third direction, thus the semiconductor device may be an MBCFET.

[0046] The insulating layer 240 may surround the sidewalls of the gate spacer 185 and may cover the source / drain layer 230. The insulating layer 240 may include, for example, an oxide, such as silicon oxide.

[0047] The semiconductor device may also include contact plugs, wiring, etc., that can be electrically connected to the source / drain layer 230 and / or the gate structure 300.

[0048] As described above, the internal spacer 220 may have a third thickness T3 that is less than the second thickness T2, where the second thickness T2 is the thickness of the portion of the gate structure 300 located between the semiconductor patterns 126 or between the active pattern 105 and the lowermost semiconductor pattern 126.

[0049] In the formation of subsequent references Figure 19 Before the second spacer layer 210 is shown, the space between the semiconductor patterns 126 can be partially filled with the channel connection portion 127. Therefore, even if the second spacer layer 210 is formed in a relatively small amount, it can completely fill the space. The second spacer layer 210 can be formed in a relatively small amount, and therefore can be easily removed. Thus, when the second spacer layer 210 is removed, no residue remains on the upper surface of the active pattern 105, and the source / drain layer 230 can be effectively formed on the upper surface of the active pattern 105. Therefore, the electrical characteristics of the semiconductor device can be improved.

[0050] Figures 5 to 24 These are top views and cross-sectional views of various stages in a method for manufacturing a semiconductor device according to an example embodiment. Specifically, Figure 5 , Figure 7 , Figure 9 , Figure 12 and Figure 22 It is a top view. Figure 6 , Figure 8 , Figures 10 to 11 , Figures 13 to 21 and Figures 23 to 24 It is a cross-sectional view.

[0051] Figure 6 , Figure 8 and Figure 10 These are cross-sectional views taken along line A-A' in the corresponding top view. Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figures 19 to 20 and Figure 23 These are cross-sectional views taken along line B-B' in the corresponding top view. Figure 14 , Figure 16 , Figure 18 and Figure 21 These are enlarged cross-sectional views of region X of the corresponding cross-sectional view.

[0052] Reference Figure 5 and Figure 6 The sacrificial layer 110 and the semiconductor layer 120 can be stacked alternately and repeatedly on the substrate 100.

[0053] In one implementation, such as Figure 6 As shown, the sacrificial layer 110 and the semiconductor layer 120 can be formed on the substrate 100 in three layers, respectively.

[0054] In one embodiment, the sacrificial layer 110 may include a material (e.g., silicon-germanium) that has etch selectivity relative to the substrate 100 and the semiconductor layer 120.

[0055] In one embodiment, the sacrificial layer 110 can be formed by performing an epitaxial growth process using, for example, a silicon source gas (such as dichlorosilane (SiH2Cl2) gas) and a germanium source gas (such as germanane (GeH4) gas), thus forming a single-crystal silicon-germanium (SiGe) layer. In another embodiment, the semiconductor layer 120 can be formed by performing an epitaxial growth process using, for example, a silicon source gas (such as disilane (Si2H6) gas), thus forming a single-crystal silicon layer.

[0056] Reference Figure 7 and Figure 8 An etching mask extending in a first direction can be formed on the uppermost semiconductor layer 120 (e.g., located at the far end of the substrate 100 in a third-direction orientation), and the etching mask can be used to etch the semiconductor layer 120, the sacrificial layer 110, and the upper part of the substrate 100.

[0057] Therefore, an active pattern 105 extending in a first direction can be formed on the substrate 100, and a fin structure including sacrificial lines 112 and semiconductor lines 122 alternately and repeatedly stacked on the active pattern 105 can be formed. In one embodiment, a plurality of fin structures can be formed on the substrate 100 to be spaced apart from each other in a second direction.

[0058] An isolation pattern 130 covering the sidewalls of the active pattern 105 can be formed on the substrate 100.

[0059] Reference Figures 9 to 11 A dummy gate structure 175 can be formed on the substrate 100 to partially cover the fin structure and the isolation pattern 130.

[0060] In one embodiment, a dummy gate insulating layer, a dummy gate electrode layer, and a dummy gate mask layer may be sequentially formed on a substrate 100 on which a fin structure and an isolation pattern 130 are formed. An etch mask extending in a second direction may be formed on the dummy gate mask layer, and the dummy gate mask layer may be etched using the etch mask to form a dummy gate mask 165 on the substrate 100.

[0061] The dummy gate insulating layer may include, for example, an oxide, such as silicon oxide. The dummy gate electrode layer may include, for example, polysilicon. The dummy gate mask layer may include, for example, a nitride, such as silicon nitride.

[0062] The dummy gate mask 165 can be used as an etching mask to etch the dummy gate electrode layer and the dummy gate insulating layer, thereby forming the dummy gate electrode 155 and the dummy gate insulating pattern 145 on the substrate 100, respectively.

[0063] The dummy gate structure 175 may include a dummy gate insulating pattern 145, a dummy gate electrode 155, and a dummy gate mask 165 sequentially stacked on a portion of the active pattern 105 and the adjacent isolation pattern 130. In one embodiment, the dummy gate structure 175 may extend along a second direction on the fin structure and the isolation pattern 130, and may cover the upper surface of the fin structure and the opposite sidewalls in the second direction.

[0064] Reference Figures 12 to 14 Gate spacers 185 can be formed on the sidewall of the dummy gate structure 175.

[0065] In one embodiment, after a first spacer layer is formed on a substrate 100 on which a fin structure, an isolation pattern 130 and a dummy gate structure 175 are formed, the first spacer layer can be anisotropically etched to form gate spacers 185 covering each opposite sidewall of the dummy gate structure 175 in a first direction.

[0066] The dummy gate structure 175 and gate spacer 185 can be used as an etching mask to etch the exposed portion of the fin structure, thereby forming an active pattern 105 of the exposed substrate 100 and a first opening 190 of a portion of the isolation pattern 130 adjacent thereto in the second direction.

[0067] In one embodiment, the sacrificial line 112 and semiconductor line 122 located below the dummy gate structure 175 and the gate spacer 185 can be patterned into a sacrificial pattern 114 and a preliminary semiconductor pattern 124, respectively, and the fin structure extending along the first direction can be divided into a plurality of pieces spaced apart from each other along the first direction.

[0068] In the following text, for ease of explanation, the dummy gate structure 175, the gate spacers 185 located on each of its opposite sidewalls, and the fin structure located below the dummy gate structure 175 and the gate spacers 185 may be referred to as the first structure. In one embodiment, the first structure may extend along a second direction, and a plurality of first structures may be spaced apart from each other along a first direction.

[0069] Reference Figure 15 and Figure 16 The sacrificial pattern 114 exposed by the first opening 190 can be etched on each of the opposite sidewalls in the first direction to form the first recess 200.

[0070] In one embodiment, the first recess 200 can be formed by performing a wet etching process on the sacrificial pattern 114. In one embodiment, the first recess 200 may have a convex shape that protrudes inward toward the center of the sacrificial pattern 114 along a first direction. In one embodiment, the cross-section of the first recess 200 in the first direction may have a semi-circular shape.

[0071] In one embodiment, the end of the initial semiconductor pattern 124 adjacent to the first recess 200 (in the first direction) can be a rectangular shape with rounded corners. The portion of the active pattern 105 located below the lowermost sacrificial pattern 114 can be a trapezoidal shape with rounded corners.

[0072] In one embodiment, the initial semiconductor pattern 124 may have a first thickness T1 (e.g., in the third direction), the sacrificial pattern 114 may have a second thickness T2, and the maximum thickness of the first recess 200 may be substantially equal to the second thickness T2 of the sacrificial pattern 114. In one embodiment, the first thickness T1 may be less than the second thickness T2.

[0073] Reference Figure 17 and Figure 18The surface of a layer including silicon can be used as a seed crystal, for example, the surface of the preliminary semiconductor pattern 124 exposed by the first opening 190 and the first recess 200, the surface of the sacrificial pattern 114 and the upper surface of the active pattern 105 can be used as a seed crystal to perform a first selective epitaxial growth (SEG) process.

[0074] In one embodiment, the width of the preliminary semiconductor pattern 124 in the first direction may be increased, and the thickness of its edge portion in the third direction may also be increased. The preliminary semiconductor pattern 124 with the increased width may be a semiconductor pattern 126.

[0075] In one embodiment, the semiconductor pattern 126 may include a first semiconductor pattern 126a at the top level (e.g., at the far end of the substrate 100 in the third-order direction), a third semiconductor pattern 126c at the bottom level (e.g., at the near end of the substrate 100 in the third-order direction), and a second semiconductor pattern 126b located between them, and in a top view, the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c may protrude from the gate spacer 185 in a first direction (e.g., outward beyond the gate spacer 185).

[0076] The sacrificial pattern 114 may include silicon germanium, and therefore, the silicon included in the sacrificial pattern 114 may also be used as a seed in the first SEG process. In one embodiment, a channel connection portion 127 may be formed to cover each opposite sidewall of each sacrificial pattern 114.

[0077] In the following text, the portion of semiconductor pattern 126 grown from preliminary semiconductor pattern 124 in a first direction by the first SEG process can be considered as part of semiconductor pattern 126. In one embodiment, the portion of semiconductor pattern 126 grown from preliminary semiconductor pattern 124 in a third direction by the first SEG process can be considered as channel connection portion 127.

[0078] In one embodiment, a plurality of channel connection portions 127 may be formed along a third direction between adjacent semiconductor patterns in the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c, and may connect the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c to each other. In one embodiment, the channel connection portions 127 may also be formed between the third semiconductor pattern 126c and the active pattern 105, and may connect the third semiconductor pattern 126c to the active pattern 105. The first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c, as well as the channel connection portions 127 located therebetween, may all comprise monocrystalline silicon.

[0079] In one embodiment, the channel connection portion 127 may have a convex shape projecting inward toward the center of each sacrificial pattern 114 along a first direction. In one embodiment, the cross-section of the channel connection portion 127 in the first direction may have a C or inverted C shape. In one embodiment, the cross-section of the channel connection portion 127 in the first direction may have the shape of a ring in which a portion of it is cut off in the first direction.

[0080] Because the first SEG process is performed, the channel connection portion 127 can be formed at the upper and lower portions of the first recess 200, respectively. Therefore, the maximum thickness of the first recess 200 in the third direction can be reduced, and the first recess 200 can subsequently become the second recess 205.

[0081] In one embodiment, the thickness of the semiconductor pattern 126 after the first SEG process can be substantially the same as the thickness of the semiconductor pattern 126 before the first SEG process (e.g., a first thickness T1), and the thickness of the sacrificial pattern 114 after the first SEG process can also be substantially the same as the thickness of the sacrificial pattern 114 before the first SEG process (e.g., a second thickness T2). In one embodiment, the thickness of the second recess 205 can be less than the thickness of the sacrificial pattern 114 (e.g., a third thickness T3). In one embodiment, the third thickness T3 of the second recess 205 can be the distance between the uppermost surface facing upward and the uppermost surface facing downward of the channel connection portion 127.

[0082] The first SEG process can also be performed on the upper surface of the active pattern 105 through the first opening 190, so the thickness of the active pattern 105 can be increased.

[0083] Reference Figures 19 to 21 The second spacer layer 210 can be formed on the dummy gate structure 175, gate spacer 185, fin structure, active pattern 105 and isolation pattern 130, and the second spacer layer 210 can be anisotropically etched to form an internal spacer 220 that at least partially fills the second recess 205.

[0084] Internal spacers 220 may be formed on the sidewalls of the sacrificial pattern 114 between the third-order adjacent semiconductor patterns in the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c. In one embodiment, the internal spacers 220 may be spaced apart from the sacrificial pattern 114 by the channel connection portion 127, thereby not contacting the sacrificial pattern 114 (e.g., due to the presence of the channel connection portion 127).

[0085] In one embodiment, a plurality of internal spacers 220 may be formed along a third direction (e.g., a plurality of internal spacers 220 are formed at intervals), and the maximum thickness of each internal spacer 220 may be substantially equal to the thickness of the second recess 205, for example, thickness T3.

[0086] In one embodiment, the inner sidewall of the inner spacer 220 that contacts the sacrificial pattern 114 may have a convex shape that protrudes inward toward the center of the sacrificial pattern 114 along a first direction, and the outer sidewall of the inner spacer 220 that is exposed by or to the first opening 190 may have a concave shape that opens along or toward the first direction. In one embodiment, the cross-section of the inner spacer 220 in the first direction may have a semi-circular shape.

[0087] In one embodiment, the sidewalls of the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c in the first direction, the sidewalls of the channel connection portion 127 that connect with the upper and / or lower portions of the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c in the first direction, and the outer sidewalls of the internal spacer 220 located between the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c in the first direction can together form an uneven surface. The sidewalls of the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c may protrude in the first direction, and the outer sidewalls of the internal spacer 220 may be recessed in the first direction.

[0088] In one embodiment, in a top view, the outer wall of the inner spacer 220 may protrude from or beyond the sidewall of the gate spacer 185 in a first direction. In another embodiment, in a top view, the sidewall of the gate spacer 185 may protrude from or beyond the outer wall of the inner spacer 220 in a first direction.

[0089] Reference Figure 22 and Figure 23 A second selective epitaxial growth (SEG) process can be performed using the sidewalls of the semiconductor pattern 126 exposed by the first opening 190 and the upper surface of the active pattern 105 as seed crystals, thereby forming a source / drain layer 230 on the sidewalls of the semiconductor pattern 126. The source / drain layer 230 can fill the first opening 190 on the active pattern 105 and further grow in a third-order upward direction to contact the lower sidewall of the gate spacer 185.

[0090] During the second SEG process, the channel connection portion 127 and the internal spacer 220 are sequentially stacked on the sidewalls of the sacrificial pattern 114, thus the sacrificial pattern 114 may not be used as a seed. In one embodiment, the portion of the channel connection portion 127 directly above and below the semiconductor pattern 126 may be exposed by the first opening 190, and thus can be used as a seed for the second SEG process. In one embodiment, the sacrificial pattern 114 may not contact the source / drain layer 230 due to the presence of the channel connection portion 127 and the internal spacer 220. In one embodiment, the portion of the channel connection portion 127 directly above and below the semiconductor pattern 126 may at least partially contact the source / drain layer 230.

[0091] In one embodiment, a second SEG process can be performed using a silicon source gas (e.g., disilane (Si₂H₆) gas) and a carbon source gas (e.g., SiH₃CH₃ gas), thus forming a single-crystal silicon carbide (SiC) layer. In another embodiment, the second SEG process can be performed using only a silicon source gas (e.g., disilane (Si₂H₆) gas), thus forming a single-crystal silicon layer. The source / drain layer 230 can be used as the source / drain of an NMOS transistor.

[0092] In one embodiment, a second SEG process can be performed using a silicon source gas (e.g., dichlorosilane (SiH2Cl2) gas) and a germanium source gas (e.g., germanane (GeH4) gas), thus forming a single-crystal silicon-germanium (SiGe) layer. The source / drain layer 230 can be used as the source / drain of a PMOS transistor.

[0093] In one embodiment, the source / drain layer 230 may be formed as a contact semiconductor pattern 126 and an internal spacer 220 located therebetween. Corresponding to the uneven surfaces of the sidewalls of the first semiconductor pattern 126a, the second semiconductor pattern 126b, the third semiconductor pattern 126c, the channel connection portion 127, and the internal spacer 220, the sidewalls of the source / drain layer 230 may also have uneven surfaces.

[0094] In one embodiment, the portion of the sidewall of the source / drain layer 230 that contacts each of the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c may be concave in a first direction, and the portion of the sidewall of the source / drain layer 230 that contacts each internal spacer 220 may be convex in the first direction.

[0095] Reference Figure 24After forming an insulating layer 240 on the substrate 100 to cover the first structure and the source / drain layer 230, the insulating layer 240 can be planarized until the upper surface of the dummy gate electrode 155 of the first structure is exposed. The dummy gate mask 165 can also be removed, and the upper part of the gate spacer 185 can be partially removed.

[0096] Planarization processes can be performed using chemical mechanical polishing (CMP) and / or etching-back processes.

[0097] The exposed dummy gate electrode 155, the dummy gate insulating pattern 145 below it, and the sacrificial pattern 114 can be removed, for example, by wet etching and / or dry etching processes, and a second opening 250 can be formed to expose the inner sidewall of the gate spacer 185, the inner sidewall of the channel connection portion 127, the surface of the semiconductor pattern 126, and the upper surface of the active pattern 105.

[0098] Refer again Figures 1 to 4 A gate structure 300 can be formed on the substrate 100 to fill the second opening 250.

[0099] In one embodiment, the interface pattern 260 can be formed by performing a thermal oxidation process on the upper surface of the active pattern 105 exposed by the second opening 250, the inner sidewall of the channel connection portion 127, and the surface of the semiconductor pattern 126. A gate insulating layer and a work function control layer can be conformally formed on the surface of the interface pattern 260, and a gate electrode layer can be formed to fully fill the remainder of the second opening 250.

[0100] The gate insulating layer, work function control layer, and gate electrode layer can be formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) processes. In one embodiment, the interface pattern 260 can also be formed using CVD or ALD processes instead of thermal oxidation.

[0101] The gate electrode layer, work function control layer, and gate insulating layer can be planarized until the upper surface of the insulating layer 240 is exposed, thereby forming the gate electrode 290, work function control pattern 280, and gate insulating pattern 270, respectively. The interface pattern 260, gate insulating pattern 270, work function control pattern 280, and gate electrode 290 can form the gate structure 300.

[0102] Interface pattern 260 may include, for example, oxides, such as silicon oxide. Gate insulating pattern 270 may include, for example, metal oxides having a high dielectric constant, such as hafnium oxide, tantalum oxide, zirconium oxide, etc. Work function control pattern 280 may include, for example, titanium nitride, tantalum nitride, tungsten nitride, aluminum oxide, etc. Gate electrode 290 may include, for example, metals (such as titanium and aluminum), metal alloys, or nitrides or carbides of metals.

[0103] Interface pattern 260 can be formed on the upper and lower surfaces of semiconductor pattern 126, which is exposed by second opening 250 and includes monocrystalline silicon, and on the inner sidewall of channel connection portion 127, and can completely surround the edge of second opening 250. Active pattern 105 can also include monocrystalline silicon, so interface pattern 260 can also be formed on the upper surface of active pattern 105.

[0104] In one embodiment, the sidewall of the interface pattern 260 of the gate structure 300 facing the source / drain layer 230 may have a concave shape toward the source / drain layer 230 in a first direction and may contact the inner sidewall of the channel connection portion 127 of the semiconductor pattern 126.

[0105] In one embodiment, the gate structure 300 and the internal spacer 220 are spaced apart from each other by the channel connection portion 127, so that they do not contact each other.

[0106] In one embodiment, the thickness of the gate structure 300 may be substantially equal to the thickness of the sacrificial pattern 114; for example, the gate structure 300 may have a second thickness T2. The thickness of the internal spacer 220 may be less than the second thickness T2 of the sacrificial pattern 114; for example, the internal spacer 220 may have a third thickness T3.

[0107] As described above, a first SEG process can be performed on the surface of the semiconductor pattern 126 exposed by the first opening 190 and the first recess 200 to form a second recess 205 with a thickness less than that of the first recess 200. Therefore, even with a relatively small amount of the second spacer layer formed, the second spacer layer 210 used to form the internal spacer 220 can be formed to completely fill the second recess 205. Furthermore, the second spacer layer 210 can be more easily removed after the internal spacer 220 is formed, and no residue is left on the upper surface of the active pattern 105. Therefore, the upper surface of the active pattern 105 can be completely exposed by the first opening 190, and the source / drain layer 230 can be effectively formed on the exposed upper surface of the active pattern 105, thereby improving the electrical characteristics of the semiconductor device.

[0108] The sacrificial pattern 114 may include silicon germanium, and the surface of the silicon-containing layer can be used as a seed crystal to perform the first SEG process. Therefore, a channel connection portion 127 can be formed on the sidewall of the sacrificial pattern 114, which connects the active pattern 105 and the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c to each other in a third-direction orientation. The channel connection portion 127 may include monocrystalline silicon, and an interface pattern 260 may also be formed on the inner sidewall of the channel connection portion 127 exposed by the second opening 250. The sequentially stacked gate insulating pattern 270, work function control pattern 280, and gate electrode 290 can be electrically insulated from the source / drain layer 230 through the interface pattern 260, the channel connection portion 127, and the internal spacer 220.

[0109] Figures 25 to 27 These are cross-sectional views of various stages in a method for manufacturing a semiconductor device according to an example embodiment, and are respectively cross-sectional views taken along line B-B' of the corresponding top view. Apart from the shape of some components, the manufacturing method may include, as referenced... Figures 5 to 24 as well as Figures 1 to 4 The processes shown are substantially the same or similar, therefore the same reference numerals refer to the same elements, and repeated descriptions of them may be omitted here.

[0110] Reference Figure 25 and Figure 26 It can be executed and referenced. Figures 5 to 24 The processes shown are essentially the same or similar.

[0111] In one embodiment, when the sacrificial pattern 114 is removed by, for example, a wet etching process and / or a dry etching process, the surfaces of the semiconductor pattern 126 located above and below the sacrificial pattern 114 may also be partially removed.

[0112] In one embodiment, a wet etching process and / or a dry etching process for removing the sacrificial pattern 114 can be performed using an etchant and / or an etch gas that selectively removes silicon and germanium. In one embodiment, the surface of the semiconductor pattern 126 comprising monocrystalline silicon and the upper surface of the active pattern 105 may also be partially removed together with the sacrificial pattern 114.

[0113] In one embodiment, the portion of the second opening 250 located between the active pattern 105 and the third semiconductor pattern 126c, and the portion of the second opening 250 located between the first semiconductor pattern 126a, the second semiconductor pattern 126b, and the third semiconductor pattern 126c, can be expanded in the third direction.

[0114] In one embodiment, after performing a wet etching process and / or a dry etching process, the central portion of the topmost first semiconductor pattern 126a in the semiconductor pattern 126 in a first direction may have a fourth thickness T4 less than the first thickness T1, and the central portions of each of the second semiconductor pattern 126b and the third semiconductor pattern 126c located below it may have a fifth thickness T5 less than the fourth thickness T4 in the first direction. The internal spacer 220 may have a third thickness T3 that is the same as the thickness before the wet etching process and / or the dry etching process.

[0115] Reference Figure 27 It can be executed and referenced. Figures 1 to 4 The processes described are substantially the same or similar, thereby forming a gate structure 300 that fills the second opening 250.

[0116] In one embodiment, the sixth thickness T6 of the gate structure 300 may be greater than the third thickness T3 of the internal spacer 220, the fourth thickness T4 of the central portion of the first semiconductor pattern 126a, and the fifth thickness T5 of the central portion of each of the second semiconductor pattern 126b and the third semiconductor pattern 126c.

[0117] Figure 28 and Figure 29 This is a cross-sectional view of a semiconductor device according to an example embodiment, and it is along... Figure 1 An enlarged cross-sectional view of region X, taken by line B-B'. Apart from the shape of the semiconductor pattern, this semiconductor device is similar to a reference... Figures 1 to 4 The semiconductor devices shown are substantially the same or similar, the same reference numerals refer to the same elements, and repeated descriptions of them may be omitted here.

[0118] Reference Figure 28 The thickness of the portion of the channel connection portion 127 that contacts the source / drain layer 230 in the third direction can be greater than the thickness of other portions of the channel connection portion 127.

[0119] In one implementation, the first SEG process can be performed on the portion of the initial semiconductor pattern 124 exposed by the first opening 190 to a greater extent than on the portion of the initial semiconductor pattern 124 exposed by the first recess 200, so that the portion of the semiconductor pattern 126 in contact with the source / drain layer 230 can have a relatively large thickness.

[0120] In one embodiment, the cross-section of the channel connection portion 127 in the first direction may have a C or inverted C shape, wherein the end of the C has a relatively large thickness.

[0121] In one embodiment, the outer wall of the internal spacer 220 that contacts the source / drain layer 230 may have a seventh thickness T7 (e.g., in the third direction) that is less than the third thickness T3 (which is the maximum thickness of the internal spacer 220).

[0122] Reference Figure 29 The thickness of the portion of the channel connection portion 127 that contacts the source / drain layer 230 in the third direction can be less than the thickness of the other portions of the channel connection portion 127.

[0123] In one implementation, the first SEG process can be performed on the portion of the preliminary semiconductor pattern 124 exposed by the first recess 200 to a greater extent than on the portion of the preliminary semiconductor pattern 124 exposed by the first opening 190, so that the portion of the semiconductor pattern 126 in contact with the source / drain layer 230 can have a relatively small thickness.

[0124] In one embodiment, the cross-section of the channel connection portion 127 in the first direction may have a C or inverted C shape, wherein the end of the C has a relatively small thickness.

[0125] In one embodiment, the thickness of the outer wall of the internal spacer 220 that contacts the source / drain layer 230 can be substantially equal to the second thickness T2 of the portion of the gate structure 300 located between the semiconductor patterns 126. In one embodiment, the thickness of the portion of the channel connection portion 127 that contacts the semiconductor pattern 126 in a third direction can increase as it moves further away from the source / drain layer 230 (e.g., moving inward in the first direction).

[0126] Figure 30 and Figure 31 This is a cross-sectional view of a semiconductor device according to an example embodiment, and it is along... Figure 1 A cross-sectional view taken along line B-B'. In addition to the further formation of metal silicide patterns and contact plugs on the source / drain layers, this semiconductor device can be compared with a reference... Figures 1 to 4 The semiconductor devices shown are substantially the same or similar; therefore, the same reference numerals refer to the same elements, and repeated descriptions of them may be omitted here.

[0127] Reference Figure 30 The second insulating intermediate layer 310 can be formed on the gate structure 300 and the insulating layer 240. The contact hole can be formed to pass through the insulating layer 240 and the second insulating intermediate layer 310 to expose the upper surface of the source / drain layer 230, and the contact plug 330 can be formed to fill the contact hole.

[0128] In one embodiment, a plurality of contact plugs 330 may be formed along a first direction.

[0129] The metal silicide pattern 320 can be further formed on the source / drain layer 230. In one embodiment, after a metal layer is formed on the upper surface of the source / drain layer 230 exposed by the contact hole, the sidewalls of the insulating layer 240, and the sidewalls and upper surface of the second insulating intermediate layer 310, a heat treatment process can be performed on the metal layer to form the metal silicide pattern 320 on the source / drain layer 230.

[0130] In one embodiment, the metal silicide pattern 320 may include, for example, nickel silicide, cobalt silicide, titanium silicide, etc., and the contact plug 330 may include, for example, metal, metal nitride, and / or polycrystalline silicon doped with impurities.

[0131] In one embodiment, the contact plug 330 may have a structure consisting of a conductive pattern and a stack of blocking patterns covering its sidewalls. The conductive pattern may include, for example, a metal such as copper, tungsten, or aluminum. The blocking pattern may include, for example, a metal (such as titanium or tantalum) or a metal nitride (such as titanium nitride or tantalum nitride).

[0132] In one implementation, such as Figure 30 As shown, the lower surface of the contact plug 330 (e.g., the surface facing the substrate 100) may have the same height as the upper surface of the source / drain layer 230. In one embodiment, the contact plug 330 may be formed to extend in a third direction to have various depths, such that the lower surface of the contact plug 330 may be formed below the upper surface of the source / drain layer 230.

[0133] Reference Figure 31 The lower surface of the contact plug 330 may be lower than the lower surface of the first semiconductor pattern 126a and higher than the upper surface of the third semiconductor pattern 126c, and may be formed, for example, at a height between the lower and upper surfaces of the second semiconductor pattern 126b.

[0134] In one embodiment, the lower surface of the contact plug 330 may be formed at a height between the lower surface of the first semiconductor pattern 126a and the upper surface of the second semiconductor pattern 126b, or at a height between the lower surface of the second semiconductor pattern 126b and the upper surface of the third semiconductor pattern 126c.

[0135] In one implementation, such as Figure 31 As shown, the metal silicide pattern 320 located on the source / drain layer 230 can have a cylindrical shape. In one embodiment, the metal silicide pattern 320 can be cylindrical.

[0136] In summary and review, the internal spacer layer used to form the internal spacers can be formed between adjacent channels in multiple channels to completely fill the space between the gate structure and the source / drain layers. If the internal spacer layer has a thick enough thickness to completely fill the space, residue may be left when the internal spacer layer is removed.

[0137] One or more embodiments may provide a semiconductor device having multiple channels stacked vertically.

[0138] The example embodiments provide semiconductor devices with improved electrical characteristics.

[0139] In the method of manufacturing a semiconductor device according to the example embodiment, a selective epitaxial growth (SEG) process may be further performed on the surface of the channel to reduce the thickness of the recess, wherein internal spacers are formed between the channels in the recess. Therefore, even if an internal spacer layer for forming the internal spacers is provided in a relatively small amount on the active pattern, the internal spacer layer can be formed to completely fill the recess between the channels, and when the internal spacer layer is removed, residue can be completely removed without leaving any residue.

[0140] Example embodiments have been disclosed herein. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, from the time of filing of this application, unless otherwise expressly indicated, the features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: An active pattern, the active pattern being located on a substrate, the active pattern extending longitudinally in a first direction parallel to the upper surface of the substrate; A gate structure located on the active pattern, the gate structure extending longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; The channels are spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, and each channel extends longitudinally through the gate structure along the first direction; A source / drain layer is located on the portion of the active pattern adjacent to the gate structure in the first direction, and the source / drain layer contacts the channel; An internal spacer is located between the gate structure and the source / drain layer, and the internal spacer contacts the source / drain layer; as well as A channel connection portion is located between each of the internal spacers and the gate structure, the channel connection portion connecting the channels to each other. The channel connection portion comprises the same semiconductor material as the channel.

2. The semiconductor device according to claim 1, wherein, Each of the internal spacers has a shape that protrudes inward toward the center of the gate structure in the first direction.

3. The semiconductor device according to claim 2, wherein, Each of the channel connection portions covers the inner wall, upper surface, and lower surface of the corresponding internal spacer.

4. The semiconductor device according to claim 3, wherein, Each of the channel connection portions directly contacts the source / drain layer.

5. The semiconductor device according to claim 1, wherein, The gate structure includes an interface pattern, a gate insulating pattern, a work function control pattern, and a gate electrode that are sequentially stacked from the surface of each channel, the upper surface of the active pattern, and the inner sidewall of the channel connection portion.

6. The semiconductor device according to claim 5, wherein: The interface pattern includes silicon oxide, and The gate insulation pattern comprises a metal oxide.

7. The semiconductor device according to claim 5, further comprising: A gate spacer that covers the sidewall of the uppermost portion of the channel of the gate structure. The interface pattern is not formed on the inner sidewall of the gate spacer.

8. The semiconductor device according to claim 7, wherein, In the top view, each of the channels extends outward toward the source / drain layer beyond the gate spacer.

9. The semiconductor device according to claim 1, wherein, Both the channel and the channel connection portion comprise monocrystalline silicon.

10. The semiconductor device according to claim 1, wherein, The internal spacers include silicon nitride, silicon carbonitride, silicon boronitride, or silicon carbonitride.

11. The semiconductor device according to claim 1, wherein, The thickness of the portion of the gate structure located between the channels in the third direction is greater than the thickness of the corresponding internal spacer adjacent to it in the first direction in the third direction.

12. The semiconductor device according to claim 1, wherein, The thickness of each of the internal spacers in the third direction gradually increases toward the source / drain layer in the first direction.

13. The semiconductor device according to claim 1, wherein, The thickness of each of the internal spacers in the third direction gradually increases to a maximum thickness and then gradually decreases in the first direction toward the source / drain layer.

14. A semiconductor device, the semiconductor device comprising: An active pattern, the active pattern being located on a substrate, the active pattern extending longitudinally in a first direction parallel to the upper surface of the substrate; A gate structure located on the active pattern, the gate structure extending longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; The channels are spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, and each channel extends longitudinally through the gate structure along the first direction; A source / drain layer is located on the portion of the active pattern adjacent to the gate structure in the first direction, and the source / drain layer contacts the channel; as well as The channel connection portion and the internal spacer are sequentially stacked along the first direction between the gate structure and the source / drain layer. The channel connection portion comprises the same semiconductor material as the channel, and the internal spacer comprises silicon nitride. The gate structure includes an interface pattern, a gate insulating pattern, and a gate electrode sequentially stacked along the first direction from the channel connection portion. The interface pattern includes silicon oxide, the gate insulating pattern includes a metal oxide, and the gate electrode includes a metal.

15. The semiconductor device according to claim 14, wherein, The channel connection portion connects the channels to each other, and connects the lowermost channel to the active pattern.

16. The semiconductor device according to claim 14, wherein, The internal spacer has a shape that protrudes inward toward the center of the gate structure in the first direction.

17. The semiconductor device according to claim 16, wherein, The channel connection portion covers the inner wall, upper surface, and lower surface of the internal spacer.

18. The semiconductor device according to claim 17, wherein, The channel connection portion directly contacts the source / drain layer.

19. A semiconductor device, the semiconductor device comprising: An active pattern, the active pattern being located on a substrate, the active pattern extending longitudinally in a first direction parallel to the upper surface of the substrate; The channels are located on the active pattern and are spaced apart from each other along a third direction perpendicular to the upper surface of the substrate; A gate structure extending longitudinally over the active pattern in a second direction parallel to the upper surface of the substrate and intersecting the first direction, the gate structure at least partially covering each of the channels; Source / drain layers, the source / drain layers being located on the active pattern at respective opposite sides of the gate structure in the first direction, each of the source / drain layers contacting the channel; Internal spacers are located between the active pattern and the bottommost channel and between the channels, respectively, and the internal spacers contact the source / drain layers; Gate spacers that cover the respective opposite sidewalls of the uppermost portion of the channel of the gate structure; as well as A channel connection portion is located between the gate structure and the corresponding internal spacer. The channel connection portion connects the active pattern and the lowermost channel and connects the channels to each other. The channel connection portion covers the inner sidewall, upper surface, and lower surface of the corresponding internal spacer. The channel connection portion comprises the same semiconductor material as the channel. The gate structure includes an interface pattern, a gate insulating pattern, and a gate electrode that are sequentially stacked from the surface of each channel, the upper surface of the active pattern, and the inner sidewall of the channel connection portion. The interface pattern includes silicon oxide, the gate insulating pattern includes metal oxide, and the gate electrode includes metal.

Images