Method and system for generating a circuit layout

Abstract

A method of generating a circuit layout includes generating a circuit design based on design information for an integrated circuit, including an initial power supply network for the integrated circuit, performing a pre-layout simulation on the circuit design to determine whether the circuit design meets predetermined specifications, including the initial power supply network, and generating a power supply network layout for the integrated circuit when the circuit design meets the predetermined specifications, and generating a circuit layout for the integrated circuit after the power supply network layout is generated.

Description

Technical Field

[0001] The embodiments of this disclosure relate to a method, and more particularly to a method and system for generating circuit layouts for integrated circuits. Background Technology

[0002] An integrated circuit (IC) typically comprises semiconductor devices represented in an IC layout. The IC layout is derived from a circuit diagram, such as an IC. Throughout the IC design process, from IC design to the actual manufacturing of the IC layout, various checks and tests are performed to ensure the IC is manufactureable and will function as designed. Summary of the Invention

[0003] This disclosure relates to a method for generating a circuit layout, characterized by the following steps: Generating a circuit design based on design information for an integrated circuit, the circuit design including an initial power supply network (PDN) for the integrated circuit. Performing a pre-layout simulation on the circuit design to determine whether the circuit design, including the initial power supply network, meets predetermined specifications. If the circuit design meets the predetermined specifications, generating a power supply network layout for the integrated circuit, and after generating the power supply network layout, generating a circuit layout for the integrated circuit. If the circuit design does not meet the predetermined specifications, modifying the initial power supply network into a modified power supply network based on the relationship between the pillar density and the maximum pillar density of the initial power supply network.

[0004] This disclosure relates to a method for generating a circuit layout, characterized by the following steps: performing at least one of a voltage drop pre-check process or an electromigration pre-check process on a circuit design including a power supply network (PDN); generating a power supply network layout for the integrated circuit design layout when the circuit design meets predetermined specifications; generating a circuit layout for the integrated circuit design layout after the power supply network layout is generated; performing a voltage drop and electromigration verification process on the design layout; generating a final design layout for the integrated circuit when the voltage drop and electromigration requirements are met during the voltage drop and electromigration verification process; and modifying the power supply network into a modified power supply network according to the relationship between the pillar density and the maximum pillar density of the power supply network when the circuit design does not meet predetermined specifications.

[0005] This disclosure relates to a system for generating circuit layouts, characterized by comprising: a memory for storing design information for an integrated circuit, the design information including parameters associated with a plurality of power rails and a plurality of conductive pillars coupled to the power rails; and at least one processor communicating with the memory and for performing operations including: generating a circuit design based on the design information, the circuit design including a power supply network (PDN) for the integrated circuit; performing at least one of a voltage drop pre-check process or an electromigration pre-check process on the circuit design including the power supply network to determine whether the circuit design meets predetermined specifications; generating a power supply network layout and subsequently generating a circuit layout for the design layout of the integrated circuit when the circuit design meets the predetermined specifications; performing voltage drop and electromigration verification processes on the design layout; generating a final design layout of the integrated circuit when the voltage drop and electromigration requirements are met during the voltage drop and electromigration verification processes; and modifying the power supply network into a modified power supply network according to the relationship between the pillar density and the maximum pillar density of the power supply network when the circuit design does not meet the predetermined specifications.

[0006] The embodiments of this disclosure relate to a method for generating a circuit layout, characterized by comprising the following steps: generating a circuit design based on design information for an integrated circuit, the circuit design including an initial power supply network (PDN) for the integrated circuit; performing a pre-layout simulation on the circuit design to determine whether the circuit design meets predetermined specifications, the circuit design including the initial power supply network; generating a circuit layout for the integrated circuit when the circuit design meets the predetermined specifications; and adding at least one additional conductive post or at least one additional power rail to the initial power supply network according to the relationship between the post density and the maximum post density of the initial power supply network when the circuit design does not meet the predetermined specifications.

[0007] The embodiments of this disclosure relate to a method for generating a circuit layout, characterized by comprising the following steps: performing at least one of a voltage drop pre-check process or an electromigration pre-check process on a circuit design including a power supply network (PDN); during at least one of the voltage drop pre-check process or the electromigration pre-check process, if the circuit design meets predetermined specifications, generating a circuit layout for the design layout of an integrated circuit to perform voltage drop and electromigration verification processes on the design layout; and during at least one of the voltage drop pre-check process or the electromigration pre-check process, if the circuit design does not meet predetermined specifications, modifying the pillar density of the power supply network according to the relationship between the pillar density of the power supply network and the maximum pillar density.

[0008] This disclosure relates to a system for generating circuit layouts, characterized by comprising: a memory for storing design information for an integrated circuit, the design information including parameters associated with a plurality of power rails and a plurality of conductive posts coupled to the power rails; and at least one processor communicating with the memory and for performing operations including: performing a pre-layout simulation on the circuit design to determine whether the circuit design meets predetermined specifications, the circuit design including a power supply network; generating a final design layout of the integrated circuit when voltage drop and electromigration requirements are met during a voltage drop and electromigration verification process; adding at least one additional conductive post to the power supply network when the circuit design does not meet predetermined specifications and the post density of the power supply network is not at the maximum post density; and adding at least one additional power rail to the power supply network when the circuit design does not meet predetermined specifications and the post density of the power supply network is at the maximum post density.

[0009] The embodiments of this disclosure relate to a method for generating a circuit layout, characterized by comprising the following steps: generating a circuit design based on design information for an integrated circuit, the circuit design including an initial power supply network (PDN) for the integrated circuit; performing a pre-layout simulation on the circuit design to determine whether the circuit design includes the initial power supply network and whether it meets predetermined specifications; generating a circuit layout for the integrated circuit when the circuit design meets the predetermined specifications; repeatedly modifying the pillar density of the initial power supply network until the circuit design meets the predetermined specifications when the circuit design does not meet the predetermined specifications, thereby generating a circuit layout for the integrated circuit; and performing a post-layout simulation on the circuit layout.

[0010] The embodiments of this disclosure relate to a method for generating a circuit layout, characterized by comprising the following steps: performing at least one of a voltage drop pre-check process or an electromigration pre-check process on a circuit design including a power supply network (PDN), wherein the power supply network includes a plurality of internal pillars and a plurality of dominant pillars; during at least one of the voltage drop pre-check process or the electromigration pre-check process, if the circuit design meets predetermined specifications, generating a circuit layout for an integrated circuit design layout to perform voltage drop and electromigration verification processes on the design layout; and during at least one of the voltage drop pre-check process or the electromigration pre-check process, if the circuit design does not meet predetermined specifications, increasing a first number of internal pillars and maintaining a second number of dominant pillars.

[0011] This disclosure relates to a system for generating circuit layouts, characterized by comprising: a memory for storing design information for an integrated circuit, the design information including parameters associated with a plurality of power rails and a plurality of conductive posts coupled to the power rails; and at least one processor communicating with the memory and for performing operations including: performing a pre-layout simulation on the circuit design to determine whether the circuit design meets predetermined specifications, the circuit design including a power supply network; generating a final design layout of the integrated circuit when voltage drop and electromigration requirements are met during a voltage drop and electromigration verification process; adding at least one additional power rail to the power supply network when the circuit design does not meet predetermined specifications and the post density of the power supply network is at the maximum post density; and adding at least one additional conductive post to the power supply network after the addition of at least one additional power rail. Attached Figure Description

[0012] One embodiment of this disclosure is similar to the accompanying document. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0013] Figure 1 This is a flowchart of at least a portion of an integrated circuit (IC) design flow according to some embodiments of this disclosure;

[0014] Figure 2 The illustrations are for some embodiments according to this disclosure. Figure 1 A schematic diagram of the power supply network generated in the method;

[0015] Figure 3A According to some embodiments of this disclosure Figure 2 A schematic diagram of the cross-section of a pillar in a power supply network;

[0016] Figure 3B Illustrations of some embodiments according to this disclosure Figure 3A A schematic diagram of the equivalent circuit of the guide post in the diagram;

[0017] Figure 4A To enable the implementation of some embodiments of this disclosure Figure 2 A schematic diagram of the cross-sectional views of various guide pillars used in the power supply network;

[0018] Figure 4B Illustrations of some embodiments according to this disclosure Figure 4A A schematic diagram of the equivalent circuit of the middle guide pillar;

[0019] Figure 5 This is a schematic diagram of a circuit suitable for an IR drop pre-check process according to some embodiments of this disclosure, which is related to... Figure 2 The power supply network is described in the discussion;

[0020] Figure 6 This is a schematic diagram of a circuit suitable for an EM pre-inspection process according to some embodiments of this disclosure, which is related to... Figure 2 The power supply network is described in the discussion;

[0021] Figure 7 This is a flowchart of a method applicable to an IR down-check process according to some embodiments of this disclosure, which is related to... Figure 2 The power supply network is described in the discussion;

[0022] Figure 8A This is a schematic diagram of a power supply network according to some embodiments of the present disclosure;

[0023] Figure 8B Illustrations of some embodiments according to this disclosure Figure 8A A schematic diagram of the equivalent resistance network of the power supply network in the diagram;

[0024] Figures 8C to 8E Illustrations of various embodiments according to this disclosure Figure 8A A schematic diagram illustrating the changes in the power supply network;

[0025] Figure 9 This is a flowchart of a method applicable to an EM pre-inspection process according to some embodiments of this disclosure, which is related to... Figure 2 The power supply network is described in the discussion;

[0026] Figure 10 Illustrations of various embodiments according to this disclosure Figure 8A A schematic diagram of other changes to the power supply network;

[0027] Figure 11 This is a schematic diagram of a circuit suitable for an IR drop and / or EM pre-check process according to some embodiments of this disclosure, the IR drop and / or EM pre-check process being as per the description of... Figure 2 The power supply network is described in the discussion;

[0028] Figure 12 According to some embodiments of this disclosure, in Figure 1 A schematic diagram of the circuit layout generated in the method;

[0029] Figure 13 For the purpose of performing certain embodiments of this disclosure regarding Figure 1 , Figure 7 and Figure 9 A schematic diagram of an integrated circuit (IC) design system.

[0030] [Symbol Explanation]

[0031] 100: Method

[0032] 200: Power Supply Network

[0033] 210: Electric Rails

[0034] 220: Electric Rails

[0035] 300: Circuit

[0036] 400: Circuit

[0037] 500: Circuit

[0038] 510: Power supply network circuit

[0039] 520: Power supply circuit / Power supply unit circuit

[0040] 530: Operating Circuit

[0041] 600: Circuit

[0042] 630: Operating Circuit

[0043] 700: Method applicable to IR down-checking process

[0044] 800: Power Supply Network

[0045] 802: Equivalent Resistance Network

[0046] 804: Equivalent Resistance Network

[0047] 810: Power Supply Network

[0048] 820: Power Supply Network

[0049] 900: Methods applicable to electromigration (EM) pre-inspection processes

[0050] 1020: Power Supply Network

[0051] 1100: Circuit

[0052] 1102: Drive

[0053] 1104: Controller

[0054] 1200: Circuit Layout

[0055] 1210: District

[0056] 1220: District

[0057] 1230: District

[0058] 1230a: Block

[0059] 1230b: Block

[0060] 1230c: Block

[0061] 1230d: Block

[0062] 1300: Integrated Circuit (IC) Design System

[0063] 1305: System Bus

[0064] 1310: Memory

[0065] 1312: Design Specification

[0066] 1314: Process Design Kit (PDK)

[0067] 1316: Integrated Circuit (IC) Design Layout

[0068] 1318: The program of the instruction

[0069] 1320: Processor

[0070] 1330: Manufacturing Tools

[0071] 1350: Manufacturing Tools

[0072] Mt: Top conductive layer

[0073] Mb: Bottom conductive layer

[0074] Mt: conductive layer

[0075] Mt-1: Conductive layer

[0076] Mt-2: Conductive layer

[0077] Mt-3: Conductive layer

[0078] Mb: Bottom conductive layer

[0079] Mb+1: Conductive layer

[0080] Mb+2: Conductive layer

[0081] Mb+3: Conductive layer

[0082] Pi: Guide post

[0083] Pm: Guide Post

[0084] Pm0: Dominant column

[0085] Pm1: Dominant column

[0086] Pm2: Dominant column

[0087] Rb+1: Resistor

[0088] Rt-1: Resistor

[0089] Rb+2: Resistor

[0090] Rb+1: Resistor

[0091] S110: Operation

[0092] S120: Operation

[0093] S125: Operation

[0094] S130: Operation

[0095] S140: Operation

[0096] S150: Operation

[0097] S160: Operation

[0098] S170: Operation

[0099] S175: Operation

[0100] S180: Operation

[0101] S190: Operation

[0102] S702: Operation

[0103] S704: Operation

[0104] S706: Operation

[0105] S708: Operation

[0106] S710: Operation

[0107] S712: Operation

[0108] S714: Operation

[0109] S716: Operation

[0110] S718: Operation

[0111] S902: Operation

[0112] S904: Operation

[0113] S906: Operation

[0114] S908: Operation

[0115] S910: Operation

[0116] S912: Operation

[0117] S914: Operation

[0118] S916: Operation

[0119] S918: Operation

[0120] VDD: Supply voltage / Power supply voltage

[0121] VDDI: Voltage

[0122] VSS: Supply voltage / Ground voltage

[0123] VSSI: Voltage

[0124] Vi[1:N]: Voltage

[0125] Vo[1:N]: Voltage

[0126] Vt: Through hole

[0127] Vt-1: Through hole

[0128] Vt-2: Through hole

[0129] Vt-3: Through hole

[0130] Vt-n: Through hole

[0131] Vb+1: Through hole

[0132] Vb+2: Through hole

[0133] Vb: Through hole

[0134] X: Direction

[0135] Y: direction Detailed Implementation

[0136] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify some embodiments of this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, some embodiments of this disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0137] The terms used in this specification generally have their general meaning in the art and in the specific context in which each term is used. Examples used in this specification, including instances containing any terms discussed herein, are illustrative only and do not limit the scope or meaning of any embodiments of this disclosure or any of the illustrated terms. Similarly, some embodiments of this disclosure are not limited to the various embodiments given in this specification.

[0138] Although the terms “first,” “second,” etc., are used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the embodiments. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0139] In this document, the term “coupled” may also be referred to as “electrical coupling”, and the term “connected” may be referred to as “electrical connection”. “Coupled” and “connected” may also be used to indicate that two or more components cooperate or interact with each other.

[0140] Additionally, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” and similar terms, may be used herein for ease of description to describe the relationship between one element or feature and another, as illustrated in the figures. Spatial relative terms are intended to cover orientations of the device other than those depicted in the figures during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0141] Figure 1 This is a flowchart of at least a portion of an integrated circuit (IC) design flow / method 100 according to some embodiments of this disclosure. (For...) Figure 1 The illustration shows that IC design flow 100 includes operations S110, S120, S130, S140, S150, S160, and S170. IC design flow 100 is executed to test the IC design before IC manufacturing. In some embodiments, IC design flow 100 uses one or more electronic design automation (EDA) tools to test the IC design. In some embodiments, the EDA tool is one or more executable instruction sets that are supplied to a processor (e.g., ...). Figure 13 The processor 1320), controller, or programmable computer or similar device executes the indicated functionality.

[0142] In operation S110, a circuit design for the IC is generated. In some embodiments, the circuit design for the IC is provided by a circuit designer and / or stored in memory (e.g., ...). Figure 13 The IC is stored in memory 1310. In some embodiments, the circuit design of the IC includes an IC schematic. In some embodiments, the IC schematic is generated or provided in the form of a schematic netlist, such as a Simulation Program with Integrated Circuit Emphasis (SPICE) netlist. Other data formats for describing the design are available in some embodiments. In some embodiments, SPICE simulation is performed on the SPICE netlist. In other embodiments, other simulation tools are used instead of SPICE simulation.

[0143] In operation S120, pre-layout simulation, for example, is performed on the circuit design using EDA tools to determine whether the circuit design meets predetermined specifications. If the circuit design does not meet the predetermined specifications, at least a portion of the IC is redesigned. In some embodiments, pre-layout simulation is performed through several steps to determine whether each part of the circuit design meets the corresponding requirements in the predetermined specifications. If a part of the circuit design does not meet the predetermined specifications, that part of the circuit design is redesigned.

[0144] In operation S125, the pre-layout simulation result from operation S120 is compared with the expected pre-layout simulation result. When the pre-layout simulation result does not match the expected simulation result, the process returns to operation S110 to generate a new circuit design for the IC and then performs subsequent operations accordingly. On the other hand, when the pre-layout simulation result matches the expected simulation result, the process continues to operation S130.

[0145] In operation S130, the IC design layout (or layout diagram) is generated based on the circuit design. In some embodiments, the design layout is generated using EDA tools in the form of a Graphic Design System (GDS) file. Other tools and / or data formats for describing the layout are available in various embodiments.

[0146] In operation S140, a layout-versus-schematic (LVS) check is performed. The LVS check is performed to ensure that the resulting layout corresponds to the circuit design. In some embodiments, such as an LVS check tool implemented via an EDA tool, electrical components and the connections between these components are identified from the pattern of the resulting layout. The LVS check tool then generates a layout netlist representing the identified electrical components and connections. The layout netlist generated from the design layout is compared with a schematic netlist of the circuit design using the LVS check tool. If the two netlists match within a matching tolerance, the LVS check passes. Otherwise, at least one of the design layout or the circuit design is corrected.

[0147] In operation S150, a design rule check (DRC), performed, for example, on a GDS file representing the design layout using an EDA tool, ensures that the design layout meets certain manufacturing design rules to ensure the manufacturability of the IC. If one or more design rules are violated, at least one of the design layout or circuit design is corrected. Examples of design rules include, but are not limited to, the following: width rules, which specify the minimum width of a pattern in the design layout; spacing rules, which specify the minimum spacing between adjacent patterns in the design layout; area rules, which specify the minimum area of ​​a pattern in the design layout; or similar rules.

[0148] In some embodiments, at least one of the design rules is voltage-dependent. For example, a metal-to-via spacing rule specifies the minimum spacing between a metal pattern and an adjacent via in the IC's design layout. In some embodiments, this minimum spacing depends on the voltage expected or predicted to occur at the metal pattern or via during IC operation. Examples of other voltage-dependent design rules include, but are not limited to, metal-to-metal spacing rules, polysilicon-to-oxide definition (PO-to-OD) spacing rules, PO-to-PO spacing rules, etc. In some embodiments, a DRC performed to check the layout's compliance with one or more voltage-dependent design rules is also referred to as VDRC.

[0149] In operation S160, resistance and capacitance (RC) extraction is performed, for example, by an EDA tool, to determine or extract parasitic parameters, which include, for example, the parasitic resistance or capacitance of interconnects in a design layout used for timing simulation in subsequent operations.

[0150] In operation S170, post-layout simulation is performed by a simulation tool, such as one implemented by an EDA tool, to determine whether the design layout meets predetermined specifications or requirements. When the simulation indicates that the design layout does not meet predetermined specifications, at least one of the design layout or circuit design is corrected. For example, regarding the extracted parasitic parameters as discussed above, when the parasitic parameters cause undesirable delays, the simulation is determined to indicate that the layout does not meet predetermined specifications, and correction is then performed on at least one of the design layout or circuit design. On the other hand, when the layout meets predetermined specifications, the design layout passes manufacturing or additional verification processes. For example, in various embodiments, voltage drop and electromigration (EM) verification processes are also performed in the post-layout simulation. When the voltage drop and electromigration requirements are met during the voltage drop and electromigration verification process, the final design layout of the IC is generated. The term "voltage drop" is also referred to as "IR drop" in this art, and for brevity, it will be referred to as "IR drop" hereinafter in some embodiments of this disclosure.

[0151] In operation S175, the post-layout simulation result from operation S170 is compared with the expected post-layout simulation result. When the post-layout simulation result does not match the expected simulation result, the process returns to operation S110 to generate a new circuit design for the IC and then performs subsequent operations accordingly again. On the other hand, when the post-layout simulation result matches the expected simulation result, the process continues to operation S180.

[0152] In operation S180, a photomask is generated from operation S130 based on the IC's design layout (or layout diagram). In some embodiments, the photomask is generated by performing one or more lithographic exposures based on the IC design layout. In some embodiments, an electron beam (e-beam, e-beam) or multi-electron beam mechanism is used to form a pattern on the mask based on the IC design layout. In operation S190, the IC is using the photomask from operation S180. In some embodiments, manufacturing the IC involves at least indirectly performing one or more lithographic exposures on the IC design layout.

[0153] It should be understood that additional operations can be performed via... Figure 1 The diagram is provided before, during, and after the operation, and Figure 1 Some additional embodiments of the method in the operations may be replaced, eliminated, or interchanged. For example, in various embodiments, RC extraction in operation S160 and post-layout simulation in operation S170 are omitted.

[0154] As discussed above, IR drop and EM verification processes are normally performed during post-layout simulation, which occurs later in the design process. Therefore, if it is determined that the IR drop and EM requirements are not met, the IC design process must be completely reworked. Specifically, as discussed above... Figure 1 The operations described must be repeated repeatedly when IR drop and EM requirements are not met. Therefore, completely reworking the IC design in this way adds a significant amount of time to the IC design process.

[0155] To address the above issues, the embodiments disclosed herein represent currently known integrated circuit (IC) design methods and systems that generate an appropriate power delivery network (PDN) for the IC early in the design process (e.g., operation S110) to generate IC design layout in a real-time manner. Using the PDN, in addition to the IR drop and EM verification processes in post-layout simulation, IR drop and / or EM pre-check processes can be performed on the PDN in pre-layout simulation (e.g., operation S120). Therefore, IR drop and / or EM problems can be optimized early in the pre-layout simulation. The following detailed discussion is for further explanation.

[0156] exist Figure 1 In some embodiments, during operation S110, a circuit design including a power delivery network (PDN) for the IC is generated. To generate the circuit design including the power delivery network, corresponding design information in the form of a process design kit (PDK) is also provided and stored in memory (e.g., ...). Figure 13 The design information is stored in memory 1310. Therefore, the above design information is also referred to as "PDK" in some embodiments. For IC design purposes, the above design information can also be transmitted to one or more processors of a design system that executes EDA tools on a computer-aided design (CAD) system (e.g., ...). Figure 13 Access to the processor 1320.

[0157] To generate a circuit design that includes a power supply network, in some embodiments, the design information (or PDK) above includes parameters associated with power rails and conductive pillars in the power supply network, which are described below. Figure 2 To elaborate further. In some other embodiments, the design information (or PDK) also includes a base-specific set of documents, including, but not limited to, technical documents, library elements, library design rules, and the like, for a specific technology node. In other words, the design information (or PDK) contains parameters that indicate predetermined specifications for the circuit design of the IC. For example, parameters include voltage drop across the power supply network, current flowing through the power supply network, resistance of the leads, number of power rails in the power supply network, number of leads, maximum lead density, and the like. In some embodiments, EDA tools are executed to obtain these parameters from the PDK. In some embodiments, the parameters of the design information (or PDK) are adjustable via an input / output interface.

[0158] Figure 2 The illustrations are for some embodiments according to this disclosure. Figure 1 A schematic diagram of the power supply network 200 generated in method 100. (For...) Figure 2 As illustrated, the power supply network 200 includes power rails 210 and 220 that intersect each other in the layout view. The power rails 210 are evenly spaced apart and have the same width, and... Figure 2 The conductive layer Mt-1 is disposed along, for example, the X direction (shown in...). Figures 3A-3B In the process, the electric rails 220 are evenly spaced from each other and have the same width, and in Figure 2 The conductive layer Mt (e.g., the top metal layer) is disposed above the conductive layer Mt-1 along, for example, the Y direction (illustrated in...). Figures 3A-3B In addition, power rails 210 are configured in a pattern that alternately couples to supply voltage VDD (e.g., power supply voltage) and supply voltage VSS (e.g., ground voltage). Power rails 220 are also configured in a pattern that alternately couples to supply voltages VDD and VSS. Therefore, in some embodiments, when power rails 210 and 220 are configured in a mesh form, the power supply network 200 is also referred to as a power / ground mesh. In some embodiments, power rails 210 and 220 are made of a conductive material comprising, for example, metal.

[0159] against Figure 2 As illustrated, the power supply network 200 also includes guide posts Pm and guide posts Pi. Each of the guide posts Pm is indicated by a frame with an inner cross, and each of the guide posts Pi is indicated by an empty frame, as shown in the diagram. Figure 2As illustrated in the figure. In some embodiments, each of the conductor posts Pi is coupled to one of the conductive rails 210 in the conductive layer Mt-1, and each of the conductor posts Pm is coupled to one of the conductive rails 220 in the conductive layer Mt via a corresponding electric rail 210 in the conductive layer Mt-1, the foregoing of which will be further explained with reference to the figure. Figure 3A Discussion. In the above configuration, in the prior art and in some embodiments of this disclosure, the guide pillar Pm is also referred to as the "major pillar" and the guide pillar Pi is also referred to as the "intra pillar".

[0160] Although for the sake of simplicity, only one power rail 210, only one power rail 220, only one guide post Pi, and only one guide post Pm are labeled, it should be understood that each of these labels collectively represents as follows: Figure 2 Other similar components are shown in the diagram.

[0161] As discussed above, in some embodiments, the power supply network 200 is constructed with several layers and has several vias disposed between the layers to conduct current from the input to the output. For ease of understanding, Figure 2 See also the power supply network 200. Figure 3A This will be discussed.

[0162] Figure 3A According to some embodiments of this disclosure Figure 2 A schematic diagram of the cross-sectional view of the guide pillars in the power supply network 200. Figure 3A For simplicity, a primary guide post Pm and an internal guide post Pi are shown in the diagram. Figure 3A The illustration illustrates that each of the main pillar Pm and the internal pillar Pi is configured with a via (collectively indicated as Vt) in a separate layer. For the main pillar Pm, the via Vt is configured in a stacked structure from a top conductive layer Mt coupled to, for example, an input terminal to a bottom conductive layer Mb coupled to, for example, an output terminal. For the internal pillar Pi, the via Vt is in another stacked structure from a conductive layer Mt-1 below the top conductive layer Mt to the bottom conductive layer Mb. Detailed illustrations of the main pillar Pm and the internal pillar Pi are provided below.

[0163] exist Figure 3AIn the diagram, the main guide post Pm includes through-holes Vt-1, Vt-2, Vt-3, ..., and Vt-n. Through-hole Vt-1 is located between the top conductive layer Mt and conductive layer Mt-1, through-hole Vt-2 is located between conductive layers Mt-1 and Mt-2, through-hole Vt-3 is located between conductive layers Mt-2 and Mt-3, and through-hole Vt-n is located between conductive layer Mb+1 and bottom conductive layer Mb. The internal guide post Pi includes through-holes Vt-2, Vt-3, and Vt-n. Similarly, through-hole Vt-2 is located between conductive layers Mt-1 and Mt-2, through-hole Vt-3 is located between conductive layers Mt-2 and Mt-3, and through-hole Vt-n is located between conductive layer Mb+1 and bottom conductive layer Mb. For ease of understanding, Figure 3A Not every through-hole contained in the main guide post Pm and the inner guide post Pi is illustrated. However, it should be understood that more or fewer through-holes may be provided in the main guide post Pm and / or the inner guide post Pi.

[0164] To perform the IR drop and / or EM pre-check processes as described above, the equivalent resistance of each of the main lead post Pm and the inner lead post Pi is required. In some embodiments, the equivalent resistance of each of the main lead post Pm and the inner lead post Pi is obtained from the equivalent circuit of the corresponding lead post or a resistor network connection table indicating the equivalent circuit.

[0165] Figure 3B Illustrations of some embodiments according to this disclosure Figure 3A A schematic diagram of the equivalent circuit 300 of the dominant pillar Pm. (See diagram below.) Figure 3B As shown in the illustration, targeting Figure 3A The dominant pillar Pm, the equivalent circuit 300 shows the resistor (corresponding to Figure 3A (Individual vias), these resistors are connected in series from the top conductive layer Mt to the bottom conductive layer Mb. Therefore, the equivalent resistance of the dominant pillar Pm can be calculated and obtained by summing the resistances of the series-connected resistors.

[0166] In some embodiments, under different configurations of the dominant post Pm and the internal post Pi, the equivalent circuit 300 of the dominant post Pm differs from the equivalent circuit of the internal post Pi. Therefore, the equivalent resistance of the internal post Pi differs from the equivalent resistance of the dominant post Pm.

[0167] For illustrative purposes, the above configurations of the main pillar Pm and the internal guide pillar Pi are given. Various configurations of the main pillar Pm and the internal guide pillar Pi are within the scope of some embodiments of this disclosure. For example, in various embodiments, the main pillar Pm or the internal guide pillar Pi includes various numbers of vias between individual conductive layers, as will be further explained below. Figure 4A This will be discussed.

[0168] Figure 4A To enable the implementation of some embodiments of this disclosure Figure 2 A schematic diagram of the cross-sectional views of various main columns used in the power supply network 200. For example... Figure 4A As shown in the diagram, the dominant columns Pm0, Pm1, and Pm2 have different configurations. Dominant column Pm0 corresponds to... Figure 3A The dominant post Pm. Compared to the dominant post Pm0, in some embodiments, the number of through-holes disposed between at least two adjacent layers in the dominant posts Pm1 and / or Pm2 is greater than 1. For example, in Figure 4A In one example, the number of vias for the main pillars Pm0, Pm1, and Pm2 located between the conductive layer Mb+1 and the bottom conductive layer Mb are 1, 2, and 3, respectively. In another example, the number of vias for the main pillars Pm0, Pm1, and Pm2 located between the conductive layer Mb+3 and the conductive layer Mb+2 are 1, 1, and 2, respectively.

[0169] like Figure 4A The diagram illustrates that when the number of vias between any two adjacent layers is greater than one, the vias are positioned between the two adjacent layers and coupled in parallel. Because more vias in a conductive layer provide greater conductivity, more vias in a layer therefore result in lower resistance within the same layer. In other words, the resistance between two adjacent conductive layers with two vias is less than the resistance between two adjacent layers with one via. Therefore, for example in... Figure 4A In the process, the resistance of the dominant column Pm2 is less than the resistance of the dominant column Pm1, and the resistance of the dominant column Pm1 is less than the resistance of the dominant column Pm0.

[0170] Figure 4B Illustrations of some embodiments according to this disclosure Figure 4A A schematic diagram of the equivalent circuit 400 of the dominant column Pm1. Figure 4B As shown in the illustration, targeting Figure 4A The dominant pillar Pm1, the equivalent circuit 400 shows resistors Rt-1, Rb+2, Rb+1, Rb, etc. (corresponding to Figure 4A (Each via is present in the structure), and these resistors are connected in series from the top conductive layer Mt to the bottom conductive layer Mb. Therefore, the equivalent resistance of the main pillar Pm1 can be calculated and obtained by summing the resistances of the series-connected resistors.

[0171] Figure 4A and Figure 4B The configurations and corresponding equivalent circuits of the central guide pillars are given for illustrative purposes. Various configurations of the guide pillars and their corresponding equivalent circuits are within the scope of some embodiments of this disclosure. For example, in various embodiments, in addition to those illustrated in... Figure 4AIn addition to the main conductive post Pm, the internal conductive post Pi also has one or more through holes disposed between at least two adjacent conductive layers.

[0172] Continue reading Figure 1 In some embodiments, after operation S110, pre-layout simulation is performed on the circuit design in operation S120 to determine whether the circuit design, including the power supply network as described above, meets predetermined specifications. If the circuit design meets the predetermined specifications, method 100 continues to operation S130 as described above. For example, in operation S120, verification processes, such as timing and signal integrity verification, functional verification, and the like, are performed on the circuit design to determine whether the circuit design meets predetermined specifications.

[0173] In some embodiments, during operation S120, in addition to the verification process described above, an IR drop and / or EM pre-check process is performed on the power supply network as discussed above to determine whether the power supply network meets predetermined specifications. The IR drop and EM pre-check process will be referred to... Figures 5 to 9 To elaborate further.

[0174] Figure 5 This is a schematic diagram of circuit 500 applicable to an IR down-check process according to some embodiments of this disclosure, which is related to... Figure 2 The power supply network is described in the discussion. For example... Figure 5 The diagram illustrates that circuit 500 includes operating circuit 530, power supply circuit 520, and [other components]. Figure 2 The power delivery network (PDN) 200 implements a power delivery network (PDN) circuit 510. The PDN circuit 510 is coupled between the power supply circuit 520 and the operating circuit 530. The PDN circuit 510 is used to deliver sufficient power to the operating circuit 530 and withstand sufficient current during power delivery. In other words, the PDN circuit 530 is designed and / or configured with an existing voltage drop to deliver sufficient voltage to the operating circuit 530. To have the existing voltage drop, the PDN circuit 510 can withstand sufficient current corresponding to its power and resistance.

[0175] like Figure 5 The diagram illustratively illustrates that the PDN circuit 510 includes input terminals for receiving voltages VDD and VSS from the power supply circuit 520; and output terminals for outputting voltages VDDI and VSSI to the operation circuit 530. In some embodiments, voltage VDDI is generated by subtracting the IR drop across the PDN circuit 510 from voltage VDD, and voltage VSSI is generated by subtracting the IR drop across the PDN circuit 510 from voltage VSS.

[0176] In some embodiments, the operating circuit 530 is implemented via a driver circuit and is used to operate with a peak current of, for example, 50 mA. When the operating circuit 530 operates with the peak current, the peak current flows across the PDN circuit 510, and therefore, the IR drop across the PDN circuit 510 can be calculated and obtained based on the peak current and resistance of the PDN circuit 510, which will be discussed in more detail below. The aforementioned IR drop across the PDN circuit 510 is then used to determine whether the IR drop meets the IR drop specification.

[0177] Figure 6 This is a schematic diagram of a circuit 600 suitable for an EM pre-inspection process according to some embodiments of this disclosure, which is related to... Figure 2 The discussion focuses on the execution of the power supply network. (and...) Figure 5 Compared to the embodiments described above, in addition to including the PDN circuit 510 and power supply circuit 520, Figure 6 Circuit 600 also includes operating circuit 630. PDN circuit 510 is coupled between power supply circuit 520 and operating circuit 630.

[0178] In some embodiments, the operating circuit 630 is implemented via an operational amplifier (OPAMP) circuit and is used to operate with an average current of, for example, 1 mA. When the operating circuit 630 operates with an average current, this indicates that the average current is the minimum current required for the operating circuit 630 to flow through the PDN circuit 510. This average current flowing through the PDN circuit 510 is then used to determine whether the current meets the EM specification.

[0179] Figure 7 This is a flowchart of a method 700 applicable to an IR down-check process according to some embodiments of this disclosure, which is related to... Figure 2 The discussion concerns the execution of a power supply network. In some embodiments, method 700 is performed by executing an EDA tool to perform an IR drop pre-check process on the power supply network in order to determine whether the IR drop of the power supply network meets the IR drop specification.

[0180] Figure 8A This is a schematic diagram of a power supply network 800 according to some embodiments of the present disclosure. Figure 8B Illustrations of some embodiments according to this disclosure Figure 8A A schematic diagram of the equivalent resistance networks 802 and 804 of the power supply network 800 in the diagram. Figures 8C to 8E Illustrations of various embodiments according to this disclosure Figure 8A A schematic diagram illustrating the changes in the power supply network 800. For ease of understanding, see method 700 below. Figures 8A to 8E Let's discuss this.

[0181] against Figure 8A The diagram illustrates a power supply network 800 comprising four power rails disposed in a conductive layer Mt-1 and four power rails disposed in a top conductive layer Mt above the conductive layer Mt-1. These power rails together form the power grid as described above. Furthermore, in the layout view, the power supply network 800 further includes eight main posts Pm disposed at the intersections of the power rails in the top conductive layer Mt and the conductive layer Mt-1. The number of power rails and main posts in the power supply network 800 is given for illustrative purposes. Various numbers of conductive rails and main posts in the power supply network 800 are within the contemplated scope of some embodiments of this disclosure.

[0182] for Figure 7 Method 700, in operation S702, provides an IR downsizing specification. In some embodiments, the IR downsizing specification includes parameters in the PDK as discussed above. See Figure 8A The above parameters are associated with the IR drop across the power supply network 800. In some embodiments, the IR drop specification is stored in the processor (e.g., Figure 13 The memory of the processor 1320 (e.g., Figure 13 It is stored in memory 1310 for access.

[0183] exist Figure 7 In operation S704, the power rails of the power grid are initialized. In some embodiments, to initialize the power rails of the power grid, the number of power rails configured in columns and the number of power rails configured in rows of the power grid are determined. For example, in Figure 8A In the power supply network 800, the number of power rails arranged in columns is determined to be four, and the number of power rails arranged in rows is determined to be four. In some embodiments, an EDA tool is executed to generate a design that includes a power supply network 800 having the determined number of power rails. In some embodiments, when the number of power rails is determined, the area of ​​the power supply network 800 is determined because the distance between two power rails is fixed.

[0184] exist Figure 7 In operation S706, the pillar density of the power supply network is initialized. In some embodiments, to initialize the pillar density, the number of main pillars and / or internal pillars, as discussed above, is initially determined, and the pillars are configured in the power supply network. For example, eight main pillars Pm are initially determined and configured in the power supply network 800, such as... Figure 8AAs illustrated in the figure. In some embodiments, an EDA tool is executed to generate a design that includes a power supply network 800 having a determined number of leads. The lead density of the leads is thus determined using the determined number of leads.

[0185] exist Figure 7 In operation S708, the IR drop of the power supply network is calculated. In some embodiments, in order to calculate the IR drop of the power supply network, the IR drop across the power rails and the conductive posts coupled to those power rails is calculated, which will be discussed in more detail below.

[0186] After operation S708, the calculated IR drop is compared with the IR drop specification in operation S710 to determine whether the IR drop meets the specification. If the calculated IR drop meets the specification, operation S712 is executed, in which the power supply network (PDN) layout is generated. This operation also corresponds to... Figure 1 Operation S130. On the other hand, if the calculated IR drop does not meet the IR drop specification, method 700 continues to operation S714. For further explanation, examples are provided below.

[0187] against Figure 8A and Figure 8B As illustrated, the resistance of power supply network 800 is equivalent to the sum of the resistance of equivalent resistance network 802 and equivalent resistance network 804. Equivalent resistance network 802 includes the resistance of the conductive rails in conductive layer Mt-1 and the resistance of the power rails in the top conductive layer Mt. Equivalent resistance network 804 includes the resistance of the dominant posts Pm. Regarding the illustration of equivalent resistance network 804, each of the dominant posts Pm associated with voltage VDDI includes a resistance coupled between the power rail of the received voltage VDD and the output terminal of the output voltage VDDI. Correspondingly, each of the dominant posts Pm associated with voltage VSSI includes a resistance coupled between the power rail of the received voltage VSS and the output terminal of the output voltage VSSI. Therefore, when the IR drop of power supply network 800 is calculated, the IR drop across the power rails and conductive posts is calculated based on the resistances of equivalent resistance networks 802 and 804 and the current flowing through these equivalent resistance networks.

[0188] In some embodiments, to simplify the calculation of the IR drop of the power supply network 800, the resistance of the equivalent resistance network 802 is ignored because the power rails are made of, for example, a thick upper metal layer. In some embodiments, without considering the resistance of the equivalent resistance network 802, the resistance of the equivalent resistance network 804 corresponding to the dominant post Pm is used to substantially determine the IR drop of the power supply network 800.

[0189] For example, such as Figure 8CAs illustrated, the power supply network 800 includes four dominant pillars associated with the voltage VDD (hereinafter referred to as "VDD dominant pillars" for simplicity) and has no internal pillars for calculating the IR drop. Furthermore, the following conditions are proposed: the IR drop specification is set to 50mV, the peak current is set to 10mA as discussed above, the resistance Rm of each VDD dominant pillar is set to 50 ohms, and the resistance of the equivalent resistance network 802 is ignored as discussed above. Under these conditions, the current Ip flowing through each of the VDD dominant pillars is equal to (10mA / 4) = 2.5mA. Therefore, the IR drop of the power supply network 800 is equal to Ip × Rm = 2.5mA × 50 ohms = 125mV. Because the calculated IR drop is greater than the 50mV IR drop specification of 125mV, the IR drop of the power supply network 800 does not meet the IR drop specification, and therefore method 700 continues to operation S714.

[0190] exist Figure 7 In operation S714, it is determined whether the conductor density, as discussed above, is the maximum conductor density. If the conductor density is not the maximum conductor density, method 700 continues to operation S716, in which the conductor density is modified, as will be discussed in more detail below. On the other hand, if the conductor density is the maximum conductor density, method 700 continues to operation S718, in which the power rail is modified, as will be discussed in more detail below. In other words, if the IR drop of the initially provided power supply network does not meet the IR drop specification, the power supply network is modified. After the power supply network is modified, method 700 then continues to operations S708 and S710 again to determine whether the IR drop meets the IR drop specification. If the calculated IR drop still does not meet the IR drop specification, operations S714, S716 (or S718), S708, and S710 are repeated.

[0191] In some embodiments, to modify the lead density in operation S714, at least one additional conductive lead is added to the power supply network, as discussed above. In some embodiments, internal leads Pi are added to the power supply network as discussed above. Examples are provided below for further explanation.

[0192] For example, in operating S716, see Figure 8C and Figure 8DPower supply network 800 is modified into power supply network 810 by adding a certain number of internal leads Pi, the number of which is the same as the number of main leads Pm. Therefore, for example, power supply network 810 includes four VDD main leads and four internal leads associated with the voltage VDD (hereinafter referred to as "VDD internal leads" for simplicity) to calculate the IR drop. Under this condition, the current Ip flowing through each of the VDD main leads and VDD internal leads is (10mA / 8) = 1.25mA. Therefore, the IR drop of power supply network 800 is equal to Ip × Rm = 1.25mA × 50 ohms = 62.5mV. Because the calculated IR drop is greater than the 50mV IR drop specification of 62.5mV, the IR drop of power supply network 810 still does not meet the IR drop specification, and therefore method 700 continues again to operations S714, S716 (or S718) and S708.

[0193] For example, in operating S716, see Figure 8D and Figure 8E Power supply network 810 is further modified into power supply network 820 by adding a certain number of internal leads Pi, the number of which is the same as the number of main leads Pm. Therefore, for example, power supply network 820 includes four VDD main leads and eight VDD internal leads to calculate the IR drop. Under this condition, the current Ip flowing through each of the VDD main leads and VDD internal leads is (10mA / 12) = 0.83mA. Therefore, the IR drop of power supply network 820 is equal to Ip × Rm = 0.83mA × 50 ohms = 41.5mV. Since the calculated IR drop is 41.5mV, which is less than the 50mV IR drop specification, the IR drop of power supply network 820 meets the IR drop specification. Therefore, method 700 continues to operation S712.

[0194] In some embodiments, Figures 8C to 8E Power supply networks 800, 810, and 820 have the same area, but they each have a different number of internal guide pillars Pi. Therefore, Figures 8C to 8E The lead density of power supply networks 800, 810, and 820 differs from each other. For illustration purposes, the lead density of power supply network 820 is higher than that of power supply networks 800 and 810, and the lead density of power supply network 810 is higher than that of power supply network 800.

[0195] As discussed above, when the lead density is not the maximum lead density, method 700 continues to operation S716, and when the lead density is the maximum lead density, method 700 continues to operation S718. In some embodiments, in order to modify the power rail in operation S718, as discussed above, at least one additional power rail is added to the power supply network. In some embodiments, at least one power rail in conductive layer Mt-1 or in the top conductive layer Mt is added to the power supply network.

[0196] In some embodiments, after modifying the power rails in operation S718, the IR drop of the power supply network may not meet the IR drop specification in S710. However, the post density of the modified power supply network will not be the maximum post density because at least one additional power rail is available for the additional post to be added. In such embodiments, method 700 will again continue to operations S716, S708, and S710 until the IR drop of the modified power supply network meets the IR drop specification.

[0197] The above illustrations contain illustrative operations, but the operations need not be performed in the order shown. According to the spirit and scope of various embodiments of this disclosure, operations may be added, substituted, reordered, and / or eliminated as appropriate. For example, in various embodiments, operation S706 is performed before operation S704.

[0198] Figure 9 This is a flowchart of a method 900 applicable to an EM pre-inspection process according to some embodiments of this disclosure, the EM pre-inspection process being as described in... Figure 2 The discussion concerns the execution of a power supply network. In some embodiments, method 900 is performed by executing an EDA tool to perform an EM pre-check process on the power supply network to determine whether the EM current of the power supply network meets the EM specification. For ease of understanding, method 900 also refers to Figures 8A to 8E Let's discuss this.

[0199] exist Figure 9 In some embodiments, method 900 includes operations S902, S904, S906, S908, S910, S912, S914, S916, and S918. (And...) Figure 7 Compared to method 700, Figure 9 Operations S904, S906, S912, S914, S916, and S918 correspond to operations S704, S706, S712, S714, S716, and S718, respectively. Figure 9 Operations S902, S908, and S910 differ from those in the following context: Figure 7 The operations described therein will be discussed in more detail below.

[0200] Compared to Figure 7 Operation of S702, in Figure 9 In operation S902, the EM specification is provided. In some embodiments, the IR downgrade specification includes parameters in the PDK as discussed above. See Figure 8A The above parameters are associated with the EM current flowing through the power supply network 800. In some embodiments, the EM specification is stored in a processor (e.g., Figure 13 The memory of the processor 1320 (e.g., Figure 13 It is stored in memory 1310 for access.

[0201] Compared to Figure 7 Operating the S708, in Figure 9 In operation S908, the EM current of the power supply network is calculated. In some embodiments, in order to calculate the EM current of the power supply network, the EM current flowing through the power rails and the conductive posts coupled to the power rails of the power supply network is calculated, which will be discussed in more detail below.

[0202] After operation S908, the calculated EM current is compared with the EM current specification in operation S910 to determine whether the EM current meets the EM specification. If the calculated EM current meets the EM specification, operation S912, which generates the power supply network layout, is executed. This operation also corresponds to... Figure 1 Operation S130. On the other hand, when the calculated EM current does not meet the EM specification, method 900 continues to operation S914, which corresponds to the operation regarding... Figure 7 The operations discussed.

[0203] For example, consider the following conditions: the VDD EM specification is set to 1mA (or 1000μA), the EM current Im of the main conductor is set to 100μA, and the EM current Ii of the internal conductor is set to 100μA. Under these conditions, for Figure 8C The power supply network 800, the VDD EM current flowing through the VDD main conductor and the internal VDD conductors is equal to (Im×4)+(Ii×0)=(100μA×4)+(100μA×0)=400μA. Since the calculated EM current is less than 1mA (or 1000μA) according to the EM specification of 400μA, therefore... Figure 8C The EM current of the power supply network 800 does not meet the EM specification, and therefore... Figure 9 Method 900 continues to operation S914 and then continues to operation S916 (or S918) and S908.

[0204] Correspondingly, after operating the S916, Figure 8C The power supply network 800 has been modified as follows: Figure 8DThe power supply network 810 is illustrated in the figure. Under these conditions, the VDD EM current flowing through the VDD main conductor and the internal VDD conductors is equal to (Im×4)+(Ii×4)=(100μA×4)+(100μA×4)=800μA. Because the calculated EM current is still less than 800μA, which is less than the EM specification of 1mA (or 1000μA), the EM current of the power supply network 810 does not meet the EM specification, and therefore... Figure 9 Method 900 continues to operation S914 and then continues again to operation S916 (or S918) and S908.

[0205] Correspondingly, after operating the S916, Figure 8D The power supply network 810 has been modified as follows: Figure 8E The power supply network 820 is illustrated in the diagram. Under these conditions, the VDD EM current flowing through the VDD main conductor and the internal VDD conductors is equal to (Im×4)+(Ii×8)=(100μA×4)+(100μA×8)=1200μA. Since the calculated EM current is greater than 1mA (or 1000μA) according to the EM specification of 1200μA, therefore... Figure 8E The EM current of the power supply network 820 meets the EM specification. Therefore, method 900 continues to operation S912.

[0206] Figures 8C to 8E The above-mentioned number of main guide pillars Pm and internal guide pillars Pi are given for illustrative purposes. Various numbers of main guide pillars Pm and internal guide pillars Pi are within the contemplated scope of some embodiments of this disclosure. For example, in various embodiments, additional internal guide pillars Pi are... Figure 8E Further additions will be made to the power supply network 820, this move will refer to Figure 10 To elaborate further.

[0207] Figure 10 Illustrations of various embodiments according to this disclosure Figure 8A A schematic diagram of other variations of the power supply network 800. (For...) Figure 10 The diagram corresponds to Figure 8A The power supply network of the 800 has been modified to power supply network 1020.

[0208] Compared to Figure 8E The power supply network 820 contains more internal leads Pi, and the number of internal leads Pi in power supply network 1020 is three times (3X) the number of main leads Pm in power supply network 820. In other words, the total number of leads in power supply network 1020 is four times (4X) the total number of leads in power supply network 800. Therefore, based on the information regarding... Figures 8C to 8EBased on the above discussion, the IR drop of power supply network 1020 is 0.25 times (0.25X) that of power supply network 800, and the EM current of power supply network 1020 is four times (4X) that of power supply network 820.

[0209] Looking back Figure 1 Although both the IR drop pre-check process and the EM pre-check process described above are applicable to pre-layout simulation during operation S120, in various embodiments, the IR drop pre-check process and the EM pre-check process can be performed independently of each other. In other words, in various embodiments, at least one of the IR drop pre-check process or the EM pre-check process is performed during pre-layout simulation.

[0210] In some embodiments, after operation S120, which includes performing an IR downcheck process and / or an EM downcheck process, the power supply network layout of the IC is generated based on the power supply network design as described above. After the power supply network layout is generated, the circuit layout of the IC is generated based on the circuit design as described above. In some embodiments, at least one element in the IC is manufactured based on the power supply network layout and the IC's circuit layout.

[0211] As discussed above, the calculation of the IR drop of the power supply network is related to... Figure 5 The circuit 500 is associated with it, and the calculation of the EM of the power supply network is related to... Figure 6 The circuit 600 is associated with this. To improve the accuracy of IR drop and EM calculations, Figure 11 Circuit 1100 is applicable in some embodiments.

[0212] Figure 11 This is a schematic diagram of circuit 1100 applicable to an IR drop and / or EM pre-check process according to various embodiments of this disclosure, which is related to... Figure 2 The discussion focuses on the execution of the power supply network. (Regarding...) Figure 11 The illustration, and Figure 5 or Figure 6 In contrast, circuit 1100 includes a driver 1102 and a controller 1104, each of which is coupled to PDN circuit 510. In some embodiments, driver 1102 has a higher current consumption than controller 1104. Therefore, in some embodiments, driver 1102 is also referred to as a “hot device” and controller 1104 is also referred to as a “cold device”.

[0213] In some embodiments, to improve the accuracy of IR drop and / or EM calculations, the ratio of the hot device area to the total device area (e.g., hot device area plus cold device area) is used as a coefficient for calculating the IR drop and / or EM of the power supply network. For example, when the device area of ​​driver 1102 is 80 and the device area of ​​controller 1104 is 20, the ratio is equal to 80 / (80+20) = 0.8. In such embodiments, the IR drop of the power supply network is modified to the value of (IR drop) / ratio, and the EM current of the power supply network is modified to the value of EM×ratio. Examples are provided below for further explanation.

[0214] As mentioned above Figure 8C In the example of the power supply network 800 discussed, the current Ip flowing through each of the VDD master pillars becomes (10mA / 4) / 0.8 = 3.125mA. Therefore, the IR drop of the power supply network 800 is equal to Ip × Rm = 3.125mA × 50 ohms = 156.25mV. The calculation of the IR drop for other power supply networks can be inferred by analogy, and therefore these power supply networks are not other details in this paper.

[0215] Correspondingly, in the above text regarding Figure 8C In the example discussed for power supply network 800, the VDD EM current flowing through the VDD main conductor and the internal VDD conductors is equal to (Im×4+Ii×0)×0.8=(100μA×4+100μA×0)×0.8=320μA. EM calculations for other power supply networks can be inferred by analogy, and therefore these power supply networks are not part of the other details discussed herein.

[0216] As discussed above, in the case of power supply networks, IR drop and / or EM pre-checks can be performed during pre-layout simulation. Therefore, IR drop and / or EM issues can be optimized early in the pre-layout simulation. Furthermore, the power supply network layout can be generated before the circuit layout is generated. Therefore, the area of ​​the power supply network layout can be known and predicted before the entire circuit layout is generated, thus reducing the time spent designing the entire layout. See [link to previous section]. Figure 12 To illustrate with examples.

[0217] Figure 12 According to some embodiments of this disclosure Figure 1 A schematic diagram of the circuit layout 1200 generated in method 100. For Figure 12As illustrated in the diagram, circuit layout 1200 includes regions 1210, 1220, and 1230. In some embodiments, each of regions 1210 and 1220 has a fixed area in circuit layout 1200. Region 1230 includes blocks 1230a, 1230b, 1230c, and 1230d. In some embodiments, block 1230a is implemented with transistors and overlaid by a power supply network layout. Therefore, the power supply network layout is implemented to deliver power to the transistors in block 1230a. In some embodiments, block 1230a implemented with transistors is also referred to as an active region.

[0218] In some embodiments, the area of ​​block 1230a is determined to be larger than the area of ​​the power supply network layout, for example, during method 100, method 700, method 900, or a combination thereof. Because the area of ​​block 1230a is larger than the area of ​​the power supply network layout, the area of ​​block 1230 does not need to be changed and can remain the same.

[0219] On the other hand, in some embodiments, the area of ​​block 1230a is determined to be smaller than the area of ​​the power supply network layout, for example, during method 100, method 700, method 900, or a combination thereof. Because the area of ​​block 1230a is smaller than the area of ​​the power supply network layout, the area of ​​region 1230 needs to be enlarged to have space for the power supply network layout to be placed, so as to prevent the power supply network layout from affecting other components in region 1230.

[0220] Based on the above, since the power supply network layout is generated before the circuit layout 1200 is generated, as discussed above, the area of ​​the power supply network layout is known before the circuit layout 1200 is generated. Therefore, the area of ​​region 1230 can be estimated based on the area of ​​the power supply network layout. Therefore, the area of ​​region 1230 can be predicted. For example, in Figure 12 In this context, when the dashed box indicates the area of ​​block 1230a and the solid line of 1230a indicates the area of ​​the power supply network layout, the area of ​​the power supply network layout is larger than the area of ​​block 1230a. In such instances, the predicted area of ​​block 1230a is applied to the area enclosed by the solid line.

[0221] In some methods, the area of ​​the transistor block must be enlarged because the power supply network layout area is too large. Furthermore, the area of ​​the power supply network layout is only known after the entire circuit layout has been generated. In such cases, the entire layout design must be reworked to allow space for the power supply network layout.

[0222] Compared to the methods described above, the area of ​​the power supply network layout can be known before the circuit layout is generated. The area of ​​the transistor-containing blocks can be predicted before the entire circuit layout is generated. Therefore, if the area of ​​the power supply network layout is larger than the area of ​​the transistor-containing blocks, the layout design only needs to be reworked by designing the power supply network in an earlier stage of the design process. The time spent designing the circuit layout is thus reduced.

[0223] Figure 13 For the purpose of performing certain embodiments of this disclosure regarding Figure 1 , Figure 7 and Figure 9 This is a schematic diagram of an integrated circuit (IC) design system 1300. In some embodiments, the design system 1300 is implemented using a computer-aided design (CAD) system. For the purposes of this illustration, the design system 1300 includes at least a memory 1310, a processor 1320, and a manufacturing tool 1350 connected via a system bus 1305. The processor 1320 communicates with the memory 1310 via the system bus 1305 and accesses data stored in the memory 1310 to perform operations related to... Figure 1 , Figure 7 and Figure 9 The operation.

[0224] In some embodiments, memory 1310 is implemented via at least one computer-readable storage medium including, for example, a computer-readable storage device. In some embodiments, memory 1310 is used to store instructions (e.g., electronic design automation (EDA) tools) 1318 for performing various design processes as described above. Memory 1310 is also used to store design information for the various design processes as described above, for example, in the form of a process design kit (PDK) 1314. In some embodiments, the design information (e.g., PDK 1314) includes parameters associated with conductive rails and conductive posts in a power supply network, as described above. In various embodiments, the design information (e.g., PDK 1314) also includes a base-specific set of documents, including, but not limited to, technical documents, library element libraries, design rules, and the like, for a specific technology node.

[0225] In some embodiments, processor 1320 is implemented by a single dedicated processor that performs multiple processes as described above during IC design (or executes instructions 1318 to perform multiple processes as described above).

[0226] In some embodiments, manufacturing tool 1350 is coupled to processor 1320. Manufacturing tool 1350 is used to manufacture the integrated circuit and / or at least one element of the integrated circuit as described above, based on the power supply network layout and circuit layout of the IC as described above.

[0227] The number of memory 1310 and processor 1320 is given for illustrative purposes. Various numbers of memory 1310 and processor 1320 are within the expected range of some embodiments of this disclosure. For example, in various embodiments, design system 1300 includes a plurality of dedicated processors, each of which performs one or more of the processes discussed above.

[0228] In some embodiments, the design system 1300 is configured to receive design inputs for an IC at a particular technology node, the design inputs including, for example, design specifications 1312 stored in memory 1310. The processor 1320 accesses and uses the design specifications 1312 earlier in the design process as described above in order to generate an IC design layout 1316 in an on-the-fly manner, which can be used to manufacture an IC device.

[0229] In some embodiments, a method for generating circuit layout is disclosed, characterized by comprising the following operations: generating a circuit design based on design information for an integrated circuit, the circuit design including an initial power supply network (PDN) for the integrated circuit; performing a pre-layout simulation on the circuit design to determine whether the circuit design including the initial power supply network meets a predetermined specification; and, if the circuit design meets the predetermined specification, generating a power supply network layout for the integrated circuit; and, after generating the power supply network layout, generating a circuit layout for the integrated circuit. In some embodiments, the method for generating circuit layout further comprises providing the design information in the form of a process design kit (PDK) to be accessed, wherein the design information includes parameters associated with power rails and conductive pillars in the initial power supply network. In some embodiments, the step of performing the pre-layout simulation on the circuit design including the initial power supply network includes performing at least one of a voltage drop pre-check process or an electromigration pre-check process on the initial power supply network. In some embodiments, the step of performing the voltage drop pre-check process includes calculating a voltage drop across the power rails of the initial power supply network and the conductive posts coupled to the power rails. In some embodiments, the step of performing the electromigration pre-check process includes calculating an electromigration current flowing through the power rails of the initial power supply network and the conductive posts coupled to the power rails. In some embodiments, the circuit layout generation method further includes: modifying the initial power supply network into a modified power supply network when the circuit design does not meet the predetermined specifications, and performing at least one of a voltage drop pre-check process or an electromigration pre-check process on the modified power supply network. In some embodiments, the step of modifying the initial power supply network includes adding at least one additional conductive post to the initial power supply network. In some embodiments, the step of modifying the initial power supply network includes adding at least one additional power rail to the initial power supply network. In some embodiments, the circuit layout generation method further includes fabricating at least one element in the integrated circuit based on the power supply network layout and the circuit layout of the integrated circuit.

[0230] A method for generating circuit layout is also disclosed, characterized by comprising the following operations: performing at least one of a voltage drop pre-check process or an electromigration pre-check process on a circuit design including a power supply network (PDN); generating a power supply network layout for a design layout of an integrated circuit when the circuit design meets a predetermined specification; generating a circuit layout of the design layout of the integrated circuit after generating the power supply network layout; performing a voltage drop and electromigration verification process on the design layout; and generating a final design layout of the integrated circuit when the voltage drop and electromigration requirements are met during the voltage drop and electromigration verification process. In some embodiments, the step of performing the voltage drop pre-check process includes performing a calculation of a voltage drop across a plurality of power rails of the power supply network and a plurality of conductive pillars coupled to the power rails to determine whether the circuit design meets a predetermined specification. In some embodiments, the step of performing the voltage drop pre-check process further includes: increasing a pillar density of the power supply network by adding at least one additional conductive pillar when the circuit design does not meet the predetermined specification. In some embodiments, the step of performing the voltage drop pre-check process further includes modifying the power supply network by adding at least one additional power rail when the lead density of the power supply network is a maximum lead density of the power supply network. In some embodiments, the step of performing the electromigration pre-check process includes performing a calculation of an electromigration current flowing through a plurality of power rails of the power supply network and a plurality of conductive posts coupled to the power rails to determine whether the circuit design meets a predetermined specification. In some embodiments, the step of performing the electromigration pre-check process further includes increasing a lead density of the power supply network when the circuit design does not meet the predetermined specification. In some embodiments, the step of performing the electromigration pre-check process further includes modifying the power supply network by adding at least one additional power rail when the lead density of the power supply network is a maximum lead density of the power supply network. In some embodiments, the step of increasing the density of the conductive pillars in the power supply network includes adding at least one additional conductive pillar to the power supply network, wherein the power supply network includes conductive pillars, each of which includes a via coupled between a bottom layer and a top layer, and each of the at least one additional conductive pillar includes a via coupled between the bottom layer and a conductive layer below the top layer.

[0231] A circuit layout generation system is also disclosed, characterized by comprising a memory and at least one processor. The memory stores design information for an integrated circuit, the design information including parameters associated with a plurality of power rails and a plurality of conductive posts coupled to the power rails. The at least one processor communicates with the memory and performs operations including: generating a circuit design based on the design information, the circuit design including a power supply network (PDN) for the integrated circuit; performing at least one of a voltage drop pre-check process or an electromigration pre-check process on the circuit design including the power supply network to determine whether the circuit design meets a predetermined specification; when the circuit design meets the predetermined specification, generating a power supply network layout and then generating a circuit layout for a design layout of the integrated circuit; performing a voltage drop and electromigration verification process on the design layout; and when the voltage drop and electromigration requirements are met during the voltage drop and electromigration verification process, generating a final design layout of the integrated circuit. In some embodiments, in order to perform the voltage drop pre-check process, the at least one processor is configured to perform a calculation of a voltage drop across the power rails of the power supply network and the conductive posts coupled to the power rails. In some embodiments, in order to perform the electromigration pre-check process, the at least one processor is configured to perform a calculation of an electromigration current flowing through the power rails of the power supply network and the conductive posts coupled to the power rails.

[0232] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of some embodiments of this disclosure. Those skilled in the art should understand that some embodiments of this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same benefits. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of some embodiments of this disclosure.

Claims

1. A method for generating a circuit layout, characterized in that, Includes the following steps: A circuit design is generated based on design information for an integrated circuit, the circuit design including an initial power supply network for the integrated circuit. A pre-layout simulation is performed on the circuit design to determine whether the circuit design, which includes the initial power supply network, meets a predetermined specification. When the circuit design meets the predetermined specifications, The power supply network layout that produces the integrated circuit, and After the power supply network layout is generated, a circuit layout for the integrated circuit is generated; and When the circuit design does not meet the predetermined specifications, Based on a relationship between a lead density and a maximum lead density of the initial power supply network, the initial power supply network is modified into a modified power supply network.

2. The method as described in claim 1, characterized in that, Further includes: Provides design information in one form of a process design suite to be accessed. This design information includes parameters associated with the power rails and conductive posts in the initial power supply network.

3. The method as described in claim 1, characterized in that, The step of performing the pre-layout simulation on the circuit design that includes the initial power supply network includes: Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on the initial power supply network.

4. The method as described in claim 3, characterized in that, The steps involved in performing this voltage drop pre-check process include: Perform a calculation of the voltage drop across the power rails of the initial power supply network and the conductive posts coupled to those power rails.

5. The method as described in claim 3, characterized in that, The steps involved in performing this electromigration pre-inspection process include: Perform a calculation of an electromigration current flowing through the power rails of the initial power supply network and coupled to the conductive posts of those power rails.

6. The method as described in claim 1, characterized in that, Further includes: Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on the modified power supply network.

7. The method as described in claim 6, characterized in that, The steps involved in modifying the initial power supply network include: If the density of the conductor pillars in the initial power supply network is not the maximum density, at least one additional conductor pillar shall be added to the initial power supply network.

8. The method as described in claim 6, characterized in that, The steps involved in modifying the initial power supply network include: When the conductor density of the initial power supply network is the maximum conductor density, at least one additional power rail is added to the initial power supply network.

9. The method as described in claim 1, characterized in that, Further includes: Based on the power supply network layout and the circuit layout of the integrated circuit, at least one component is manufactured in the integrated circuit.

10. A method for generating a circuit layout, characterized in that, Includes the following steps: Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on a circuit design that includes a power supply network. When the circuit design meets a predetermined specification, a power supply network layout is generated for a design layout of an integrated circuit. After the power supply network layout is generated, a circuit layout for the design layout of the integrated circuit is generated. A voltage drop and electromigration verification process was performed on this design layout. When the voltage drop and electromigration requirements are met during the voltage drop and electromigration verification process, a final design layout of the integrated circuit is produced. and When the circuit design does not meet the predetermined specifications, the power supply network is modified into a modified power supply network based on a relationship between a lead density and a maximum lead density of the power supply network.

11. The method as described in claim 10, characterized in that, The steps involved in performing this voltage drop pre-check process include: A calculation is performed across multiple power rails of the power supply network and multiple conductive posts coupled to those power rails to determine whether the circuit design meets the predetermined specifications.

12. The method as described in claim 11, characterized in that, The steps involved in performing this voltage drop pre-check process further include: When the circuit design does not meet the predetermined specifications and the conductor density of the power supply network is not the maximum conductor density. The density of the conductive posts in the power supply network is increased by adding at least one additional conductive post.

13. The method as described in claim 11, characterized in that, The steps involved in performing this voltage drop pre-check process further include: When the circuit design does not meet the predetermined specifications and the conductor density of the power supply network is the maximum conductor density. The power supply network is modified by adding at least one additional power rail.

14. The method as described in claim 10, characterized in that, The steps involved in performing this electromigration pre-inspection process include: A calculation is performed on the electromigration current flowing through the multiple power rails of the power supply network and the multiple conductive posts coupled to the power rails to determine whether the circuit design meets the predetermined specifications.

15. The method as described in claim 14, characterized in that, The steps of performing this electromigration pre-check process further include: When the circuit design does not meet the predetermined specifications and the conductor density of the power supply network is not the maximum conductor density. Increase the density of the conductors in the power supply network.

16. The method as described in claim 14, characterized in that, The steps of performing this electromigration pre-check process further include: When the circuit design does not meet the predetermined specifications and the conductor density of the power supply network is the maximum conductor density. The power supply network is modified by adding at least one additional power rail.

17. The method as described in claim 15, characterized in that, The step of increasing the density of the conductors in the power supply network includes: Add at least one additional conductive post to the power supply network. The power supply network includes conductive pillars, each of which includes a via coupled between a bottom layer and a top layer, and each of the at least one additional conductive pillar includes a via coupled between the bottom layer and a conductive layer below the top layer.

18. A system for generating circuit layouts, characterized in that, Include: A memory for storing design information for an integrated circuit, the design information including parameters associated with a plurality of power rails and a plurality of conductive posts coupled to the power rails; and At least one processor, which communicates with the memory and performs operations including: Based on this design information, a circuit design is generated, which includes a power supply network for the integrated circuit. Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on the circuit design that includes the power supply network to determine whether the circuit design meets a predetermined specification. When the circuit design meets the predetermined specifications, a power supply network layout is generated and then a circuit layout for a design layout of the integrated circuit is generated. A voltage drop and electromigration verification process was performed on this design layout. When the voltage drop and electromigration requirements are met during the voltage drop and electromigration verification process, a final design layout of the integrated circuit is produced. and When the circuit design does not meet the predetermined specifications, the power supply network is modified into a modified power supply network based on a relationship between a lead density and a maximum lead density of the power supply network.

19. The system as claimed in claim 18, characterized in that, In order to perform this voltage drop pre-check process The at least one processor is used to perform a calculation of a voltage drop across the power rails of the power supply network and the conductive posts coupled to the power rails.

20. The system as described in claim 18, characterized in that, In order to perform this electromigration pre-check process, The at least one processor is used to perform a calculation of an electromigration current flowing through the power rails of the power supply network and coupled to the conductive posts of the power rails.

21. A method for generating a circuit layout, characterized in that, Includes the following steps: A circuit design is generated based on design information for an integrated circuit, the circuit design including an initial power supply network for the integrated circuit. A pre-layout simulation is performed on the circuit design to determine whether the circuit design, which includes the initial power supply network, meets a predetermined specification. When the circuit design meets the predetermined specifications, a circuit layout of the integrated circuit is generated; and When the circuit design does not meet the predetermined specifications, at least one additional conductive post or at least one additional power rail is added to the initial power supply network according to a relationship between a post density and a maximum post density.

22. The method as described in claim 21, characterized in that, Further includes: Provides design information in one form of a process design suite to be accessed. This design information includes parameters associated with the power rails and conductive posts in the initial power supply network.

23. The method as described in claim 21, characterized in that, The step of performing the pre-layout simulation on the circuit design that includes the initial power supply network includes: Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on the initial power supply network.

24. The method as described in claim 23, characterized in that, The steps involved in performing this voltage drop pre-check process include: Perform a calculation of the voltage drop across the power rails of the initial power supply network and the conductive posts coupled to those power rails.

25. The method as described in claim 23, characterized in that, The steps involved in performing this electromigration pre-inspection process include: Perform a calculation of an electromigration current flowing through the power rails of the initial power supply network and coupled to the conductive posts of those power rails.

26. The method as described in claim 21, characterized in that, Further includes: Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on a modified power supply network.

27. The method as described in claim 21, characterized in that, Further includes: When the density of the conductor pillars in the initial power supply network is not the maximum density, at least one additional conductor pillar is added to the initial power supply network.

28. The method as described in claim 21, characterized in that, Further includes: When the conductor density of the initial power supply network is the maximum conductor density, at least one additional power rail is added to the initial power supply network.

29. The method as described in claim 21, characterized in that, Further includes: Based on a power supply network layout and the circuit layout of the integrated circuit, at least one element is manufactured in the integrated circuit.

30. A method for generating a circuit layout, characterized in that, Includes the following steps: Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on a circuit design that includes a power supply network. During at least one of the voltage drop pre-check process or the electromigration pre-check process, when the circuit design meets a predetermined specification, a circuit layout for a design layout of an integrated circuit is generated to perform a voltage drop and electromigration verification process on the design layout. and During at least one of the voltage drop pre-check process or the electromigration pre-check process, if the circuit design does not meet the predetermined specification, the pillar density of the power supply network is modified according to a relationship between a pillar density and a maximum pillar density of the power supply network.

31. The method as described in claim 30, characterized in that, The steps involved in performing this voltage drop pre-check process include: A calculation is performed across multiple power rails of the power supply network and multiple conductive posts coupled to those power rails to determine whether the circuit design meets the predetermined specifications.

32. The method as described in claim 31, characterized in that, The steps involved in performing this voltage drop pre-check process further include: When the circuit design does not meet the predetermined specifications and the conductor density of the power supply network is not the maximum conductor density. The density of the conductive posts in the power supply network is increased by adding at least one additional conductive post.

33. The method as described in claim 32, characterized in that, The steps involved in performing this voltage drop pre-check process further include: When the circuit design does not meet the predetermined specifications and the conductor density of the power supply network is the maximum conductor density. The power supply network is modified by adding at least one additional power rail.

34. The method as described in claim 30, characterized in that, The steps involved in performing this electromigration pre-inspection process include: A calculation is performed on the electromigration current flowing through the multiple power rails of the power supply network and the multiple conductive posts coupled to the power rails to determine whether the circuit design meets the predetermined specifications.

35. The method as described in claim 34, characterized in that, The steps of performing this electromigration pre-check process further include: When the circuit design does not meet the predetermined specifications and the conductor density of the power supply network is not the maximum conductor density. Increase the density of the conductors in the power supply network.

36. The method as described in claim 35, characterized in that, The steps of performing this electromigration pre-check process further include: When the circuit design does not meet the predetermined specifications and the conductor density of the power supply network is the maximum conductor density. The power supply network is modified by adding at least one additional power rail.

37. The method as described in claim 35, characterized in that, The step of increasing the density of the conductors in the power supply network includes: Add at least one additional conductive post to the power supply network. The power supply network includes conductive pillars, each of which includes a via coupled between a bottom layer and a top layer, and each of the at least one additional conductive pillar includes a via coupled between the bottom layer and a conductive layer below the top layer.

38. A system for generating circuit layouts, characterized in that, Include: A memory for storing design information for an integrated circuit, the design information including parameters associated with a plurality of power rails and a plurality of conductive posts coupled to the power rails; and At least one processor, which communicates with the memory and performs operations including: Perform a pre-layout simulation on a circuit design to determine whether the circuit design includes a power supply network and meets a predetermined specification. A final design layout for the integrated circuit is generated when the voltage drop and electromigration requirements are met during a voltage drop and electromigration verification process. When the circuit design does not meet the predetermined specifications and the pillar density of the power supply network is not a maximum pillar density, at least one additional conductive pillar shall be added to the power supply network; and If the circuit design does not meet the predetermined specifications and the post density of the power supply network is the maximum post density, at least one additional power rail shall be added to the power supply network.

39. The system as described in claim 38, characterized in that, In order to perform this pre-layout simulation, The at least one processor is used to perform a calculation of a voltage drop across the power rails of the power supply network and the conductive posts coupled to the power rails.

40. The system as described in claim 38, characterized in that, In order to perform this pre-layout simulation, The at least one processor is used to perform a calculation of an electromigration current flowing through the power rails of the power supply network and coupled to the conductive posts of the power rails.

41. A method for generating a circuit layout, characterized in that, Includes the following steps: A circuit design is generated based on design information for an integrated circuit, the circuit design including an initial power supply network for the integrated circuit. A pre-layout simulation is performed on the circuit design to determine whether the circuit design, which includes the initial power supply network, meets a predetermined specification. When the circuit design meets the predetermined specifications, a circuit layout of the integrated circuit is generated; If the circuit design does not meet the predetermined specifications, the density of a pillar in the initial power supply network is repeatedly modified until the circuit design meets the predetermined specifications, thereby producing the circuit layout of the integrated circuit; and Perform a post-layout simulation on the circuit layout.

42. The method as described in claim 41, characterized in that, The steps involved in simulating the circuit layout after its execution include: A voltage drop and electromigration verification process was performed on the circuit layout.

43. The method as described in claim 41, characterized in that, The step of performing the pre-layout simulation on the circuit design that includes the initial power supply network includes: Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on the initial power supply network.

44. The method as described in claim 43, characterized in that, The steps involved in performing this voltage drop pre-check process include: Perform a calculation of the voltage drop across the power rails of the initial power supply network and the conductive posts coupled to those power rails.

45. The method as described in claim 43, characterized in that, The steps involved in performing this electromigration pre-inspection process include: Perform a calculation of an electromigration current flowing through the power rails of the initial power supply network and coupled to the conductive posts of those power rails.

46. ​​The method as described in claim 41, characterized in that, Further includes: Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on a modified power supply network.

47. The method as described in claim 41, characterized in that, The step of modifying the conductor density of the initial power supply network includes: If the density of the conductors in the initial power supply network is not a maximum conductor density, at least one additional conductor is added to the initial power supply network.

48. The method as described in claim 41, characterized in that, The step of modifying the conductor density of the initial power supply network includes: When the conductor density of the initial power supply network is at a maximum conductor density, at least one additional power rail is added to the initial power supply network.

49. The method as described in claim 41, characterized in that, Further includes: Based on a power supply network layout and the circuit layout of the integrated circuit, at least one element is manufactured in the integrated circuit.

50. A method for generating a circuit layout, characterized in that, Includes the following steps: Perform at least one of a voltage drop pre-check process or an electromigration pre-check process on a circuit design including a power supply network, wherein the power supply network includes a plurality of internal leads and a plurality of main leads. During at least one of the voltage drop pre-check process or the electromigration pre-check process, when the circuit design meets a predetermined specification, a circuit layout for a design layout of an integrated circuit is generated to perform a voltage drop and electromigration verification process on the design layout. and During at least one of the voltage drop pre-check process or the electromigration pre-check process, if the circuit design does not meet the predetermined specifications, a first number of the internal leads is increased and a second number of the main leads is maintained.

51. The method as described in claim 50, characterized in that, The steps involved in performing this voltage drop pre-check process include: A calculation is performed across multiple power rails of the power supply network and multiple conductive posts coupled to those power rails to determine whether the circuit design meets the predetermined specifications. These conductive pillars include internal conductive pillars and main conductive pillars.

52. The method as described in claim 50, characterized in that, These internal guide posts are coupled to a first power rail in a first layer.

53. The method as described in claim 52, characterized in that, The main columns are coupled to a second power rail in a second layer above the first layer via a first power rail in the first layer.

54. The method as described in claim 50, characterized in that, The steps involved in performing this electromigration pre-inspection process include: A calculation is performed on the electromigration current flowing through multiple power rails of the power supply network and multiple conductive posts coupled to those power rails to determine whether the circuit design meets the predetermined specifications. These conductive pillars include internal conductive pillars and main conductive pillars.

55. The method as described in claim 54, characterized in that, The steps of performing this electromigration pre-check process further include: When the circuit design does not meet the predetermined specifications and the density of one conductor in the power supply network is not a maximum conductor density. Increase the density of the conductors in the power supply network.

56. The method as described in claim 55, characterized in that, The steps of performing this electromigration pre-check process further include: When the circuit design does not meet the predetermined specifications and the conductor density of the power supply network is the maximum conductor density. The power supply network is modified by adding at least one additional power rail.

57. The method as described in claim 55, characterized in that, The step of increasing the density of the conductors in the power supply network includes: Add at least one additional conductive post to the power supply network.

58. A system for generating circuit layouts, characterized in that, Include: A memory for storing design information for an integrated circuit, the design information including parameters associated with a plurality of power rails and a plurality of conductive posts coupled to the power rails; and At least one processor, which communicates with the memory and performs operations including: Perform a pre-layout simulation on a circuit design to determine whether the circuit design includes a power supply network and meets a predetermined specification. A final design layout for the integrated circuit is generated when the voltage drop and electromigration requirements are met during a voltage drop and electromigration verification process. When the circuit design does not meet the predetermined specifications and the lead density of the power supply network is a maximum lead density, at least one additional power rail shall be added to the power supply network; and After at least one additional power rail is added, at least one additional conductive post is added to the power supply network.

59. The system as described in claim 58, characterized in that, In order to perform this pre-layout simulation, The at least one processor is used to perform a calculation of a voltage drop across the power rails of the power supply network and the conductive posts coupled to the power rails.

60. The system as described in claim 58, characterized in that, In order to perform this pre-layout simulation, The at least one processor is used to perform a calculation of an electromigration current flowing through the power rails of the power supply network and coupled to the conductive posts of the power rails.

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