Source driver integrated circuit, display device, and method for operating the display device

Abstract

Source driver integrated circuit, display device, and method for operating a display device. A source driver integrated circuit IC according to the present disclosure is provided, the source driver IC comprising: a first buffer in which first sensing data transmitted from the first source driver IC is stored; a sensing data generating circuit configured to sense a characteristic of a driving element included in each pixel and generate second sensing data; a second buffer in which the second sensing data is stored; a control circuit configured to generate a selection signal in response to an operation command; and a selector configured to transmit one of the first sensing data stored in the first buffer and the second sensing data stored in the second buffer to the second source driver IC in response to the selection signal.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to an organic light emitting diode (OLED) display device. Background Art

[0002] The display panel transmits various visual information to people through images. A display driver integrated circuit (IC) is a semiconductor chip used to drive a plurality of pixels included in a light emitting diode (LED) display panel, an organic LED (OLED) display panel, and a liquid crystal display (LCD) panel.

[0003] Display driver ICs may be divided into display driver ICs for mobile devices used in mobile devices such as smartphones and display driver ICs for large and medium-sized products used in large and medium-sized electronic products such as tablet personal computers (PCs) or televisions (TVs).

[0004] The display driver IC includes a plurality of gate driver ICs and a plurality of source driver ICs. The plurality of gate driver ICs play a role in turning pixels on and off, and the plurality of source driver ICs play a role in generating differences in colors to be represented by the pixels.

[0005] When the above-described display driver IC is applied to an OLED display panel, a plurality of source driver ICs sense characteristic information (eg, threshold voltage or mobility) of a driving transistor formed in each pixel and transmit the characteristic information to a timing controller.

[0006] However, the physical length of transmitting the sensing data is inevitably different depending on the position of each source driver IC on the OLED display panel. Therefore, the time required for each source driver IC to transmit the sensing data is also inevitably different, so there is a problem that difficulties may occur when the timing controller processes the sensing data. Summary of the invention

[0007] The present disclosure relates to providing a source driver integrated circuit (IC), a display device including the source driver IC, and a method of operating the display device, wherein the source driver IC is capable of selectively outputting sensing data or self-sensing data received from a previous source driver IC in response to a control command.

[0008] The present disclosure also relates to providing a source driver IC which enables a timing controller to receive sensing data acquired by a plurality of source driver ICs through a single source driver IC, a display device including the same, and a method of operating the display device.

[0009] According to one aspect of the present disclosure, there is provided a source driver IC including: a first buffer in which first sensing data transmitted from the first source driver IC is stored; a sensing data generating circuit configured to sense characteristics of a driving element included in each pixel and generate second sensing data; a second buffer in which the second sensing data is stored; a control circuit configured to generate a selection signal in response to an operation command; and a selector configured to transmit one of the first sensing data stored in the first buffer and the second sensing data stored in the second buffer to the second source driver IC in response to the selection signal.

[0010] According to another aspect of the present disclosure, a display device is provided, which includes a data driving circuit block, the data driving circuit block including a plurality of source driver integrated circuits (ICs), each of the plurality of source driver ICs being configured to sense characteristics of a driving element included in each pixel and obtain sensing data, wherein each of the plurality of source driver ICs includes a first source driver IC connected to a first pixel and configured to transmit first sensing data obtained by sensing characteristics of the driving element included in the first pixel to a timing controller when a first transmission command is received from the timing controller, and a second source driver IC connected to a second pixel and configured to transmit second sensing data obtained by sensing characteristics of the driving element included in the second pixel to the first source driver IC when the first transmission command is received.

[0011] According to another aspect of the present disclosure, a method for operating a display device is provided, which includes a timing controller, a first source driver integrated circuit (IC) connected to a first pixel group, and a second source driver IC connected to a second pixel group, the method including the following steps: in response to a sensing command output from the timing controller, the first source driver IC generates first sensing data by sensing pixels included in the first pixel group, and the second source driver IC generates second sensing data by sensing pixels included in the second pixel group; in response to a first transfer command output from the timing controller, the first sensing data is transmitted to the timing controller through the first source driver IC, and the second sensing data is transmitted to the first source driver IC through the second source driver IC; and in response to a second transfer command output from the timing controller, the second sensing data transmitted from the second source driver IC is transmitted to the timing controller through the first source driver IC. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0013] Figure 1 is a block diagram of a display device including a timing controller and a source driver integrated circuit (IC) according to one embodiment of the present disclosure;

[0014] Figure 2 Is used to describe Figure 1 A diagram of a connection structure between a timing controller and a source driver IC shown in FIG.

[0015] Figure 3 Is used to describe Figure 2 FIG. 1 is a diagram showing an embodiment of a connection structure between a timing controller and a first group of source driver ICs;

[0016] Figure 4 It is shown Figure 3 A block diagram of a source driver IC is shown;

[0017] Figure 5 Is used to describe Figure 3 A diagram of a sensing data transmission operation of a first group of source driver ICs shown;

[0018] Figure 6 Is used to describe Figure 2 FIG. 1 is a diagram showing another embodiment of a connection structure between a timing controller and a first group of source driver ICs;

[0019] Figure 7 yes Figure 6 A block diagram of a source driver IC is shown; and

[0020] Figure 8 is a flowchart illustrating an operation of a display device including a timing controller and a source driver IC according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In the specification, it should be noted that the same reference numerals used to represent the same elements in other drawings will be used for elements as much as possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

[0022] The advantages and features of the present disclosure and their implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0023] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. The same reference numerals always represent the same elements. In the following description, when it is determined that the detailed description of the related known functions or configurations unnecessarily obscures the main points of the present disclosure, the detailed description will be omitted.

[0024] In the case where “including,” “having,” and “comprising” described in the present specification are used, another component may be added unless “only” is used. Unless otherwise specified, terms in the singular form may include plural forms.

[0025] When interpreting an element, although there is no explicit description, the element is interpreted as including an error range.

[0026] When describing a positional relationship, for example, when the positional relationship between two components is described as "on", "over", "under", and "next", one or more other components may be arranged between the two components unless "just" or "directly" is used.

[0027] When describing a time relationship, for example, when a time order is described as "after", "subsequently", "next", and "before", discontinuous cases may be included unless "directly" or "directly" is used.

[0028] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0029] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, the meaning of "at least one of the first, second, and third items" means the combination of all items proposed from two or more of the first, second, and third items.

[0030] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate and technically drive with each other in different ways as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0031] Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram of a display device including a timing controller and a source driver integrated circuit (IC) according to one embodiment of the present disclosure. Figure 1 , the display device 100 includes a timing controller 110 , a data driving circuit block 120 , a gate driving circuit block 130 , and an organic light emitting diode (OLED) display panel 140 .

[0033] The display device 100 may be a display device including pixels including OLEDs. For example, the display device 100 may be a display device for a television (TV), or a rollable display device.

[0034] The timing controller 110 uses the timing control signal TCTR to generate a first control signal DCS for controlling the operation of the data driving circuit block 120 and a second control signal GCS for controlling the operation of the gate driving circuit block 130. For example, the timing control signal TCTR may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal, a data enable signal, and the like.

[0035] Furthermore, the timing controller 110 converts image data Idata received from a host system (not shown) into digital video data Idata′ in a form that can be processed by the data driving circuit block 120 , and transmits the digital video data Idata′ to the data driving circuit block 120 .

[0036] The data driving circuit block 120 includes a data driving IC (or source driving IC) to be described herein. During normal driving (or normal operation), the data driving circuit block 120 converts the digital video data Idata' into a data voltage for image display using a first control signal DCS, and provides the data voltage for image display to the pixel P through the data lines DL1 to DLm (where m is a natural number greater than or equal to 2).

[0037] During normal driving, the gate driving circuit block 130 generates a gate pulse for image display using the second control signal GCS, and sequentially provides the gate pulse for image display to the pixels P through the gate lines GL1 to GLn (where n is a natural number greater than or equal to 2) in a row sequential manner.

[0038] During a sensing drive (or sensing operation), the data driving circuit block 120 generates a data voltage for sensing using a first control signal DCS, and provides the data voltage for sensing to the pixels P through the data lines DL1 to DLm.

[0039] During the sensing drive period, the gate driving circuit block 130 generates a gate pulse for sensing using the second control signal GCS, and sequentially supplies the gate pulse for sensing to the pixels P through the gate lines GL1 to GLn in a row sequential manner.

[0040] The display panel 140 includes pixels P arranged in the form of an m×n matrix, and corresponding pixels among the pixels P are connected to corresponding data lines among data lines DL1 to DLm, corresponding sensing lines among sensing lines SL1 to SLm, and corresponding gate lines among gate lines GL1 to GLn. In response to gate pulses respectively input through the gate lines GL1 to GLn, the pixels P are respectively connected to the data lines DL1 to DLm to receive data voltages, and transmit sensing signals to the data driving circuit block 120 through the sensing lines SL1 to SLm, respectively. Each pixel P includes an OLED.

[0041] Figure 2 Is used to describe Figure 1 The connection structure between the timing controller and the source driver IC is shown in FIG. Figure 1 and Figure 2 , the timing controller 110 may transmit a signal (or data) to the data driving circuit block 120 through the cables 205 and 210, and may receive a signal (or data) from the data driving circuit block 120 through the cables 205 and 210. Figure 2 Only two cables 205 and 210 are shown in the figure, but the number of cables connected between the timing controller 110 and the data driving circuit block 120 can be determined according to the number of boards 300 and 400 or the number of conductors (or wires) formed on each of the boards 300 and 400.

[0042] The data driving circuit block 120 includes a first board 300, a first group of source driver ICs 315-1 to 315-8, a second board 400, and a second group of source driver ICs 415-1 to 415-8. Figure 2The data driving circuit block 120 is illustrated in FIG. 1 as including eight source driver ICs for each of the boards 300 and 400 , but this is merely an example, and the number of source driver ICs to be included in each of the boards 300 and 400 may vary.

[0043] In one implementation, the first group of source driver ICs 315 - 1 to 315 - 8 may be connected to each other in a cascade manner, and the second group of source driver ICs 415 - 1 to 415 - 8 may be connected to each other in a cascade manner.

[0044] Each of the boards 300 and 400 may be implemented as a printed circuit board (PCB) or a flexible PCB (FPCB), but the present disclosure is not limited thereto. A conductor (or wire) is additionally formed on each of the boards 300 and 400 to connect the corresponding two source driver ICs in a point-to-point manner or in a cascade manner.

[0045] The first group of source driver ICs 315-1 to 315-8 can transmit signals (or data) to the timing controller 110 through the first board 300 and the cable 205, and receive signals (or data) from the timing controller 110 through the first board 300 and the cable 205, and the second group of source driver ICs 415-1 to 415-8 can transmit signals (or data) to the timing controller 110 through the second board 400 and the cable 210, and receive signals (or data) from the timing controller 110 through the second board 400 and the cable 210.

[0046] The first group of source driver ICs 315 - 1 to 315 - 8 may be implemented as chips on films (COFs) 310 - 1 to 310 - 8 , respectively, and the second group of source driver ICs 415 - 1 to 415 - 8 may be implemented as COFs 410 - 1 to 410 - 8 , respectively.

[0047] The source driver ICs 315 - 1 to 315 - 8 and 415 - 1 to 415 - 8 are connected to pixels included in the display panel 140 through data lines DL1 to DLm and sensing lines SL1 to SLm, respectively.

[0048] Figure 3 Is used to describe Figure 2 FIG. 1 is a diagram showing an embodiment of a connection structure between a timing controller and a first group of source driver ICs, and Figure 6 Is used to describe Figure 2 FIG. 1 is a diagram of another embodiment of a connection structure between a timing controller and a first group of source driver ICs.

[0049] Reference Figure 3 and Figure 6In order to receive the data packet CEDSP or CDATA output from the timing controller 110, each of the source driver ICs 315-1 to 315-8 or 315'-1 to 315'-8 (which can be collectively represented as 315-1 to 315-8) is connected to the timing controller 110 in a point-to-point manner through the board 300, and the source driver ICs 315-1 to 315-8 are connected to each other in a cascade manner to transmit transmission sensing data (transmission sensing data) TDi (where 1<=i<=7) and a transmission clock signal (transmission clock signal) OCi, and among the source driver ICs 315-1 to 315-8, the output source driver IC (for example, the first source driver IC 315-1) that outputs the output sensing data (output sensing data) OD and the output clock signal (output sensing data) OC to the timing controller 110 is connected to the timing controller 110 in a point-to-point manner.

[0050] Reference Figures 1 to 3 , it is assumed that the timing controller 110 uses a clock embedded data signaling (CEDS) protocol to control the first group of source driver ICs 315 - 1 to 315 - 8 and the second group of source driver ICs 415 - 1 to 415 - 8 .

[0051] It is assumed that the operation between the timing controller 110 and the second group of source driver ICs 415-1 to 415-8 is the same as the operation between the timing controller 110 and the first group of source driver ICs 315-1 to 315-8. Therefore, hereinafter, for the convenience of description, only the operation between the timing controller 110 and the first group of source driver ICs 315-1 to 315-8 will be described.

[0052] The transmission clock signal OCi is a clock signal for transmitting the transmission sensing data TDi, and the output clock signal OC is a clock signal for transmitting the output sensing data OD. Each transmission clock signal OCi is transmitted together with each transmission sensing data TDi (or is transmitted by synchronization), and the output clock signal OC is transmitted together with the output sensing data OD (or is transmitted by synchronization).

[0053] Except for the first source driver IC 315-1 and the last source driver IC 315-8, according to the command (or operation instruction signal) included in the CEDS control group CEDSP, the source driver ICs 315-2 to 315-7 respectively transmit self-sensing data to the next source driver IC 315-1 to 315-6, or respectively transmit the transmission sensing data output from the previous source driver IC 315-3 to 315-8 to the next source driver IC 315-1 to 315-6.

[0054] In this article, self-sensing data refers to sensing data generated by the source driver IC itself, and transmission sensing data refers to sensing data transmitted from other source driver ICs. In addition, the command (or operation instruction signal) included in the CEDS control packet CEDSP is generated by the packet generator 115 included in the timing controller 110, and indicates whether the operation to be performed in each of the source driver ICs 315-1 to 315-8 is a sensing operation or a transmission operation.

[0055] For example, when referring to the second source driver IC 315-2, the next source driver IC is the first source driver IC 315-1, and the previous source driver IC is the third source driver IC 315-3. In addition, when referring to the seventh source driver IC 315-7, the next source driver IC is the sixth source driver IC 315-6, and the previous source driver IC is the eighth source driver IC 315-8.

[0056] The first source driver IC 315-1 outputs the self sensing data SD1 generated (or sensed) by the first source driver IC 315-1 as the output sensing data OD to the timing controller 110 according to the command included in the CEDS control packet CEDSP, or outputs the transmission sensing data TD1 output from the second source driver IC 315-2 as the output sensing data OD to the timing controller 110. In this case, the first source driver IC 315-1 may transmit the output clock signal OC to the timing controller 110 together with the output sensing data OD.

[0057] The last source driver IC 315-8 outputs the self-sensing data SD8 generated (or sensed) by the last source driver IC 315-8 as the transmission sensing data TD7 to the seventh source driver IC 315-7 according to the command included in the CEDS control packet CEDSP, or outputs dummy data (e.g., all-zero data) having a specific pattern as the transmission sensing data TD7 to the seventh source driver IC 315-7, the dummy data indicating no output due to the absence of the previous source driver IC. In this case, the last source driver IC 315-8 outputs the transmission clock signal OC7 together with the transmission sensing data TD7 to the seventh source driver IC 315-7.

[0058] Reference Figure 3 and Figure 4 When a source driver IC having the same configuration as the first source driver IC 315-1 is used as the last source driver IC 315-8, the data pins 323-1 and 325-1 may be grounded. Therefore, all zero data may be stored in the first buffer of the last source driver IC 315-8.

[0059] On the first board 300, wires LW1 to LW7 for transmitting transmission sensing data TDi (1<=i<=7) and a transmission clock signal OCi output from one of two adjacent source driver ICs to the other of the two source driver ICs are formed, and an output wire LW0 for transmitting output sensing data OD and an output clock signal OC output from the first source driver IC 315-1 to the timing controller 110 is formed. The number of wires included in each of the wires LW0 to LW7 may be determined according to the number of transmitted signals.

[0060] On the second board 400, wires are also formed for transmitting transmission sensing data and transmission clock signals output from one of two adjacent source driver ICs to the other of the two source driver ICs, and wires are also formed for transmitting output sensing data and output clock signals output from the eighth source driver IC 415-8 to the timing controller 110.

[0061] Each signal CEDSP, TDi, OCi, OD, OC, CDATA, or ACLK described herein refers to a single signal or a differential signal. Therefore, when each signal CEDSP, TDi, OCi, OD, OC, CDATA, or ACLK has a differential signal, the conductors (or wires) transmitting the differential signals are formed (or arranged) in pairs.

[0062] Figure 4 It is shown Figure 3 The source driver IC is shown in Figure 1. Figures 1 to 4 , since it is assumed that the structure and function of each of the source driver ICs 315-1 to 315-8 and 415-1 to 415-8 are the same, reference will be made to Figure 4 The structure and operation of each of the two source driver ICs 315 - 1 and 315 - 2 are described in detail.

[0063] The first source driver IC 315-1 includes a pin 321-1 configured to receive a CEDS control packet CEDSP, a pin 323-1 configured to receive input transmission sensing data TD1, a pin 325-1 configured to receive an input transmission clock signal OC1, a pin 327-1 configured to output an output clock signal OC, and a pin 329-1 configured to output output sensing data OD.

[0064] The second source driver IC 315-2 includes a pin 321-2 configured to receive a CEDS control packet CEDSP, a pin 323-2 configured to receive input transmission sensing data TD2, a pin 325-2 configured to receive an input transmission clock signal OC2, a pin 327-2 configured to output a transmission clock signal OC1, and a pin 329-2 configured to output transmission sensing data TD1.

[0065] The number of each pin 321-k, 323-k, 325-k, 327-k or 329-k (where k is 1 or 2) can be designed to be suitable for the characteristics of input and output signals (e.g., differential signals, serial data or parallel data). Therefore, each pin 321-k, 323-k, 325-k, 327-k or 329-k can refer to one or two or more pins. Each pin 321-k, 323-k, 325-k, 327-k or 329-k can be a port or a pad.

[0066] The first source driver IC 315-1 may include a control circuit 335-1, a first buffer 340-1, a sensing data generating circuit 345-1 including a second buffer 350-1, and a selector 355-1. The second source driver IC 315-2 may include a control circuit 335-2, a first buffer 340-2, a sensing data generating circuit 345-2 including a second buffer 350-2, and a selector 355-2. The second buffer 350-1 or 350-2 may be implemented outside each sensing data generating circuit 345-1 or 345-2. Each buffer 340-1, 340-2, 350-1 or 350-2 may be implemented as a latch or a register.

[0067] When the CEDS control packet CEDSP is a packet in which a clock signal and a control data signal are embedded between data signals, each control circuit 335 - 1 or 335 - 2 may extract the clock signal and the command from the CEDS control packet CEDSP.

[0068] For example, the control circuit 335-2 outputs the transmission clock signal OC1 corresponding to the clock signal included in the CEDS control packet CEDSP input to the second source driver IC 315-2 to the pin 325-1 of the first source driver IC 315-1 through the pin 327-2 and the wire LW1, and the control circuit 335-1 outputs the output clock signal OC corresponding to the clock signal included in the CEDS control packet CEDSP input to the first source driver IC 315-1 to the timing controller 110 through the pin 327-1 and the wire LW0. Therefore, since the timing controller 110 receives the output clock signal OC from the first source driver IC 315-1 that is closest to the timing controller 110, the timing controller 110 is allowed to receive the output clock signal OC having almost no skew compared to the clock signal included in the CEDS control packet CEDSP.

[0069] The control circuit 335-2 controls the operation of storing the transmission sensing data TD2 transmitted from the third source driver IC 315-3 in the first buffer 340-2, the operation of transmitting the transmission sensing data TD2 stored in the first buffer 340-2 to the pin 329-2 through the selector 355-2, the operation of transmitting the transmission clock signal OC1 to the first source driver IC 315-1, the operation of transmitting the self-sensing data SD2 stored in the second buffer 350-2 to the pin 329-2 through the selector 355-2, and / or the operation of the sensing data generating circuit 345-2 for performing an operation of generating the self-sensing data SD2.

[0070] The first buffer 340 - 2 receives and stores the transmission sensing data TD2 transmitted from the third source driver IC 315 - 3 .

[0071] The sensing data generating circuit 345-2 generates the self-sensing data SD2 based on the sensing signal output from the pixel included in the second pixel group 140-2, and stores the self-sensing data SD2 in the second buffer 350-2. In one embodiment, the sensing signal may include a threshold voltage or mobility of a driving element (e.g., a driving transistor) included in each pixel. Since the method of generating the self-sensing data SD2 by the sensing data generating circuit 345-2 is a known technology, its detailed description will be omitted.

[0072] The control circuit 335 - 2 generates a selection signal SEL based on a command included in the CEDS control packet CEDSP.

[0073] In one embodiment, when the selection signal SEL has a first level (e.g., a low level or data "0"), the selector 355-2 outputs the transmission sensing data TD2 stored in the first buffer 340-2 to the pin 329-2. When the selection signal SEL has a second level (e.g., a high level or data "1"), the selector 355-2 outputs the self-sensing data SD2 stored in the second buffer 350-2 to the pin 329-2.

[0074] The control circuit 335-1 controls an operation of storing the transmission sensing data TD1 transmitted from the second source driver IC 315-2 in the first buffer 340-1, an operation of transmitting the transmission sensing data TD1 stored in the first buffer 340-1 to the pin 329-1 through the selector 355-1, an operation of transmitting the output clock signal OC to the timing controller 110, an operation of transmitting the self-sensing data SD1 stored in the second buffer 350-1 to the pin 329-1 through the selector 355-1, and / or an operation of the sensing data generating circuit 345-1 for performing an operation of generating the self-sensing data SD1.

[0075] The first buffer 340 - 1 receives and stores the transmission sensing data TD1 transmitted from the second source driver IC 315 - 2 .

[0076] The sensing data generating circuit 345 - 1 generates self sensing data SD1 based on sensing signals output from pixels included in the first pixel group 140 - 1 and stores the self sensing data SD1 in the second buffer 350 - 1 .

[0077] The control circuit 335 - 1 generates a selection signal SEL based on a command included in the CEDS control packet CEDSP.

[0078] When the selection signal SEL has a first level, the selector 355-1 outputs the transmission sensing data TD1 stored in the first buffer 340-1 to the pin 329-1. When the selection signal SEL has a second level, the selector 355-1 outputs the self sensing data SD1 stored in the second buffer 350-1 to the pin 329-1.

[0079] Since the structure and operation of each of the source driver ICs 315-3 to 315-8 are the same as those of the first source driver IC 315-1 or the second source driver IC 315-2, a description of the operation of each of the source driver ICs 315-3 to 315-8 will be omitted.

[0080] Figure 5 Is used to describe Figure 3 A diagram of the sensing data transfer operation of the first group of source driver ICs is shown.

[0081] Reference Figures 1 to 5 For the sensing operation, the packet generator 115 of the timing controller 110 generates a CEDS control packet CEDSP including a command (eg, a sensing command) indicating that the sensing operation is to be performed, and transmits the CEDS control packet CEDSP to each of the source driver ICs 315-1 to 315-8.

[0082] The control circuit of each of the source driver ICs 315-1 to 315-8 generates a control signal corresponding to the sensing command included in the CEDS control packet CEDSP. The sensing data generating circuit of each of the source driver ICs 315-11 to 315-8 receives a sensing signal from a pixel included in each pixel group connected (or allocated) to each of the source driver ICs 315-1 to 315-8 in response to the control signal, generates sensing data (e.g., self-sensing data) corresponding to the sensing signal, and stores the self-sensing data in a second buffer of each of the source driver ICs 315-1 to 315-8.

[0083] For example, the second buffers of the source driver ICs 315 - 1 to 315 - 8 store the self-sensing data SD1 to SD8 , respectively.

[0084] The packet generator 115 of the timing controller 110 generates a CEDS control packet CEDSP including a command (eg, a transfer command) indicating a transfer operation, and transfers the CEDS control packet CEDSP to each of the source driver ICs 315 - 1 to 315 - 8 .

[0085] In the first transfer operation TO1, the control circuit of each of the source driver ICs 315-1 to 315-8 generates a selection signal having a second level based on the transfer command included in the CEDS control packet CEDSP, and thus the selectors of the source driver ICs 315-1 to 315-8 output the self-sensing data SD1 to SD8 respectively stored in the second buffers of the source driver ICs 315-1 to 315-8 to other devices (the timing controller 110 and the source driver ICs 315-1 to 315-7), respectively.

[0086] In the first transmission operation TO1, the first source driver IC 315-1 transmits the self-sensing data SD1 stored in the second buffer 350-1 of the first source driver IC 315-1 as the output sensing data OD to the timing controller 110, and the source driver ICs 315-2 to 315-8 transmit the self-sensing data SD2 to SD8 respectively stored in their second buffers to the adjacent source driver ICs 315-1 to 315-7. Therefore, the adjacent source driver ICs 315-1 to 315-7 store the transmission sensing data TD1=SD2, TD2=SD3, TD3=SD4, TD4=SD5, TD5=SD6, TD6=SD7, and TD7=SD8 respectively output from the second buffers of the source driver ICs 315-2 to 315-8 in their first buffers. Since the pin of the last source driver IC 315 - 8 (the pin corresponding to the pin 323 - 1 and the pin 325 - 1 ) is grounded, the all-zero data AZ may be stored in the first buffer of the last source driver IC 315 - 8 .

[0087] In the second transfer operation TO2, the control circuit of each of the source driver ICs 315-1 to 315-8 generates a selection signal having a first level based on the transfer command included in the CEDS control packet CEDSP, and thus the selectors of the source driver ICs 315-1 to 315-8 output the self-sensing data SD2 to SD8 and AZ respectively stored in the first buffers of the source driver ICs 315-1 to 315-8 to other devices (timing controller 110 and source driver ICs 315-1 to 315-7), respectively.

[0088] In the second transmission operation TO2, the first source driver IC 315-1 transmits the sensing data SD2 stored in the first buffer 340-1 of the first source driver IC 315-1 as the output sensing data OD to the timing controller 110, and the source driver ICs 315-2 to 315-8 transmit the sensing data TD1=SD3, TD2=SD4, TD3=SD5, TD4=SD6, TD5=SD7, TD6=SD8, and TD7=AZ respectively stored in their first buffers to the adjacent source driver ICs IC315-1 to 315-7. Therefore, the adjacent source driver ICs 315-1 to 315-7 store the sensing data TD1=SD3, TD2=SD4, TD3=SD5, TD4=SD6, TD5=SD7, TD6=SD8, and TD7=AZ respectively output from the first buffers of the source driver ICs 315-2 to 315-8 in their first buffers.

[0089] In the third transmission operation TO3, the first source driver IC 315-1 transmits the sensing data SD3 stored in the first buffer 340-1 of the first source driver IC 315-1 as the output sensing data OD to the timing controller 110, and the source driver ICs 315-2 to 315-8 transmit the sensing data respectively stored in their first buffers to the adjacent source driver ICs 315-1 to 315-7, respectively. Therefore, the adjacent source driver ICs 315-1 to 315-7 store the sensing data TD1=SD4, TD2=SD5, TD3=SD6, TD4=SD7, TD5=SD8, TD6=AZ, and TD7=AZ respectively output from the first buffers of the source driver ICs 315-2 to 315-8 in their first buffers, respectively.

[0090] In the fourth transmission operation TO4, the first source driver IC 315-1 receives the self-sensing data SD4 generated by the fourth source driver IC 315-4 through the transmission sensing data shift operation performed between the source driver ICs in a point-to-point (or cascade) manner as described above, and transmits the self-sensing data SD4 as the output sensing data OD to the timing controller 110. In the fifth transmission operation TO5, the first source driver IC 315-1 receives the self-sensing data SD5 generated by the fifth source driver IC 315-5 and transmits the self-sensing data SD5 as the output sensing data OD to the timing controller 110, and in the sixth transmission operation TO6, the first source driver IC 315-1 receives the self-sensing data SD6 generated by the sixth source driver IC 315-6 and transmits the self-sensing data SD6 as the output sensing data OD to the timing controller 110. In the seventh transmission operation TO7, the first source driver IC 315-1 receives the self-sensing data SD7 generated by the seventh source driver IC 315-7, and transmits the self-sensing data SD7 as the output sensing data OD to the timing controller 110, and in the eighth transmission operation TO8, the first source driver IC 315-1 receives the self-sensing data SD8 generated by the eighth source driver IC 315-8, and transmits the self-sensing data SD8 as the output sensing data OD to the timing controller 110.

[0091] As reference Figures 1 to 5As described, the eighth sensing data (SD8=TD7) generated by the eighth source driver IC 315-8 is transmitted to the seventh source driver IC 315-7 through the seventh wire LW7 through the first transmission operation TO1, the eighth sensing data (SD8=TD6) transmitted to the seventh source driver IC 315-7 is transmitted to the sixth source driver IC 315-6 through the sixth wire LW6 through the second transmission operation TO2, the eighth sensing data (SD8=TD5) transmitted to the sixth source driver IC 315-6 is transmitted to the fifth source driver IC 315-5 through the fifth wire LW5 through the third transmission operation TO3, the eighth sensing data (SD8=TD4) transmitted to the fifth source driver IC 315-5 is transmitted to the fourth source driver IC 315-4 through the fourth wire LW4 through the fourth transmission operation TO4, and the eighth sensing data (SD8=TD5) transmitted to the fifth source driver IC 315-5 is transmitted to the fourth source driver IC 315-4 through the fifth transmission operation TO5. The eighth sensing data (SD8=TD3) of 315-4 is transmitted to the third source driver IC 315-3 through the third wire LW3, the eighth sensing data (SD8=TD2) transmitted to the third source driver IC 315-3 is transmitted to the second source driver IC 315-2 through the second wire LW2 through the sixth transmission operation TO6, the eighth sensing data (SD8=TD1) transmitted to the second source driver IC 315-2 is transmitted to the first source driver IC 315-1 through the first wire LW1 through the seventh transmission operation TO7, and the eighth sensing data (SD8=OD) transmitted to the first source driver IC 315-1 is transmitted to the timing controller 110 through the output wire LW0 through the eighth transmission operation TO8.

[0092] Since the process in which each sensing data SD1, SD2, SD3, SD4, SD5, SD6 or SD7 is transmitted to the first source driver IC 315-1 through one or two or more transmission operations and then transmitted to the timing controller 110 through the output wire LW0 is similar to the process in which the eighth sensing data SD8 is transmitted to the first source driver IC 315-1 through the other source driver ICs 315-2 to 315-7 and then transmitted to the timing controller 110 through the output wire LW0, its detailed description will be omitted.

[0093] Through the above process, the first source driver IC 315 - 1 sequentially transmits all sensing data SD1 to SD8 to the timing controller 110 through the output wire LW0 .

[0094] Meanwhile, when the output sensing data OD is transmitted to the timing controller 110, the timing controller 110 may be regarded as a slave device (or in a slave state), and each of the source driver ICs 315-1 to 315-8 may be regarded as a master device (or in a master state). In this case, since there are eight master devices among the source driver ICs 315-1 to 315-8, at least one source driver IC that does not transmit sensing data should indicate that it does not output sensing data.

[0095] In one embodiment, among the source driver ICs 315-1 to 315-8, the source driver IC that does not transmit sensing data may clear its first buffer 340-i and second buffer 350-i, or cause the selector 355-i to output a value of a predetermined level (e.g., "0") to indicate that the source driver IC does not output sensing data.

[0096] As described above, according to the present disclosure, since the timing controller 110 receives the sensing data and the clock signal of each of the source driver ICs 315-1 to 315-8 only through the first source driver IC 315-1 among the source driver ICs 315-1 to 315-8, there is no need to perform an additional tuning operation for matching the phase of the clock signal, which is different from a conventional timing controller that receives the sensing data and the clock signal from each source driver IC and therefore needs to perform a tuning operation to match the phase of the clock signal of the source driver IC, thereby simplifying the logic design of the timing controller 110.

[0097] Figure 6 Is used to describe Figure 2 FIG. 1 is a diagram of another embodiment of a connection structure between a timing controller and a first group of source driver ICs.

[0098] Reference Figure 1 , Figure 2 and Figure 6 , assuming that the timing controller 110 uses the data packet CDATA and the reference clock signal ACLK to control the first group of source driver ICs 315'-1 to 315'-8 and the second group of source driver ICs (ie, they are connected in the same manner as Figure 2 The second set of source driver ICs 415-1 to 415-8 are arranged in the same manner as shown).

[0099] The operation of each of the source driver ICs 315'-1 to 315'-8 in the first group is similar to the operation of each of the source driver ICs 315'-1 to 315'-8 in the second group, and thus a description of the operation of each of the source driver ICs in the second group will be omitted.

[0100] When the data packet CDATA is not a data packet complying with the CEDS protocol, the reference clock signal ACLK is required to transmit the data packet CDATA. The reference clock signal ACLK refers to a clock signal used when the timing controller 110 transmits the data packet CDATA, and the output clock signal OC refers to a clock signal used when transmitting the output sense data OD.

[0101] For ease of description, reference will be made to Figure 6 and Figure 7 The operation of the timing controller 110 and the first group of source driver ICs 315'-1 to 315'-8 is described. Assume that the timing controller 110 and the second group of source driver ICs (having Figure 2 The operation of the source driver ICs 415 - 1 to 415 - 8 of the same arrangement) is the same as that of the timing controller 110 and the first group of source driver ICs 315 ′- 1 to 315 ′- 8.

[0102] Except for the first source driver IC 315'-1 and the last source driver IC 315'-8, the source driver ICs 315'-2 to 315'-7 transmit the self-sensing data to the next source driver ICs 315'-1 to 315'-6, respectively, or transmit the transfer sensing data output from the previous source driver ICs 315'-3 to 315'-8 to the next source driver ICs 315'-1 to 315'-6, respectively, according to the command included in the data packet CDATA. As described above, the command instructing to perform the sensing operation or the transfer operation may be generated by the packet generator 115 included in the timing controller 110.

[0103] For example, when referring to the second source driver IC 315 ′- 2 , the next source driver IC is the first source driver IC 315 ′- 1 , and the previous source driver IC is the third source driver IC 315 ′- 3 .

[0104] The first source driver IC 315'-1 outputs the self-sensing data generated (or sensed) by the first source driver IC 315'-1 as the output sensing data OD to the timing controller 110 according to the command included in the data packet CDATA, or outputs the transmission sensing data TD1 transmitted from the second source driver IC 315'-2 as the output sensing data OD to the timing controller 110. In this case, the first source driver IC 315'-1 may transmit the output clock signal OC to the timing controller 110 together with the output sensing data OD.

[0105] The last source driver IC 315'-8 outputs the self-sensing data SD8 generated (or sensed) by the last source driver IC 315'-8 as the transmission sensing data TD7 to the seventh source driver IC 315'-7 according to the command included in the data packet CDATA, or outputs data having a specific pattern (for example, all zeros) (because the previous source driver IC does not exist) as the transmission sensing data TD7 to the seventh source driver IC 315'-7. In this case, the last source driver IC 315'-8 outputs the transmission clock signal OC7 together with the transmission sensing data TD7 to the seventh source driver IC 315'-7.

[0106] Reference Figure 6 and Figure 7 , when a source driver IC having the same configuration as the first source driver IC 315 ′- 1 is used as the last source driver IC 315 ′- 8, Figure 7 Pins 323-1 and 325-1 in can be grounded.

[0107] Figure 7 Shows Figure 6 Figure 1 is a block diagram of a source driver IC.

[0108] Reference Figure 1 , Figure 2 , Figure 6 and Figure 7 Since it is assumed that the structure and function of each of the source driver ICs 315 ′- 1 to 315 ′- 8 are the same, the structure and operation of the two source driver ICs 315 ′- 1 and 315 ′- 2 will be described in detail.

[0109] The first source driver IC 315'-1 includes a pin 321-1a configured to receive a data packet CDATA including a command, a pin 322-1a configured to receive a reference clock signal ACLK, a pin 323-1 configured to receive input transmission sensing data TD1, a pin 325-1 configured to receive an input transmission clock signal OC1, a pin 327-1 configured to output an output clock signal OC, and a pin 329-1 configured to output output sensing data OD.

[0110] The second source driver IC 315'-2 includes a pin 321-2a configured to receive a data packet CDATA including a command, a pin 322-2a configured to receive a reference clock signal ACLK, a pin 323-2 configured to receive input transmission sensing data TD2, a pin 325-2 configured to receive an input transmission clock signal OC2, a pin 327-2 configured to output a transmission clock signal OC1, and a pin 329-2 configured to output transmission sensing data TD1.

[0111] The number of each pin 321-ka, 322-ka, 323-k, 325-k, 327-k or 329-k (where k is 1 or 2) can be designed to be suitable for the characteristics of input and output signals (e.g., differential signals, serial data or parallel data). Therefore, each pin 321-ka, 322-ka, 323-k, 325-k, 327-k or 329-k can refer to one or two or more pins. Each pin 321-ka, 322-ka, 323-k, 325-k, 327-k or 329-k can be a port or a pad.

[0112] The first source driver IC 315'-1 may include a control circuit 335-1a, a first buffer 340-1, a sensing data generating circuit 345-1 including a second buffer 350-1, and a selector 355-1. The second source driver IC 315'-2 may include a control circuit 335-2a, a first buffer 340-2, a sensing data generating circuit 345-2 including a second buffer 350-2, and a selector 355-2.

[0113] The control circuit 335-1a may extract a command from the data packet CDATA and may determine the output clock signal OC using the reference clock signal ACLK. In addition, the control circuit 335-2a may extract a command from the data packet CDATA and may determine the transmission clock signal OC1 using the reference clock signal ACLK.

[0114] The control circuit 335 - 2 a outputs the transmission clock signal OC1 to the pin 325 - 1 of the first source driver IC 315 ′- 1 through the pin 327 - 2 , and the control circuit 335 - 1 a outputs the output clock signal OC to the timing controller 110 through the pin 327 - 1 .

[0115] The control circuit 335-2a controls the operation of storing the transmission sensing data TD2 output from the third source driver IC 315'-3 in the first buffer 340-2, the operation of transmitting the transmission sensing data TD2 stored in the first buffer 340-2 to the pin 329-2 through the selector 355-2, the operation of transmitting the transmission clock signal OC1 to the first source driver IC 315'-1, the operation of transmitting the self-sensing data SD2 stored in the second buffer 350-2 to the pin 329-2 through the selector 355-2, and / or the operation of the sensing data generating circuit 345-2 for performing an operation of generating the self-sensing data SD2.

[0116] The first buffer 340 - 2 receives and stores the transmission sensing data TD2 output from the third source driver IC 315 ′- 3 .

[0117] The sensing data generation circuit 345 - 2 generates self sensing data SD2 based on the sensing signals output from the pixels included in the second pixel group 140 - 2 and stores the self sensing data SD2 in the second buffer 350 - 2 .

[0118] The control circuit 335 - 2 a generates a selection signal SEL based on a command included in the data packet CDATA.

[0119] When the selection signal SEL has a first level, the selector 355-2 outputs the transmission sensing data TD2 stored in the first buffer 340-2 to the pin 329-2. When the selection signal SEL has a second level, the selector 355-2 outputs the self sensing data SD2 stored in the second buffer 350-2 to the pin 329-2.

[0120] The control circuit 335-1a controls an operation of storing the transmission sensing data TD1 transmitted from the second source driver IC 315'-2 in the first buffer 340-1, an operation of transmitting the transmission sensing data TD1 stored in the first buffer 340-1 to the pin 329-1 through the selector 355-1, an operation of transmitting the output clock signal OC to the timing controller 110, an operation of transmitting the self-sensing data SD1 stored in the second buffer 350-1 to the pin 329-1 through the selector 355-1, and / or an operation of the sensing data generating circuit 345-1 for performing an operation of generating the self-sensing data SD1.

[0121] The first buffer 340 - 1 receives and stores the transmission sensing data TD1 transmitted from the second source driver IC 315 ′- 2 .

[0122] The sensing data generation circuit 345 - 1 generates self sensing data SD1 based on sensing signals output from pixels included in the first pixel group 140 - 1 and stores the self sensing data SD1 in the second buffer 350 - 1 .

[0123] The control circuit 335 - 1 a generates a selection signal SEL based on a command included in the data packet CDATA.

[0124] When the selection signal SEL has a first level, the selector 355-1 outputs the transmission sensing data TD1 stored in the first buffer 340-1 to the pin 329-1. When the selection signal SEL has a second level, the selector 355-1 outputs the self sensing data SD1 stored in the second buffer 350-1 to the pin 329-1.

[0125] Since the structure and operation of each of the source driver ICs 315'-3 to 315'-8 are the same as those of the first source driver IC 315'-1 or the second source driver IC 315'-2, a description of the operation of each of the source driver ICs 315'-3 to 315'-8 will be omitted.

[0126] Figure 8 is a flowchart illustrating an operation of a display device including a timing controller and a source driver IC according to an embodiment of the present disclosure.

[0127] Reference Figures 1 to 8 For the sensing operation, the packet generator 115 of the timing controller 110 generates a packet CEDSP or CDATA including a sensing command indicating that the sensing operation is performed, and transmits the packet to each source driver IC (S110).

[0128] The control circuit of each source driver IC generates a control signal corresponding to the sensing command included in the group CEDSP or CDATA, and the sensing data generating circuit of each source driver IC receives the sensing signal from the pixels included in each pixel group connected (or allocated) to each source driver IC in response to the control signal, generates sensing data (e.g., self-sensing data) corresponding to the sensing signal, and stores the self-sensing data in the second buffer of each source driver IC (S120).

[0129] The packet generator 115 of the timing controller 110 generates a packet CEDSP or CDATA including a transfer command indicating a transfer operation, and transmits the packet to each source driver IC (S130).

[0130] As reference Figure 5As described, each source driver IC transmits self-sensing data to the next source driver IC based on the transmission command included in the group CEDSP or CDATA in the first transmission operation TO1, and transmits the transmission sensing data transmitted from the previous source driver IC to the next source driver IC based on the transmission command included in the group CEDSP or CDATA in each transmission operation TO2, TO3, ..., or TO7 (S140 and the case of "No" in S150).

[0131] In the final transmission operation TO8, each source driver IC transmits the transmission sensing data transmitted from the previous source driver IC to the next source driver IC (the case of “Yes” in S140 and S150), and ends the transmission operation (S160).

[0132] According to the present disclosure, a timing controller receives sensing data of multiple source driver ICs through some source driver ICs, which is different from a conventional timing controller that receives sensing data from each source driver IC and therefore needs to perform a tuning operation to match the phase of a clock signal output from the source driver IC, thereby having the effect of not needing to perform an additional tuning operation for matching the phase of the clock signal.

[0133] In addition, according to the present disclosure, since only some of the multiple source driver ICs transmit clock signals and sensing data to the timing controller, the number of wires formed on the board of the display device to transmit clock signals and sensing data to the timing controller can be reduced compared to the number of wires formed on the board of a conventional display device, thereby having the effect of being able to reduce the size of the board of the display device.

[0134] Furthermore, according to the present disclosure, since the number of wires formed on the board is reduced compared to the number of wires formed in a conventional board, the number of wires included in a cable connected between the board and a timing controller can be reduced, thereby having the effect of being able to reduce the size of the cable.

[0135] CROSS-REFERENCE TO RELATED APPLICATIONS

[0136] This application claims the benefit of Korean Patent Application No. 10-2020-0011453, filed on January 31, 2020, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A source driver IC, comprising: a first buffer in which first sensing data transmitted from the first source driver IC is stored; a sensing data generating circuit configured to sense a characteristic of a driving element included in each pixel and generate second sensing data; a second buffer, wherein the second sensing data is stored in the second buffer; a control circuit configured to generate a selection signal in response to a transfer command; as well as a selector configured to transmit one of the first sensing data stored in the first buffer and the second sensing data stored in the second buffer to a second source driver IC or a timing controller in response to the selection signal, wherein, when receiving a first transmission command from the timing controller, the selector transmits the second sensing data to the second source driver IC, the second source driver IC transmits the third sensing data generated by the second source driver IC to the timing controller, and When receiving a second transmission command from the timing controller, the selector transmits the first sensing data to the second source driver IC, and the second source driver IC transmits the second sensing data transmitted from the selector to the timing controller.

2. The source driver IC according to claim 1, further comprising: a first pin, the first pin being configured to receive the first sensing data; a second pin, the second pin being configured to receive a first clock signal associated with transmission of the first sensing data; a third pin connected to an output terminal of the selector to transmit one of the first sensing data and the second sensing data to the second source driver IC or the timing controller; as well as and a fourth pin configured to transmit a second clock signal related to the transmission of the second sensing data to the second source driver IC or the timing controller. 3 . The source driver IC according to claim 2 , further comprising a Clock Embedded Data Signaling (CEDS) control packet receiving pin configured to receive a CEDS control packet including the transmission command and output from a timing controller.

4. The source driver IC according to claim 2, wherein: The second clock signal is determined according to a clock signal included in a CEDS control packet complying with the CEDS protocol.

5. The source driver IC according to claim 2, further comprising: a data packet receiving pin configured to receive a data packet (CDATA) including the transmission command and output from the timing controller; as well as A reference clock receiving pin is configured to receive a reference clock signal (ACLK) output from the timing controller and related to the transmission of the data packet (CDATA).

6. The source driver IC according to claim 5, wherein: The control circuit generates the second clock signal according to the reference clock signal (ACLK).

7. The source driver IC according to claim 1, wherein: When a first transfer command is received from the timing controller, sensing data generated by sensing a characteristic of a driving element included in each pixel connected to the first source driver IC is received as the first sensing data, and When the second transmission command is received from the timing controller, the sensing data transmitted from another source driver IC to the first source driver IC is received as the first sensing data.

8. A display device comprising a data driving circuit block, the data driving circuit block comprising a plurality of source driver ICs, each of the plurality of source driver ICs being configured to sense a characteristic of a driving element included in each pixel and obtain sensing data, in, Each of the plurality of source driver ICs includes: a first source driver IC connected to a first pixel and configured to transmit first sensing data obtained by sensing a characteristic of a driving element included in the first pixel to the timing controller when receiving a first transmission command from the timing controller, and A second source driver IC connected to a second pixel and configured to transmit second sensing data obtained by sensing a characteristic of a driving element included in the second pixel to the first source driver IC when receiving the first transmission command.

9. The display device according to claim 8, wherein: When receiving a second transmission command from the timing controller, the first source driver IC transmits the second sensing data received from the second source driver IC to the timing controller, and When receiving the second transfer command, the second source driver IC transfers the third sensing data or dummy data received from the third source driver IC to the first source driver IC.

10. The display device according to claim 8, wherein: The plurality of source driver ICs are connected in a cascade manner for transmitting the sensing data.

11. The display device according to claim 8, wherein: The data driving circuit block further includes a board connected to the first source driver IC and the second source driver IC, Wherein, the board includes a first wire and a second wire, the first wire is used to transmit the second sensing data transmitted from the second source driver IC to the first source driver IC, and the second wire is used to transmit the clock signal output from the second source driver IC and related to the transmission of the second sensing data to the first source driver IC.

12. The display device according to claim 9 further comprises a timing controller, which is configured to generate a control command and transmit the control command to the multiple source driver ICs, the control command comprising a sensing command for enabling the multiple source driver ICs to obtain the sensing data, one of the first transmission command and the second transmission command.

13. The display device according to claim 12, wherein: The timing controller generates the control command in the form of a control packet complying with the Clock Embedded Data Signaling (CEDS) protocol, and The plurality of source driver ICs output an output clock signal together with the sensing data, the output clock signal being determined based on a clock signal included in the control packet.

14. The display device according to claim 12, wherein: The timing controller generates the control command in the form of a data packet (CDATA), and transmits a reference clock signal (ACLK) associated with transmission of the data packet (CDATA) to the plurality of source driver ICs in a point-to-point manner.

15. The display device according to claim 14, wherein: The plurality of source driver ICs generate output clock signals related to transmission of the sensing data according to the reference clock signal (ACLK), and output the sensing data using the output clock signals.

16. The display device according to claim 12, wherein: The timing controller is connected to the plurality of source driver ICs in a point-to-point manner to transmit the control command to the plurality of source driver ICs, and The first source driver IC is connected to the timing controller in a point-to-point manner to transmit the first sensing data to the timing controller.

17. A method of operating a display device, the display device comprising a timing controller, a first source driver IC connected to a first pixel group, and a second source driver IC connected to a second pixel group, the method comprising the following steps: generating, by the first source driver IC, first sensing data by sensing pixels included in the first pixel group, and generating, by the second source driver IC, second sensing data by sensing pixels included in the second pixel group in response to a sensing command output from the timing controller; transmitting the first sensing data to the timing controller through the first source driver IC, and transmitting the second sensing data to the first source driver IC through the second source driver IC in response to a first transmission command output from the timing controller; as well as The second sensing data transmitted from the second source driver IC is transmitted to the timing controller through the first source driver IC in response to a second transmission command output from the timing controller.

18. The method according to claim 17, further comprising the steps of: generating, by the first source driver IC, a first clock signal related to transmission of the first sensing data according to a reference clock signal output from the timing controller, and transmitting the first clock signal and the first sensing data to the timing controller; as well as A second clock signal related to transmission of the second sensing data is generated by the second source driver IC according to the reference clock signal, and the second clock signal and the second sensing data are transmitted to the first source driver IC.

Images