Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. A method includes: forming a fin extending from a substrate; forming a first isolation region along opposite sidewalls of the fin; forming a gate structure on the fin; forming an epitaxial source / drain region in the fin adjacent to the gate structure; forming an etch stop layer on the epitaxial source / drain region and on the gate structure; forming a protective layer on the etch stop layer, the protective layer comprising silicon oxynitride; and forming a second isolation material on the protective layer, wherein forming the second isolation material reduces the nitrogen concentration of the protective layer.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other issues arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a fin extending from a substrate; forming a first isolation region along opposite side walls of the fin; forming a gate structure above the fin; forming an epitaxial source / drain region in the fin adjacent to the gate structure; forming an etch stop layer above the epitaxial source / drain region and above the gate structure; forming a protective layer above the etch stop layer, the protective layer comprising silicon oxynitride; and forming a second isolation material above the protective layer, wherein forming the second isolation material reduces the nitrogen concentration of the protective layer.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a semiconductor fin protruding from a substrate; forming a gate stack above the semiconductor fin; forming a source / drain region adjacent to the gate stack on the semiconductor fin; forming a first dielectric layer extending above the source / drain region and the gate stack; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is a material different from the first dielectric layer, wherein the second dielectric layer is formed to have a first nitrogen atomic percentage; forming an insulating layer on the second dielectric layer, wherein the insulating layer is a material different from the second dielectric layer; performing an annealing process, wherein after performing the annealing process, the second dielectric layer has a second nitrogen atomic percentage, the second nitrogen atomic percentage being less than the first nitrogen atomic percentage; and after performing the annealing process, forming a conductive feature extending through the insulating layer, the second dielectric layer, and the first dielectric layer to contact the source / drain region.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a fin extending from a semiconductor substrate; a gate stack above the fin and along the sidewall of the fin; a gate spacer along the sidewall of the gate stack and the sidewall of the fin; an epitaxial source / drain region in the fin and adjacent to the gate stack; a silicon nitride layer extending above the epitaxial source / drain region and the gate spacer; a silicon oxynitride layer on the silicon nitride layer; an insulating layer on the silicon oxynitride layer; and a contact extending through the insulating layer, the silicon oxynitride layer, and the silicon nitride layer to the epitaxial source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a FinFET in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig.17A and Fig. 17B is a three-dimensional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Fig.18 and Fig.19 Experimental data for the conversion of a protection layer to a conversion layer according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0013] According to various embodiments, a method for forming a protective layer over a source / drain region of a transistor device (e.g., a FinFET) is provided. An intermediate stage of forming a protective layer is shown according to some embodiments. Some variations of some embodiments are discussed. The protective layer may be a dielectric layer, such as silicon oxynitride, formed over an etch stop layer. The protective layer may reduce or prevent damage to the source / drain region during subsequent processing steps. For example, the protective layer may reduce or prevent oxidation of the source / drain region during the formation of an interlayer dielectric (ILD) layer. The protective layer may allow the use of a thinner etch stop layer without increasing the risk of damaging the source / drain region. In some cases, a thinner etch stop layer may improve the repeatability and reliability of forming source / drain contacts. An annealing process may be performed to reduce the nitrogen content of the protective layer, which may allow the protective layer to be etched more easily. The annealing process may be part of an ILD layer formation process. In this way, the source / drain region may be protected by the protective layer without significantly affecting the contacts formed to the source / drain region. Furthermore, the protection layer allows the formation of a thinner contact etch stop layer (CESL), which can provide a better metal landing (MD) window on the thinner CESL.

[0014] Figure 1An example of a FinFET in a three-dimensional view according to some embodiments is shown. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is disposed in the substrate 50, and the fin 52 is above and protrudes from adjacent isolation regions 56. Although the isolation region 56 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 52 is shown as a single continuous material of the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to a portion extending between adjacent isolation regions 56.

[0015] Gate dielectric layer 92 is along the sidewalls of fin 52 and over the top surface of fin 52, and gate electrode 94 is over gate dielectric layer 92. Source / drain regions 82 are disposed on an opposite side of fin 52 relative to gate dielectric layer 92 and gate electrode 94. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of fin 52 and in a direction of current flow, for example, between source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0016] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0017] Figures 2 to 17B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 Shows Figure 1 Reference cross section AA is shown, except for multiple fins / FinFETs. Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A Figure 15A Fig.16A and Fig.17A Along Figure 1 The reference cross section AA shown is shown, and Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 15C , Figure 16B and Fig. 17B Along Figure 1 A similar cross section BB is shown, except with multiple fins / FinFETs. Fig. 10C and Fig. 10D Along Figure 1 Reference cross section CC is shown showing, in addition to multiple fins / FinFETs.

[0018] exist Figure 2 In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. For example, the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0019] Substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor (such as an n-type FinFET). Region 50P can be used to form a p-type device, such as a PMOS transistor (such as a p-type FinFET). Region 50N can be physically separated from region 50 (as shown by separator 51), and any number of device features (such as other active devices, doped regions, isolation structures, etc.) can be set between region 50N and region 50P.

[0020] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic.

[0021] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-alignment process, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fin 52.

[0022] exist Figure 4 In the embodiment, an insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by a process such as high density plasma chemical vapor deposition (HDP-CVD), flowable FCVD (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it into another material (e.g., oxide)), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material such as the above-described filling material may be formed over the liner.

[0023] exist Figure 5 In the embodiment, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be utilized. The planarization process exposes the fin 52 so that the top surfaces of the fin 52 and the insulating material 54 are flush after the planarization process is completed. In embodiments where the mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that after the planarization process is completed, the mask or the top surfaces of the fin 52 and the insulating material 54, respectively, are flush.

[0024] exist Figure 6Insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. Insulating material 54 is recessed so that the upper portions of fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56. In addition, the top surface of STI region 56 may have a flat surface, a convex surface, a concave surface (e.g., dished), or a combination thereof as shown. The top surface of STI region 56 may be formed to be flat, convex, and / or concave by appropriate etching. STI region 56 may be recessed using an acceptable etching process (e.g., an etching process that is selective to the material of insulating material 54 (e.g., etches the material of insulating material 54 at a faster rate than the material of fin 52)). For example, oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.

[0025] refer to Figures 2 to 6 The process described is only one example of how fin 52 may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 52. For example, Figure 5 The fin 52 in the substrate 50 may be recessed, and a material different from the fin 52 may be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 includes the recessed material, and the epitaxially grown material arranged over the recessed material. In another embodiment, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments in which a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and subsequent implantations, but in-situ doping and implantation doping may be used together.

[0026] In addition, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SiGe). x Ge 1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to: indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0027] Further in Figure 6 In the embodiment of the present invention, appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the region 50N, and an N-well may be formed in the region 50P. In some embodiments, a P-well or an N-well is formed in both the region 50N and the region 50P.

[0028] In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, e.g., a PMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N (e.g., an NMOS region). The n-type impurity may be phosphorus, arsenic, antimony, etc., and is implanted to a level equal to or less than 10 18 cm -3 (For example, at about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0029] After the implantation of region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, for example, an NMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P (for example, a PMOS region). The p-type impurity may be boron, boron fluoride, indium, etc., and is implanted to a density equal to or less than 10 18 cm -3(For example, at about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0030] After implantation of regions 50N and 50P, annealing may be performed to repair implantation damage and activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0031] exist Figure 7 In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. For example, the dummy dielectric layer 60 can be silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized (e.g., by CMP). The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive material or a non-conductive material, and can be selected from the group including: amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polycrystalline SiGe), metal nitride, metal silicide, metal oxide and metal. The dummy gate layer 62 can be deposited by the following processes: physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 may be made of other materials having high etch selectivity relative to the etching of the isolation region. For example, the mask layer 64 may include silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. Note that the dummy dielectric layer 60 is shown not to cover only the fin 52 for illustration purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited so that the dummy dielectric layer 60 covers the STI region 56 extending between the dummy gate layer 62 and the STI region 56.

[0032] FIG. 8A to FIG. 17B Various additional steps in the fabrication of example devices are shown. Fig. 8A to Fig. 17B Features in either region 50N or region 50P are shown. For example, Fig. 8A to Fig. 17B The structure shown is applicable to both region 50N and region 50P. Differences in the structure of region 50N and region 50P, if any, are described in the text accompanying each figure.

[0033] exist Fig. 8A In 8B, the mask layer 64 (see Figure 7 ) is patterned to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form a dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from an adjacent dummy gate. The dummy gate 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

[0034] Further in Fig. 8A and Figure 8B In the embodiment, a gate sealing spacer 80 may be formed on the exposed surface of the dummy gate 72, the mask 74, and / or the fin 52. Thermal oxidation or deposition followed by anisotropic etching may form the gate sealing spacer 80. The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0035] After forming the gate sealing spacer 80, an implant for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments with different device types, similar to the above, Figure 6 As discussed in the implantation described above, a mask (e.g., photoresist) may be formed over region 50N, leaving region 50P exposed, and an appropriate type (e.g., p-type) of impurity may be implanted into the exposed fin 52 in region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over region 50P, leaving region 50N exposed, and an appropriate type (e.g., n-type) of impurity may be implanted into the exposed fin 52 in region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a doping level ranging from about 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0036] exist Fig. 9A and Fig. 9BIn the embodiment, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, and the like.

[0037] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the gate sealing spacer 80 may not be etched before the gate spacer 86 is formed, thereby producing an "L-shaped" gate sealing spacer), spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type and p-type devices. For example, an LDD region for an n-type device may be formed before the gate sealing spacer 80 is formed, and an LDD region for a p-type device may be formed after the gate sealing spacer 80 is formed.

[0038] exist Fig. 10A and Fig. 10B In the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fins 52 to apply stress in the corresponding channel regions 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in the fins 52 so that each dummy gate 72 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52 and may also extend through the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 70 do not short-circuit a subsequently formed gate of the resulting FinFET.

[0039] The epitaxial source / drain regions 82 in the region 50N (e.g., NMOS region) may be formed by masking the region 50P (e.g., PMOS region) and etching the source / drain regions of the fin 52 in the region 50N to form recesses in the fin 52. The epitaxial source / drain regions 82 in the region 50N are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 may include any acceptable material (e.g., suitable for n-type FinFETs). For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphide, etc. The epitaxial source / drain regions 82 in the region 50N may have surfaces that protrude from the corresponding surfaces of the fin 52 and may have small facets.

[0040] The epitaxial source / drain regions 82 in the region 50P (e.g., the PMOS region) can be formed by masking the region 50N (e.g., the NMOS region) and etching the source / drain regions of the fin 52 in the region 50P to form recesses in the fin 52. The epitaxial source / drain regions 82 in the region 50P are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 can include any acceptable material (e.g., suitable for p-type FinFETs). For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50P can include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 70 in the region 50P can also have surfaces that protrude from the corresponding surfaces of the fin 52 and can have small facets.

[0041] The epitaxial source / drain regions 82 and / or fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a dopant density of about 10 19 cm -3 and about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 80 may be doped in-situ during growth.

[0042] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets allow adjacent source / drain regions 82 of the same FinFET to merge, such as Fig. 10C In other embodiments, adjacent source / drain regions 82 remain separated after the epitaxial process is completed, such as Fig. 10D As shown. Fig. 10C and Fig. 10D In the illustrated embodiment, gate spacers 86 are formed to cover portions of the sidewalls of fins 52 that extend over STI regions 56, thereby blocking epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 86 can be adjusted to remove spacer material to allow the region of epitaxial growth to extend to the surface of STI regions 56.

[0043] exist Fig.11A and Fig. 11B in Fig. 10A and Fig. 10BA contact etch stop layer (CESL) 87 and a protective layer 100 are formed over the structure shown. The CESL 87 is formed over the epitaxial source / drain regions 82 and serves as an etch stop during the etching of the openings for forming the source / drain contacts 112 (see FIG. Figure 17A-17B CESL 87 may also help protect epitaxial source / drain regions 82 during subsequent process steps (eg, during formation of first ILD 88) (see Figure 12A-12B ). CESL 87 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxycarbonitride, etc., or a combination thereof, and may be formed using ALD, CVD, or another suitable process. The material of CESL 87 may be selected to have a different etch rate than the material of first ILD 88 above (see Figure 12A-12B ). For example, CESL 87 may be silicon nitride and first ILD 88 may be silicon oxide, but materials other than these may be used. In some embodiments, CESL 87 may have a thickness between about 2 nm and about 100 nm, but other thicknesses are possible. In some cases, a relatively thin CESL 87 may allow for easier, more controllable, and / or more reproducible etching of the openings for source / drain contacts 112.

[0044] According to some embodiments, a protective layer 100 is then formed over the CESL 87. As previously described, a relatively thin CESL 87 can allow for the formation of improved source / drain contacts 112. However, in some cases, a thinner CESL 87 provides reduced protection for the epitaxial source / drain regions 82. In some embodiments, the protective layer 100 is formed over the CESL 87 to provide additional protection for the epitaxial source / drain regions 82 during subsequent process steps. For example, the protective layer 100 can protect the epitaxial source / drain regions 82 from oxidation during the formation of the first ILD 88 (see FIG. 1 ). Fig. 12A - Figure 12B). The use of a protective layer 100 may allow the use of a relatively thin CESL 87 with less risk of damaging (eg oxidizing) the epitaxial source / drain regions 82 during subsequent processing steps.

[0045] In some embodiments, the protective layer 100 includes silicon oxynitride having a thickness between about 2 nm and about 100 nm, but other thicknesses are possible. For example, the protective layer 100 may include silicon oxynitride having a nitrogen atomic percentage between about 1% and about 10%, or may include silicon oxynitride having an oxygen atomic percentage between about 40% and about 80%. In some embodiments, the ratio of nitrogen to oxygen in the protective layer 100 formed of silicon oxynitride may be between about 1:6 and about 1:70. Other compositions or ratios of silicon, nitrogen, or oxygen in the protective layer 100 are possible, and in some cases, the protective layer 100 may include other atomic species, such as carbon. In some embodiments, an annealing or curing process is performed that reduces the nitrogen concentration of the protective layer 100, as described below with respect to Figure 12A-12B For example, using a silicon oxynitride layer as the protective layer 100 allows the source / drain regions 82 to be protected during the formation of the first ILD 88 including silicon oxide (see Figure 12A-12B ), and also allows the protection layer to be converted into a layer having a composition more similar to (eg, having a similar etch rate) the first ILD 88 (eg, silicon oxide), thus making some subsequent process steps such as etching easier to perform.

[0046] The protective layer 100 may be deposited using a suitable process such as ALD, CVD, PVD, etc. For example, in some embodiments, the protective layer 100 is a silicon oxynitride layer deposited using an ALD process, which may be performed in a processing chamber. The ALD process may use a suitable precursor for silicon oxynitride, such as O2, O3, NH3, H2O, N2, N2H2, etc. In some embodiments, the precursor may flow at a rate between about 0.1 sccm and about 10 sccm. Other gases (e.g., carrier gases) may also flow during the ALD process. In some embodiments, the concentration or ratio of nitrogen or oxygen within the silicon oxynitride layer may be controlled by controlling the flow rate or duration of the precursor. For example, the nitrogen concentration in the silicon oxynitride layer may be increased by increasing the flow rate or duration of a nitrogen-generating precursor such as NH3, N2, N2H2, etc. The oxygen concentration in the silicon oxynitride layer may be increased by increasing the flow rate or duration of an oxygen-generating precursor such as O2, H2O, O3, etc. The ratio of nitrogen to oxygen in the silicon oxynitride layer can be controlled by controlling the relative flow rates or durations of the nitrogen-generating precursor and the oxygen-generating precursor. For example, a longer duration of the flow of the oxygen-generating precursor can reduce the amount of nitrogen in the formed protective layer 100 (see also below). Fig.18 Other process parameters, materials, or techniques are possible.

[0047] exist Fig. 12A and Fig. 12B In some embodiments, Figure 11A-11BA first interlayer dielectric (ILD) 88 is formed on the structure shown. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The first ILD 88 can be formed of a dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. For example, in some embodiments, the first ILD 88 is silicon oxide formed using FCVD, wherein a CVD-based material is deposited in a remote plasma system and then cured to convert the deposited material into a silicon oxide material. In the embodiment shown, the insulating material 54 is silicon oxide formed by an FCVD process. Other dielectric materials formed by any acceptable process may be used instead.

[0048] In some embodiments, an annealing process is performed to reduce the nitrogen content of the protective layer 100. The annealing process may be performed as a curing step in the FCVD process, or may be performed outside the FCVD curing step. Figure 12A-12B 100 'is shown as a conversion layer. The annealing process can be performed in a suitable processing chamber (e.g., a deposition chamber), an oven, etc. In some embodiments, the annealing process is performed at a temperature between about 400°C and about 1000°C. In some embodiments, the annealing process is performed using one or more process gases, which may include argon, N2, H2, steam, H2O, O2, O3, etc. or a combination thereof. In some embodiments, the annealing process can be performed for a duration between about 0.5 hours and about 4 hours.

[0049] The annealing process removes nitrogen from the protective layer 100, so the nitrogen concentration of the conversion layer 100' is lower than that of the protective layer 100. In some cases, the annealing process removes nitrogen by reacting H2O with the silicon oxynitride to replace nitrogen atoms with oxygen atoms, and captures the nitrogen as a reaction product of NH3, which can be purged from the processing chamber. For example, in some embodiments, the protective layer 100 is a silicon oxynitride having a first nitrogen atomic percentage, and the conversion layer 100' is a silicon oxynitride having a second nitrogen atomic percentage, which is less than the first nitrogen atomic percentage. In some embodiments, the annealing process can form a conversion layer 100' having less than about half the amount of nitrogen in the initial protective layer 100. For example, the conversion layer 100' can have 0% to about 5% of the amount of nitrogen in the initial protective layer 100.

[0050] This is Fig.18FIG. 4 shows experimental data of the nitrogen atomic percentage in four sample protective layers A, B, C and D and the corresponding conversion layers A, B, C and D after performing an annealing process. Fig.18 As shown, the annealing process reduces the nitrogen atomic percentage in the protective layer 100. For example, the conversion layer of sample A has only about 5.6% of the nitrogen atomic percentage in the initial protective layer of sample A. Similarly, the conversion layers of samples B, C, and D have about 15.8%, about 20%, and about 47.8% of the nitrogen atomic percentage in their initial protective layers, respectively. In this way, the nitrogen atomic percentage of the conversion layer can be less than one-fifth of the nitrogen atomic percentage of the initial protective layer. The amount of nitrogen in the conversion layer 100' can depend on the amount of nitrogen in the initial protective layer 100, or the parameters of the annealing process. For example, an annealing process using a longer duration and / or a higher temperature can remove more nitrogen than an annealing process using a shorter duration and / or a lower temperature. These are just examples, and other results are possible.

[0051] also, Fig.18 It is shown how controlling the exposure of different precursors can be used to control the concentration of nitrogen in the protective layer 100. For example, a longer duration of oxygen precursor flow was used to form the protective layer of sample A than to form the protective layers of samples B, C, or D. Due to the increased duration of the oxygen precursor flow, the protective layer (and conversion layer) of sample A has the smallest nitrogen atomic percentage of the four samples. As another example, sample D has the shortest duration of oxygen precursor flow of the four samples and therefore has the largest nitrogen atomic percentage. These are examples, and other results or techniques for controlling layer composition are possible.

[0052] By using an annealing process to convert the protective layer 100 into the conversion layer 100', the impact of the protective layer 100 on subsequent process steps can be reduced. For example, by using an annealing process to reduce the nitrogen content of the protective layer 100, the remaining conversion layer 100' can be more easily etched, such as during the formation of the opening for the source / drain contact 112 (see Figure 17A-17B ). In some cases, by converting the protective layer 100 to the conversion layer 100', the protective layer 100 does not significantly serve as an additional etch stop layer, thereby retaining the benefits of the thin CESL 87. In this way, the epitaxial source / drain regions 82 can be protected from oxidation even when the thin CESL 87 is used. For example, Fig.19 8 shows experimental data of the relative concentrations of several atomic species versus depth after forming ILD 88. Fig.19 As shown, the oxygen concentration in the epitaxial source / drain region 82 is very small, indicating that due to the presence of the protective layer 100 (e.g. Fig.19 The conversion layer 100' in the embodiment reduces oxidation.

[0053] Go to Fig.13A and Fig. 13B , a planarization process such as CMP may be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process also removes the mask 74 on the dummy gate 72, and portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0054] exist Fig.14A and Fig. 14B In the embodiment of the present invention, the dummy gate 72 and the mask 74 (if present) are removed in (one or more) etching steps, thereby forming a recess 90. The portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in the first area of ​​the die (e.g., the core logic area) and remains in the recess 90 in the second area of ​​the chip (e.g., the input / output area). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using such (one or more) reactive gases that selectively etch the dummy gate 72 without etching the first ILD 88 or the gate spacer 86. Each recess 90 exposes and / or overlies the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then be optionally removed after the dummy gate 72 is removed.

[0055] exist Fig.15A and Fig. 15B In the embodiment, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Fig. 15C Shows Fig. 15BDetailed view of region 89 of . A gate dielectric layer 92 is conformally deposited in the recess 90, for example on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate seal spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments in which a portion of the dummy gate dielectric 60 remains in the recess 90, the gate dielectric layer 92 includes the material of the dummy gate dielectric 60 (e.g., SiO2).

[0056] The gate electrodes 94 are deposited on the gate dielectric layer 92 and fill the rest of the recess 90. The gate electrodes 94 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although a single-layer gate electrode 94 is shown in FIG. 14B , the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler materials 94C, such as Fig. 15C As shown. After filling the recess 90, a planarization process such as CMP may be performed to remove the material of the gate electrode 94 and the excess portion of the gate dielectric layer 92 that is above the top surface of the ILD layer 88. The material of the gate electrode 94 and the remaining portion of the gate dielectric layer 92 thus form a replacement gate for the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0057] The formation of gate dielectric layer 92 in region 50N and region 50P may occur simultaneously, such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 94 may occur simultaneously, such that gate electrode 94 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region may be formed by a different process, such that gate dielectric layer 92 may be a different material, and / or gate electrode 94 in each region may be formed by a different process, such that gate electrode 94 may be a different material. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0058] exist Fig.16A and Fig. 16B In some embodiments, the second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD (FCVD) method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. According to some embodiments, before forming the second ILD 108, the gate stack (including the gate dielectric layer 92 and the corresponding overlying gate electrode 94) is recessed to form a groove directly above the gate stack and between the opposing portions of the gate spacer 86, such as Fig.16A 16B. A gate mask 96 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and then a planarization process is performed to remove the excess portion of the dielectric material extending above the first ILD 88. The gate contact 110 ( Fig.17A 17B ) through the gate mask 96 to contact the top surface of the recessed gate electrode 94 .

[0059] exist Fig.17A and Fig. 17B 88, a gate contact 110 and a source / drain contact 112 are formed through the second ILD 108 and the first ILD 88 according to some embodiments. An opening for the gate contact 110 is formed through the second ILD 108 and the gate mask 96. An opening for the source / drain contact 112 is formed through the first and second ILDs 88, 108 and the CESL 87. The opening for the source / drain contact 112 also extends through the conversion layer 100′ ( Figure 17A-17B108). Acceptable photolithography and etching techniques may be used to form the opening. For example, one or more suitable anisotropic dry etching processes may be used to etch the opening. A liner such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of ILD 108. The remaining liner and conductive material form a source / drain contact 112 and a gate contact 110 in the opening. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. The source / drain contact 112 and the gate contact 110 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the source / drain contact 112 and the gate contact 110 may be formed in different cross sections, which may avoid shorting of the contacts.

[0060] Embodiments herein can achieve advantages. As described herein, using a protective layer over the source / drain region can reduce damage to the source / drain region during subsequent process steps. For example, the protective layer can reduce or prevent oxidation of the source / drain region during the formation of the ILD layer. Using a protective layer can also allow a thinner contact etch stop layer to be formed without increasing the risk of damage to the source / drain region. In some cases, a thinner contact etch stop layer can allow contacts to be formed to the source / drain region more easily or more reproducibly. In addition, an annealing process can be performed to convert the protective layer into a conversion layer with less nitrogen. For example, a protective layer of silicon oxynitride can be converted into a conversion layer of silicon oxide, or a conversion layer of silicon oxynitride with a smaller nitrogen concentration. Reducing the nitrogen content of the protective layer in this way can also allow contacts to be formed to the source / drain region more easily or more reproducibly.

[0061] According to an embodiment, a method includes: forming a fin extending from a substrate; forming a first isolation region along opposite sidewalls of the fin; forming a gate structure above the fin; forming an epitaxial source / drain region in the fin adjacent to the gate structure; forming an etch stop layer above the epitaxial source / drain region and above the gate structure; forming a protective layer above the etch stop layer, the protective layer comprising silicon oxynitride; and forming a second isolation material above the protective layer, wherein forming the second isolation material reduces the nitrogen concentration of the protective layer. In an embodiment, the second isolation material comprises silicon oxide. In an embodiment, forming the protective layer comprises using an atomic layer deposition (ALD) process. In an embodiment, after forming the second isolation material, the nitrogen atomic percentage of the protective layer is less than 10%. In an embodiment, forming the second isolation material comprises performing an annealing process that converts the protective layer from silicon oxynitride to silicon oxide. In an embodiment, the thickness of the protective layer is between 1 nm and 3 nm. In an embodiment, forming the second isolation material comprises a flowable chemical vapor deposition (FCVD) process. In an embodiment, the method includes forming an opening extending through the second isolation material, the protection layer, and the etch stop layer to expose the epitaxial source / drain region, and depositing a conductive material within the opening.

[0062] According to an embodiment, a method of forming a semiconductor device includes: forming a semiconductor fin protruding from a substrate; forming a gate stack on the semiconductor fin; forming a source / drain region on the semiconductor fin adjacent to the gate stack; forming a first dielectric layer extending over the source / drain region and the gate stack; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is a material different from the first dielectric layer, wherein the second dielectric layer is formed to have a first nitrogen atomic percentage; forming an insulating layer on the second dielectric layer, wherein the insulating layer is a material different from the second dielectric layer; performing an annealing process, wherein after performing the annealing process, the second dielectric layer has a second nitrogen atomic percentage, which is less than the first nitrogen atomic percentage; and after performing the annealing process, forming a conductive feature extending through the insulating layer, the second dielectric layer, and the first dielectric layer to contact the source / drain region. In an embodiment, the first dielectric layer is silicon nitride. In an embodiment, the thickness of the first dielectric layer is between 2 nm and 100 nm. In an embodiment, the annealing process is performed at a temperature between 400° C. and 1000° C. In an embodiment, the second dielectric layer is silicon oxynitride and the first nitrogen atomic percentage is between 1% and 20%. In an embodiment, the second nitrogen atomic percentage is less than one fifth of the first nitrogen atomic percentage. In an embodiment, the insulating layer is silicon oxide.

[0063] According to an embodiment, a device includes: a fin extending from a semiconductor substrate; a gate stack over the fin and along the sidewall of the fin; a gate spacer along the sidewall of the gate stack and the sidewall of the fin; an epitaxial source / drain region in the fin and adjacent to the gate stack; a silicon nitride layer extending over the epitaxial source / drain region and the gate spacer; a silicon oxynitride layer on the silicon nitride layer; an insulating layer on the silicon oxynitride layer; and a contact extending through the insulating layer, the silicon oxynitride layer, and the silicon nitride layer to the epitaxial source / drain region. In an embodiment, the insulating layer includes silicon oxide. In an embodiment, the silicon oxynitride layer is thicker than the silicon nitride layer. In an embodiment, the thickness of the silicon oxynitride layer is between 1 nm and 3 nm. In an embodiment, the nitrogen atomic concentration of the silicon oxynitride layer is between 1% and 20%.

[0064] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0065] Example 1 is a method for forming a semiconductor device, comprising: forming a fin extending from a substrate; forming a first isolation region along relative side walls of the fin; forming a gate structure above the fin; forming an epitaxial source / drain region in the fin adjacent to the gate structure; forming an etch stop layer above the epitaxial source / drain region and above the gate structure; forming a protective layer above the etch stop layer, the protective layer comprising silicon oxynitride; and forming a second isolation material above the protective layer, wherein forming the second isolation material reduces the nitrogen concentration of the protective layer.

[0066] Example 2 is the method of Example 1, wherein the second isolation material includes silicon oxide.

[0067] Example 3 is the method of Example 1, wherein forming the protective layer includes using an atomic layer deposition (ALD) process.

[0068] Example 4 is the method of Example 1, wherein after forming the second isolation material, the nitrogen atomic percentage of the protection layer is less than 10%.

[0069] Example 5 is the method of Example 1, wherein forming the second isolation material includes performing an annealing process that converts the protective layer from silicon oxynitride to silicon oxide.

[0070] Example 6 is the method of Example 1, wherein the thickness of the protective layer is between 1 nm and 3 nm.

[0071] Example 7 is the method of Example 1, wherein forming the second isolation material comprises a flowable chemical vapor deposition (FCVD) process.

[0072] Example 8 is the method of Example 1, further comprising: forming an opening extending through the second isolation material, the protective layer, and the etch stop layer to expose the epitaxial source / drain region, and depositing a conductive material in the opening.

[0073] Example 9 is a method for forming a semiconductor device, the method comprising: forming a semiconductor fin protruding from a substrate; forming a gate stack above the semiconductor fin; forming a source / drain region on the semiconductor fin adjacent to the gate stack; forming a first dielectric layer extending above the source / drain region and the gate stack; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is a material different from the first dielectric layer, wherein the second dielectric layer is formed to have a first nitrogen atomic percentage; forming an insulating layer on the second dielectric layer, wherein the insulating layer is a material different from the second dielectric layer; performing an annealing process, wherein after performing the annealing process, the second dielectric layer has a second nitrogen atomic percentage, the second nitrogen atomic percentage being less than the first nitrogen atomic percentage; and after performing the annealing process, forming a conductive feature extending through the insulating layer, the second dielectric layer, and the first dielectric layer to contact the source / drain region.

[0074] Example 10 is the method of Example 9, wherein the first dielectric layer is silicon nitride.

[0075] Example 11 is the method of Example 9, wherein the thickness of the first dielectric layer is between 2 nm and 100 nm.

[0076] Example 12 is the method of Example 9, wherein the annealing process is performed at a temperature between 400°C and 1000°C.

[0077] Example 13 is the method of Example 9, wherein the second dielectric layer is silicon oxynitride, and wherein the first nitrogen atomic percentage is between 1% and 20%.

[0078] Example 14 is the method of Example 9, wherein the second nitrogen atomic percentage is less than one-fifth of the first nitrogen atomic percentage.

[0079] Example 15 is the method of Example 9, wherein the insulating layer is silicon oxide.

[0080] Example 16 is a semiconductor device comprising: a fin extending from a semiconductor substrate; a gate stack over the fin and along the sidewalls of the fin; a gate spacer along the sidewalls of the gate stack and the sidewalls of the fin; an epitaxial source / drain region in the fin and adjacent to the gate stack; a silicon nitride layer extending over the epitaxial source / drain region and the gate spacer; a silicon oxynitride layer on the silicon nitride layer; an insulating layer on the silicon oxynitride layer; and a contact extending through the insulating layer, the silicon oxynitride layer, and the silicon nitride layer to the epitaxial source / drain region.

[0081] Example 17 is the device of Example 16, wherein the insulating layer comprises silicon oxide.

[0082] Example 18 is the device of Example 16, wherein the silicon oxynitride layer is thicker than the silicon nitride layer.

[0083] Example 19 is the device of Example 16, wherein the silicon oxynitride layer has a thickness between 1 nm and 3 nm.

[0084] Example 20 is the device of Example 16, wherein the nitrogen atomic concentration of the silicon oxynitride layer is between 1% and 20%.

Claims

1. A method for forming a semiconductor device, comprising: forming a fin extending from the substrate; forming a first isolation region along opposite sidewalls of the fin; forming a dummy gate structure on the fin; forming an epitaxial source / drain region in the fin adjacent to the dummy gate structure; forming an etch stop layer over the epitaxial source / drain region and over the dummy gate structure; forming a protective layer on the etch stop layer, the protective layer comprising silicon oxynitride; forming a second isolation material on the protective layer, wherein forming the second isolation material comprises performing an annealing process, wherein the annealing process reduces the nitrogen concentration of the protective layer, wherein the annealing process comprises controlling the annealing temperature or the annealing duration so that the nitrogen concentration in the protective layer is reduced by at least 80 percent; and After performing the annealing process, the dummy gate structure is replaced with a replacement gate structure.

2. The method according to claim 1, wherein: The second isolation material includes silicon oxide.

3. The method according to claim 1, wherein: Forming the protection layer includes using an atomic layer deposition (ALD) process.

4. The method according to claim 1, wherein: After forming the second isolation material, the nitrogen atomic percentage of the protection layer is less than 10%.

5. The method according to claim 1, wherein: The annealing process converts the protective layer from silicon oxynitride to silicon oxide.

6. The method according to claim 1, wherein: The thickness of the protective layer is between 1 nm and 3 nm.

7. The method according to claim 1, wherein: Forming the second isolation material includes a flowable chemical vapor deposition (FCVD) process.

8. The method according to claim 1, further comprising: An opening is formed extending through the second isolation material, the protection layer, and the etch stop layer to expose the epitaxial source / drain region, and a conductive material is deposited in the opening.

9. A method for forming a semiconductor device, the method comprising: forming a semiconductor fin protruding from a substrate; forming a gate stack on the semiconductor fin; forming a source / drain region on the semiconductor fin adjacent to the gate stack; forming a first dielectric layer extending over the source / drain regions and a topmost surface of the gate stack; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is a different material than the first dielectric layer, wherein the second dielectric layer is formed to have a first atomic percentage of nitrogen, wherein after forming the second dielectric layer, the first dielectric layer and the second dielectric layer extend above a topmost surface of the gate stack; forming an insulating layer on the second dielectric layer, wherein the insulating layer is a material different from that of the second dielectric layer; performing an annealing process, wherein after performing the annealing process, the second dielectric layer has a second nitrogen atomic percentage, the second nitrogen atomic percentage being less than one fifth of the first nitrogen atomic percentage; and After performing the annealing process, conductive features are formed extending through the insulating layer, the second dielectric layer, and the first dielectric layer to contact the source / drain regions.

10. The method according to claim 9, wherein: The first dielectric layer is silicon nitride.

11. The method according to claim 9, wherein: The thickness of the first dielectric layer is between 2 nm and 100 nm.

12. The method according to claim 9, wherein: The annealing process is performed at a temperature between 400°C and 1000°C.

13. The method according to claim 9, wherein: The second dielectric layer is silicon oxynitride, and wherein the first nitrogen atomic percentage is between 1% and 20%.

14. The method according to claim 9, wherein: The insulating layer is silicon oxide.

15. A semiconductor device comprising: a fin extending from a semiconductor substrate; a gate stack over the fin and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and a sidewall of the fin; an epitaxial source / drain region in the fin and adjacent to the gate stack; a silicon nitride layer extending over the epitaxial source / drain regions and the gate spacers; a silicon oxynitride layer on the silicon nitride layer, wherein the silicon oxynitride layer is subjected to an annealing process, the annealing process comprising controlling an annealing temperature or an annealing duration such that a nitrogen concentration in the silicon oxynitride layer is reduced by at least eighty percent; an insulating layer on the silicon oxynitride layer; and A contact extends through the insulating layer, the silicon oxynitride layer, and the silicon nitride layer to the epitaxial source / drain region.

16. The device according to claim 15, wherein The insulating layer includes silicon oxide.

17. The device according to claim 15, wherein The silicon oxynitride layer is thicker than the silicon nitride layer.

18. The device according to claim 15, wherein The thickness of the silicon oxynitride layer is between 1 nm and 3 nm.

19. The device according to claim 15, wherein The silicon oxynitride layer has a nitrogen atomic concentration between 1% and 20%.

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