EEPROM memory device and corresponding method

Abstract

The present disclosure relates to an EEPROM memory device and a corresponding method. An electrically erasable programmable read-only memory type memory device comprises a write circuit device, the write circuit device being designed to: in response to receiving a command for writing at least one selected byte in at least one selected memory word in a memory plane, perform a write operation, the write operation comprising an erase cycle followed by a programming cycle, and the write circuit device being configured to: generate an erase voltage in memory cells of all bytes of the at least one selected memory word during the erase cycle, and generate an erase inhibit potential, the erase inhibit potential being configured relative to the erase voltage to prevent erasure of memory cells of unselected bytes of the at least one selected memory word, the unselected bytes being not the at least one selected byte.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French application No. 2001195, filed on February 6, 2020, which is hereby incorporated by reference. Technical Field

[0003] Embodiments and implementations thereof relate to integrated memory circuits and corresponding methods, and in particular to electrically erasable programmable read-only memories (EEPROMs) and corresponding methods. Background Art

[0004] In EEPROM memory, smaller memory cells and more compact high voltage transistors may require more complex activation mechanisms that occupy more surface area, which offsets the benefits of reduced memory cell size. Summary of the invention

[0005] For example, a technique called shared voltage technology, which uses a combination of positive and negative potentials to generate programming voltages, allows the shrinking of memory cells, with the disadvantage that more complex control gate switching circuits of the inverter type with complementary doped wells are required, which increases the surface area occupied by these circuits. Conventionally, a control gate switching circuit is provided for each memory word (usually composed of a byte of memory cells).

[0006] The problem becomes more severe the lower the memory density, in other words, the larger the ratio of the surface area occupied by the activation mechanism relative to the surface area occupied by the memory cells.

[0007] It is desirable to overcome the additional cost in surface area in order to gain the real advantage of reduced overall size and cost of the integrated circuit or chip of the EEPROM memory.

[0008] One solution that has been provided is to share the control gate switching circuits for a memory word consisting of several bytes, for example four bytes, in order to limit the surface area occupied by the control gate switching circuits.

[0009] However, for control gate switching circuits, grouping of several bytes in a memory word has disadvantages in terms of life expectancy.

[0010] In practice, it is advantageous for the EEPROM memory to have a "client" granularity of one byte, in other words the memory is designed to receive write commands that modify only a single byte, at least in the memory plane.

[0011] However, grouping of a few bytes per memory word imposes a "physical" granularity of a few bytes (eg, 4), in other words, the memory can only modify bytes of the memory plane in groups of a few bytes.

[0012] Conventionally, the operation for writing in a memory word erases all the bits of the memory word in a first phase and selectively programs certain bits of the word in a second phase, depending on the data to be written.

[0013] In order to be able to provide a client granularity that is smaller than the physical granularity of the memory, during the write of one byte, the other bytes of the same memory word are read and then rewritten, in other words, collectively erased and then selectively programmed based on the data they contained before being erased.

[0014] Therefore, if a number N of bytes are grouped in the same memory word, the worst possible acceleration factor for the stress on the memory cell is N. This divides the lifetime over the number of write cycles by N, which is equivalent to dividing the true expected lifetime of the memory cell by N in order to specify a nominal value for the expected lifetime of a commercially available product. In addition, a power outage during a write cycle will destroy the byte as it is being rewritten into the memory word.

[0015] Therefore, with respect to life expectancy and the ability of the isolated memory cells to retain data, the overall device specifications in terms of life expectancy and data retention are degraded.

[0016] Embodiments and implementations thereof are provided to achieve speed-up factors approaching 1 in architectures of the type described above, while fully benefiting from the reduced surface area advantages of this type of architecture.

[0017] In other words, the provided embodiments and their implementations allow for improved specifications regarding life expectancy and data retention in compact memory architectures.

[0018] According to one aspect, there is provided a memory device of the electrically erasable programmable read-only memory type, comprising: a matrix memory plane arranged in rows and columns of memory words, each memory word comprising a number of bytes of memory cells; and a write component, designed to: in response to receiving a command for writing at least one selected byte in at least one selected memory word from the memory plane, perform a write operation, the write operation comprising an erase cycle followed by a programming cycle. The number of selected bytes are usually consecutive and may also be consecutive to the bytes of the number of selected memory words.

[0019] According to a general feature of this aspect, the write component is configured to, during an erase cycle: on the one hand, generate an erase voltage in the memory cells of all bytes of at least one selected memory word, the erase voltage being designed so that the memory cells are erased; and on the other hand, generate an erase inhibit potential, the erase inhibit potential being configured relative to the erase voltage to prevent erasure of memory cells of unselected bytes of at least one selected memory word.

[0020] It goes without saying that the unselected bytes of a selected memory word are the bytes of the memory word that are not the selected bytes.

[0021] In other words, the idea is to inhibit the process of erasing bytes of a memory word that are not replaced by new data to be written, thereby avoiding rewriting of previous data (which could degrade the memory cells).

[0022] Therefore, the nominal life expectancy of the memory is not divided by N (N is the number of bytes per memory word), and there is no risk of corruption of unmodified data.

[0023] According to one embodiment, the memory cells each include a floating gate state transistor capable of storing a data value, the source of the state transistor being coupled to a source line, the source line being common to the memory cells of the same byte and being distinguishable from the source lines of other bytes of the same memory word, the device including a source line decoder, the source line decoder being configured to selectively transmit an erase inhibit potential in the source lines of unselected bytes of at least one selected memory word.

[0024] In other words, each byte of a memory word has its individual source line, and during the erase phase, the unselected bytes are selectively inhibited at the source potential.

[0025] Since the shift of the threshold voltage of the memory cell (state transistor) from a programmed state to an erased state is typically 3 to 4 volts, the inhibit potential is advantageously 3 to 4 volts.

[0026] According to one embodiment, the state transistor includes a control gate coupled to a control gate line common to memory cells of the same memory word, and the write component is configured to generate an erase voltage on the control gate line of at least one selected memory word during an erase cycle.

[0027] Thus, during an erase cycle, an erase voltage, typically about 15 volts, is collectively applied to the control gates of the state transistors of the selected memory word. Advantageously, the sign of the erase voltage is biased so as to drive the state transistors conductive (in other words, forward biased if the state transistors are N-type).

[0028] Conventionally, a voltage at the erase voltage level between the floating gate and the drain of the state transistor causes injection of charge (of a sign corresponding to the erased state) into the floating gate by the Fowler-Nordheim effect.

[0029] According to one embodiment, the write unit is configured to generate a ground reference potential in a source line of at least one selected byte during an erase cycle.

[0030] Therefore, the ground potential to the source line is transmitted to the drain of the state transistor of the selected byte via the conductive channel region, and the inhibit potential is transmitted to the drain of the state transistor in the memory cell of the unselected byte. Therefore, the erasure of the selected byte is selectively enabled, while the erasure of the unselected byte is selectively inhibited.

[0031] According to one embodiment, a device includes a read component configured to: read data contained in memory cells of at least one unselected byte of at least one selected memory word during a write operation and prior to an erase cycle, and a write component configured to: generate a programming voltage in previously programmed memory cells of at least one unselected byte of at least one selected memory word during a programming cycle.

[0032] The read component and the write component include, for example, a logic portion and an analog portion, wherein the logic portions of the read component and the write component may be incorporated into the same circuit (eg, a logic block referred to as a state machine).

[0033] Furthermore, for example, each memory cell is coupled to a bit line, and the write component is configured to generate a programming voltage on the bit line of the memory cell to be programmed during a programming cycle.

[0034] In practice, the write component may advantageously be configured to rewrite the unselected bytes using the previous data contained in the unselected bytes before and during the erase cycle, since the inhibition may be partial or complete depending on the embodiment. A series of partially inhibited erase cycles in the unselected bytes may eventually lead to an erased state of the memory cell, so providing a rewrite operation in the unselected bytes is advantageous.

[0035] However, in this embodiment, the degradation of the memory cell caused by the re-write operation in the incompletely erased memory cell is lower relative to the degradation caused by the full re-write operation in the completely erased cell. In fact, the acceleration factor of the stress on the memory cell (in other words, the degradation of the expected lifetime) is related to the amplitude of the variation of the threshold voltage of the state transistor and to the fact that these variations are in both erase-programming directions (in other words, from the programmed state to the erased state and then from the erased state to the programmed state). However, partial inhibition leads to incomplete erasure and reduces this amplitude in both directions (programming towards erasure, and erasure towards programming). The reduction in the amplitude of the variation of the threshold voltage (for example, a reduction of 4 times) correspondingly reduces the degradation of the expected lifetime.

[0036] According to one embodiment, the read component is configured to read previous data and measure a quantization of programming of previously programmed memory cells in at least one unselected byte of at least one selected memory word, and the write component is configured to generate a programming voltage in previously programmed memory cells of at least one unselected byte of at least one selected memory word if the quantization of programming measured in these memory cells is less than a margin taken on a nominal value of the quantization of programming.

[0037] In other words, in this embodiment, the reading means are configured to test whether the programming state of the memory cells of the unselected bytes has undergone a change, for example due to an incomplete erase, in order to adjust the rewriting of the memory cells with respect to the margin. This allows limiting the number of rewritings in order to limit the number of actions that can degrade the unselected bytes (even in a lesser way).

[0038] The programmed quantized and margin values ​​may, for example, correspond to a measurement of the value of the threshold voltage of a state transistor in a programmed state, and the quantized nominal value can correspond to the threshold voltage of a correctly programmed state transistor.

[0039] According to one embodiment, the erase inhibit potential is configured relative to the erase voltage to cause erase changes in memory cells of unselected bytes of at least one selected memory word, thereby causing incomplete erasure of these memory cells to prevent complete erasure of the memory cells.

[0040] According to another embodiment, the erase inhibit potential is configured relative to the erase voltage so as to cause negligible erase changes in memory cells of unselected bytes of at least one selected memory word, thereby causing negligible partial erase of these memory cells so as to prevent erasure of the memory cells.

[0041] This further embodiment may be combined with an embodiment of providing generation of a programming voltage in previously programmed memory cells of at least one unselected byte, since overprogramming of a memory cell in a programmed state (where the effect of the erase change is negligible) will not reasonably result in any wear in the memory cell.

[0042] Nevertheless, a very large number of repetitions of partial erasures (although individually negligible) may result in a change of the programmed state of the memory cell. Although theoretically an exception, this situation is covered by the following embodiments: the generation of the programming voltage is provided in the previously programmed memory cells of the unselected bytes, and advantageously, in a manner adjusted by a quantized measurement of the programming.

[0043] There is also provided an integrated circuit comprising a memory device such as defined above.

[0044] According to another aspect, a method for writing in an electrically erasable programmable read-only memory type memory is provided, the memory comprising a matrix memory plane arranged in rows and columns of memory words, each memory word comprising several bytes of memory cells, the method comprising: in response to receiving a command for writing at least one selected byte in at least one selected memory word in the memory plane, performing a write operation, the write operation comprising an erase cycle followed by a programming cycle, wherein the erase cycle comprises: on the one hand, generating an erase voltage in the memory cells of all bytes of the at least one selected memory word, the erase voltage enabling the memory cells to be erased; and on the other hand, generating an erase inhibit potential, the erase inhibit potential being configured relative to the erase voltage to prevent erasing of memory cells of unselected bytes of the at least one selected memory word.

[0045] According to one embodiment, in which memory cells of a memory each include a floating gate state transistor capable of storing a data value, sources of the state transistor being coupled to a source line that is common to the memory cells of the same byte and is distinct from source lines of other bytes of the same memory word, a method includes decoding the source lines to selectively transmit an erase inhibit potential in source lines of unselected bytes of at least one selected memory word.

[0046] According to one embodiment, wherein the state transistor includes a control gate coupled to a control gate line common to memory cells of the same memory word, the erase cycle includes generating an erase voltage on the control gate line of at least one selected memory word.

[0047] According to one embodiment, the erase cycle includes generating a ground reference potential in the source line of at least the selected byte.

[0048] According to one embodiment, a write operation includes: prior to an erase cycle, reading data contained in at least one unselected byte of at least one selected memory word; and during a programming cycle, generating a programming voltage in previously programmed memory cells of at least one unselected byte of at least one selected memory word.

[0049] According to one embodiment, each memory cell is coupled to a bit line, and a programming cycle includes generating a programming voltage on the bit line of the memory cell to be programmed.

[0050] According to one embodiment, a write operation includes: reading and measuring a programmed quantization of previously programmed memory cells in at least one unselected byte of at least one selected memory word; and generating a programming voltage in previously programmed memory cells of at least one unselected byte of at least one selected memory word if the programmed quantization measured in these memory cells is less than a margin taken on a nominal value of the programmed quantization.

[0051] According to one embodiment, the erase inhibit potential is configured relative to the erase voltage to cause erase changes in memory cells of unselected bytes of at least one selected memory word, thereby causing incomplete erasure of these memory cells to prevent complete erasure of the memory cells.

[0052] According to one embodiment, the erase inhibit potential is configured relative to the erase voltage so as to cause negligible erase changes in memory cells of unselected bytes of at least one selected memory word, thereby causing negligible partial erase of these memory cells so as to prevent erasure of the memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Other advantages and features of the present invention will become apparent upon examination of the detailed description of non-limiting examples and implementations thereof, and in light of the accompanying drawings, in which:

[0054] Figure 1 An EEPROM including a memory plane is illustrated;

[0055] Figure 2 Picture shows Figure 1 A memory cell of a memory plane;

[0056] Figure 3 Picture shows Figure 1 A portion of a memory plane;

[0057] Figure 4 illustrates a portion of a memory plane of a compact memory device; and

[0058] Figure 5 Picture shows Figure 1part of the memory plane. DETAILED DESCRIPTION

[0059] We will now describe Figures 1 to 5 , where common reference numerals in the drawings represent the same elements or elements of similar function in different embodiments. When describing a drawing, reference may be made to an element that is not shown but is described with respect to another drawing that shows it.

[0060] Generally speaking, about Figures 1 to 5 , an index "i" in a reference number indicates that the referenced element belongs to the column of index "i", and an index "j" in a reference number indicates that the referenced element belongs to the row of index "j". The index may be incremented or decremented as "i-1", "j+1", etc., and indicates that the referenced element belongs to the column or row with the respectively changed index.

[0061] Figure 1 An electrically erasable and programmable non-volatile memory device EE of the EEPROM (Electrically Erasable and Programmable Read Only Memory) type is shown, which can be manufactured in an integrated circuit in the form of an integrated circuit chip.

[0062] The memory device EE comprises a matrix memory plane PM comprising memory cells CEL ( Figure 2 The memory cells CEL are organized in memory words, in rows RGj ( Figures 3 to 5 ) and column COLi( Figures 3 to 5 ) is arranged in the word area MWEM of the memory plane PM. The memory word MWi,j( Figures 3 to 5 ) at a single intersection point between a column COLi and a row RGj of the memory plane PM. In summary, access to a memory word MWi,j is performed by matrix selection of the column COLi and row RGj to which it belongs.

[0063] Therefore, the physical granularity of the memory, in other words, the smallest unit modified in a write operation, is defined by the memory word.

[0064] At the periphery of the memory plane PM, the memory device EE comprises a write element ME, a read element ML, a column decoder DECX and a row decoder DECY.

[0065] The read means ML and the write means ME comprise a logic part and an analog part, the logic parts of the read means and the write means may be incorporated into the same circuit, for example a logic block (not shown) called a state machine.

[0066] The state machine is a unit for controlling and managing the device EE and is configured to receive commands COM, which come from outside the memory device EE and are called user commands. The user commands COM may include commands for writing a minimum of one byte and a maximum of one complete page. A byte is a group of eight memory cells, and a page corresponds to a full row of memory cells.

[0067] Therefore, the "client" granularity of the memory, in other words, the smallest unit modifiable in a write command is a byte.

[0068] However, in order to limit the space occupied by the control gate switching circuit CGSW (see below), the memory words MWi,j of the memory plane PM comprise at least two bytes of memory cells.

[0069] Therefore, the physical granularity of memory (one memory word) is larger than the client granularity for write operations (one byte).

[0070] The byte to be written is called the selected byte and the memory word comprising the byte to be written is called the selected memory word. Typically, a write command COM comprises the address of the first byte and comprises the data to be written starting from this address of the memory plane PM.

[0071] The state machine is configured to decode the address of the command into physical coordinates of the arrangement of the memory plane PM, and is configured to control the column decoder DECX and the row decoder DECY, respectively.

[0072] The write means ME are configured for performing a write operation in response to the receipt of a write command COM. The write operation comprises a collective erase cycle on all memory cells of a selected memory word followed by a selective programming cycle on each memory cell to be programmed depending on the data to be written.

[0073] The write means ME are configured to generate erase and program stimuli and to transmit them to the memory cells of the memory plane PM via the column decoder DECX and the row decoder DECY.

[0074] Figure 2 The memory plane PM ( Figure 1 ) of a memory cell CEL. The memory cell CEL includes an NMOS type state transistor TE having a floating gate and a control gate, and includes an NMOS type access transistor TA having a simple gate.

[0075] The state transistor TE and the access transistor TA are coupled in series, and the drain of the state transistor TE is coupled to the source of the access transistor TA.

[0076] The drain of the access transistor TA is coupled to the bit line BL, and the source of the state transistor TE is coupled to the source line SL.

[0077] The gate of the access transistor TA is coupled to the word line WL, and the control gate of the state transistor TE is coupled to the control gate line CG.

[0078] In order to erase the memory cell CEL, a sufficiently high voltage is applied between the control gate CG and the drain of the state transistor TE to inject charge into the floating gate of the state transistor TE by the Fowler-Nordheim effect. This erase voltage is usually about 15V between the gate and the drain (positive on the gate), and the injected charge is of negative sign. For example, an erase voltage of 15V is applied to the control gate CG of the state transistor TE, and a potential such as ground is transmitted from the source line SL via the channel region of the state transistor TE at the drain of the state transistor TE, so that the state transistor TE is controlled to be conductive.

[0079] As will be seen below, especially with regard to Figure 5 It will be seen that an erase inhibition potential of, for example, 3 V or 4 V is transmitted on the source line SL, and a constant erase voltage of 15 V is transmitted on the control gate CG of the state transistor TE. The voltage thus generated between the control gate and the drain of the state transistor TE is therefore substantially 12 V or 11 V, respectively. A gate-drain voltage of approximately 12 V or 11 V is not sufficient to cause an injection of charge by the Fowler-Nordheim effect, or at least is insufficient for injecting an amount of charge sufficient to cause complete erasure of the memory cell CEL.

[0080] In other words, the erase inhibit potential transmitted on the source line SL of the memory cell, for example, is configured with respect to the erase voltage so as to prevent the memory cell CEL from being erased.

[0081] To program the memory cell CEL, a voltage sufficient to inject charge into the floating gate of the state transistor TE by the Fowler-Nordheim effect is applied between the control gate CG and the drain of the state transistor TE. This programming voltage is typically about -15 V between the gate and the drain (negative on the gate), and the injected charge is therefore of positive sign.

[0082] In a technique known as shared voltage technology, a negative programming potential of, for example, -7 V is applied to the control gate CG of the state transistor TE, and a positive programming potential of, for example, +8 V is applied from the bit line BL to the drain of the state transistor TE via the access transistor TA, which is controlled to be conductive by a control voltage of, for example, 10 V transmitted on the word line WL.

[0083] In a technique that does not provide for the generation of a negative potential, a ground potential is applied to the control gate CG, and a positive programming potential of, for example, +15 V is applied from the bit line BL to the drain of the state transistor TE via the access transistor TA, which is controlled to be conductive by a control voltage of, for example, 17 V transmitted on the word line WL.

[0084] Figure 3 Shows Figure 1 3. A portion 300 of a memory plane PM in FIG. 3 illustrates in particular a memory word MWi,j belonging to a row RGj and a column COLi.

[0085] Also shown is a memory word MWi,j+1 belonging to row RGj+1 and column COLi, and a byte OCT0i-1 of memory words MWi-1,j and MWi-1,j+1 belonging to column COLi-1 and belonging to rows RGj, RGj+1, respectively.

[0086] Each memory word MWi,j comprises at least two bytes OCT0i to OCT3i, for example four bytes, each byte comprising eight memory cells CEL.

[0087] In the following section, the phrase "coupling of a memory cell to an element" is understood to mean the same as in the above description of Figure 2 The coupling of corresponding components is shown.

[0088] For column COLi, each memory cell is coupled to a dedicated and individual bit line BL0i, BL1i, ..., BL7i, ..., BL24i, BL25i, ..., BL31i (BL0i-1, BL1i-1, ..., BL7i-1, ... for column COLi-1).

[0089] However, the bit line BL is coupled to the corresponding memory cells of every other row RGj+1.

[0090] Memory cells CEL of the same byte OCT0i, ..., OCT3i (and OCT0i-1) are coupled to common and dedicated source lines SL0i, ..., SL3i (and SL0i-1) for each byte.

[0091] In a noteworthy manner, the source of the state transistor TE is thus coupled to a source line SL0i which is common to the memory cells of the same byte OCT0i and which is distinct from the source lines of the other bytes OCT1i-OCT3i of the same memory word MWi,j.

[0092] However, the source lines SL0i, ..., SL3i are coupled to the corresponding bytes OCT0i, ..., OCT3i of the other row RGj+1.

[0093] All memory cells of the same row RGj, RGj+1 are coupled to a word line WLj, WLj+1 that is common and specific to each row.

[0094] The memory cells of the same memory word MWi,j, MWi,j+1, MWi-1,j, MWi-1,j+1 are coupled to a common control gate line CGi,j, CGi,j+1, CGi-1,j, CGi-1,j+1. Each control gate line CGi,j is exclusively dedicated to one memory word MWi,j of column COLi and row RGj.

[0095] Access (decoding) to the control gate lines CGI,j, CGI,j+1, CGI-1,j, CGI-1,j+1 in the memory plane PM is obtained with the help of control gate switching circuits CGSWi,j, CGSWi,j+1, CGSWi-1,j, CGSWi-1,j+1, which are located in the area CGSW of the memory plane PM, close to the corresponding memory words MWi,j, MWi,j+1, MWi-1,j, MWi-1,j+1.

[0096] Each control gate switching circuit CGSWi,j comprises an inverter circuit comprising a PMOS transistor and an NMOS transistor controlled by control signals on their gates. In the region CGSW of the memory plane PM, well bias lines Bn, Bp allow the complementary wells containing the PMOS and NMOS transistors to be biased in a manner suitable for routing signals (Dpi, Dni, see below).

[0097] The control signals are transmitted on control lines CLj, CLj+1 which are common and specific to each row RGj, RGj+1.

[0098] The drains of the complementary transistors of the inverters of the respective switching circuits CGSWi,j, CGSWi-1,j are coupled to bias lines Dpi, Dni, Dpi-1, Dni-1 which are common and dedicated to each of the columns COLi, COLi-1.

[0099] The sources of the complementary transistors of the inverters of the switching circuits CGSWi,j are coupled to the corresponding control gate lines CGi,j.

[0100] Thus, the control line CLj of the row RGj and the bias lines Dpi, Dni of the column COLi allow selective transmission of a bias potential on the control gate line CGi,j of the memory word MWi,j belonging to the column COLi and the row RGj.

[0101] Such control gate switching circuits CGSWi,j occupy a non-negligible surface area, in particular due to the presence of wells with complementary doping, and in order to limit the number of control gate switching circuits, several bytes OCT0i-OCT3i are grouped within each memory word MWi,j, at the expense of a physical granularity greater than 1 byte.

[0102] It will be noted that by using a complementary circuit of the inverter type in the control gate switching circuit CGSWi,j, the bias potential on the control gate line CGi,j can be of positive or negative sign.

[0103] This enables a shared voltage write technique.

[0104] Reference again Figure 1 .

[0105] The row decoder DECY comprises a word line lock WLL configured to distribute signals in word lines WLj of the memory plane PM and a control line lock CLL configured to distribute signals in control lines CLj controlling a control gate switch CGSWi,j of each row RGj of the memory plane PM.

[0106] The column decoder DECX includes: a bit line lock BLL, configured to distribute signals among various bit lines BL0i-BL32i of the memory plane PM; a source line lock SLL, configured to distribute signals among various source lines SL0i-SL3i of the memory plane PM; and a control gate signal lock CGL, configured to distribute control gate line bias potentials Dpi, Dni to the control gate switches CGSWi,j of each column COLi of the memory plane PM.

[0107] The control gate switches CGSWi,j are located in the memory plane PM, in a middle region CGSW comprising a complementary doped well. The middle region is surrounded by a word region WMEM of the memory plane PM. The word region WMEM comprises memory cells grouped in memory words. Figure 1 In the example in , two intermediate regions of the control gate switch CGSW are provided, each intermediate region being located in the middle (in the row direction) of half of the total surface area of ​​the word area MWEM of the memory plane.

[0108] As previously mentioned Figures 1 to 3 The described area of ​​the control gate switch CGSW occupies a non-negligible surface area, but advantageously allows shared voltage write operations.

[0109] The shared voltage technique allows the size of the memory cell to be reduced, which can compensate for the surface area occupied by the control gate switch CGSW for high-density memory.

[0110] Figure 4 A portion 400 of a memory plane of an example of a memory of the type described in publication FR 3 070 537 A1 is illustrated, which describes a compact device in which the surface area occupied by the control gate switching circuits CGSi,j is reduced.

[0111] The architecture of the portion 400 of the memory plane is similar to that previously described with respect to control gate switching circuits CGSi,j, CGSi,j+1, CGSi-1,j, CGSi-1,j+1. Figures 1 to 3 The architecture of the portion 300 of the described memory plane PM is exactly the same.

[0112] In fact, in this example, each control gate switching circuit includes a single control gate selection transistor, each control gate selection transistor is accommodated within and above a semiconductor well PW1, PW0, which is adjacent to a semiconductor well PW0, PW1, which accommodates the memory word WDi,j to which it is assigned.

[0113] Figure 4 The wells PW0 and PW1 in the Figure 1 Describes the two-word area WMEM.

[0114] Therefore, in each of the two rows RGj, RGj+1, the control gate selection transistors CGSi,j, CGSi,j+1 assigned to the memory words MWi,j, MWi,j+1 are accommodated in the well PW0, which is adjacent to the well PW1, and the well PW0 accommodates the memory words MWi-1,j, MWi-1,j+1.

[0115] In contrast, the control gate selection transistors CGSi-1,j, CGSi-1,j+1 assigned to the memory words MWi-1,j, MWi-1,j+1 are accommodated in the well PW1, which is adjacent to the well PW0 and accommodates the memory words MWi,j, MWi,j+1.

[0116] Each well PW0, PW1 can accommodate several memory words belonging to several columns (within the same row RGj), as described, for example, below with respect to Figure 5 As shown, or as disclosed in FR 3070537 A1 Figure 4 Special description.

[0117] Furthermore, each memory word MWi,j comprises several bytes OCT0i-OCT3i of memory cells connected to individual bit lines BL0i-BL31i, word lines WLj and control gate lines CGi,j, such as previously described with respect to Figure 3described above; therefore, identical elements bear identical reference numerals.

[0118] The control gate selection transistors are controlled by control lines CLj, CLj+1 shared by the entire rows RGj, RGj+1, respectively, and are used to transmit signals transmitted on bias control gate lines CGSLi, CGSLi-1 dedicated to each column COLi, COLi-1 to control gate lines CGi,j, CGi-1,j, CGi,j+1, CGi-1,j+1.

[0119] In contrast to the device described in publication FR 3070537 A1, in this embodiment the source of the state transistor TE is coupled to a source line SL0i which is common to the memory cells of the same byte OCT0i and is distinct from the source lines of the other bytes OCT1i-OCT3i of the same memory word MWi,j.

[0120] It also provides information such as Figure 1 The source decoder SLL described above is formed such as by Figure 1 The illustrated memory device EE is however more compact due to the absence of the intermediate region CGSW in the memory plane PM and due to the simpler (and therefore smaller) control gate signal latch CGL.

[0121] In short, it has been about Figures 1 to 4 A memory device EE is described, comprising a matrix memory plane PM arranged in rows RGj and columns COLi of memory words MWi,j, each memory word MWi,j comprising a number of bytes OCT0i-OCT3i of memory cells CEL. A write means ME is designed to, in response to receiving a write command COM for at least one selected byte OCT0i-OCT1i in at least one selected memory word MWi,j of the memory plane PM, perform a write operation comprising an erase cycle followed by a programming cycle. The write means ME is configured to, during the erase cycle, generate an erase voltage in the memory cells CEL of all bytes OCT0i-OCT3i of the at least one selected memory word MWi,j, the erase voltage being designed such that the memory cells are erased.

[0122] According to the general characteristics of the memory device EE, and as will be described below with respect to Figure 5 Seen in more detail, the write means ME is configured to: generate, in addition, during an erase cycle, an erase inhibit potential in memory cells of unselected bytes OCT2i-OCT3i of at least one selected memory word MWi,j, the unselected bytes OCT2i-OCT3i being not at least one selected byte OCT0i-OCT1i.

[0123] The erase inhibit potential is configured relative to the erase voltage to prevent erasure of memory cells of unselected bytes OCT2i-OCT3i of at least one selected memory word MWi,j.

[0124] The memory cells CEL each comprise a floating gate state transistor TE capable of storing a data value, the source of which is coupled to a source line SL0i which is common to the memory cells of the same byte OCT0i and which is distinguished from the source lines of the other bytes OCT1i-OCT3i of the same memory word MWi,j.

[0125] The source line decoder SLL advantageously allows selective transmission of an erase inhibition potential in the source lines SL2i-SL3i of the unselected bytes OCT2i-OCT3i of at least one selected memory word MWi,j.

[0126] Figure 5 Schematically illustrates Figure 1 A portion 500 of a memory plane PM in the embodiment of the present invention comprises in particular: control gate switches CGSW dedicated to memory words MWi,j-MWi+3,j located in the word region MWEM and along a single row RGj; and corresponding memory words MWi,j-MWi+3,j.

[0127] In this example, the word area WMEM contains four memory words MWi,j, MWi+1,j, MWi+2,j, MWi+3,j in four respective columns COLi, COLi+1, COLi+2, COLi+3.

[0128] The number of memory words per word region WMEM (here 4) is essentially limited by the interconnections required to route the control gate lines CGLi,j to the corresponding memory words MWi,j. The more levels of interconnections there are in the integrated circuit, and / or the more the pitch of the interconnections decreases (the pitch of the interconnections corresponds to the width of the metal track and the distance between two adjacent tracks), the larger the number of memory words per word region WMEM can be.

[0129] To review, each memory word MWi,j-MWi+3,j includes four bytes OCT0i-OCT3i to OCT0i+3-OCT3i+3, and one control gate switching circuit CGSWi,j, CGSWi+1,j, CGSWi+2,j, CGSWi+3,j is dedicated to each memory word and is configured to transmit voltages on corresponding control gate lines CGi,j, CGi+1,j, CGi+2,j, CGi+3,j.

[0130] To recap, a source line SL0i is provided which is common to the memory cells of the same byte OCT0i and is distinguished from the source lines SL1i, SL2i, SL3i of the other bytes OCT1i, OCT2i, OCT3i of the same memory word MWi,j.

[0131] It will be noted that Figure 5 In the diagram in FIG. 1 , the point at the intersection between a source line (eg, SL0i) and a control gate line (eg, CGi,j) does not show the coupling between the two lines, but does show that: Figures 2 to 4 In the manner described, each of these two lines is coupled to the memory cells of a corresponding byte (OCT0i in this example).

[0132] Now about Figure 5 Describe a method for using in an application such as the one previously described Figures 1 to 4 An embodiment of a method of writing in a memory device EE is described.

[0133] Write component ME( Figure 1 ) is configured to perform a write operation in response to receiving a write command COM, the write operation including an erase cycle followed by a program cycle.

[0134] The user command COM may include a write command for at least one selected byte (up to a whole page) in at least one selected memory word.

[0135] The selected byte will be written with the new data transmitted in command COM.

[0136] The addresses of the selected bytes are usually consecutive in the same row from the first selected byte to the last selected byte. Preferably, the bytes of consecutive addresses are physically arranged consecutively in the memory plane, however this is not required.

[0137] According to a first example, in a write command, the selected bytes are the first two bytes OCT0i and OCT1i of the memory word MWi,j. The selected memory word is MWi,j.

[0138] In the selected memory word MWi,j, the unselected bytes OCT2i, OCT3i are the bytes that are not the selected bytes OCT0i, OCT1i.

[0139] The erase cycle comprises generating, via the control gate switching circuit CGSWi, an erase voltage of, for example, 15 V on the control gate line CGi,j of the selected memory word MWi,j and thus in all bytes OCT0i-OCT3i of the selected memory word MWi,j.

[0140] At the same time, a ground reference potential is generated in the source lines SL0i, SL1i of the selected bytes OCT0i, OCT1i; and an erase inhibition potential of, for example, 3 V is generated in the source lines SL2i, SL3i of the unselected bytes OCT2i, OCT3i.

[0141] Refer to the previous Figure 2 In the example of a programming cycle described, such an erase voltage enables erasing of memory cells, whereas such an erase inhibit potential allows preventing complete erasure of memory cells of unselected bytes OCT2i, OCT3i of the selected memory word MWi,j.

[0142] For example, depending on the state machine and the write component ME ( Figure 1 ) re-transcribed command, the source line lock SLL allows decoding to selectively transmit the erase inhibit potential and ground voltage in the corresponding source line.

[0143] In this first example, an erase inhibit potential of 3V is configured relative to an erase voltage of 15V in order to cause erase changes in the memory cells of the unselected bytes OCT2i, OCT3i.

[0144] The erase change does not result in complete erasure of the memory cells, but causes incomplete erasure of these memory cells, which do not completely lose their programmed state (if that is the case).

[0145] In fact, under these conditions, a previously programmed cell has a threshold voltage of typically -1.5V before the erase change and typically -0.5V after the erase change, while full erasure results in a threshold voltage of typically +2.5V.

[0146] After the erase cycle, the programming cycle consists of: Figure 2 In one of the described approaches, a programming voltage is generated on the bit lines BL0i-BL31i selectively for the memory cells to be programmed, and on the control gate line CGi,j.

[0147] Conventionally, a memory cell to be programmed is one that is intended to store a "1".

[0148] On the one hand, the memory cells of the selected bytes OCT0i, OCT1i are thus selectively programmed according to the data of the write command.

[0149] On the other hand, previously programmed memory cells of unselected bytes OCT2i, OCT3i of the selected memory word MWi,j are programmed again.

[0150] For this purpose, the device EE comprises conventional reading means ML configured to read the data contained in the unselected bytes OCT2i, OCT3i before an erase cycle.

[0151] Therefore, all cells programmed with a "1" end up having a threshold voltage of typically -1.5V.

[0152] The aging of these cells is determined by two shifts in threshold voltage during the erase-program cycle of +1 V and -1 V. Due to the inhibition of erase, this shift is 4 times lower than the fully erased case (i.e., from -1.5 V to +2.5 V and then from +2.5 V to -1.5 V, consisting of a shift of +4 V and -4 V).

[0153] According to the second example, in the write command, the selected bytes are all consecutive bytes from OCT3i+1 to OCT0i+3 (in other words, bytes OCT3i+1, OCT0i+2, OCT1i+2, OCT2i+2, OCT3i+2, OCT0i+3). Therefore, the selected memory words are MWi+1,j, MWi+2,j and MWi+3,j.

[0154] In the selected memory words MWi+1,j, MWi+2,j, MWi+3,j, the unselected bytes are bytes OCT0i+1, OCT1i+1, OCT2i+1 and OCT1i+3, OCT2i+3, OCT3i+3.

[0155] In a similar manner, the erase cycle includes generating an erase voltage of 15V on the control gate lines CGi+1,j, CGi+2,j, CGi+3,j of the selected memory words MWi+1,j, MWi+2,j, MWi+3,j via the control gate switching circuits CGSWi+1, CGSWi+2, CGSWi+3.

[0156] At the same time, a ground reference potential is generated in the source lines SL3i+1, SL0i+2, SL1i+2, SL2i+2, SL3i+2, SL0i+3 of the selected bytes OCT3i+1-OCT0i+3; and in the source lines SL0i+1, SL1i+1, SL2i+1 and SL1i+3, SL2i+3, SL3i+3 of the unselected bytes OCT0i+1, OCT1i+1, OCT2i+1 and OCT1i+3, OCT2i+3, OCT3i+3, an erase inhibit potential, for example 4 V this time, is generated.

[0157] In this second example, an erase inhibit potential of 4V is configured relative to an erase voltage of 15V so as to result in negligible erase changes in memory cells of unselected bytes.

[0158] Negligible erase changes cause negligible partial erasure of these memory cells, thereby preventing erasure of the memory cells, which thus retain their programmed state (if this is the case).

[0159] In fact, under these conditions, a previously programmed cell has a threshold voltage of typically -1.5V before the erase change and an unchanged threshold voltage after the erase change, while full erasure results in a threshold voltage of typically +2.5V.

[0160] After the erase cycle, you can implement Figure 2 programming cycle as described.

[0161] In a first alternative, programming is performed only in the selected bytes, given that memory cells of the unselected bytes are not modified.

[0162] According to a second alternative, programming such as described with respect to the first example is carried out in the selected bytes with the new data to be written on the one hand and in the unselected bytes with the old data contained by them on the other hand.

[0163] In practice, a very large amount of negligible erase change effect may result in an erased state of the memory cell, and this alternative prevents this from happening.

[0164] In this case, all cells that were previously programmed with a "1" end up having a threshold voltage of typically -2V.

[0165] The shift of the threshold voltage is on the one hand of low amplitude (0.5 V) and on the other hand varies monotonically (programmed on memory cells in the programmed state).

[0166] Accordingly, the aging of these units is zero.

[0167] If the operation is repeated, the cell can be programmed again with a threshold voltage of typically -2.5V or the like.

[0168] Subsequently, the inhibit potential of 4V no longer completely inhibits the erase operation, a change effect similar to that of the first example occurs during the erase phase, and equilibrium is reached at -2.5V for the programmed threshold voltage.

[0169] According to a third alternative, generation of programming voltages in previously programmed memory cells of unselected bytes of a selected memory word is adjusted by measuring a quantization of programming of the memory cells relative to a margin taken on a nominal value of the quantization of programming.

[0170] For example, the nominal value is the value of the threshold voltage of a memory cell normally programmed at -1.5V, and the margin is, for example, 1V, then any measurement for a threshold voltage greater than -0.5V in the programmed state will satisfy the condition.

[0171] In this regard, a write operation includes a quantified measurement of programming, typically the measurement of the threshold voltages of previously programmed memory cells in the unselected bytes.

[0172] For example, such a measurement of the quantization corresponds to a reading in a 'margin mode' which is usually provided in the reading means ML of an EEPROM memory.

[0173] This third alternative allows limiting the number of re-writing operations and exhibiting zero aging of the unselected cells and without any risk of data corruption.

[0174] The first, second and third alternatives each have advantages and disadvantages. The second alternative is significantly better for the reduction of aging and there is no risk of data corruption. In fact, errors during write operations (power failures, etc.) will not result in corruption of the data of the prohibited bytes. However, the second alternative may result in over-programming of the memory cells, making them more susceptible to degradation caused by hot carriers. This is not the case with the first alternative. The third alternative will not suffer from any failure of the other two alternatives, at the expense of additional measurements of quantification of programming (reading in margin mode).

[0175] For all the embodiments, examples and alternatives given above, it will be noted that since the inhibit voltage is transmitted to the source of bytes belonging to the same column but different rows, too high an inhibit voltage may generate interference in the bytes of adjacent rows. In order to maintain a good safety level, the voltage difference between the source of the unselected row and the control gate voltage of the unselected row does not exceed 4V. Since the control gate voltage in the unselected row is usually at 3V, an erase inhibit potential of up to 7V can be provided.

[0176] The embodiments described above can be applied to any given number of bytes per memory word greater than 2, up to full page operation, where the word size is the entire page, in other words, all memory cells of a row.

[0177] The embodiments described above form an optimal compromise in terms of minimization of the occupied surface area and reliability of the EEPROM memory device, in particular in terms of lifetime expectancy and data retention.

[0178] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art upon reference to the description. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. An electrically erasable programmable read-only memory device comprising: A matrix memory plane arranged in rows and columns of memory words, each memory word comprising several bytes of memory cells; a write circuit arrangement configured to, in response to receiving a command to write at least one selected byte in at least one selected memory word of the matrix memory plane, perform a write operation, wherein the write operation comprises an erase cycle followed by a program cycle, wherein the write circuit arrangement is configured to: During the erase cycle: generating an erase voltage in memory cells of all bytes of the at least one selected memory word, wherein the erase voltage is configured to cause the memory cells of the at least one selected memory word to be erased, and generating an erase inhibit potential configured relative to the erase voltage to prevent erasure of memory cells of unselected bytes of the at least one selected memory word; as well as generating, during the programming cycle, a programming voltage in previously programmed memory cells of at least one unselected byte of the at least one selected memory word; as well as A read circuit arrangement is configured to read data contained in the memory cells of the at least one unselected byte of the at least one selected memory word during the write operation and prior to the erase cycle.

2. The apparatus of claim 1 , wherein the memory cells each include a floating gate state transistor capable of storing a data value, a source of the state transistor being coupled to a source line, the source line being common to the memory cells of the same byte and being distinguishable from source lines of other bytes of the same memory word, the apparatus including a source line decoder configured to selectively transmit the erase inhibit potential in the source lines of the unselected bytes of the at least one selected memory word.

3. The apparatus of claim 2 , wherein the state transistor comprises a control gate, the control gate of the state transistor being coupled to a control gate line common to the memory cells of the same memory word, and the write circuit device is configured to: generate the erase voltage on the control gate line of the at least one selected memory word during the erase cycle.

4. The apparatus of claim 3, wherein the write circuitry is configured to generate a ground reference potential in the source line of the at least one selected byte during the erase cycle.

5. The apparatus of claim 1, wherein each memory cell is coupled to a bit line, and the write circuitry is configured to generate the programming voltage on the bit line of the memory cell to be programmed during the programming cycle.

6. The apparatus of claim 1 , wherein the read circuitry is configured to read previous data and measure a quantification of programming of previously programmed memory cells in the at least one unselected byte of the at least one selected memory word, and the write circuitry is configured to generate the programming voltage in the previously programmed memory cells of the at least one unselected byte of the at least one selected memory word in response to the quantification of programming measured in these memory cells being less than a margin taken on a nominal value of the quantification of programming.

7. The apparatus of claim 1 , wherein the erase inhibit potential is configured relative to the erase voltage so as to cause erase changes in the memory cells of the unselected bytes of the at least one selected memory word, thereby causing incomplete erasure of these memory cells so as to prevent complete erasure of the memory cells.

8. A device according to claim 1, wherein the erase inhibit potential is configured relative to the erase voltage so as to cause negligible erase changes in the memory cells of the unselected bytes of the at least one selected memory word, thereby causing negligible partial erasure of these memory cells so as to prevent the erasure of the memory cells.

9. An integrated circuit comprising: Electrically erasable programmable read-only memory devices, including: A matrix memory plane arranged in rows and columns of memory words, each memory word comprising several bytes of memory cells; a write circuit arrangement configured to, in response to receiving a command to write at least one selected byte in at least one selected memory word of the matrix memory plane, perform a write operation, wherein the write operation comprises an erase cycle followed by a program cycle, wherein the write circuit arrangement is configured to: During the erase cycle: generating an erase voltage in memory cells of all bytes of the at least one selected memory word, wherein the erase voltage is configured to cause the memory cells of the at least one selected memory word to be erased, and generating an erase inhibit potential configured relative to the erase voltage to prevent erasing of memory cells of unselected bytes of the at least one selected memory word; and During the programming cycle, generating a programming voltage in previously programmed memory cells of at least one unselected byte of the at least one selected memory word; and A read circuit arrangement is configured to read data contained in the memory cells of the at least one unselected byte of the at least one selected memory word during the write operation and prior to the erase cycle.

10. An integrated circuit as claimed in claim 9, wherein the memory cells each include a floating gate state transistor capable of storing a data value, the source of the state transistor being coupled to a source line, the source line being common to the memory cells of the same byte and being distinguishable from the source lines of other bytes of the same memory word, the device including a source line decoder, the source line decoder being configured to selectively transmit the erase inhibit potential in the source lines of the unselected bytes of the at least one selected memory word.

11. A method for writing in an electrically erasable programmable read-only memory, the electrically erasable programmable read-only memory comprising a matrix memory plane arranged in rows and columns of memory words, each memory word comprising a number of bytes of memory cells, the method comprising: receiving a command for writing at least one selected byte in at least one selected memory word in the matrix memory plane; as well as In response to receiving the command, performing a write operation, the write operation comprising: prior to the erase cycle, reading data contained in at least one unselected byte of the at least one selected memory word; The erase cycle is followed by a programming cycle, wherein the erase cycle includes: generating an erase voltage in memory cells of all bytes of the at least one selected memory word, the erase voltage enabling the memory cells to be erased; and generating an erase inhibit potential, the erase inhibit potential being configured relative to the erase voltage to prevent erasure of memory cells of unselected bytes of the at least one selected memory word; and The programming cycle includes generating a programming voltage in previously programmed memory cells of the at least one unselected byte of the at least one selected memory word.

12. A method according to claim 11, wherein the memory cells of the memory each include a floating gate state transistor capable of storing a data value, the source of the state transistor is coupled to a source line, the source line is common to the memory cells of the same byte and is different from the source lines of other bytes of the same memory word, and the method includes decoding the source line to selectively transmit the erase inhibit potential in the source line of the unselected bytes of the at least one selected memory word.

13. The method of claim 12, the state transistor comprising a control gate, the control gate of the state transistor coupled to a control gate line common to the memory cells of the same memory word, wherein the erase cycle comprises: The erase voltage is generated on the control gate line of the at least one selected memory word.

14. The method of claim 12, wherein the erase cycle comprises: A ground reference potential is generated in the source line of at least the selected byte.

15. The method of claim 11, wherein each memory cell is coupled to a bit line, and the programming cycle comprises: The program voltage is generated on the bit line of the memory cell to be programmed.

16. The method according to claim 11, wherein the writing operation comprises: reading and measuring a quantification of programming of previously programmed memory cells in said at least one unselected byte of said at least one selected memory word; and generating the programming voltage in the previously programmed memory cells of the at least one unselected byte of the at least one selected memory word in response to the quantification of the programming measured in these memory cells being less than a margin taken on a nominal value of the quantification of the programming.

17. A method according to claim 11, wherein the erase inhibit potential is configured relative to the erase voltage so as to cause erase changes in the memory cells of the unselected bytes of the at least one selected memory word, thereby causing incomplete erasure of these memory cells so as to prevent complete erasure of the memory cells.

18. A method according to claim 11, wherein the erase inhibit potential is configured relative to the erase voltage so as to cause negligible erase changes in the memory cells of the unselected bytes of the at least one selected memory word, thereby causing negligible partial erase of these memory cells so as to prevent the erase of the memory cells.

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