Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application provides a semiconductor device and a manufacturing method of a semiconductor device, in which an adverse situation caused by generation of thermal stress is suppressed in a semiconductor device having a wiring layer formed on a circuit element. The semiconductor device includes a wiring (13) formed of a conductive body extending on a surface of a semiconductor substrate through an insulating film (12), and an insulating layer (14) covering the surface of the semiconductor substrate including the wiring (13), in which a gap (18) from an upper surface of the wiring (13) to a lower portion of the insulating film (12) is provided in the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method of a semiconductor device, and particularly to a semiconductor device and a manufacturing method of a semiconductor device which suppresses a bad situation caused by thermal stress generated in a wiring. BACKGROUND

[0002] In the past, as a document which takes stress (pressure) generated in a wiring as a problem, for example, Patent Document 1 is known. In Patent Document 1, in a chip size package (hereinafter, referred to as "CSP". CSP: Chip Size Package), in an environment such as a temperature cycle test at the time of mounting the CSP, Cu wiring and a metal pillar interact with each other, give a large pressure to a transistor of an LSI located directly below, and there is a concern that the transistor characteristics are deteriorated. Further, the feature of the chip size package of Patent Document 1 is that a plurality of slits are provided in a wiring layer at the time of the chip size package, wherein the above chip size package is provided with: a wiring layer connected to a metal electrode pad and composed of Cu extending on a chip surface; an insulating layer covering a chip surface including the wiring layer; an opening portion formed in the insulating layer on the wiring layer; and a columnar terminal formed in the opening portion.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2000-183214

[0004] Figure 5 The above columnar terminal and the structure of its periphery which are generally used at the time of the CSP of the related art are shown. As shown in FIG. 1, at the time of the CSP of the related art, a circuit element region 11 formed on a semiconductor substrate (omitted from illustration) is provided, and provided are: a pad 15 formed on the circuit element region 11, a passivation film 19, an insulating film 12 formed on the passivation film 19, a wiring 13 formed on the insulating film 12 as a redistribution, and a molding resin 14 formed on the wiring 13. The wiring 13 is formed using a conductor such as copper (Cu), for example. An opening is provided at the position of the pad 15 of the passivation film 19, and the pad 15 is exposed from the opening. Figure 5 The wiring 13 is formed so as to be connected to the pad 15 at one end and extend in a predetermined direction. A columnar body 20 which corresponds to the above columnar terminal is formed at the other end of the wiring 13, and the columnar body 20 is composed of: a terminal 17, and a solder bump 21. The columnar body 20 is open to the outside, and is mounted on a printed board, for example, by the solder bump 21. In other words, the wiring 13 relays the pad 15 connected to the circuit element region 11 by a wiring which is omitted from illustration, and the columnar body 20, and connects the circuit element region 11 to the outside by the relay.

[0005]

[0006] ​However, not limited to CSP, as one of the reliability tests of semiconductor devices in general, there is a temperature cycle test. The temperature cycle test is a test in which a printed board on which a CSP or the like is mounted is put into a thermostat tank, for example, exposed to an ambient temperature in the range of -40°C to +85°C, and then a characteristic test is performed to confirm the presence or absence of defects. In the past, if a temperature cycle test is performed on a printed board on which a CSP is mounted, there are cases where electrical characteristics are defective. This is because, in a laminate of a passivation film 19, an insulating film 12, a wiring 13, a molding resin 14, or the like formed on the circuit element region 11, thermal stress caused by a difference in thermal expansion coefficient is generated, the thermal stress is applied to the circuit element region 11, and the characteristics of the circuit element formed on the circuit element region 11 are varied.

[0007] In particular, in Figure 5 The region X shown, that is, the region from the pad 15 to the terminal 17 is likely to generate the thermal stress described above. Therefore, in the related art, for example, generation of characteristic defects is suppressed by a method of not providing the circuit element region 11 or the like at the lower portion of the wiring 13 as a re-wiring. However, such a wiring rule is not sufficient as a countermeasure, and according to the countermeasure, there are cases where the characteristics are varied. Further, such a wiring rule becomes a large constraint on the layout in the design of the CSP, and in particular, in a recent CSP in which the degree of integration is rising, a fundamental solution to the thermal stress problem described above is required. SUMMARY

[0008] The present application is based on the above-described circumstances, and an object thereof is to provide a semiconductor device in which generation of defects caused by thermal stress is suppressed in a semiconductor device having a wiring layer formed on a circuit element, and a manufacturing method of a semiconductor device.

[0009] To solve the above-described problem, the semiconductor device of the present application includes a wiring formed of a conductive body extending on a surface of a semiconductor substrate with an insulating film interposed therebetween, and an insulating layer covering the surface of the semiconductor substrate including the wiring, and a gap from an upper surface of the wiring to a lower portion of the insulating film is provided in the semiconductor device.

[0010] To solve the above-described problem, the manufacturing method of a semiconductor device of the present application includes a step of forming a circuit element including a first wiring on one surface of a semiconductor substrate, the circuit element being connected to a pad through the first wiring, a step of forming an insulating film on an upper portion of the circuit element, a step of forming the insulating film having an opening in a region of the pad and a predetermined region, and a step of forming a second wiring connected to the pad on an upper portion of the insulating film, the second wiring being formed to have an opening in the same region as the predetermined region.

[0011] According to the present invention, a semiconductor device and a method for manufacturing the semiconductor device are provided that can suppress adverse conditions caused by the generation of thermal stress in a semiconductor device having a wiring layer formed on a circuit element. Attached Figure Description

[0012] Figure 1 This is a rear top view showing an example of the structure of a semiconductor device according to an embodiment.

[0013] Figure 2 The connection structure of the semiconductor device shown in the embodiment is illustrated. Figure 2 (a) is a top view. Figure 2 (b) is a sectional view.

[0014] Figure 3 The connection structure of the semiconductor device shown in the comparative example is illustrated. Figure 3 (a) is a top view. Figure 3 (b) is a sectional view.

[0015] Figure 4 This is a top view of a comparative example semiconductor device.

[0016] Figure 5 It is a cross-sectional view showing the columnar body of a prior art semiconductor device and the structure surrounding the columnar body.

[0017] Explanation of reference numerals in the attached figures

[0018] 10, 100… Semiconductor device, 11, 11a… Circuit element area, 12… Insulating film, 13… Wiring, 14… Molding resin, 15… Pad, 17… Terminal, 18, 18-1, 18-2, 18-3, 18-4… Gap, 19… Passivation film, 20… Column, 21… Solder bump, 22… Wiring, L1, L2… Edge, S0, S1, S2, S3… Stress application area, X… Area. Detailed Implementation

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, in the following description, an example of applying the semiconductor device of the present invention to a CSP will be given. Additionally, due to the rewiring structure and... Figure 5 The prior art shown is the same, so refer to it if necessary. Figure 5 (Detailed explanation omitted.)

[0020] Figure 1 A top view of the back of the semiconductor device 10, which is a CSP, is shown. Figure 1As shown, the semiconductor device 10 is configured to include a circuit element region 11, a pad 15, a terminal 17, and a wiring 13 connecting the pad 15 and the terminal 17. However, in Figure 1 the illustration of the gap 18 described later is omitted.

[0021] The circuit element region 11 is a region in which active devices such as transistors and diodes, and passive devices such as resistors and capacitors, which are used to realize functions as the purpose of the semiconductor device 10, are arranged.

[0022] The pad 15 is a connection region with the outside formed of a conductor, and is connected to the circuit element region 11 through a wiring, not shown, formed of a conductor. The wiring 13 is a so-called redistribution wiring formed of a conductor, and is connected to the pad 15 and a terminal 17, not shown, for connection with the outside. In Figure 1 In the example shown, the circuit element region 11a denoted by reference symbol "A" is led to the pad 15 through a wiring, not shown, and extends to the terminal 17 denoted by reference symbol "A" via the wiring 13, and the circuit element region 11a is connected to the outside via the terminal 17. At this time, the fact that the wiring 13 can be arranged on the upper portion of the circuit element region 11 is one feature of the semiconductor device 10 of the present embodiment, and details thereof will be described later.

[0023] As one example, there is also a case where the terminal 17 of the present embodiment is a columnar body having a substantially circular cross section, and a solder bump (not shown) as a solder member in the case where the semiconductor device 10 is mounted on a printed board or the like is provided on the upper surface of the terminal 17. In other words, as the semiconductor device 10 of the present embodiment, there are two types of a type in which the solder bump is formed on the upper surface of the terminal 17 and a type in which the solder bump is not formed.

[0024] Here, the pad (corresponding to the pad 15) of the semiconductor circuit surface of the wafer on which the process has been completed is opened through an opening portion of a passivation layer (corresponding to the passivation film 19) shown. Figure 5 In a normal package, a bare chip obtained by dicing the wafer is connected to a mounting surface of a printed board or the like by adhesion or the like. On the other hand, in a CSP, a connection structure is constructed on the chip before dicing. In the present embodiment, the so-called "connection structure" refers to a structure in which a redistribution layer (corresponding to the wiring 13) of a conductor is formed on the pad of the semiconductor circuit surface, and a connection portion (corresponding to the terminal 17) of the remaining redistribution layer is sealed with a sealing resin. As needed, a solder bump or the like in a hemispherical shape is formed on the connection portion.

[0025] Here, as described above, in the case of the CSP, there is a case where thermal stress is generated in the laminated structure that constitutes the connection structure including the terminal of a columnar shape, the thermal stress brings damage to the circuit elements in the circuit element region 11, and the characteristics of the circuit element region 11 are changed. Therefore, in the present embodiment, a gap (air gap) to which the redistribution wiring provided on the circuit surface of the semiconductor device 10 on which the circuit element region 11 is formed reaches the circuit surface. The gap penetrates the insulating film formed in the lower portion of the redistribution wiring. Thus, since the stress generated in the laminated structure that constitutes the connection structure is dispersed, according to the semiconductor device 10 of the present embodiment, it is possible to provide a semiconductor device in which an adverse situation caused by generation of thermal stress is suppressed in a semiconductor device having a wiring layer formed on a circuit element, and a manufacturing method of a semiconductor device.

[0026] Reference Signs Figure 2 The connection structure in the semiconductor device 10 of the present embodiment will be described. Figure 2 (a) of FIG. 10 is a plan view of the connection structure of the semiconductor device 10, and the pad 15 and the terminal 17 are connected by the wiring 13. However, in Figure 2 The illustration of the molding resin 14 is omitted in (a) of FIG. 10. As Figure 2 As shown in (a) of FIG. 10, in the semiconductor device 10, the gap 18-1, 18-2, 18-3, and 18-4 (hereinafter, in the case of being collectively referred to, referred to as "gaps 18") are provided in a part of the region in which the wiring 13 is formed. Figure 2 (b) of FIG. 10 shows a cross section of the gap 18, and as Figure 2 As shown in (b) of FIG. 10, the gap 18 penetrates the wiring 13 and the insulating film 12 from the upper surface of the wiring 13 to the lower portion of the insulating film 12. In the gap 18 of the present embodiment, air is filled inside. In other words, it is preferable that a solid substance is not filled inside the gap 18. On the other hand, as long as it is a gas, for example, nitrogen or the like can be enclosed.

[0027] Figure 2 The reference signs "S1", "S2", and "S3" shown in (b) of FIG. 10 indicate stress application regions in which the possibility of the thermal stress generated is applied in the laminated structure that constitutes the connection structure. As Figure 2 Since the gap 18 is present, it is possible to disperse the stress application regions that are generated uniformly in the region close to the entire laminated structure that constitutes the connection structure of the related art, and thus according to the semiconductor device 10 of the present embodiment, it is possible to mitigate the influence of the stress to the circuit element region 11.

[0028] Figure 3 The connection structure of the comparative example will be described. Figure 3 (a) of FIG. 11 is a plan view of the connection structure, Figure 3(b) is a cross-sectional view. Figure 3 (a) from Figure 2 (a) of the present embodiment. As shown in Figure 3 (b), since the connecting structure of the comparative example does not have the void 18, the stress application region SO becomes the entire lower portion of the wiring 13. Therefore, compared to the connecting structure of the present embodiment, the influence of thermal stress on the circuit element region 11 is greater.

[0029] Here, as one of the features of the semiconductor device 10 of the present embodiment, as shown in Figure 1 , it can be cited that the wiring 13 can be disposed on the upper portion of the circuit element region 11. Although omitted in Figure 1 , as shown in Figure 1 , a void is formed in a part of the region of the wiring 13. Therefore, since the thermal stress in the laminated structure constituting the connecting structure is relaxed, the wiring 13 can be disposed on the upper portion of the circuit element region 11 (across the circuit element region 11). The wiring 13 can be formed in the semiconductor device 10 like this, so the degree of freedom of the layout of the wiring increases compared to the semiconductor device of the comparative example.

[0030] Here, the pad 15 is generally disposed in the region of the periphery of the semiconductor device 10 where no circuit element is formed. For example, in the case of the example shown in Figure 1 , the pad 15 connected to the circuit element region 11a is disposed in the region along the side of the semiconductor device 10. At this time, depending on the pin disposition of the CSP, there are cases where it is desired to dispose the terminal 17 in the region along the side L2. In such a case, in the semiconductor device 10, as shown in Figure 1 , it is also possible to connect the wiring 13 to the pad 15 disposed at the position along the side LI and extend the wiring 13 across the circuit element region 11 to connect to the terminal 17 disposed at the position along the side L2. In this way, according to the semiconductor device 10 of the present embodiment, the degree of freedom of the wiring is significantly improved compared to the semiconductor device of the comparative example.

[0031] Figure 4 A plan view of the back surface of the semiconductor device 100 of the comparative example is shown. In the plan view shown in Figure 4 , the circuit element region 11, and the pad 15 are disposed in the same positions as the semiconductor device 10 shown in Figure 1 . The pad 15 is connected to the circuit element region 11a by the wiring 22. Here, since the semiconductor device 100 does not have the void 18, the wiring 13 cannot be disposed across the circuit element region 11. Therefore, the terminal 17 has to be disposed in the region along the side LI, and cannot be disposed in the region along the side L2 Figure 4In this case, for example, it is necessary to correspond to the pattern of a printed board on which the semiconductor device 100 is mounted, and a greater constraint is imposed on the pin arrangement of the semiconductor device 100.

[0032] Further, in Figure 2 In (a) of the semiconductor device 10, the manner in which four voids 18 are provided in the region of the wiring 13 is illustrated, but the number of voids 18 is not particularly limited. However, the more the number of voids 18 is increased, the greater the resistance of the wiring 13 is increased, so the number of voids 18 can be set taking into account the influence on the electrical characteristics of the semiconductor device 10 (the influence on the amplitude of the signal passing through the terminal 17, etc.). In other words, it is more preferable to arrange as many square-shaped voids 18 as possible within a range in which the electrical characteristics are not affected. At this time, the voids 18 can be arranged in an array or in a zigzag shape.

[0033] On the other hand, in the case where the shape in plan view is a square shape, the length of one side is preferably 10 μm or less, and in the case where the shape in plan view is a circular shape, the diameter is preferably 10 μm or less. By making the size of the void 18 this size, in the manufacturing process of the semiconductor device 10, it is possible to suppress the molding resin 14 from being filled into the inside of the void 18, so this is preferable. On the other hand, the lower limit of the size of the void 18 can be set taking into account the efficient dispersion of thermal stress, constraints in the manufacturing process, etc., and for example, the length of one side or the diameter described above can be set to 5 μm or more.

[0034] The width of the wiring 13 having the void 18 formed therein in the semiconductor device 10 will be described. Although this will differ depending on the use of the semiconductor device 10, particularly in the case where thermal stress is a problem (for example, in the case of a semiconductor device for a power supply system), the width of the wiring 13 is, for example, a width equivalent to the base of the terminal 17. As one example, in the case where the diameter of the terminal 17 is about 200 μm, the diameter of the base is about 220 μm, so the wiring width after the void 18 is removed is set to be able to secure about 220 μm. On the other hand, the minimum value of the wiring width is, for example, the minimum at the connection portion of the wiring 13 and the land 15, so as one example, the wiring width after the void 18 is removed needs to be about 40 μm or so in width. In addition, the interval of the void 18 and the void 18 (i.e., the density of the void 18) differs depending on the use of the semiconductor device 10, but for example, using simulation or the like, it is set to be able to secure the optimum wiring area for the drive voltage passing through the terminal 17.

[0035] Next, the manufacturing method of the semiconductor device 10 of the present embodiment will be described. In addition, in the following description, it is assumed that the process up to the formation of the pad 15 and the passivation film 19 is completed on the circuit surface of the semiconductor substrate (not shown), that is, the process treatment for the wafer is completed, and that it is in the stage before the re-wiring process.

[0036] First, the insulating film 12 (lower insulating film) is formed. That is, a material such as a thermosetting material that will become the insulating film is formed on the circuit surface, and is patterned by photolithography. Then, thermosetting is performed. In the patterning process of the present process, patterning that forms a void in the passivation film 19 and the insulating film 12 is also performed.

[0037] Next, the re-wiring, that is, the wire 13 is formed on the upper portion of the insulating film 12. That is, a conductor that will become a seed layer is formed on the circuit surface (not shown), and is patterned by photolithography. Then, a resist used for forming a mask is applied on the circuit surface, and the wire 13 is formed based on Cu plating. Then, the resist used for the mask is removed. In the patterning process of the present process, patterning that forms a void in the wire 13 is also performed.

[0038] Next, the terminal 17 is formed. That is, Cu plating is performed by photolithography, and the terminal 17 is formed on the wire 13. Then, the resist used for the mask is removed.

[0039] Next, the molding resin 14 is formed. That is, a resin such as a thermosetting resin that will become the molding resin 14 is formed on the circuit surface, and then thermosetting is performed.

[0040] Next, the solder bump 21 is formed. That is, solder is printed on the circuit surface, and is reflowed. In addition, in the semiconductor device 10 of the type in which the terminal 17 is directly exposed without using the solder bump 21, the present process is omitted.

[0041] Here, the manufacturing method of the semiconductor device of the related art differs from the manufacturing method of the semiconductor device 10 of the present embodiment in that, in the manufacturing method of the semiconductor device 10 of the present embodiment, the void 18 is formed at the same time in the process of forming the lower insulating film (insulating film 12) and the re-wiring (wire 13). Thus, the void 18 can be formed without increasing the number of processes of the manufacturing method of the semiconductor device of the related art.

[0042] In addition, although in the above-described embodiment, the shape of the void 18 in plan view is exemplified as a square shape and a circular shape, a suitable shape such as a rectangular shape and an elliptical shape can be adopted in consideration of the efficiency of dispersing thermal stress and the like.

Claims

1. A semiconductor device comprising: a wiring formed of a conductive body extending across an insulating film on a surface of a semiconductor substrate; and an insulating layer covering the surface of the semiconductor substrate including the wiring, a gap is provided from an upper surface of the wiring to a lower portion of the insulating film in the semiconductor device, the gap is any one of a circular shape having a diameter of 10 micrometers or less and a square shape having one side of 10 micrometers or less.

2. The semiconductor device according to claim 1, wherein a circuit element is formed on the surface side of the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein the gap is provided at an upper portion of the circuit element.

4. The semiconductor device according to any one of Claims 1 to 3, wherein further comprising: an opening portion formed in the insulating layer on the wiring; and a columnar terminal formed in the opening portion and connected to the wiring, the gap is not provided at a lower portion of the columnar terminal.

5. The semiconductor device according to any one of claims 1 to 3, wherein a plurality of the gaps are included, the plurality of the gaps are provided in an array shape.

6. The semiconductor device according to claim 4, wherein a plurality of the gaps are included, the plurality of the gaps are provided in an array shape.

7. A method for manufacturing a semiconductor device, wherein comprising: a step of forming a circuit element on one surface of a semiconductor substrate, wherein the circuit element is a circuit element including a first wiring, and the circuit element is connected to a pad through the first wiring; a step of forming an insulating film on an upper portion of the circuit element, in which step the insulating film is formed to have an opening in a region of the pad and a predetermined region; and a step of forming a second wiring connected to the pad on an upper portion of the insulating film, in which step the second wiring is formed to have an opening in the same region as the predetermined region, in the step of forming the insulating film and the step of forming the second wiring, a gap is formed from an upper surface of the second wiring to a lower portion of the insulating film, the gap is any one of a circular shape having a diameter of 10 micrometers or less and a square shape having one side of 10 micrometers or less.

Images