Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application provides a semiconductor device and a manufacturing method of a semiconductor device, when an electrode including a terminal composed of copper and a solder bump composed of silver-tin is formed on a wiring, connection reliability and conductivity between the terminal and the solder bump can be achieved. The semiconductor device includes a terminal (19) electrically connected to a circuit element, and the terminal (19) has an upper surface (S) of the solder bump (12) composed of silver-tin formed across a nickel layer (20), and the terminal (19) is formed using copper, in the semiconductor device, the nickel layer (20) is formed on a partial region of the upper surface (S).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and particularly to a semiconductor device and a method for manufacturing a semiconductor device that can simultaneously achieve connection reliability and conductivity of terminals formed on wiring. Background Technology

[0002] Previously, as related to terminal reliability, there is known literature, such as the semiconductor wafer disclosed in Patent Document 1. The semiconductor wafer disclosed in Patent Document 1 has a barrier metal layer consisting of an anti-diffusion layer and a bonding layer deposited beneath the solder bumps formed on the semiconductor wafer, and the bonding layer is divided into multiple segments. In Patent Document 1, because the bonding layer is divided into multiple segments, the thermal expansion of the bonding layer is reduced. As a result, the stress generated in the passivation film due to the difference in thermal expansion coefficients between the barrier metal layer and the passivation film can be reduced, and peeling and cracking in the passivation film can be prevented.

[0003] On the other hand, as a prior art addressing the issue of connection reliability when welding terminals made of specific materials to solder made of specific materials, the welding material disclosed in Patent Document 2 is known. The welding material disclosed in Patent Document 2 is characterized by being a welding material containing Sn, Cu6Sn5 intermetallic compound, and Cu, in order to suppress the formation of Kirkendal voids. It has a structure in which Sn, Cu6Sn5 intermetallic compound, and Cu are dispersed, and during welding, Cu practically forms compounds with Sn and other substances. Kirkendal voids refer to voids that arise during metal-to-metal welding due to the non-disappearance and aggregation of atomic vacancies (lattice defects) caused by uneven interdiffusion. In the case of the Sn-Cu interface, Sn diffusion is less than Cu diffusion, so it is believed that vacancies accumulate at the interface between the intermetallic compound and Cu.

[0004] Patent Document 1: Japanese Patent Application Publication No. 9-129680

[0005] Patent Document 2: Japanese Patent Application Publication No. 2019-141908

[0006] Here, refer to Figure 5 The reliability and conductivity of the connection when solder bumps are formed on cylindrical terminals (hereinafter referred to as "terminals") are explained. Figure 5 The example shown is a case where the material of the terminal is copper (hereinafter referred to as "Cu") and the material of the solder bump is silver-tin (hereinafter referred to as "Sn-Ag"). Hereinafter, the structure including the terminal and the solder bump formed on the terminal will be referred to as a "pillar". Figure 5(a) shows the structure of the columnar body in the case where the solder bump 12 is formed directly on the terminal 19 without the provision of a blocking metal. Figure 5 (b) shows the structure of the column when a nickel (hereinafter referred to as “Ni”) layer 20 is configured as a barrier metal between the terminal 19 and the solder bump 12.

[0007] exist Figure 5 In the case of the columnar structure shown in (a), there is a possibility of voids 25 caused by Kirkendall voids. If Kirkendall voids occur, there is a concern that the interface between the terminal 19 and the solder bump 12 will become brittle, leading to reduced connection reliability. On the other hand, Figure 5 (b) shows a columnar structure connected to the solder bump 12 via the Ni connection terminal 19, which acts as a blocking metal, in order to suppress the generation of void 25. Figure 5 In the case of the columnar structure shown in (b), there is a concern that the performance of the circuit elements (devices) formed in the semiconductor device may be reduced. This is because the conductivity of terminal 19 is reduced due to the presence of nickel.

[0008] In other words, when forming pillars in a semiconductor device, nickel-freeing is required to improve conductivity, while blocking the presence of metal is needed to improve connection reliability. Generally speaking, it is difficult to achieve both objectives simultaneously, but it would be convenient to create a pillar that achieves both connection reliability and conductivity. Summary of the Invention

[0009] Based on the above, the present invention aims to provide a semiconductor device and a method for manufacturing the semiconductor device that can achieve both reliable connection and conductivity between the terminals and solder bumps when electrodes comprising copper terminals and silver-tin solder bumps are formed on the wiring.

[0010] To solve the above-mentioned technical problems, the semiconductor device of the present invention includes a semiconductor device that is electrically connected to a circuit element and has a forming surface with solder bumps made of silver and tin formed therebetween through a nickel layer and terminals formed of copper, wherein the nickel layer is formed on a portion of the forming surface.

[0011] To address the aforementioned issues, a semiconductor device according to another aspect of the present invention includes: a terminal electrically connected to a circuit element and formed using copper; a nickel layer formed on a portion of the upper surface of the terminal; and a solder bump formed of silver tin and formed on the copper and nickel layer exposed on the upper surface.

[0012] To address the aforementioned issues, the semiconductor device manufacturing method of the present invention includes: a step of forming a circuit element on a semiconductor wafer, the circuit element including wiring, a portion of the wiring including an opening that exposes the wiring to the outside; a step of forming a terminal made of copper in the opening; and a step of forming a nickel layer on a portion of the upper surface of the terminal.

[0013] According to the present invention, a semiconductor device and a method of manufacturing the semiconductor device are provided that, when electrodes comprising terminals made of copper and solder bumps made of silver tin are formed on the wiring, both reliability of the connection between the terminals and the solder bumps and conductivity are achieved. Attached Figure Description

[0014] Figure 1 This is a rear top view showing an example of the structure of a semiconductor device according to an embodiment.

[0015] Figure 2 (a) is a cross-sectional view showing an example of the structure of the columnar body in the case of no redistribution of the semiconductor device of the embodiment. Figure 2 (b) is a cross-sectional view showing an example of the structure of the columnar body in the case of redistribution of the semiconductor device of the embodiment.

[0016] Figure 3 (a) is a cross-sectional view showing an example of the structure of the columnar body in the first embodiment. Figure 3 (b) is a cross-sectional view showing an example of the structure of the columnar body in a modified example of the first embodiment.

[0017] Figure 4 This is a cross-sectional view showing an example of the structure of the columnar body in the second embodiment.

[0018] Figure 5 of (a), Figure 5 (b) is a cross-sectional view showing the structure of the columnar body of the comparative example.

[0019] Explanation of reference numerals in the attached figures

[0020] 10… Semiconductor device, 11… Circuit element area, 12… Solder bump, 13… Pad, 14… Wiring, 15… Semiconductor substrate, 17… Insulating film, 18… Seed layer, 19… Terminal, 20… Nickel layer, 21… Lower insulating film, 22… Seed layer, 23… Wiring, 24… Surface insulating film, 25… Void, 30, 30a, 30b, 30c… Columnar body, d… Distance, S… Upper surface, E… End. Detailed Implementation

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the case in which the semiconductor device of the present invention is applied to a CSP (Chip Size Package) and terminals are formed on the circuit surface of the CSP will be illustrated.

[0022] [First Implementation Method]

[0023] Figure 1 A top view of the back side of the semiconductor device 10, which is the CSP in this embodiment, is shown. Figure 1 As shown, the semiconductor device 10 is configured to include: a circuit element region 11, solder bumps 12, pads 13, and wiring 14.

[0024] The circuit element region 11 is a region in which active devices such as transistors and diodes, as well as passive devices such as resistors and capacitors, are arranged to perform functions for the purpose of semiconductor device 10.

[0025] The pad 13 is a connection area to the outside formed by a conductor, and is connected to the circuit element area 11 by wiring formed by the conductor (not shown). The wiring 14 is a so-called rewiring formed by the conductor, and is connected to the pad 13 and the terminal for connection to the outside (not shown). The solder bump 12 is a soldering component provided on this terminal when mounting the semiconductor device 10 on a printed circuit board or the like. Furthermore, although this embodiment describes a semiconductor device 10 with solder bumps 12 as an example, it is not limited to this, and a semiconductor device 10 may also be provided without solder bumps 12, with the terminals exposed as described later.

[0026] Here, the pads (equivalent to pad 13) on the semiconductor circuit surface of the wafer after the processing is completed are opened through the openings in the passivation layer. In conventional packaging, the bare chip obtained by dicing the wafer is connected to the mounting surface such as a printed circuit board by bonding or the like. On the other hand, in CSP, the connection structure is built on the chip before dicing. That is, a redistribution layer (equivalent to wiring 14) of conductive material is formed on the pads on the semiconductor circuit surface, and the surface is sealed with sealing resin, leaving the connection portion (terminals described later) on the redistribution layer. If necessary, hemispherical solder bumps (equivalent to solder bump 12) are formed on the connection portion.

[0027] Next, refer to Figure 2 The connection structure in the semiconductor device 10 will be described. In the semiconductor device 10, pillar-shaped bodies (combinations of terminals and solder bumps) are formed at predetermined locations on the circuit surface; however, there are two methods for forming these pillar-shaped bodies. That is, Figure 2 The first method of forming a columnar body on the upper part of pad 13, as shown in (a), and Figure 2(b) shows two methods of forming the upper part of the rerouting 23 extending from the pad 13. In other words, the first method is a method of forming without rerouting, and the second method is a method of forming with rerouting.

[0028] Reference Figure 2 (a) describes the first formation method. For example... Figure 2 As shown in (a), in the first formation method, the structure includes: pads 13 and an insulating film 17 formed on the circuit surface of a semiconductor substrate 15, and pillars 30 formed on the upper part of the pads 13. The material of the semiconductor substrate 15 is not particularly limited; in this embodiment, a silicon (Si) substrate is used. The insulating film 17 is formed, for example, using a silicon nitride film (SiN film) or a silicon oxide film (SiO2 film). The pads 13 are formed, for example, of aluminum (Al), and openings in the insulating film 17 are provided in a portion of the area of ​​the pads 13. Alternatively, a seed layer 18 may be formed between the pads 13 and the pillars 30. The seed layer 18 is a conductor in the subsequent electroplating process, for example, a stacked structure of titanium (Ti) and copper (Cu).

[0029] The columnar body 30 includes: a terminal 19, solder bumps 12, and a nickel layer 20 formed between the upper surface of the terminal 19 and the solder bumps 12. In this embodiment, the terminal 19 is formed using Cu, and the solder bumps 12 are formed using Sn-Ag. In the semiconductor device 10, a nickel layer 20 is formed on a portion of the upper surface of the terminal 19, and its specific formation method will be described later.

[0030] Reference Figure 2 (b) explains the second formation method. For example... Figure 2 As shown in (b), since the structures of the semiconductor substrate 15, pads 13, and insulating film 17 are the same as those in the first formation method described above, they are formed using the same method as in the first formation method. In the second formation method, a lower insulating film 21 is further formed on the upper part of the insulating film 17, and wiring 23 as a rewiring is formed on the upper part of the lower insulating film 21, and a surface insulating film 24 is formed on the upper part of the wiring 23. There is also a case where a seed layer 22 is disposed between the wiring 23 and the lower insulating film 21. Since the structure of the columnar body 30 is the same as that in the first formation method described above, its description is omitted.

[0031] Next, the structure of the columnar body 30 in this embodiment will be described in detail. As described above, in the columnar body 30 of this embodiment, Cu is used as the material for the terminal 19, and Sn-Ag is used as the material for the solder bump 12. As described above, with such a combination of materials, the reliability of the connection and the compatibility of conductivity between the Kirkendall void suppression and the nickel-free terminal 19 and the solder bump 12 become problematic. Therefore, in this embodiment, instead of forming the nickel layer 20 on the entire surface of the upper surface of the terminal 19, the nickel layer 20 is formed only in a limited area.

[0032] Reference Figure 3 The columnar body 30a of the semiconductor device 10 of this embodiment will be specifically described, including the method for forming the nickel layer 20. Figure 3 (a) shows an example of a method for forming the columnar body 30a according to this embodiment. Figure 3 (a) of <1> shows a top view of columnar body 30a. Figure 3 (a) <2> shows a sectional view. Additionally, in Figure 3 The illustration of solder bump 12 is omitted in (a) <1>. Figure 3 As shown in <1> of (a), the upper surface S of terminal 19 is circular. However, the shape of the upper surface S is not limited to a circular shape; for example, it can also be rectangular. Figure 3 As shown in (a) <1>, in this embodiment, the nickel layer 20 is shaped as a circle concentric with the upper surface S and with a diameter smaller than that of the upper surface. In other words, in a certain area including the center of the upper surface S, the solder bump 12 is connected to the terminal 19 through the nickel layer 20, and in a certain area around the upper surface S, the solder bump 12 is directly connected to the terminal 19.

[0033] Figure 3 The black circle shown in (a) <2> schematically represents the void 25. Since the solder bump 12 is directly connected to the terminal 19 in a certain area encompassing the periphery of the upper surface S, there is a possibility of Kirkendall voids forming. Furthermore, the void 25 conceptually represents a location where a Kirkendall void is possible, and does not imply that it will necessarily form. Figure 3 As shown in (a), in this embodiment, since the area where the solder bump 12 is directly connected to the terminal 19 is defined, even if Kirkendall voids are generated, they will hardly affect the connectivity.

[0034] Compared to the peripheral portion of the aforementioned upper surface S, in the central portion, such as Figure 3As shown in (a)<2>, the solder bump 12 is connected to the terminal 19 through the nickel layer 20. Therefore, voids 25 are not easily generated in principle. On the other hand, although it is assumed that the conductivity of the nickel layer 20 is a problem, since the proportion of the nickel layer 20 occupying the upper surface S is limited, the conductivity problem is limited compared to the technology of the comparative example described above.

[0035] Furthermore, when the signal passing through columnar body 30a is an AC signal, due to the skin effect, such as Figure 3 As shown in <3> of (a), the signal current is flows along the side of the column 30, increasing the current flowing without passing through the nickel layer 20, thus mitigating conductivity issues. Furthermore, since the higher the frequency, the more concentrated the current is is on the side of the column 30, the distance d from the side of the terminal 19 to the nickel layer 20 can be reduced. In other words, the distance d can be determined based on the frequency of the AC signal flowing in the column 30a.

[0036] Next, the manufacturing method of the semiconductor device 10 according to this embodiment will be described. In addition, in the following description, the formation of pads 13 and insulating film 17 is completed on the circuit surface of semiconductor substrate 15, that is, the wafer processing is completed and it is in the stage before the rewiring process.

[0037] First, a lower insulating film 21 is formed. That is, a thermosetting material, for example, is formed on the circuit surface to serve as the insulating film, and patterned by photolithography. Then, thermosetting is performed.

[0038] Next, rewiring, or wiring 23, is formed on the upper part of the lower insulating film 21. That is, a conductor, which serves as the seed layer 22, is formed on the circuit surface and patterned by photolithography. Then, a photoresist is coated on the circuit surface to form a mask, and Cu-based electroplating is performed to form the wiring 23. Afterward, the photoresist and the seed layer are removed.

[0039] Next, a surface insulating film 24 is formed. That is, a thermosetting material, for example, is formed on the circuit surface to serve as an insulating film, and patterned by photolithography. Then, thermosetting is performed.

[0040] Next, terminal 19 is formed. That is, after the seed layer 18 is formed, Cu is plated on the seed layer 18 by a first photolithography to form terminal 19. Then, Ni is plated on the terminal 19 by a second photolithography to form nickel layer 20. In this embodiment, as described above, nickel layer 20 is formed on a portion of the upper surface S of terminal 19. Then, the resist used for masking is removed.

[0041] Next, solder bumps 12 are formed. That is, solder (Sn-Ag in this embodiment) is printed on the circuit surface and reflowed to remove the resist and seed layer used in this process. In addition, in semiconductor devices 10 that directly open the terminals 19 without using solder bumps 12, this process is omitted.

[0042] Here, the difference between the manufacturing method of the prior art semiconductor device and the manufacturing method of the semiconductor device 10 of this embodiment is that the manufacturing method of the semiconductor device 10 of this embodiment includes a second photolithography, which is not present in the manufacturing method of the prior art semiconductor device. This is because in order to form the nickel layer 20 specifically on a portion of the upper surface of the terminal 19, it is necessary to pattern the nickel layer 20 into a shape different from the upper surface S.

[0043] Furthermore, the above-described semiconductor device 10 manufacturing method is the manufacturing method when there is wiring 23 as rewiring. The manufacturing method when there is no wiring 23 omits the formation of the lower insulating film 21, the formation of wiring 23, and the formation of the surface insulating film 24 in the above-described manufacturing method, and proceeds to the steps after forming the terminal 19.

[0044] <Modifications of the First Embodiment>

[0045] Reference Figure 3 (b) will describe the columnar body 30b provided in the semiconductor device 10 of this embodiment. Figure 3 (b) shows an example of a method for forming the columnar body 30b of this embodiment. Figure 3 (b) of <1> shows a top view of column 30b. Figure 3 (b) <2> shows a sectional view. Additionally, in Figure 3 In (b) of <1>, the illustration of solder bump 12 is omitted. Figure 3 As shown in (b) <1>, in this embodiment, the nickel layer 20 is formed into a ring shape (donut shape) concentric with the upper surface S. The periphery of this ring shape is arranged around the terminal 19. Furthermore, in the portion of the hole in this ring shape, the solder bump 12 is directly connected to the terminal 19.

[0046] Therefore, in a certain region including the center of the upper surface S, the conductivity problem is mitigated for the same reasons as in the first embodiment described above. On the other hand, in a certain region including the periphery of the upper surface S, the connection reliability problem is mitigated for the same reasons as in the first embodiment described above. Here, results from experiments, simulations, etc., show that: Figure 3The connection reliability of the end column 30 shown in (b) <3> is particularly problematic. That is, it is known that if temperature cycling is performed on a printed circuit board or similar device with semiconductor devices mounted via the column, a higher proportion of connection failures occur, especially due to the condition near the end E. This is believed to be because stress is concentrated near the end E. In this embodiment, since the structure makes it difficult to generate gaps 25 near the end E, the strength degradation of the column caused by gaps 25 can be effectively suppressed.

[0047] [Second Implementation]

[0048] Reference Figure 4 The columnar body 30c of the semiconductor device 10 of this embodiment will be described. Figure 4 (a) shows a cross-sectional view of columnar body 30c. Figure 4 (b) shows a top view. Figure 4 The sectional view shown in (a) is along Figure 4 (b) is a cross-sectional view cut off by line A-A'.

[0049] like Figure 4 As shown in (b), in the columnar body 30c, the area without the nickel layer 20 is formed into a cross shape when viewed from above, resulting in a arrangement of nickel layers 20 in a quarter-circle shape in four directions. With this structure, as in the embodiment described above, both reliable connection and conductivity between the terminal and the solder bump can be achieved.

[0050] That is, although in the above embodiments the nickel layer 20 is configured to occupy a continuous certain area, it can also be configured in an island-like manner, as in the columnar body 30c of this embodiment. Although the proportion of the nickel layer 20 occupying the upper surface S is a problem, it can be determined, for example, based on whether connection reliability or conductivity is prioritized. As an example, when connection reliability is prioritized, results from experiments, simulations, and other studies show that a proportion of 1 / 3 or more (of course, less than 1) is sufficient.

[0051] Furthermore, while the embodiments described above exemplify a columnar terminal, this approach is not limited to this. For instance, it can also be applied to the case where solder bumps 12 are formed on electrode pads formed on a portion of a wiring made of Cu. That is, when Sn-Ag solder bumps 12 are formed on Cu electrode pads formed on a portion of the wiring with the nickel layer 20 in between, the nickel layer is also specifically formed on a portion of the electrode pad. Thus, in the case of electrode pads, both reliable connection and conductivity between the electrode pads and solder bumps can be achieved.

Claims

1. A semiconductor device comprising a terminal, the terminal being electrically connected to a circuit element, and the terminal being formed of copper, and the terminal having a formation surface on which a solder bump composed of silver and tin is formed via a nickel layer, the nickel layer being formed on a part of the formation surface, the solder bump being formed on an upper portion of the terminal and the nickel layer exposed on the formation surface, and an area on the formation surface on which the nickel layer is not formed being formed so that the formation surface has a cross shape when viewed from above.

2. The semiconductor device according to claim 1, wherein an area of the area on which the nickel layer is formed is an area of 1 / 3 or more of an area of the formation surface.

3. The semiconductor device according to claim 1 or 2, wherein Further comprising: a circuit element formed on a semiconductor substrate; and a pad connected to the circuit element via a first wiring, the terminal being formed on the pad.

4. The semiconductor device according to claim 1 or 2, wherein Further comprising: a circuit element formed on a semiconductor substrate; a pad connected to the circuit element via a first wiring; and a second wiring connected to the pad, the terminal being formed on the second wiring. Further comprising: a circuit element formed on a semiconductor substrate; a pad connected to the circuit element via a first wiring; and a second wiring connected to the pad, the terminal being formed on the second wiring.

Images