Supports highly integrated semiconductor devices with stacked structures.

Abstract

A semiconductor device having a stacked structure is provided. The semiconductor device includes an upper stacked structure extending on a lower stacked structure, the lower stacked structure extending on a lower substrate. A channel structure extends through the upper and lower stacked structures. The lower stacked structure includes a first lower electrode layer configured to be adjacent to an interface between the lower and upper stacked structures, and a second lower electrode layer configured to be adjacent to the center of the lower stacked structure. The upper stacked structure includes a first upper electrode layer configured to be adjacent to an interface, and a second upper electrode layer configured to be adjacent to the center of the upper stacked structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2020-0013087, filed on February 4, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The disclosed exemplary embodiments relate to a semiconductor memory device utilizing a stacked structure and a method for forming the semiconductor memory device. Background Technology

[0003] Given the high integration density of semiconductor devices, technologies for sequentially stacking multiple stacked structures on a substrate are under development. Forming an upper stacked structure on a lower stacked structure, as well as forming multiple channel structures extending vertically through the upper and lower stacked structures, may face various technical challenges and limitations. For example, a device positioned adjacent to the interface between the lower and upper stacked structures can exhibit a variety of variations in electrical characteristics. Summary of the Invention

[0004] The disclosed exemplary embodiments provide a semiconductor device capable of supporting reliable electrical characteristics of a device disposed adjacent to the interface between a lower stacked structure and an upper stacked structure, and a method for forming the semiconductor device.

[0005] A semiconductor device according to a disclosed embodiment includes a lower stacked structure comprising a plurality of lower insulating layers and a plurality of lower electrode layers stacked in an alternating sequence of electrode layers and insulating layers. An upper stacked structure is provided disposed on the lower stacked structure. The upper stacked structure includes a plurality of upper insulating layers and a plurality of upper electrode layers stacked in an alternating sequence of electrode layers and insulating layers. A channel structure extending in the upper stacked structure and the lower stacked structure is provided. The plurality of lower electrode layers includes a first lower electrode layer and a second lower electrode layer. The plurality of upper electrode layers includes a first upper electrode layer and a second upper electrode layer. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one of the plurality of lower insulating layers and the plurality of upper insulating layers is disposed between the first lower electrode layer and the first upper electrode layer. Among the plurality of lower electrode layers, the first lower electrode layer is configured to be closest to the interface between the lower stacked structure and the upper stacked structure. The second lower electrode layer is configured to be adjacent to the center of the lower stacked structure. Among the plurality of upper electrode layers, the first upper electrode layer is configured to be closest to the interface. The second upper electrode layer is configured to be adjacent to the center of the upper stacked structure.

[0006] A semiconductor device according to a disclosed embodiment includes a horizontal conductive layer disposed on a substrate. A lower stacked structure is provided disposed on the horizontal conductive layer. The lower stacked structure includes a plurality of lower insulating layers and a plurality of lower electrode layers stacked in an alternating sequence of electrode layers and insulating layers. An upper stacked structure is provided disposed on the lower stacked structure. The upper stacked structure includes a plurality of upper insulating layers and a plurality of upper electrode layers stacked in an alternating sequence of electrode layers and insulating layers. A channel structure is provided that extends into the interior of the horizontal conductive layer while extending through the upper and lower stacked structures. A bit line is provided disposed on the upper stacked structure and electrically connected to the channel structure. A first lower electrode layer, which is positioned closest to the interface between the lower and upper stacked structures, is thicker than a second lower electrode layer, which is positioned adjacent to the center of the lower stacked structure. At least one of the plurality of lower insulating layers and the plurality of upper insulating layers directly contacts the interface.

[0007] A semiconductor device according to a disclosed embodiment includes a horizontal conductive layer disposed on a substrate. A lower stacked structure is provided disposed on the horizontal conductive layer. The lower stacked structure includes a plurality of lower insulating layers and a plurality of lower electrode layers stacked in an alternating sequence of electrode layers and insulating layers. An upper stacked structure is provided disposed on the lower stacked structure. The upper stacked structure includes a plurality of upper insulating layers and a plurality of upper electrode layers stacked in an alternating sequence of electrode layers and insulating layers. A channel structure is provided extending into the interior of the horizontal conductive layer and extending through the upper and lower stacked structures. A bit line is provided disposed on the upper stacked structure and electrically connected to the channel structure. Among the plurality of upper electrode layers, a first upper electrode layer, positioned closest to the interface between the lower and upper stacked structures, is thicker than a second upper electrode layer, positioned adjacent to the center of the upper stacked structure. At least one of the plurality of lower insulating layers and the plurality of upper insulating layers directly contacts the interface. Attached Figure Description

[0008] Figure 1 and Figure 12 This is a cross-sectional view illustrating a semiconductor device according to a disclosed exemplary embodiment.

[0009] Figures 2 to 11 It is shown Figure 1 A magnified view of the part.

[0010] Figures 13 to 19 This is a cross-sectional view illustrating a method for forming a semiconductor device according to a disclosed exemplary embodiment. Detailed Implementation

[0011] Figure 1 This is a cross-sectional view illustrating a semiconductor device according to the disclosed exemplary embodiments. Figure 2 It is shown Figure 1 Enlarged view of part 12. Figure 3 It is shown Figure 1 Enlarged view of part 13. Figure 4 It is shown Figure 1 Enlarged view of part 14. Figures 5 to 8 It is shown Figure 1 Enlarged view of part 13. Figure 9 It is shown Figure 1 Enlarged view of part 15. Figure 10 It is shown Figure 1 Enlarged view of part 16. Figure 11 It is shown Figure 1 A magnified view of portion 17. A semiconductor device according to the disclosed exemplary embodiments may include non-volatile memory such as VNAND or other 3D flash memory. A semiconductor device according to the disclosed exemplary embodiments can be interpreted as including a cell-on-periphery (COP) structure.

[0012] Reference Figure 1 Each of the semiconductor devices according to the disclosed exemplary embodiments may include a substrate 31, a component isolation layer 33, a plurality of transistors 35, a first interlayer insulating layer 37, a plurality of peripheral circuit wirings 39, a capping layer 43, a second interlayer insulating layer 45, a horizontal conductive layer 51, a connecting conductive layer 55, a support 57, a third interlayer insulating layer 58, a lower stack structure 100, an upper stack structure 200, a plurality of channel structures 350, a fourth interlayer insulating layer 332, a plurality of isolation patterns 344, a plurality of bit plugs 375, and a plurality of bit lines 377.

[0013] The lower stack structure 100 may include a plurality of lower insulating layers 161 to 174 and a plurality of lower electrode layers 181 to 191 that are alternately stacked. The upper stack structure 200 may include a plurality of upper insulating layers 261 to 273 and a plurality of upper electrode layers 281 to 291 that are alternately stacked. In an exemplary embodiment, each of the plurality of channel structures 350 may include a step configured to be adjacent to the interface S1 between the lower stack structure 100 and the upper stack structure 200. Each sidewall of the plurality of channel structures 350 may have a stepped profile in the region adjacent to the interface S1.

[0014] In an exemplary embodiment, the horizontal conductive layer 51 may correspond to a source line or a common-source line (CSL). The first lower electrode layer 181 and the second lower electrode layer 182 may correspond to gate-induced drain leakage (GIDL) control lines, respectively. The third lower electrode layer 183 may correspond to a ground selection line (GSL). The fourth lower electrode layer 184 and the fifth lower electrode layer 185 may correspond to dummy word lines, respectively. The sixth to tenth lower electrode layers 190 may correspond to word lines, respectively. The eleventh lower electrode layer 191 may be a dummy word line.

[0015] The first upper electrode layer 281 can correspond to a dummy word line. The second to fifth upper electrode layers 282 can each correspond to a word line. The sixth upper electrode layer 286 and the seventh upper electrode layer 287 can each correspond to a dummy word line. The eighth upper electrode layer 288 and the ninth upper electrode layer 289 can each correspond to a serial select line (SSL). The tenth upper electrode layer 290 and the eleventh upper electrode layer 291 can each correspond to a gate-induced drain leakage (GIDL) control line.

[0016] Reference Figure 2 The third interlayer insulating layer 58 may have a first thickness T1. The first lower insulating layer 161 may have a second thickness T2. The first lower electrode layer 181 may have a third thickness T3. The second lower insulating layer 162 may have a fourth thickness T4. The second lower electrode layer 182 may have a fifth thickness T5. The third lower insulating layer 163 may have a sixth thickness T6. The third lower electrode layer 183 may have a seventh thickness T7. The fourth lower insulating layer 164 may have an eighth thickness T8. The fifth lower insulating layer 165 may have a ninth thickness T9. The fourth lower electrode layer 184 may have a tenth thickness T10. The sixth lower insulating layer 166 may have an eleventh thickness T11. The fifth lower electrode layer 185 may have a twelfth thickness T12. The seventh lower insulating layer 167 may have a thirteenth thickness T13. The sixth lower electrode layer 186 may have a fourteenth thickness T14. The eighth lower insulating layer 168 may have a fifteenth thickness T15. The seventh lower electrode layer 187 may have a sixteenth thickness T16. The ninth lower insulating layer 169 may have a seventeenth thickness T17. The eighth lower electrode layer 188 may have a sixteenth thickness T16. The tenth lower insulating layer 170 may have a seventeenth thickness T17.

[0017] Reference Figure 3 The thirteenth lower insulating layer 173 may have an eighteenth thickness T18. The eleventh lower electrode layer 191 may have a nineteenth thickness T19. The fourteenth lower insulating layer 174 may have a twentieth thickness T20. The first upper insulating layer 261 may have a twenty-first thickness T21. The first upper electrode layer 281 may have a twenty-second thickness T22. The second upper insulating layer 262 may have a twenty-third thickness T23. The second upper electrode layer 282 may have a twenty-fourth thickness T24. The third upper insulating layer 263 may have a twenty-fifth thickness T25. The third upper electrode layer 283 may have a twenty-sixth thickness T26. The fourth upper insulating layer 264 may have a twenty-seventh thickness T27. The fourth upper electrode layer 284 may have a twenty-eighth thickness T28. The fifth upper insulating layer 265 may have a twenty-ninth thickness T29. The fifth upper electrode layer 285 may have a twenty-eighth thickness T28. The sixth upper insulating layer 266 may have a twenty-ninth thickness T29.

[0018] Reference Figure 4 The ninth upper insulating layer 269 may have a thickness of thirtieth T30. The eighth upper electrode layer 288 may have a thickness of thirty-first T31. The tenth upper insulating layer 270 may have a thickness of thirty-second T32. The ninth upper electrode layer 289 may have a thickness of thirty-third T33. The eleventh upper insulating layer 271 may have a thickness of thirty-fourth T34. The tenth upper electrode layer 290 may have a thickness of thirty-fifth T35. The twelfth upper insulating layer 272 may have a thickness of thirty-sixth T36. The eleventh upper electrode layer 291 may have a thickness of thirty-seventh T37. The thirteenth upper insulating layer 273 may have a thickness of thirty-eighth T38.

[0019] Refer again Figures 1 to 4 A horizontal conductive layer 51 can be disposed on a substrate 31. Multiple transistors 35 can be disposed between the substrate 31 and the horizontal conductive layer 51. A support 57 can be disposed on the horizontal conductive layer 51. A connecting conductive layer 55 can be disposed between the horizontal conductive layer 51 and the support 57. A third interlayer insulating layer 58 can be disposed on the support 57. A lower stack structure 100 can be disposed on the third interlayer insulating layer 58. An upper stack structure 200 can be disposed on the lower stack structure 100. Each of the multiple channel structures 350 can extend through the upper stack structure 200, the lower stack structure 100, the third interlayer insulating layer 58, the support 57, and the connecting conductive layer 55. A fourth interlayer insulating layer 332 can be disposed on the upper stack structure 200. Multiple bit plugs 375 can be disposed in the fourth interlayer insulating layer 332. Each of the multiple bit plugs 375, while extending through the fourth interlayer insulating layer 332, can be connected to a corresponding channel structure 350 among the multiple channel structures 350. Multiple bit lines 377 that contact multiple bit plugs 375 can be disposed on the fourth interlayer insulation layer 332. Each of the multiple bit lines 377 can be electrically connected to a corresponding channel structure 350 of the multiple channel structures 350 via a corresponding bit plug 375.

[0020] In an exemplary embodiment, a horizontal conductive layer 51 may be disposed between a substrate 31 and a lower stack structure 100. A support 57 may be disposed between the horizontal conductive layer 51 and the lower stack structure 100. A connecting conductive layer 55 may directly contact the horizontal conductive layer 51. Each of the plurality of channel structures 350 may extend into the interior of the horizontal conductive layer 51 while extending vertically through the upper stack structure 200, the lower stack structure 100, the third interlayer insulating layer 58, and the support 57.

[0021] Multiple additional lower electrode layers may be disposed between the eighth lower electrode layer 188 and the ninth lower electrode layer 189. One of the seventh lower electrode layer 187, the eighth lower electrode layer 188, the multiple additional lower electrode layers, and the ninth lower electrode layer 189 may be positioned adjacent to the center of the lower stack structure 100. The seventh lower electrode layer 187, the eighth lower electrode layer 188, the multiple additional lower electrode layers, the ninth lower electrode layer 189, and the tenth lower electrode layer 190 may have substantially the same thickness. For example, each of the seventh lower electrode layer 187 and the eighth lower electrode layer 188 may have a sixteenth thickness T16.

[0022] Each of the first to sixth lower electrode layers 181 may have a thickness greater than the sixteenth thickness T16. In an exemplary embodiment, the third thickness T3 of the first lower electrode layer 181 may be greater than the sixteenth thickness T16. The fifth thickness T5 of the second lower electrode layer 182 may be substantially equal to the third thickness T3 of the first lower electrode layer 181. The seventh thickness T7 of the third lower electrode layer 183 may be greater than the third thickness T3 of the first lower electrode layer 181. The tenth thickness T10 of the fourth lower electrode layer 184 may be less than the third thickness T3 of the first lower electrode layer 181. The twelfth thickness T12 of the fifth lower electrode layer 185 may be less than the tenth thickness T10 of the fourth lower electrode layer 184. The fourteenth thickness T14 of the sixth lower electrode layer 186 may be less than the twelfth thickness T12 of the fifth lower electrode layer 185. In an exemplary embodiment, the fourteenth thickness T14 of the sixth lower electrode layer 186 may be substantially equal to the sixteenth thickness T16 of the seventh lower electrode layer 187. The nineteenth thickness T19 of the eleventh lower electrode layer 191 can be greater than the sixteenth thickness T16 of the seventh lower electrode layer 187. For example, the nineteenth thickness T19 of the eleventh lower electrode layer 191 can be greater than the seventh thickness T7 of the third lower electrode layer 183.

[0023] Multiple additional upper electrode layers may be disposed between the fifth upper electrode layer 285 and the sixth upper electrode layer 286. One of the fifth upper electrode layer 285, the multiple additional upper electrode layers, and the sixth upper electrode layer 286 may be positioned adjacent to the center of the upper stack structure 200. The fourth upper electrode layer 284, the fifth upper electrode layer 285, the multiple additional upper electrode layers, the sixth upper electrode layer 286, and the seventh upper electrode layer 287 may have substantially the same thickness. For example, each of the fourth upper electrode layer 284 and the fifth upper electrode layer 285 may have a twenty-eighth thickness T28. In an exemplary embodiment, the twenty-eighth thickness T28 of the fourth upper electrode layer 284 may be substantially equal to the sixteenth thickness T16 of the seventh lower electrode layer 187.

[0024] Each of the first upper electrode layers 281 to the third upper electrode layers 283 may have a thickness greater than the twenty-eighth thickness T28 of the fourth upper electrode layer 284. The twenty-second thickness T22 of the first upper electrode layer 281 may be greater than the twenty-eighth thickness T28. The twenty-second thickness T22 of the first upper electrode layer 281 may be substantially equal to the tenth thickness T10 of the fourth lower electrode layer 184. The twenty-fourth thickness T24 of the second upper electrode layer 282 may be less than the twenty-second thickness T22 of the first upper electrode layer 281. The twenty-sixth thickness T26 of the third upper electrode layer 283 may be less than the twenty-fourth thickness T24 of the second upper electrode layer 282. In an exemplary embodiment, the twenty-sixth thickness T26 of the third upper electrode layer 283 may be substantially equal to the twenty-fourth thickness T24 of the second upper electrode layer 282.

[0025] Each of the eighth to eleventh upper electrode layers 288 can have a thickness greater than the twenty-eighth thickness T28 of the fourth upper electrode layer 284. The thirty-first thickness T31 of the eighth upper electrode layer 288 can be greater than the twenty-eighth thickness T28. The thirty-first thickness T31 of the eighth upper electrode layer 288 can be greater than the twenty-second thickness T22 of the first upper electrode layer 281. The thirty-third thickness T33 of the ninth upper electrode layer 289 can be substantially equal to the thirty-first thickness T31. The thirty-fifth thickness T35 of the tenth upper electrode layer 290 can be substantially equal to the thirty-third thickness T33 of the ninth upper electrode layer 289. The thirty-seventh thickness T37 of the eleventh upper electrode layer 291 can be greater than the thirty-fifth thickness T35 of the tenth upper electrode layer 290. The thirty-seventh thickness T37 of the eleventh upper electrode layer 291 can be substantially equal to the nineteenth thickness T19 of the eleventh lower electrode layer 191.

[0026] Multiple other lower insulating layers may be disposed between the tenth lower insulating layer 170 and the eleventh lower insulating layer 171. One of the eighth to tenth lower insulating layers 170, the multiple other lower insulating layers, the eleventh lower insulating layer 171, and the twelfth lower insulating layer 172 may be positioned adjacent to the center of the lower stack structure 100. The eighth to tenth lower insulating layers 170, the multiple other lower insulating layers, the eleventh lower insulating layer 171, and the twelfth lower insulating layer 172 may have substantially the same thickness. For example, each of the ninth lower insulating layer 169 and the tenth lower insulating layer 170 may have a seventeenth thickness T17. Each of the fifteenth thickness T15 of the eighth lower insulating layer 168 and the eighteenth thickness T18 of the thirteenth lower insulating layer 173 may be substantially equal to the seventeenth thickness T17. In an exemplary embodiment, each of the eleventh thickness T11 of the sixth lower insulating layer 166 and the thirteenth thickness T13 of the seventh lower insulating layer 167 may be substantially equal to the fifteenth thickness T15 of the eighth lower insulating layer 168.

[0027] Each of the first to fifth lower insulating layers 161 may have a thickness greater than the seventeenth thickness T17 of the ninth lower insulating layer 169. The second thickness T2 of the first lower insulating layer 161 may be greater than the seventeenth thickness T17. The fourth thickness T4 of the second lower insulating layer 162 may be greater than the second thickness T2 of the first lower insulating layer 161. The sixth thickness T6 of the third lower insulating layer 163 may be substantially equal to the fourth thickness T4 of the second lower insulating layer 162. The eighth thickness T8 of the fourth lower insulating layer 164 may be greater than the sixth thickness T6 of the third lower insulating layer 163. The ninth thickness T9 of the fifth lower insulating layer 165 may be less than the eighth thickness T8 of the fourth lower insulating layer 164, but greater than the eleventh thickness T11 of the sixth lower insulating layer 166. The twentieth thickness T20 of the fourteenth lower insulating layer 174 may be greater than the seventeenth thickness T17 of the ninth lower insulating layer 169. The twentieth thickness T20 of the fourteenth lower insulating layer 174 may be greater than the eighth thickness T8 of the fourth lower insulating layer 164.

[0028] Multiple additional upper insulating layers may be disposed between the sixth upper insulating layer 266 and the seventh upper insulating layer 267. One of the fourth to sixth upper insulating layers 264, the multiple additional upper insulating layers, and the seventh upper insulating layer 267 may be positioned adjacent to the center of the upper stack structure 200. The fourth to sixth upper insulating layers 264, the multiple additional upper insulating layers, and the seventh upper insulating layer 267 may have substantially the same thickness. For example, the fifth upper insulating layer 265 and the sixth upper insulating layer 266 may have a twenty-ninth thickness T29.

[0029] In an exemplary embodiment, each of the following thicknesses—the twenty-first thickness T21 of the first upper insulating layer 261, the twenty-third thickness T23 of the second upper insulating layer 262, the twenty-fifth thickness T25 of the third upper insulating layer 263, and the twenty-seventh thickness T27 of the fourth upper insulating layer 264—may be substantially equal to the twenty-ninth thickness T29 of the fifth upper insulating layer 265. Each of the ninth to thirteenth upper insulating layers 273 may have a thickness greater than the twenty-ninth thickness T29 of the fifth upper insulating layer 265. The thirtieth thickness T30 of the ninth upper insulating layer 269 may be greater than the twenty-ninth thickness T29. The thirty-second thickness T32 of the tenth upper insulating layer 270 may be substantially equal to the thirtieth thickness T30 of the ninth upper insulating layer 269. The thirty-fourth thickness T34 of the eleventh upper insulating layer 271 may be substantially equal to the thirty-second thickness T32 of the tenth upper insulating layer 270. The thirty-sixth thickness T36 of the twelfth upper insulating layer 272 may be substantially equal to the thirty-fourth thickness T34 of the eleventh upper insulating layer 271. The thickness T38 of the thirteenth upper insulating layer 273 can be greater than the thickness T36 of the twelfth upper insulating layer 272.

[0030] In an exemplary embodiment, among the plurality of lower electrode layers 181 to 191, the eleventh lower electrode layer 191 may be configured to be closest to the interface S1 between the lower stacked structure 100 and the upper stacked structure 200. The eleventh lower electrode layer 191 may be referred to as the "first lower electrode layer". One of the seventh lower electrode layer 187, the eighth lower electrode layer 188, the plurality of other lower electrode layers, and the ninth lower electrode layer 189 configured to be adjacent to the center of the lower stacked structure 100 may be referred to as the "second lower electrode layer". Among the plurality of lower electrode layers 181 to 191, the first lower electrode layer 181 may be configured to be furthest from the upper stacked structure 200. The first lower electrode layer 181 may be referred to as the "third lower electrode layer".

[0031] In an exemplary embodiment, among the plurality of upper electrode layers 281 to 291, the first upper electrode layer 281 may be configured to be closest to the interface S1. One of the fifth upper electrode layer 285, the plurality of other upper electrode layers, and the sixth upper electrode layer 286 configured to be adjacent to the center of the upper stacked structure 200 may be referred to as the "second upper electrode layer". Among the plurality of upper electrode layers 281 to 291, the eleventh upper electrode layer 291 may be configured to be furthest from the lower stacked structure 100. The eleventh upper electrode layer 291 may be referred to as the "third upper electrode layer". The second upper electrode layer 282 configured to be adjacent to the first upper electrode layer 281 may be referred to as the "fourth upper electrode layer".

[0032] In an exemplary embodiment, at least one of the plurality of lower insulating layers 167 to 174 and at least one of the plurality of upper insulating layers 261 to 273 may be disposed between the eleventh lower electrode layer 191 and the first upper electrode layer 281. For example, the fourteenth lower insulating layer 174 and the first upper insulating layer 261 may be disposed between the eleventh lower electrode layer 191 and the first upper electrode layer 281. The fourteenth lower insulating layer 174 and the first upper insulating layer 261 may be in contact with each other. An interface S1 may be formed between the fourteenth lower insulating layer 174 and the first upper insulating layer 261. The fourteenth lower insulating layer 174 and the first upper insulating layer 261 may directly contact the interface S1. The fourteenth lower insulating layer 174 may be referred to as the "first lower insulating layer". One of the eighth to tenth lower insulating layers 170, the plurality of other lower insulating layers, the eleventh lower insulating layer 171, and the twelfth lower insulating layer 172 that is adjacent to the center of the lower stack structure 100 may be referred to as the "second lower insulating layer". Optionally, at least one of the plurality of lower insulating layers 167 to 174 and the plurality of upper insulating layers 261 to 273 may directly contact the interface S1.

[0033] Reference Figure 5The nineteenth thickness T19 of the eleventh lower electrode layer 191 can be substantially equal to the sixteenth thickness T16 of the seventh lower electrode layer 187. The twenty-second thickness T22 of the first upper electrode layer 281 can be greater than the twenty-eighth thickness T28 of the fourth upper electrode layer 284.

[0034] Reference Figure 6 Each of the first upper electrode layers 281 to the third upper electrode layers 283 may have a thickness substantially the same as the twenty-eighth thickness T28 of the fourth upper electrode layer 284. The nineteenth thickness T19 of the eleventh lower electrode layer 191 may be greater than the sixteenth thickness T16 of the seventh lower electrode layer 187.

[0035] Reference Figure 7 The first upper electrode layer 281 can directly contact the fourteenth lower insulating layer 174. Interface S1 can be formed between the first upper electrode layer 281 and the fourteenth lower insulating layer 174. The nineteenth thickness T19 of the eleventh lower electrode layer 191 can be substantially equal to the sixteenth thickness T16 of the seventh lower electrode layer 187.

[0036] Reference Figure 8 Each of the first upper electrode layers 281 to the third upper electrode layers 283 may have a thickness substantially the same as the twenty-eighth thickness T28 of the fourth upper electrode layer 284. The first upper electrode layer 281 may directly contact the fourteenth lower insulating layer 174. An interface S1 may be formed between the first upper electrode layer 281 and the fourteenth lower insulating layer 174.

[0037] Reference Figure 9 Each of the plurality of channel structures 350 may include a core pattern 357, a channel layer 356 surrounding the core pattern 357, an information storage pattern 355 surrounding the channel layer 356, and a pad (also referred to as a solder pad or solder joint) 358 disposed on the channel layer 356. The information storage pattern 355 may include a tunnel insulating layer 353 surrounding the channel layer 356, a charge storage layer 352 surrounding the tunnel insulating layer 353, and an upper barrier layer 351B surrounding the charge storage layer 352. Each of the plurality of bit plugs 375 may directly contact the pad 358 while extending through the fourth interlayer insulating layer 332.

[0038] The core pattern 357 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, polycrystalline silicon, or combinations thereof. The channel layer 356 may include a semiconductor layer such as polycrystalline silicon, amorphous silicon, monocrystalline silicon, or combinations thereof. The tunnel insulating layer 353 may include an insulating layer such as silicon oxide. The charge storage layer 352 may include an insulating layer such as silicon nitride. The upper barrier layer 351B may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or combinations thereof. The pad 358 may include a conductive layer such as metal, metal nitride, metal oxide, metal silicide, conductive carbon, polycrystalline silicon, or combinations thereof.

[0039] Reference Figure 10 The information storage pattern 355 may include a tunnel insulating layer 353, a charge storage layer 352, and a lower barrier layer 351A. The lower barrier layer 351A may include a material substantially the same as that of the upper barrier layer 351B.

[0040] Reference Figure 11 The conductive layer 55 can be disposed between the support 57 and the horizontal conductive layer 51. The conductive layer 55 can directly contact the side surface of the channel layer 356 while extending through the side surface of the information storage pattern 355. For example, the conductive layer 55 can directly contact the side surface of the channel layer 356 while extending through the lower barrier layer 351A, the charge storage layer 352 and the tunnel insulating layer 353.

[0041] Refer again Figure 1 and Figures 9 to 11 The barrier layers 351A / 351B may include a lower barrier layer 351A disposed in the lower stacked structure 100 and an upper barrier layer 351B disposed in the upper stacked structure 200. The barrier layers 351A / 351B may be disposed outside the channel layer 356. The charge storage layer 352 may be disposed between the channel layer 356 and the barrier layers 351A / 351B. The tunnel insulating layer 353 may be disposed between the channel layer 356 and the charge storage layer 352. The connecting conductive layer 55, while extending through the barrier layers 351A / 351B, the charge storage layer 352, and the tunnel insulating layer 353, may directly contact the side surface of the channel layer 356.

[0042] Figure 12 This is a cross-sectional view illustrating a semiconductor device according to the disclosed exemplary embodiments.

[0043] Reference Figure 12Each of the semiconductor devices according to the disclosed exemplary embodiments may include a substrate 31, a horizontal conductive layer 51, a connecting conductive layer 55, a support 57, a third interlayer insulating layer 58, a lower stack structure 100, an upper stack structure 200, a plurality of channel structures 350, a fourth interlayer insulating layer 332, a plurality of isolation patterns 344, a plurality of bit plugs 375, and a plurality of bit lines 377. The horizontal conductive layer 51 may be disposed on the substrate 31. In an exemplary embodiment, the horizontal conductive layer 51 may be formed in the substrate 31.

[0044] Figures 13 to 19 This is a cross-sectional view illustrating a method for forming a semiconductor device according to the disclosed exemplary embodiments.

[0045] Reference Figure 13 A component isolation layer 33, multiple transistors 35, a first interlayer insulating layer 37, multiple peripheral circuit wirings 39, a capping layer 43, and a second interlayer insulating layer 45 can be formed on the substrate 31.

[0046] The substrate 31 may include a semiconductor substrate such as a silicon wafer. The element isolation layer 33 may include an insulating layer formed using a shallow trench isolation (STI) method. A plurality of transistors 35 may be formed in and / or on the substrate 31 using various methods. Each of the plurality of transistors 35 may include a fin field-effect transistor (FFET), a multi-bridge channel (MBC) transistor, a nanowire transistor, a vertical transistor, a recessed channel transistor, a 3D transistor, a planar transistor, or a combination thereof.

[0047] A first interlayer insulating layer 37 may be formed on the substrate 31 to cover a plurality of transistors 35 and a device isolation layer 33. A capping layer 43 may be formed on the first interlayer insulating layer 37. In an exemplary embodiment, the capping layer 43 may include silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbonitride (SiCN), or a combination thereof. A second interlayer insulating layer 45 may be formed on the capping layer 43.

[0048] Multiple peripheral circuit wirings 39 can be formed in the first interlayer insulating layer 37, the capping layer 43, and the second interlayer insulating layer 45. Each of the multiple peripheral circuit wirings 39 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. The multiple peripheral circuit wirings 39 can be connected to multiple transistors 35. The multiple peripheral circuit wirings 39 may include horizontal and vertical wirings of various shapes. The multiple transistors 35 and the multiple peripheral circuit wirings 39 can constitute a peripheral circuit.

[0049] A horizontal conductive layer 51 may be formed on the second interlayer insulating layer 45. A connection molding layer 55S, a support 57, and a third interlayer insulating layer 58 may be formed on the horizontal conductive layer 51. In an exemplary embodiment, the horizontal conductive layer 51 may be electrically connected to one of a plurality of peripheral circuit wirings 39. The horizontal conductive layer 51 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. For example, the horizontal conductive layer 51 may include a doped polysilicon layer. The horizontal conductive layer 51 may be a single layer or multiple layers. The connection molding layer 55S may include a material with etch selectivity relative to the horizontal conductive layer 51. The connection molding layer 55S may be a single layer or multiple layers. For example, the connection molding layer 55S may include sequentially stacked oxide layers, nitride layers, and oxide layers. The support 57 may include a material with etch selectivity relative to the connection molding layer 55S. For example, the support 57 may include a polysilicon layer.

[0050] Each of the component isolation layer 33, the first interlayer insulation layer 37, the second interlayer insulation layer 45, and the third interlayer insulation layer 58 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0051] An initial lower stack structure 100T can be formed on the third interlayer insulating layer 58. The initial stack structure 100T may include a plurality of lower insulating layers 161 to 174 and a plurality of lower molding layers 180 that are alternately and repeatedly stacked. Each of the plurality of lower molding layers 180 may have a reference... Figures 1 to 8 The corresponding lower electrode layers among the plurality of lower electrode layers 181 to 191 described are substantially the same thickness. The plurality of lower molding layers 180 may include a material having etch selectivity relative to the plurality of lower insulating layers 161 to 174. In an exemplary embodiment, the plurality of lower insulating layers 161 to 174 may include silicon oxide layers, and the plurality of lower molding layers 180 may include silicon nitride layers. In an exemplary embodiment, the plurality of lower molding layers 180 may include polysilicon layers.

[0052] Reference Figure 14 Multiple lower channel holes 150 can be formed to extend into the interior of the horizontal conductive layer 51 while extending through the initial lower stack structure 100T, the third interlayer insulating layer 58, the support 57, and the connecting molding layer 55S. Lower barrier layers 351A can be formed on the sidewalls and bottom of the multiple lower channel holes 150. Sacrificial layers 152 can be formed on the lower barrier layers 351A to fill the multiple lower channel holes 150.

[0053] The sacrificial layer 152 may include a material that is etch-selective relative to the lower barrier layer 351A. The lower barrier layer 351A may include an insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof. In an exemplary embodiment, the lower barrier layer 351A may include a silicon oxide layer, and the sacrificial layer 152 may include a polysilicon layer.

[0054] Reference Figure 15 An initial upper stack structure 200T can be formed on the initial lower stack structure 100T. The initial upper stack structure 200T may include a plurality of upper insulating layers 261 to 273 and a plurality of upper molding layers 280 that are alternately and repeatedly stacked. Each of the plurality of upper molding layers 280 may have a reference to Figures 1 to 8 The corresponding upper electrode layers among the plurality of upper electrode layers 281 to 291 described are substantially the same thickness. The plurality of upper molding layers 280 may include a material having etch selectivity relative to the plurality of upper insulating layers 261 to 273. In an exemplary embodiment, the plurality of upper insulating layers 261 to 273 may include silicon oxide layers, and the plurality of upper molding layers 280 may include silicon nitride layers. In an exemplary embodiment, the plurality of upper molding layers 280 may include polysilicon layers. The plurality of upper molding layers 280 may include the same material as the plurality of lower molding layers 180.

[0055] Reference Figure 16 Multiple upper channel vias 250 can be formed to expose the sacrificial layer 152 while extending through the initial upper stack structure 200T. Upper barrier layers 351B can be formed on the sidewalls of the multiple upper channel vias 250. The upper barrier layer 351B may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof. In an exemplary embodiment, the upper barrier layer 351B may include a silicon oxide layer. The upper barrier layer 351B may include the same material as the lower barrier layer 351A.

[0056] Reference Figure 17 Each of the plurality of upper channel holes 250 can be connected to a corresponding lower channel hole 150 of the plurality of lower channel holes 150 by removing the sacrificial layer 152. The lower barrier layer 351A can be retained on the sidewalls and bottom of the plurality of lower channel holes 150. The upper barrier layer 351B can be retained on the sidewalls of the plurality of upper channel holes 250.

[0057] Reference Figure 18 Multiple channel structures 350 can be formed in multiple upper channel holes 250 and multiple lower channel holes 150. Each of the multiple channel structures 350 may include a reference to... Figure 9 and Figure 10The described construction is similar. For example, each of the channel structures 350 may include an information storage pattern 355, a channel layer 356, a core pattern 357, and a pad 358. The information storage pattern 355 may include barrier layers 351A / 351B, a charge storage layer 352, and a tunnel insulation layer 353. The barrier layers 351A / 351B may include a lower barrier layer 351A and an upper barrier layer 351B.

[0058] Reference Figure 19 A fourth interlayer insulating layer 332 can be formed on the initial stacked structure 200T to cover multiple channel structures 350. The fourth interlayer insulating layer 332 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0059] The conductive layer 55 can be formed after the bonding molding layer 55S is removed. For example... Figure 11 As shown, the conductive layer 55 can directly contact the side surface of the channel layer 356 while extending through the side surface of the information storage pattern 355. The conductive layer 55 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. For example, the conductive layer 55 may include a doped polysilicon layer.

[0060] Multiple lower electrode layers 181 to 191 may be formed after removing multiple lower molding layers 180. Multiple lower insulating layers 161 to 174 and multiple lower electrode layers 181 to 191, alternately stacked, can constitute a lower stack structure 100. Multiple upper electrode layers 281 to 291 may be formed after removing multiple upper molding layers 280. Multiple upper insulating layers 261 to 273 and multiple upper electrode layers 281 to 291, alternately stacked, can constitute an upper stack structure 200. Each of the multiple lower electrode layers 181 to 191 and the multiple upper electrode layers 281 to 291 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. Each of the multiple lower electrode layers 181 to 191 and the multiple upper electrode layers 281 to 291 may be a single layer or multiple layers. For example, each of the plurality of lower electrode layers 181 to 191 and the plurality of upper electrode layers 281 to 291 may include W, WN, Ti, TiN, Ta, TaN, Ru, Pt, Ag or combinations thereof.

[0061] Multiple isolation patterns 344 can be formed to extend into the interior of the connecting conductive layer 55 while extending through the fourth interlayer insulating layer 332, the upper stack structure 200, the lower stack structure 100, the third interlayer insulating layer 58, and the support 57. In an exemplary embodiment, the multiple isolation patterns 344 can extend into the interior of the horizontal conductive layer 51 while extending through the connecting conductive layer 55. The multiple isolation patterns 344 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof.

[0062] Refer again Figure 1 Multiple bit plugs 375 can be formed to connect to multiple channel structures 350 while extending through the fourth interlayer insulating layer 332. Multiple bit lines 377 can be formed on the fourth interlayer insulating layer 332 to contact the multiple bit plugs 375. The multiple bit plugs 375 and the multiple bit lines 377 may include metal, metal nitride, metal silicide, metal oxide, conductive carbon, polysilicon, or combinations thereof.

[0063] According to the disclosed exemplary embodiments, a channel structure extending through an upper stacked structure and a lower stacked structure can be provided. At least one electrode layer configured to be adjacent to the interface between the lower and upper stacked structures can be thicker than a lower electrode layer configured to be adjacent to the center of the lower stacked structure. Due to the construction of the thicker electrode layer, the process margin of the channel structure can be increased. A semiconductor device capable of controlling the electrical characteristics of elements configured to be adjacent to the interface can be realized.

[0064] Although the disclosed embodiments have been described with reference to the accompanying drawings, those skilled in the art should understand that various modifications can be made without departing from the scope of the disclosure and without changing its essential features. Therefore, the embodiments described above should be considered in a descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor device comprising: a substrate having a lower stack structure disposed thereon, the lower stack structure comprising a plurality of lower insulating layers and a plurality of lower electrode layers arranged alternately and vertically, and the plurality of lower electrode layers comprising at least a first lower electrode layer and a second lower electrode layer; an upper stack structure on the lower stack structure, the upper stack structure comprising a plurality of upper insulating layers and a plurality of upper electrode layers arranged alternately and vertically, and the plurality of upper electrode layers comprising at least a first upper electrode layer and a second upper electrode layer; and a channel structure extending at least partially through the upper stack structure and at least partially through the lower stack structure, wherein the first lower electrode layer and / or the first upper electrode layer is thicker than a second lower electrode layer extending adjacent to a center of the lower stack structure; wherein at least one of the plurality of lower insulating layers and at least one of the plurality of upper insulating layers is disposed between the first lower electrode layer and the first upper electrode layer; wherein, among the plurality of lower electrode layers, the first lower electrode layer is disposed closest to an interface between the lower stack structure and the upper stack structure; and wherein, among the plurality of upper electrode layers, the first upper electrode layer is disposed closest to the interface. the first lower electrode layer is thicker than the second lower electrode layer; wherein the second upper electrode layer extends adjacent to a center of the upper stack structure.

2. The semiconductor device according to claim 1, wherein the first upper electrode layer and the second upper electrode layer have substantially the same thickness.

3. The semiconductor device according to claim 2, wherein the first upper electrode layer is thicker than the second upper electrode layer.

4. The semiconductor device according to claim 1, wherein the second upper electrode layer and the second lower electrode layer have substantially the same thickness.

5. The semiconductor device according to claim 4, wherein the plurality of lower insulating layers comprises a first lower insulating layer extending between the first lower electrode layer and the first upper electrode layer.

6. The semiconductor device according to claim 1, wherein the first lower insulating layer is thicker than a second lower insulating layer extending between the first lower insulating layer and the substrate.

7. The semiconductor device according to claim 6, wherein a third upper electrode layer of the plurality of upper electrode layers extends furthest from the interface relative to all other upper electrode layers of the plurality of upper electrode layers, and is thicker than the second upper electrode layer.

8. The semiconductor device according to claim 1, wherein a fourth upper electrode layer of the plurality of upper electrode layers extends between the first upper electrode layer and the second upper electrode layer, and is thicker than the second upper electrode layer.

9. The semiconductor device according to claim 1, wherein the at least one of the plurality of upper insulating layers extends between the first upper electrode layer and the lower stack structure.

10. The semiconductor device according to claim 1, wherein a third lower electrode layer of the plurality of lower electrode layers extends between the second lower electrode layer and the substrate, and is thicker than the second lower electrode layer.

11. The semiconductor device according to claim 1, wherein 12. The semiconductor device of claim 1, further comprising: a horizontal conductive layer extending between the substrate and the lower stack structure; a support extending between the horizontal conductive layer and the lower stack structure; and a connection conductive layer extending between the horizontal conductive layer and the support; wherein the channel structure extends through the upper stack structure, the lower stack structure, the support, and the connection conductive layer, and into an interior of the horizontal conductive layer. the channel structure comprises a channel layer, a blocking layer disposed outside the channel layer, a charge storage layer disposed between the channel layer and the blocking layer, and a tunnel insulating layer disposed between the channel layer and the charge storage layer; wherein the connection conductive layer contacts the channel layer while extending through the blocking layer, the charge storage layer, and the tunnel insulating layer. ​ 13. The semiconductor device according to claim 12, wherein ​ 14. The semiconductor device of claim 12, further comprising a plurality of transistors extending between the substrate and the horizontally conductive layer.

15. A semiconductor device comprising: a horizontally conductive layer on a substrate; a lower stack structure on the horizontally conductive layer, the lower stack structure comprising a plurality of lower insulating layers and a plurality of lower electrode layers arranged alternately vertically; an upper stack structure on the lower stack structure, the upper stack structure comprising a plurality of upper insulating layers and a plurality of upper electrode layers arranged alternately vertically; a channel structure extending through the upper stack structure and the lower stack structure and into an interior of the horizontally conductive layer; and a bit line on the upper stack structure, the bit line electrically connected to the channel structure; wherein a first lower electrode layer of the plurality of lower electrode layers is thicker than a second lower electrode layer of the plurality of lower electrode layers extending adjacent a center of the lower stack structure, the first lower electrode layer disposed closest to an interface between the lower stack structure and the upper stack structure relative to all other lower electrode layers of the plurality of lower electrode layers; and wherein at least one insulating layer of the plurality of lower insulating layers and the plurality of upper insulating layers directly contacts the interface. a first lower insulating layer of the plurality of lower insulating layers is thicker than a second lower insulating layer of the plurality of lower insulating layers extending adjacent a center of the lower stack structure, the first lower insulating layer directly contacting the interface.

16. The semiconductor device according to claim 15, wherein 17. A semiconductor device comprising: a horizontally conductive layer on a substrate; a lower stack structure on the horizontally conductive layer, the lower stack structure comprising a plurality of lower insulating layers and a plurality of lower electrode layers stacked repeatedly alternately; an upper stack structure on the lower stack structure, the upper stack structure comprising a plurality of upper insulating layers and a plurality of upper electrode layers stacked repeatedly alternately; a channel structure extending through the upper stack structure and the lower stack structure and into an interior of the horizontally conductive layer; and a bit line on the upper stack structure and electrically connected to the channel structure, wherein a first upper electrode layer of the plurality of upper electrode layers is thicker than a second upper electrode layer of the plurality of upper electrode layers extending adjacent a center of the upper stack structure, the first upper electrode layer disposed closest to an interface between the lower stack structure and the upper stack structure relative to all other upper electrode layers of the plurality of upper electrode layers; and wherein at least one insulating layer of the plurality of lower insulating layers and the plurality of upper insulating layers directly contacts the interface. a first lower electrode layer of the plurality of lower electrode layers is thicker than a second lower electrode layer of the plurality of lower electrode layers extending adjacent a center of the lower stack structure, the first lower electrode layer extending closest to the interface relative to all other lower electrode layers of the plurality of lower electrode layers. a first lower electrode layer of the plurality of lower electrode layers has a thickness substantially equal to a thickness of a second lower electrode layer of the plurality of lower electrode layers extending adjacent a center of the lower stack structure, the first lower electrode layer extending closest to the interface relative to all other lower electrode layers of the plurality of lower electrode layers.

18. The semiconductor device according to claim 17, wherein ​ 19. The semiconductor device according to claim 17, wherein ​

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