IGBT Chip, Its Manufacturing Method, and Mask Used in Manufacturing IGBT Chip

Abstract

The present invention relates to an IGBT chip, a manufacturing method thereof, and a mask used in manufacturing the IGBT chip. The IGBT chip includes cells, and each cell includes a collector region, a drift region, a well base region, an emitter region, a collector structure, and an emitter structure. The combination of the well base region and the emitter region presents a regular hexagonal prism shape. The emitter region includes three sub-emitter regions that are all regular triangles. The three sub-emitter regions intersect on the center line of the well base region and are arranged in an equidistant circular array centered on the center line within the well base region. Each sub-emitter region extends from the upper surface of the well base region towards its lower surface. The IGBT chip can improve the latch-up resistance and short-circuit resistance of its cells while maintaining a relatively large current density and a relatively small on-state voltage drop of its hexagonal cells.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to an IGBT chip, a manufacturing method of the IGBT chip, and a mask plate used when manufacturing the IGBT chip. Background Art

[0002] The IGBT chip, also known as an insulated gate bipolar transistor chip, is the core component of an IGBT device and is a core device for energy conversion and transmission. It is commonly known as the "CPU" of power electronic devices. As a national strategic emerging industry, it is widely used in fields such as rail transit, smart grid, aerospace, electric vehicles, and new energy equipment. The IGBT chip mainly consists of a plurality of cells arranged in an array and a terminal structure surrounding the plurality of cells. Among them, the cells often adopt strip, square, and hexagonal shapes. For IGBT chips of equal size, the hexagonal cell has the smallest on-state voltage drop, and the strip cell has the largest on-state voltage drop; the hexagonal cell has the largest current density, and the strip cell has the smallest current density; the hexagonal cell has the worst anti-latch-up and anti-short-circuit capabilities, and the strip cell has the best anti-latch-up and anti-short-circuit capabilities. However, the biggest problem currently faced is how to improve the anti-latch-up and anti-short-circuit capabilities of the cells of the IGBT chip while maintaining a relatively large current density and a relatively small on-state voltage drop of the hexagonal cells. Summary of the Invention

[0003] To solve all or part of the above problems, an object of the present invention is to provide an IGBT chip, a mask plate used when manufacturing the IGBT chip, and a manufacturing method of the IGBT chip. The IGBT chip can solve the problem that the anti-latch-up and anti-short-circuit capabilities of its cells cannot be improved while maintaining a relatively large current density and a relatively small on-state voltage drop of its hexagonal cells.

[0004] According to a first aspect of the present invention, there is provided an IGBT chip. The IGBT chip includes a plurality of cells arranged in an array. The cells include a collector region, a drift region, a well base region, and an emitter region that are sequentially arranged and jointly form a PNPN-type semiconductor structure, and a collector electrode structure connected to the collector region and an emitter electrode structure connected to the well base region and the emitter region. Among them, the combination of the well base region and the emitter region presents a regular hexagonal prism shape. The emitter region includes three sub-emitter regions that are all regular triangles. The three sub-emitter regions intersect on the center line of the well base region and are arranged in an equidistant circular array in the well base region with the center line as the center. Each sub-emitter region extends from the upper surface of the well base region towards its lower surface.

[0005] The cell of the IGBT chip according to the first aspect of the present invention is an improvement on the original hexagonal cell. Although the shapes and structures of the emitter region and the well base region are adjusted, since the combination of the emitter region and the well base region still presents a regular hexagonal prism shape, it belongs to the hexagonal cell. Thus, it can be ensured that the improvement has little impact on the current density and on-state voltage drop of the cell, and the cell still has the advantages of relatively large current density and relatively small on-state voltage drop. The IGBT chip of the present invention adjusts the original hexagonal emitter region into three sub-emitter regions arranged in an equidistant circular array, and makes the shape and structure of the well base region change adaptively, forcing the overlapping area of the emitter region and the well base region in the up-down direction to be reduced, so as to reduce the current flowing through the PNPN semiconductor structure when the IGBT chip works, thereby improving the anti-latch-up ability and anti-short-circuit ability of the cell. In addition, since the shapes of the emitter layer and the well base region are relatively regular, the IGBT chip is not only easy to manufacture, but also can ensure that the current can pass through the NPNP semiconductor structure uniformly, so as to prevent the IGBT chip from being damaged due to excessive local current.

[0006] According to the second aspect of the present invention, there is provided a mask used in manufacturing an IGBT chip. The mask includes a plate body and a plurality of hole groups provided on the plate body. Each hole group includes three equilateral triangle holes, and the three equilateral triangle holes intersect at a point and are arranged in an equidistant circular array with this point as the center.

[0007] The mask according to the second aspect of the present invention can be applied in the IGBT chip manufacturing method and ensure that the emitter region of the IGBT chip according to the first aspect of the present invention can be successfully formed, that is, the original hexagonal emitter region is adjusted into three sub-emitter regions arranged in an equidistant circular array, and the shape and structure of the well base region change adaptively, forcing the overlapping area of the emitter region and the well base region in the up-down direction to be reduced, so as to reduce the current flowing through the PNPN semiconductor structure when the IGBT chip works, thereby improving the anti-latch-up ability and anti-short-circuit ability of the cell.

[0008] According to a third aspect of the present invention, there is provided a method for manufacturing an IGBT chip, which includes: step a, forming trenches on a first surface of a semiconductor substrate; step b, sequentially forming a gate oxide layer and a gate structure in the trenches; step c, sequentially forming a well base region and an emitter region in the first surface of the semiconductor substrate; step d, forming a silicon oxide layer with vias on the emitter region; step e, forming an emitter structure on the silicon oxide layer, and connecting the emitter structure to the emitter region and the well base region through the vias; step f, sequentially forming a buffer region and a collector region in a second surface of the semiconductor substrate opposite to the first surface, and forming the semiconductor substrate between the buffer region and the well base region into a drift region; step g, forming a collector structure on the collector region. Wherein, the step c specifically includes: step c1, oxidizing, lithographing, etching, doping and annealing the first surface of the semiconductor substrate to form a semi-finished region in the first surface of the semiconductor substrate, wherein in the step c1, the first surface of the semiconductor substrate is lithographed through a photomask with regular hexagon holes; step c2, oxidizing, lithographing, etching, doping and annealing the first surface of the semiconductor substrate again, so that a part of the semi-finished region forms the well base region and the other part forms the emitter region, wherein in the step c2, the first surface of the semiconductor substrate is lithographed through the mask according to the second aspect of the present invention.

[0009] The method for manufacturing an IGBT chip according to the third aspect of the present invention can manufacture the IGBT chip according to the first aspect of the present invention, thereby ensuring that the IGBT chip can improve the latch-up resistance and short-circuit resistance of its cells while maintaining a relatively large current density and a relatively small on-state voltage drop of its hexagonal cells. Brief Description of the Drawings

[0010] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings:

[0011] Figure 1 is a schematic perspective view of a partial structure of an IGBT chip according to an embodiment of the present invention;

[0012] Figure 2 is a schematic cross-sectional view of a partial structure of an IGBT chip according to an embodiment of the present invention;

[0013] Figure 3 Schematically shows the first cross-sectional structure involved in the process of manufacturing Figure 1 the IGBT chip shown;

[0014] Figure 4 Schematically shows the first cross-sectional structure involved in the process of manufacturing Figure 1A second cross-sectional structure of the IGBT chip involved in the process is shown;

[0015] Figure 5 The schematic shows the manufacturing Figure 1 The third cross-sectional structure of the IGBT chip involved in the process is shown;

[0016] Figure 6 The schematic shows the manufacturing Figure 1 The fourth cross-sectional structure of the IGBT chip involved in the process is shown;

[0017] Figure 7 The schematic shows the manufacturing Figure 1 The fifth cross-sectional structure of the IGBT chip involved in the process is shown;

[0018] Figure 8 The schematic shows the manufacturing Figure 1 The sixth cross-sectional structure of the IGBT chip involved in the process is shown;

[0019] Figure 9 The schematic shows the manufacturing Figure 1 The seventh cross-sectional structure of the IGBT chip involved in the process is shown;

[0020] Figure 10 The schematic shows the manufacturing Figure 1 The partial structure of the mask used in the process of IGBT chip is shown.

[0021] In the drawings, like parts are given like reference numerals, but the drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0022] The present invention will be further described below with reference to the accompanying drawings.

[0023] Figure 1 Schematic diagram of the partial structure of an IGBT chip according to an embodiment of the present invention (the silicon oxide layer and emitter structure are not shown); Figure 2 FIG is a schematic cross-sectional view of a local structure of an IGBT chip according to an embodiment of the present invention. Figure 1 and Figure 2As shown, the IGBT chip 100 includes a plurality of cells 10 arranged in an array, and a terminal structure (not shown, which is a conventional structure) surrounding the plurality of cells 10. Each cell 10 includes a collector region 2, a drift region 4, a well base region 5, and an emitter region 6 that are sequentially arranged and jointly form a PNPN semiconductor structure, as well as a collector structure 1 connected to the collector region 2 and an emitter structure 9 connected to the well base region 5 and the emitter region 6. The combination of the well base region 5 and the emitter region 6 presents a regular hexagonal prism shape. The emitter region 6 includes three sub-emitter regions 61, each of which is an equilateral triangle. The three sub-emitter regions 61 intersect on the center line of the well base region 5 and are arranged in an equidistant circular array centered on this center line within the well base region 5. Each sub-emitter region 61 extends from the upper surface of the well base region 5 towards its lower surface. In this way, the well base region 5 is forced to consist of a lower layer region 52 with a regular hexagonal shape and three upper layer regions 51 with equilateral triangle shapes.

[0024] For the IGBT chip 100 according to an embodiment of the present invention, the emitter region 6 and the well base region 5 of the original hexagonal cell are improved. Although the shapes and structures of the emitter region 6 and the well base region 5 are adjusted, since the combination of the emitter region 6 and the well base region 5 still presents a regular hexagonal prism shape, it belongs to a hexagonal cell. Thus, it can be ensured that the improvement has little impact on the current density and conduction voltage drop of the cell 10, and the cell 10 still has the advantages of relatively large current density and relatively small conduction voltage drop. The IGBT chip 100 of the present invention adjusts the original hexagonal emitter region to three sub-emitter regions 61 arranged in an equidistant circular array, and adaptively changes the shape and structure of the well base region 5, forcing the overlapping area of the emitter region 6 and the well base region 5 in the vertical direction to be reduced. Thereby, the current flowing through the PNPN semiconductor structure during the operation of the IGBT chip 100 can be reduced, and the latch-up resistance and short-circuit resistance of the cell 10 can be improved. In addition, since the shapes of the well base region 5 and the emitter layer 6 are relatively regular, the IGBT chip 100 is not only easy to manufacture, but also can ensure that the current can uniformly pass through the NPNP semiconductor structure to prevent local overcurrent from damaging the IGBT chip 100.

[0025] In this embodiment, the cell 10 further includes a buffer region 3 provided between the collector region 2 and the drift region 4. The added buffer region 3 can further reduce the conduction voltage drop of the IGBT chip 100.

[0026] The IGBT chip 100 can be either a planar gate type IGBT chip or a better-performance trench gate type IGBT chip. In Figure 1 and Figure 2In the illustrated embodiment, the IGBT chip 100 is a trench-gate IGBT chip, so it further includes trenches provided in the drift region 4 and connected to the well base region 5 and the emitter region 6, a silicon oxide layer 7 provided between the emitter region 6 and the emitter structure 9, a gate oxide layer 8a attached to the sidewalls and the bottom of the trenches, and a gate structure 8b provided in the trenches and jointly wrapped by the silicon oxide layer 7 and the gate oxide layer 8a. As described above, the sub-emitter region 61 is in the shape of an equilateral triangle, and the combination of the well base region 5 and the emitter region 6 is in the shape of a regular hexagonal prism. When the area of each equilateral triangle is equal to 1 / 6 times the cross-sectional area of the regular hexagonal prism, the well base region 5 and the emitter region 6 are more likely to be adjacent to the trenches, thereby reducing the manufacturing difficulty of the trenches and saving the manufacturing cost of the IGBT chip 100.

[0027] In this embodiment, to ensure that the IGBT chip 100 has good comprehensive performance, the collector region 2 and the well base region 5 are preferably formed of a P-type semiconductor material, and the drift region 4, the buffer region 3, and the emitter region 6 are all preferably formed of an N-type semiconductor material. However, in other embodiments, the collector region 2 and the well base region 5 may be formed of an N-type semiconductor material, and the drift region 4, the buffer region 3, and the emitter region 6 may all be formed of a P-type semiconductor material.

[0028] In this embodiment, the silicon oxide layer 7 may be formed of a phosphosilicate glass material, and the gate oxide layer 8a may be formed of a silicon oxide. At the same time, the collector structure 1 and the emitter structure 9 are formed of a metal material, such as aluminum, and the gate structure 8b may be formed of a polysilicon material.

[0029] Next, Figures 3 to 9 describe the manufacturing method of the IGBT chip 100 according to the embodiment of the present invention. The manufacturing method includes: Step a, making trenches 8c on the first surface of the semiconductor substrate, see Figure 3 ; Step b, sequentially making a gate oxide layer 8a and a gate structure 8b in the trenches 8c, see Figure 4 ; Step c, sequentially making a well base region 5 and an emitter region 6 in the first surface of the semiconductor substrate, see Figure 5 ; Step d, making a silicon oxide layer 7 with a through hole 7a on the emitter region 6, see Figure 6 ; Step e, making an emitter structure 9 on the silicon oxide layer �, and connecting the emitter structure 9 to the emitter region 6 and the well base region 5 through the through hole 7a, see Figure 7 and Figure 1 ; Step f, sequentially making a buffer region 3 and a collector region 2 in the second surface of the semiconductor substrate opposite to the first surface, so that the semiconductor substrate between the buffer region 3 and the well base region 5 forms a drift region 4, see Figure 8 ; Step g, making a collector structure 1 on the collector region 2, see Figure 9 .

[0030] Step c specifically includes: step c1, oxidizing, photolithography, etching, doping and annealing the first surface of the semiconductor substrate to form a semi-finished product area in the first surface of the semiconductor substrate, wherein in step c1, the first surface of the semiconductor substrate is photolithographically processed using a photomask with regular hexagonal holes; step c2, oxidizing, photolithography, etching, doping and annealing the first surface of the semiconductor substrate again to form a portion of the semi-finished product area into a well base area 5 and another portion thereof into an emitter area 6, wherein in step c2, the mask 200 selected is photolithographically processed on the first surface of the semiconductor substrate. Figure 10 As shown, the mask 200 includes a plate 201 and a plurality of hole groups disposed on the plate 201. Each hole group includes three equilateral triangular holes 202. The three equilateral triangular holes 202 intersect at a point and are arranged in an equidistant circular array centered at that point. The mask 200 can ensure the smooth formation of the emitter region 6 of the IGBT chip 100 during the manufacturing method of the IGBT chip 100. Specifically, the original hexagonal emitter region is adjusted to three sub-emitter regions 61 arranged in an equidistant circular array. The shape and structure of the well base region 5 are adaptively changed, forcing the vertical overlap area between the emitter region 6 and the well base region 5 to be reduced. This can reduce the current flowing through the PNPN semiconductor structure during operation of the IGBT chip 100 and improve the anti-latch and anti-short circuit capabilities of the cell 10. Preferably, to reduce the manufacturing difficulty of the mask 200 and improve the forming accuracy of the three sub-emitter regions 61, all the equilateral triangular holes have the same area.

[0031] In the description of this application, it should be understood that the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0032] In addition, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. In the description of the present invention, "plurality" means more than two, unless otherwise specifically defined.

[0033] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to fixed or detachable connections, or integration; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0034] The above are only the preferred embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily make changes or variations within the technical scope disclosed by the present invention, and such changes or variations should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. As long as there is no structural conflict, the technical features mentioned in each embodiment can be combined in any way. The present invention is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A manufacturing method of an IGBT chip, characterized in that, Including: Step a: fabricate trenches on the first surface of a semiconductor substrate; Step b: sequentially fabricate a gate oxide layer and a gate structure within the trenches; Step c: sequentially fabricate a well base region and an emitter region formed of P-type semiconductor material within the first surface of the semiconductor substrate; Step d: fabricate a silicon oxide layer with vias on the emitter region; Step e: fabricate an emitter structure on the silicon oxide layer, and connect the emitter region and the well base region through the vias by the emitter structure; Step f: sequentially fabricate a buffer region and a collector region formed of N-type semiconductor material within the second surface of the semiconductor substrate opposite to the first surface, and form the semiconductor substrate between the buffer region and the well base region as a drift region by N-type semiconductor material; Step g: fabricate a collector structure on the collector region; Wherein, the specific steps of step c include: Step c1: oxidize, photolithograph, etch, dope and anneal the first surface of the semiconductor substrate to form a semi-finished product region within the first surface of the semiconductor substrate, wherein in step c1, photolithography is performed on the first surface of the semiconductor substrate through a photomask with regular hexagon holes; Step c2: oxidize, photolithograph, etch, dope and anneal the first surface of the semiconductor substrate again, so that a part of the semi-finished product region forms the well base region and the other part forms the emitter region, wherein in step c2, photolithography is performed on the first surface of the semiconductor substrate through a mask.

2. An IGBT chip manufactured by the manufacturing method of the IGBT chip according to claim 1, characterized in that, The IGBT chip includes a plurality of cells arranged in an array. The cells include a collector region, a drift region, a well base region and an emitter region that are sequentially arranged and jointly form a PNPN-type semiconductor structure, and a collector structure connected to the collector region and an emitter structure connected to the well base region and the emitter region. Among them, the combination of the well base region and the emitter region presents a regular hexagonal prism shape. The emitter region includes three sub-emitter regions that are all regular triangles. The three sub-emitter regions intersect on the center line of the well base region and are arranged in an equidistant circular array centered on the center line within the well base region. Each sub-emitter region extends from the upper surface of the well base region towards its lower surface.

3. The IGBT chip according to claim 2, wherein It further includes a buffer region provided between the collector region and the drift region.

4. The IGBT chip according to claim 3, wherein It further includes: A trench provided within the buffer region and connected to the well base region and the emitter region; A silicon oxide layer provided between the emitter region and the emitter structure; A gate oxide layer attached to the groove wall and the groove bottom of the trench; A gate structure provided within the trench and jointly wrapped by the gate oxide layer and the silicon oxide layer.

5. The IGBT chip according to claim 4, characterized in that, Both the collector region and the well base region are formed of P-type semiconductor material, and the drift region, the buffer region and the emitter region are all formed of N-type semiconductor material.

6. The IGBT chip according to claim 4, wherein, The area of each regular triangle is equal to 1 / 6 times the cross-sectional area of the regular hexagonal prism.

7. The IGBT chip according to claim 4, characterized in that, The silicon oxide layer is formed of phosphosilicate glass material, the gate oxide layer is formed of silicon oxide, the collector structure and the emitter structure are both formed of metal material, and the gate structure is formed of polysilicon material.

8. The IGBT chip according to claim 4, characterized in that, It further includes a terminal structure surrounding the plurality of cells.

9. A mask used in the manufacturing method of the IGBT chip according to claim 1, characterized in that, The mask plate includes a plate body and a plurality of hole groups provided on the plate body. Each hole group includes three equilateral triangle holes, and the three equilateral triangle holes intersect at a point and are arranged in an equidistant circular array form with this point as the center.

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