Reducing power consumption of communication interfaces through clock frequency scaling and adaptive polling interleaving

Abstract

Disclosed is a method of reducing power consumption of a communication interface by clock frequency scaling and adaptive polling interleaving. In a first aspect, a control system (514) controls the transmission of commands via an interface (510) at a higher clock frequency. After transmission, the control system (514) and the interface (510) operate at a lower clock frequency to save power during command execution. In this aspect, the reduction in polling corresponds to a reduction in the clock signal frequency. When a command is completed, the interface (510) operates at a higher frequency to send another command. In a second aspect, after the control system (514) sends a command to a receiving device (504), polling is paused and the execution time of the command is tracked. When the tracked execution time is almost equal to the expected completion time, polling begins. The two aspects disclosed above can be implemented to reduce power consumption in exchange for a small increase in latency.

Description

[0001] Priority claim under 35 USC § 119

[0002] This patent application claims priority to non-provisional application No. 16 / 222,381, filed on December 17, 2018, entitled “REDUCING POWER CONSUMPTION OF COMMUNICATION INTERFACES BY CLOCK FREQUENCY SCALING AND ADAPTIVE INTERLEAVING OF POLLING,” which priority is assigned to its assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technology of the present disclosure relates generally to communication between electronic devices, and particularly to reducing power consumption in an interface that controls communication between electronic devices. Background Art

[0004] Computing devices take many forms depending on their intended purpose. Regardless of the configuration of the computing device, its components must communicate with each other, which typically includes transmitting information in the form of signals through a wireless communication link or a wired communication link. The physical design of the wired communication link depends on several factors, including packaging limitations, cost targets, distances between components, and bandwidth requirements. In order to transmit a large amount of data in a short period of time, a wired communication link may include several lines that transmit multiple bits of binary data in parallel at the same time. However, due to packaging limitations, for example, a wired communication link can be a serial interface limited to one line, through which binary data bits are sent serially (i.e., sequentially). According to a periodic clock signal, a signal representing each binary data bit is maintained on the line for a period of time. Therefore, the frequency of the periodic clock signal determines the data transfer rate on the interface.

[0005] The binary information transmitted between components can be commands, which include address information, data and / or control information. The command to the receiving device coupled to the communication link can be a request for information or a request for the receiving device to take action. When the command is a request for information, when the sender receives the response, the sender will be notified of the request completion. The receiving response can also indicate that the receiving device is ready for another command. When the command is a request for action, when the action is completed or when the receiving device is ready for the next command, the sender can receive an answer from the receiving device. However, some components are not designed to provide automatic confirmation that the request has been completed. In this case, the sender can initiate another communication, such as a request for information to confirm that the request has been completed. The process of regularly repeating this request for information until receiving confirmation is called polling.

[0006] In order to increase the transmission rate (i.e., bandwidth), the control system and interface associated with the communication link can operate at a high frequency. Operating at a high frequency may require a high frequency clock. Repeated polling at a high frequency (set by the high frequency clock) reduces delay. Delay is the amount of time between when the receiving device is ready to receive the next command and when the sender is notified that the receiving device is ready. Minimizing delay increases interface efficiency. However, the control system that generates signals on the wired communication link includes transistors that consume power each time the transistor is triggered by a clock signal (i.e., each clock period). In addition, when a signal is generated on the wired communication link to repeat polling during a polling period (e.g., during command execution), power is consumed in the interface. Therefore, the power consumption level of the control system directly depends on the frequency of the clock signal and the total number of polling events in the polling period. The power consumed by polling reduces the operating time of the battery-powered device and may cause unwanted heating. Therefore, it is necessary to reduce the power consumption in the control system and the interface while maintaining a high transmission rate and minimum polling delay. Summary of the invention

[0007] Various aspects disclosed in the specific embodiments include a system and method for reducing power consumption of a communication interface by clock frequency scaling and adaptive polling interleaving. In particular, power consumption in a communication interface can be reduced by scaling down the frequency of a periodic clock signal of the interface and the interface control system while commands sent to a receiving device are executed by the receiving device. Power consumption can also be reduced by adaptively interleaving polling during most of the expected execution time of the command. In a first aspect, the control system controls the transmission of commands via the interface at a higher clock frequency. After transmitting the command, the control system and the interface operate at a lower clock frequency to save power during command execution. In this aspect, polling is reduced in response to a reduction in the frequency of the clock signal. When the command is completed, the interface operates at a higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is paused and the execution time of the command is tracked. When the tracked execution time is almost equal to the expected completion time, polling begins. The two aspects disclosed above can be implemented to reduce power consumption in exchange for a small increase in latency.

[0008] In this regard, in one aspect, a method of scaling the frequency of an interface is disclosed. The method includes: sending a command to a device via a serial interface operating at a first clock frequency for execution by the device; in response to sending the command, operating the serial interface at a second clock frequency; and in response to determining that the device is ready for another command, operating the serial interface at the first clock frequency.

[0009] In another aspect, an interface controller is disclosed. The interface controller includes a serial interface configured to be coupled to a wired communication link; and a control system coupled to the serial interface. The control system is configured to operate the serial interface at a first clock frequency to send a command to a device via the wired communication link for execution by the device, in response to the command being sent, operate the serial interface at a second clock frequency, and in response to determining that the device is ready for another command, operate the serial interface at the first clock frequency.

[0010] In another aspect, a method of interleaved polling on an interface is disclosed. The method includes: sending a command to a device via the interface for execution by the device; incrementing a counter value to track execution time; comparing the counter value to an operation value determined based on a previous command execution time; and polling the status of the device based on the comparison.

[0011] In another aspect, an apparatus is disclosed that includes an interface controller. The apparatus includes an interface configured to couple to a wired communication link; and a control system coupled to the interface. The control system is configured to send a command to a device via the interface for execution by the device, increment a counter value to track execution time, compare the counter value to an operation value based on a previous execution time of the command, and poll the device for a status indicating completion of the command based on the comparison.

[0012] In another aspect, a method of reducing power requirements of an interface is disclosed. The method includes: sending a command to a device for execution via the interface operating at a first clock frequency; in response to sending the command, operating the interface at a second clock frequency; incrementing a counter value to track execution time; comparing the counter value to an operation value determined based on a previous command execution time; polling a status of the device based on the comparison; and in response to the status indicating that the device is ready for another command, operating the interface at the first clock frequency.

[0013] In another aspect, an interface controller is disclosed. The interface controller includes an interface configured to couple to an interface of a wired communication link; and a control system coupled to the interface. The control system is configured to send a command to a device for execution via the interface operating at a first clock frequency; in response to sending the command, operate the interface at a second clock frequency; increment a counter value to track an execution time of the command; compare the counter value to an operation value determined based on a previous execution time of the command; poll a status of the device based on the comparison; and in response to the status indicating that the device is ready for another command, operate the interface at the first clock frequency.

[0014] In another aspect, a method of reducing power requirements generated by a bus is disclosed. The method includes: while operating the bus at a first clock frequency, sending a command from a first device associated with the bus to a second device; after sending the command, operating the bus at a second clock frequency; and after receiving an indication that the second device has completed the command, operating the bus again at the first clock frequency.

[0015] In another aspect, a method of reducing traffic on a bus is disclosed. The method includes: sending a command from a first device associated with the bus to a second device associated with the bus over the bus; predicting an amount of time for the second device to complete the command; and nearing expiration of the amount of time, beginning to poll the second device for a status of the completed command. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram of an exemplary serial peripheral interface (SPI) controller coupled to a serial NAND memory device;

[0017] Figure 2 is a timing diagram illustrating signal levels on an exemplary wired communication link through which commands are sent to a serial NAND memory device and polling is initiated;

[0018] Figure 3 is a timing diagram illustrating signal levels on an exemplary wired communication link at the end of a period of polling a serial NAND memory device;

[0019] Figure 4 is a timing diagram illustrating signal levels on an exemplary wired communication link during a polling event;

[0020] Figure 5 is a block diagram of an exemplary interface controller coupled to a memory device, the exemplary interface controller including an interface and a control system for implementing scaled clock frequency and adaptive staggered polling via the interface;

[0021] Figure 6 is a flow chart illustrating an exemplary process for reducing power requirements of an interface by scaling clock frequency and via interface adaptive staggered polling;

[0022] Figure 7 is a flow chart illustrating an exemplary process of an interface controller including a control system to reduce power consumption in a quad SPI (QSPI);

[0023] Figure 8 is a flow chart illustrating an exemplary command and polling sequence between an interface controller and a memory device without adaptive polling interleaving but with frequency scaling;

[0024] Fig. 9 is based on Figure 6 A timing diagram comparing polling with clock frequency scaling and polling without clock frequency scaling for a process of

[0025] Fig.10 is a system level block diagram of an exemplary mobile terminal, which may include Figure 6 and Figure 7 process operation Figure 5 interface controller. DETAILED DESCRIPTION

[0026] Several exemplary aspects of the present disclosure are now described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0027] Various aspects disclosed in the specific implementation include a system and method for reducing the power consumption of a communication interface by clock frequency scaling and adaptive polling interleaving. Specifically, the power consumption in the communication interface can be reduced by reducing the frequency of the periodic clock signal of the interface and the interface control system, while the command sent to the receiving device is executed by the receiving device. Power consumption can also be reduced by adaptively interleaving polling during most of the expected execution time of the command. In a first aspect, the control system controls the transmission of the command via the interface at a higher clock frequency. After transmitting the command, the control system and the interface operate at a lower clock frequency to save power during the execution of the command. In this aspect, polling is reduced in response to the reduction in the frequency of the clock signal. When the command is completed, the interface operates at a higher frequency to send another command. In a second aspect, after the control system sends the command to the receiving device, polling is suspended and the execution time of the command is tracked. When the execution time tracked is almost equal to the expected completion time, polling begins. The two aspects disclosed above can be implemented to reduce power consumption in exchange for a small increase in delay.

[0028] Power reduction systems and methods as disclosed herein reduce power consumption in a computing device by reducing power consumption in a communication interface between components of the computing device. The computing device includes a processing system that processes commands stored in a memory; and a memory controller that controls data transfer between the processing system and the memory device. Incidentally, the processing system may be a system on a chip (SOC), which may be a network on a chip (NOC). As disclosed herein, the power consumed by the memory controller in the interface to the memory device may be reduced. Figures 5 to 10 Examples of systems and methods incorporating inventive aspects disclosed herein are illustrated.

[0029] However, first, in order to improve understanding of various aspects of the present invention, a discussion of an exemplary computing device is provided, the exemplary computing device including a memory controller coupled between a memory device and a SOC, such as Figure 1 shown. Specifically, Figure 1 An exemplary serial non-AND (NAND) flash memory controller coupled to a serial NAND flash memory device via a serial peripheral interface (SPI) bus or a quad SPI (QSPI) bus is illustrated. SPI and QSPI are well-known serial interfaces for short-distance communication between a master device that issues commands and a slave device that receives and executes the commands. Figures 2 to 4 The timing diagram in Figure 1 The details of the operation of the serial interface between the memory controller and the memory devices as well as the power consumed by such an interface are discussed. Figures 2 to 4 The timing diagram in illustrates the transition of signal levels of an exemplary SPI / QSPI bus during a command sequence.

[0030] In this regard, Figure 1 An exemplary board 100 is illustrated on which a memory controller 102 is coupled between a memory device 104 and a SOC 106. The memory device 104 stores data accessible for use by the SOC 106, and the memory controller SOC 102 controls bidirectional data transfers between the SOC 106 and the memory device 104. The memory device 104 may store commands ("boot code") for starting the SOC 106 when power is turned on or in response to a system reset. The memory device 104 is a serial NAND flash memory device that is controlled by commands received from the memory controller 102 via a QSPI bus 108. The memory controller 102 includes a QSPI interface 110 for controlling the QSPI bus 108. The memory controller 102 further includes a SOC interface 112 for controlling communication with the SOC 106 , and a control system 114 for managing data flow between the SOC interface 112 and the QSPI interface 110 .

[0031] The control system 114 includes a data buffer 115 in which data transferred between the SOC interface 112 and the QSPI interface 110 can be temporarily stored because the SOC interface 112 and the QSPI interface 110 operate asynchronously with each other. The data buffer 115 transfers data between the SOC interface 112 and the QSPI interface 110 together with the SOC data stream 116 and the QSPI data stream 117.

[0032] Each of the QSPI interface 110, the SOC interface 112, and the control system 114 includes a timing logic circuit (not shown) that operates according to a periodic clock signal. In this regard, the QSPI interface 110, the SOC interface 112, and the control system 114 may operate at frequencies different from each other. The control system 114 includes a clock controller 118 that receives an external source clock signal 119. The clock controller 118 divides the source clock signal 119 and distributes the clock signal to the QSPI interface 110, the SOC interface 112, and the control system 114. The QSPI interface 110 may receive a QSPI interface clock signal 120 having a frequency that is the same as or lower than the frequency of the source clock signal 119. The SOC interface 112 receives an SOC interface clock signal 122 having a frequency that is lower than or equal to the frequency of the source clock signal 119, and the control system 114 receives a controller clock signal 124 having a frequency that is equal to or lower than the frequency of the SOC interface clock signal 122. The QSPI interface 110 corresponds to the QSPI standard known in the art. QSPI uses a signal group that is transmitted over conductors on the QSPI bus 108. The QSPI signal group includes a serial clock (SCLK) signal 126, a chip_select (active low) (CS_N) signal 128, a master output slave input (SI) signal 129, and a master input slave output (SO) signal 130. In QSPI, the SCLK signal 126 synchronizes the QSPI master and slave, the master sends the CS_N signal 128 to enable communication with the slave, the SI signal 129 is a serial data transfer signal from the master to the slave, and the SO signal 130 is a serial data transfer signal from the slave to the master.

[0033] Each signal in the QSPI bus 108 is provided as an electrical signal on a separate conductor (e.g., wire). In this regard, the SCLK signal 126 is provided to the memory device 104 at a frequency based on the QSPI interface clock signal 120 or based on the controller clock signal 124. The CS_N signal 128, the SI signal 129, and the SO signal 130 are each provided on separate wires.

[0034] The memory device 104 includes a status register 132 that includes a ready bit 134 that indicates whether the memory device 104 is ready to receive commands. Figure 1 In the board 100, the QSPI interface 110 in the memory controller 102 is the "master" of the QSPI bus 108, and the memory device 104 is the "slave" device. Figures 2 to 4 The timing diagram of 110 illustrates the communication between the memory controller 102 and the memory device 104 via the QSPI interface 110.

[0035] Figure 2 2 is a timing diagram 200 showing signals on the QSPI bus 108 between the QSPI interface 110 and the memory device 104. Figure 2 2 , a command 201 is transmitted via the QSPI bus 108. The CS_N signal 128 is asserted (low) to enable communication while the command 201 in the form of binary information is sent from the QSPI interface 110 to the memory device 104 via the SI signal 129 (before time 202). While the command 201 is being sent via the SI signal 129, the SO signal 130 is inactive. Starting at time 202, the command 201 is completed and the QSPI interface 110 begins polling events to the memory device 104 via the QSPI interface 110. To poll the memory device 104, the CS_N signal 128 remains asserted (valley 212) and the SI signal 129 is used to send a polling event 214 (e.g., a polling command requesting the value of the status register 132) to the memory device 104. In the timing diagram 200, the polling event 214 begins with the rising edge of the SI signal 129. In response to each polling event 214, the memory device 104 sends binary information 216 including the value of the status register 132 to the QSPI interface 110 via the SO signal 130. Until the memory device 104 completes execution of the command 201, the ready bit 134 remains unasserted. Figure 2 As shown in the polling event 214 , the status information returned indicates that the memory device 104 is still busy executing the command 201 .

[0036] Figure 3 3 is a timing diagram 300 showing the signals of the QSPI bus 108 at the end of the polling sequence. Figure 3At 302 in FIG. 1 , a polling event 314 (1) is initiated, and the memory device 104 returns a value of the ready bit 134 indicating that the command is not completed. Specifically, the SI signal 129 indicates the polling event 314 (1) sent from the QSPI interface 110 to the memory device 104, and the SO signal 130 indicates binary information 316 (1) sent from the memory device 104 to the QSPI interface 110 in response. When the memory device 104 completes execution of the first command, the ready bit 134 is asserted to indicate that the memory device 104 is ready to receive another command. In response to the polling event 314 (2), the memory device 104 returns binary information 316 (2) in which the value of the ready bit 134 is asserted. The polling event 314 (2) and the corresponding binary information 316 (2) are provided by the SI signal 129 and the SO signal 130, respectively. Based on binary information 316(2), control system 114 is notified that memory device 104 is ready for another command, and CS_N signal 128 remains inactive 320 while control system 114 prepares to send a new command 318. New command 318 begins with CS_N signal 128 and SI signal 129 activated.

[0037] Figure 4 4 is a timing diagram 400 showing detailed signals of the QSPI bus 108 during a polling event 406. After the CS_N signal 128 is asserted at time 402, the QSPI interface 110 sends a polling event 406 via the SI signal 129, requesting the value of the status register 132, and the memory device 104 sends a response 408 via the SO signal 130 with the value of the status register 132. While the value of the status register 132 is being evaluated in the control system 114, the CS_N signal 128 remains inactive to disable communication with the memory device 104. In the timing diagram 400, the changes in the QSPI bus 108 signals correspond to transitions in the voltage levels on the wires of the QSPI bus 108. The QSPI bus 108 signal that occurs in response to the polling event 406 is shown in FIG. Figure 4 The voltage transition in Figure 2 214. Polling events may be repeated back-to-back during a polling period. The polling period begins after a command is transmitted to the memory device 104 and ends when the memory device 104 completes execution of the command. In one example of a commercial memory device 104 (e.g., Macronix NAND Flash MX35UF1G14AB), the time to complete a command (e.g., read, write, erase, and reset) corresponds to a repeating polling period that varies from a few microseconds (μs) to a few milliseconds (ms).

[0038] As noted above, power is consumed each time a sequential circuit including transistors, such as the control system 114 and the QSPI interface 110, is triggered by a clock signal. In addition, power is consumed in the QSPI interface 100 during transitions in the voltage levels supplied on the wires of the QSPI bus 108. Thus, the control system 114 and the QSPI interface 110 consume a significant amount of power during the polling period due to the clock and voltage transitions. The power consumed by the QSPI interface 110 during the polling period reduces the operating time of the battery-powered device and causes undesirable heating.

[0039] In this regard, there is a need to reduce the amount of power consumed in the interface by issuing polling events while waiting for a device to execute a command. Since the amount of power consumed is based on the power consumed in the circuit when triggered by a periodic clock signal, reducing the number of times the interface circuit is triggered during each polling operation reduces the power consumption during the polling period. In addition, reducing the number of polling events that occur during the polling period reduces the power consumption during the polling period. However, it is necessary to avoid significantly increasing latency in the QSPI interface. The systems and methods disclosed herein reduce the power consumption during the polling period while maintaining a high transfer rate and minimal polling latency.

[0040] Figure 5 An exemplary board 500 is illustrated on which an interface controller 502 is coupled to a memory device 504, which may be Figure 1 The interface controller 502 is also coupled to the SOC 506, which may be Figure 1 The memory device 504 and the SOC 506 are based on the Figure 1 , and the interface controller 502 controls the bidirectional data flow between the SOC 506 and the memory device 504. The interface controller 502 includes a SOC interface 512, a control system 514, and a QSPI interface 510. In another example, the interface controller 502 can be located inside the SOC 506, so that the SOC interface 512 is an internal interface, and the QSPI interface 510 can be the SOC 506 that is coupled to the interface of the external memory device 504. The power reduction method disclosed herein is not limited to an interface to a memory device or a QSPI interface. The disclosed power reduction method can be applicable to any parallel or serial interface, in which a clock circuit in a sending device operates to poll the status of a receiving device after sending a command. The SOC interface 512 is configured to be coupled to the SOC 506. The QSPI interface 510 is configured to be coupled to a QSPI bus 508, which can be Figure 1The QSPI bus 508 is a wired communication link that is also coupled to the memory device 504. The control system 514 is coupled to the QSPI interface 510 and the SOC interface 512, and manages the bidirectional transfer of data. The control system 514 employs the QSPI interface 510 to send commands to the memory device 504 via the QSPI bus 508. The control system 514 also employs the QSPI interface 510 to poll the status register 532 of the memory device 504 during the polling period during which the command is executed by the memory device 504 to determine when the memory device 504 is ready for another command. The determination of the memory device 504 on the command is determined. The control system 514 includes a data buffer 515, in which data transferred between the SOC interface 512 and the QSPI interface 510 can be temporarily stored because the SOC interface 512 and the QSPI interface 510 are not operated synchronously with each other. The data buffer 515 , together with the SOC data stream 516 and the QSPI data stream 517 , transfers data between the SOC interface 512 and the QSPI interface 510 .

[0041] Control system 514 and Figure 1 1 is different from the control system 114 in that the control system 514 includes a power reduction circuit ("reduction circuit") 505 and a clock divider 518. The control system 514 including the reduction circuit 505 and the clock divider 518 can be implemented in a circuit, such as an integrated circuit (IC) including transistors. The reduction circuit 505 is configured to reduce the power consumed by the QSPI interface 510 and the interface controller 502 during the polling period after a command is sent to the memory device 504 and before the status of the memory device 504 indicating the completion of the command is received in the interface controller 502 in two aspects. In a first aspect, the reduction circuit 505 can reduce the power consumption 514 in the QSPI interface 510 by reducing (i.e., temporarily reducing) the frequency at which the QSPI interface 510 and the control system operate after the command is sent to the memory device 504. In a second aspect, the reduction circuit 505 also reduces power consumption by adaptively suspending polling for an amount of time that is approximately equal to the expected execution time of the command.

[0042] Regarding the first aspect of the operation of the reduction circuit 505, the clock divider 518 can be configured to divide the source clock 519 to generate a clock and distribute the clock to the QSPI interface 510, the SOC interface 512, and the control system 514. The QSPI interface 510 receives the QSPI interface clock signal 520, the SOC interface 512 receives the SOC interface clock signal 522, and the control system 514 receives the controller clock signal 524. The reduction circuit 505 controls the frequency of the QSPI interface clock signal 520 and the controller clock signal 524 generated by the clock divider 518. The control system 514 operates at the frequency of the controller clock signal 524, and the QSPI interface 510 operates at the frequency of the QSPI interface clock signal 520. The QSPI interface 510 can provide a QSPI bus clock (SCLK) signal 526 to the memory device 504 based on the frequency of the QSPI interface clock signal 520. Therefore, the operating frequencies of the control system 514, the QSPI interface 510, and the SCLK signal 526 can all be controlled by the reduction circuit 505.

[0043] In this regard, the control system 514 is configured to operate the QSPI interface 510 at a first clock frequency to send commands to the memory device 504 via the QSPI bus 508 to execute the commands by the memory device 504. The control system 514 is configured to operate the QSPI interface 510 at a second clock frequency in response to the commands being sent. During the polling period when the memory device 504 is executing the command, the QSPI interface 510 operates at the second clock frequency. The frequency of the polling events changes according to the change in the frequency of the QSPI interface clock signal 520 from the first clock frequency to the second clock frequency. In order to reduce power consumption during polling, the second clock frequency is lower than the higher first clock frequency. Therefore, the frequency of the polling events during the polling period is reduced, thereby reducing the total number of polling events that consume power.

[0044] For example, sending a command via the QSPI interface 510 includes sending a command and associated binary data (e.g., for addressing and control) while the QSPI interface clock signal 520 is at a first clock frequency. The higher first clock frequency provides a higher transmission rate for commands and associated binary data. The lower second clock frequency of the QSPI interface clock signal 520 during the polling period can be set to be less than or equal to 3 / 20 of the first clock frequency, for example, or 1 / 10. However, any second clock frequency lower than the first clock frequency will reduce power consumption during the polling period. Due to the reduction in clock frequency, the polling frequency of the memory device 504 can be correspondingly reduced to 3 / 20 or 1 / 10 of the polling frequency at the first clock frequency. The frequency of the SCLK signal 526 provided to the memory device 504 can also be changed to the second clock frequency to correspond to the operating frequency of the QSPI interface 510. By operating the QSPI interface 510 at the second clock frequency during the polling period, power consumption is reduced instead of continuing to operate at the first clock frequency.

[0045] Polling involves repeated polling events in which a request for a value of the status register 532 is sent to the memory device 504 and the memory device 504 returns the current value of the status register 532. Prior to completing execution of the command, the value of the status register 532 returned in response to each polling event indicates that the memory device 504 is not ready for another command. Eventually, the memory device 504 completes execution of the command and returns a value of the status register 532 indicating that the memory device 504 is ready for another command. The control system 514 is configured to operate the QSPI interface 510 at a first clock frequency in response to determining that the device is ready for another command.

[0046] The time interval of each polling event depends on the time required to serially transmit the binary information bits via the QSPI bus 508, the time to wait for the memory device 504 to begin responding, and the time to receive the binary information bits including the value of the status register 532 from the memory device 104. In the worst scenario, from an efficiency perspective, the memory device 504 can immediately complete the execution of the command and be ready for another command after sending the value of the status register 532 to the QSPI interface 510 indicating that the memory device 504 is not ready for another command. Therefore, the interface controller 502 must wait until the next polling event to determine that the memory device 504 is ready. As noted above, because during the delay, the interface controller 502 can begin to send another command to the memory device 504, but has not yet been notified that the memory device 504 is ready for another command, the longer delay reduces the efficiency of the interface.

[0047] One effect of reducing the frequency of the QSPI interface clock signal 520 and the SCLK signal 526 during the polling period is that the time interval between each polling event is longer, which increases latency and reduces interface efficiency. However, the increase in latency due to the frequency reduction relative to the total time of the polling period is an acceptable tradeoff for the power consumption savings achieved due to the frequency reduction during the polling period.

[0048] As noted above, in response to the interface controller 502 determining that the memory device 504 is ready for another command, the reduction circuit 505 controls the clock divider 518 to generate the controller clock signal 524 and the QSPI interface clock signal 520 at the first clock frequency to provide a higher transfer rate for the next command. For example, the memory device 504 can be a NAND flash device or a NOR flash device, but the various aspects disclosed herein are applicable to any comparable slave device. The command sent to the memory device 504 can include, for example, a write command, an erase command, or a reset command.

[0049] Regarding the second aspect of the operation of the reduction circuit 505, the reduction circuit 505 reduces power consumption by adaptively staggering polling, which includes suspending polling during most of the expected execution time of the command to reduce the number of unnecessary polling events. Ideally, polling may be suspended until the exact moment when the memory device 504 completes the execution of the command and sets the ready bit 534 in the status register 532. In this case, the polling event does not generate an indication that the memory device 504 is not ready for another command. Therefore, the only polling event generates an indication that the memory device 504 is ready for another command, so power is not consumed unnecessarily when polling. In order to avoid wasting any time after the memory device 504 is ready (for example, to avoid delays), the polling event must occur at the exact moment when the ready bit 534 in the status register 532 is set to indicate that the memory device 504 is ready for another command. However, due to variations between devices such as the memory device 504 and changes in behavior over time in such devices, it is generally not possible to predict the exact moment when the memory device 504 will complete the execution of the command.

[0050] In this regard, the reduction circuit 505 allows the control system 514 to save power during the polling period based on the tracked time by tracking the time the memory device 504 executes the command and adaptively pausing the polling during the majority of the polling period. For example, if the execution time of the command varies by 5% from a known amount of time, such that all command executions take at least 95% of the known amount of time, then pausing the polling during the 95% known amount of time may significantly reduce unnecessary power consumption, and the polling may be started before the command is completed, thereby avoiding delays.

[0051] like Figure 5 As shown, the reduction circuit 505 includes a reduction circuit control 530 for controlling the operation of the reduction circuit 505. The reduction circuit 505 tracks the amount of execution time of the command using a counter value 536 in a counter register 538 included in the reduction circuit 505. In response to sending a command to the memory device 504, the reduction circuit control 530 initializes the counter value 536 in the counter register 538 (e.g., to "0") and increments the counter value 536 to track the command execution time. For example, the counter value 536 can be incremented every clock cycle (e.g., one (1) is added to the counter value 536). In another example, the counter value 536 can be incremented every polling cycle, which can be several clock cycles. By incrementing the counter value 536 according to the polling cycle rather than every clock cycle, the size of the counter register 538 can be reduced. The reduction circuit 505 maintains an operation value 540 in an operation value register 542. The operation value 540 is set based on the previous execution time of the command. As used herein, an operation value 540 is a value based on the execution time of one or more previous commands, where the execution time is the time from sending a command via an interface (e.g., QSPI interface 510) until the completion of execution of the command is indicated. The reduction circuit control 530 is configured to compare the counter value 536 with the operation value 540, and the control system 514 polls the value of the status register 532 of the memory device 504 based on the result of the comparison. Specifically, the control system 514 suspends polling (i.e., does not start polling the memory device 504) until the counter value 536 is equal to or greater than the operation value 540. The reduction circuit 505 is configured to set a new operation value 540 in the operation value register 542 based on the counter value 536 after the command is completed. Setting the new operation value 540 allows the interface controller 502 to adjust to changes in the amount of time used to complete execution of the command in the memory device 504.

[0052] For example, immediately after the board 500 is reset, a first command of the first type may be sent to the memory device 504. When sending the command, the reduction circuit 505 initializes the counter value 536 and the operation value 540 (e.g., sets them to zero). The counter value 536 may be incremented and compared to the operation value 540 every clock cycle (or polling cycle). In this case, the counter value 536 is equal to or greater than the operation value 540 because both are initialized to zero. Since the counter value 536 is greater than or equal to the operation value 540, the interface controller 502 starts polling. The value of the counter value 536 continues to increment every clock cycle until the interface counter 502 stops incrementing at the moment when the memory device 504 is notified that another command is ready, and the value of the counter value 536 is based on the ready bit 534 in the value of the status register 532 received in response to the polling command. The counter value 536 at this moment indicates the execution time of the first command and can be used as the expected amount of time for executing the second command of the first type or another type of command. In this regard, based on the execution time of the first command, the operation value 540 may be set to the expected amount of time for executing the command (the counter value 536 ).

[0053] In one example, the operation value 540 can be set to 100% of the counter value 536 indicating the execution time of the first command. When the second command is sent to the memory device 504, the counter value 536 is initialized and incremented for each clock cycle. The counter value 536 is compared with the operation value 540. The counter value 536 is incremented until the counter value 536 is equal to or greater than the operation value 540, and the polling is started. If the execution time of the second command is longer than the execution time of the first command, the memory device 504 is ready for another command. However, if the interface controller 502 receives the value of the status register 532, wherein the ready bit 534 indicates that the memory device 504 is ready to receive another command, the execution of the second command is the same or less than the execution time of the first command.

[0054] In order to avoid delays in the case where the execution time varies and the execution time of the second command is less than the execution time of the first command, the operation value 540 can be set to a value that accounts for most of the execution time of the previous command. For example, when the previous command is completed, the operation value 540 can be set to 95%, 90%, or some other percentage of the counter value 536. Alternatively, the operation value 540 can be set to the average of the operation value 540 and the counter value 536 or the average of the counter values ​​536 of several previous commands. The above-mentioned determination method of the operation value 540 is a non-limiting example, and other determination methods of the operation value also fall within the scope of the present disclosure. The operation value 540 is used to start polling the memory device 504 after sending the subsequent command. Circuits that employ various algorithms for determining the operation value 540 based on one or more previous execution times fall within the scope of the present disclosure. Additionally, because different types of commands may take significantly different amounts of time to execute, the reduction circuit 505 can implement a dedicated register pair corresponding to the counter register 538 and the operation value register 542 for each type of command executed by the memory device 504. In this way, power savings based on adaptive polling pause can be optimized for each type of command.

[0055] Figure 6 An exemplary process 600 for reducing the power requirements of an interface according to aspects of clock scaling and interleaved polling disclosed herein is illustrated. Specifically, the process 600 begins with the control system 514 in the interface controller 502 sending a command to a device (e.g., a memory device 504) via an interface (e.g., a QSPI interface 510) operating at a first clock frequency for execution (block 602). In response to sending the command, the control system 514 operates the interface (e.g., the QSPI interface 510) at a second clock frequency (block 604). The reduction circuit 505 in the control system 514 increments a counter value 536 in a counter register 538 based on the execution time of the command (block 606). The reduction circuit control 530 in the reduction circuit 505 compares the counter value 536 with an operation value 540 determined based on a previous command execution time (block 608). Based on the comparison performed by the reduction circuit control 530, the control system 514 polls the status of the device (i.e., the value of the status register 532) (block 610). In response to the status indicating that the device is ready for another command, the control system 514 operates the interface at a first clock frequency (block 612).

[0056] Figure 7is an exemplary flow chart illustrating a process 700 of a control system 514 including a reduction circuit 505 operating a QSPI interface 510. After powering up the board 500, the process 700 begins by initializing the counter register 538 and the operation value register 542 by resetting each of the counter value 536 and the operation value 540 to "0" (block 702). The process 700 continues by sending commands to the memory device 504 at a first clock frequency (block 704). The control system 514 causes the QSPI interface 510 to poll the memory device 504 while operating at a second clock frequency (block 706). Based on the value of the status register 532 received in response to the polling, the control system 514 determines whether the memory device 504 is ready for another command (block 708). If the memory device 504 is not ready for another command, the counter value 536 in the counter register 538 is incremented (block 710) and the process returns to block 706. Returning to block 708, if the memory device 504 is ready for another command, the operating value 540 in the operating value register 542 is set based on the counter value 536 (block 712). In one example, the operating value 540 may be set equal to the counter value 536. The control system 514 may operate at the first clock frequency while setting the operating value 540.

[0057] The process 700 continues by sending another command (i.e., a second command) to the memory device 504 at the first clock frequency (block 714). In response to sending the command, the control system 514 operates the QSPI interface 510 at the second clock frequency. In response to sending the command, the counter register 538 is initialized by setting the counter value 536 to "0" (block 716). The counter value 536 is compared to the operation value 540 (block 718). If the counter value 536 is not equal to or greater than the operation value 540, the counter value 536 is incremented (block 720). Returning to block 718, if the counter value 536 is equal to or greater than the operation value 540, the memory device 504 is polled at the second clock frequency (block 722). Based on the value of the status register 532 received in response to the polling, the control system 514 determines whether the memory device 504 is ready for another command (block 724). If the memory device 504 is not ready for another command, the counter value 536 in the counter register 538 is incremented (block 726) and the process returns to block 724. Returning to block 724, if the memory device 504 is ready for another command, the control system 514 operates the QSPI interface 510 at the first clock frequency (block 728) and sets the operation value 540 in the operation value register 542 based on the counter value 536 (block 730). According to block 730, the process 700 returns to block 714 and repeats.

[0058] Figure 88 is a flow chart illustrating a command and polling sequence 800 between an interface controller 502 and a memory device 504 on a bus 508 that does not implement the polling interleaving aspects of the reduction circuit 505 disclosed above, but has a frequency scaled QSPI. The sequence 800 begins with the interface controller 502 sending a memory command, such as an erase command, a read command, a write command, or a reset command (or another command executable by the memory device 504) to the memory device 504 (block 802). The command may be sent by the interface controller 502 operating at a higher clock frequency, and the interface controller 502 may then operate at a lower clock frequency, as described above. To determine when execution of the memory command is complete, the interface controller 502 begins a polling sequence by sending a polling command to poll a register in the memory device 504 (block 804). The address of the status register 532 is sent to the memory device 504 (block 806), and after the address, control data for the polling command is sent (block 808). In response to the polling command, the memory device 504 responds by sending the value of the status register 532 to the interface controller 502 on the QSPI bus 508, and the interface controller 502 determines whether the memory device 504 is ready for another command by checking the ready bit 534 (block 810). If the memory device 504 is found not ready for another command, the sequence 800 returns to block 804 where the polling is repeated. If the memory device 504 is found ready for another command at block 810, the interface controller 502 operates at the first clock frequency and the sequence 800 continues with the interface controller 502 sending another memory command to the memory device 504 (block 812).

[0059] Fig. 9 9 is an illustration of the reduction in polling events achieved by operating the QSPI interface 510 at a second clock frequency that is 20% of the first clock frequency at which the QSPI interface 510 operates while sending commands. In this example, the command execution time 902 is the time for the memory device 504 to execute the command. Sequence 904 illustrates a number of polling events A1 to A15 (i.e., as shown in FIG. 1 ) performed by the QSPI interface 510 operating according to the first clock frequency. Figure 8804 to 808 in ). The delay time 906 occurs between the memory device 504 becoming ready for another command at time 908 and the time 910 at which the interface controller 502 receives the value of the status register 532 indicating that the memory device 504 is ready. Sequence 914 illustrates several polling events B1 to B3 performed by the QSPI interface 510 operating according to a second clock frequency that is 20% of the first clock frequency. As shown, the reduction in polling events corresponds to the reduction in clock frequency. In other words, because the second clock frequency is 20% of the first clock frequency, the number of polling events when operating at the second clock frequency is 20% of the number of polling events when operating at the first clock frequency. Therefore, the power consumed by the polling event during the execution of the command is reduced to 20% of the power consumption that would be consumed by the polling event without implementing clock scaling by implementing the clock scaling aspect of the reduction circuit 505. The additional latency time 916 due to the implementation of clock scaling increases the overall latency of the command, but is small compared to the total command execution time 902 and may be an acceptable tradeoff for the power consumption reduction provided by clock scaling.

[0060] The interface controller 502 that reduces power consumption of the communication interface by clock frequency scaling and adaptive polling interleaving may be included in any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0061] In this regard, Fig.10 It can be used according to Figure 6 and Figure 7 The processes 600 and 700 are operated Figure 5 1. System-level block diagram of an exemplary mobile terminal 1000 (such as a smart phone, mobile computing device tablet, etc.) with an interface controller 502.

[0062] Continue to refer Fig.10, the mobile terminal 1000 includes an application processor 1004 (sometimes referred to as a host) that communicates with a mass storage element 1006 via a universal flash memory (UFS) bus 1008. The application processor 1004 may also be connected to a display 1010 via a display serial interface (DSI) bus 1012 and to a camera 1014 via a camera serial interface (CSI) bus 1016. Various audio elements (such as a microphone 1018, a speaker 1020, and an audio codec 1022) may be coupled to the application processor 1004 via a serial low-power chip-to-chip multimedia bus (SLIMbus) 1024. Additionally, the audio elements may communicate with each other via a SOUNDWIRE bus 1026. A modem 1028 may also be coupled to the SLIMbus 1024 and / or the SOUNDWIRE bus 1026. The modem 1028 may also be connected to the application processor 1004 via a PCI link or a PCIE link 1030 and / or a system power management interface (SPMI) bus 1032.

[0063] Continue to refer Fig.10 , the SPMI bus 1032 may also be coupled to a local area network (WLAN) IC (WLAN IC) 1034, a power management integrated circuit (PMIC) 1036, a companion IC (sometimes referred to as a bridge chip) 1038, and a radio frequency IC (RFIC) 1040. It should be appreciated that separate PCI links 1042 and 1044 may also couple the application processor 1004 to the companion IC 1038 and the WLAN IC 1034. The application processor 1004 may also be connected to a sensor 1046 via a sensor bus 1048. The modem 1028 and the RFIC 1040 may communicate using a bus 1050.

[0064] Continue to refer Fig.10 , the RFIC 1040 may be coupled to one or more RFFE elements, such as an antenna tuner 1052, a switch 1054, and a power amplifier 1056, via a radio frequency front end (RFFE) bus 1058. Additionally, the RFIC 1040 may be coupled to an envelope tracking power supply (ETPS) 1060 via a bus 1062, and the ETPS 1060 may communicate with the power amplifier 1056. In summary, the RFFE elements including the RFIC 1040 may be considered to be an RFFE system 1064. It should be appreciated that the RFFE bus 1058 may be formed by a clock line and a data line (not shown). The application processor 1004 may also be coupled to an interface controller 502 that controls data transfer between the application processor 1004 and the flash memory device 1066.

[0065] Those skilled in the art will also appreciate that the various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein can be implemented as instructions stored in electronic hardware, memory or in another computer-readable medium and executed by a processor or other processing device or a combination of the two. As an example, the device described herein can be used for any circuit, hardware component, IC or IC chip. The memory disclosed herein can be a memory of any type and size and can be configured to store any type of desired information. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits and steps have been described in terms of their functionality in general. How to achieve this functionality depends on specific applications, design options and / or design constraints imposed on the entire system. The technician can implement the described functions in different ways for each specific application, but such implementation determination should not be interpreted as causing deviations from the scope of the present disclosure.

[0066] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0067] The various aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0068] It should also be noted that the operational steps described in any of the exemplary aspects in this article are described as providing examples and discussions. The described operations can be performed in many different sequences in addition to the illustrated sequence. Further, the operations described in a single operational step can actually be performed in several different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that it is obvious to those skilled in the art that the operational steps illustrated in the flowchart diagram can be modified in a variety of different ways. It should also be understood by those skilled in the art that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be cited throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0069] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for scaling the frequency of an interface, comprising: sending a command to a device via a serial interface operating at a first clock frequency for execution by the device; responsive to sending the command, operating the serial interface at a second clock frequency; incrementing a counter value to track execution time of the command; comparing the counter value with an operational value determined based on a previous command execution time; polling a status of the device based on the counter value being equal to or greater than the operational value; as well as In response to the status indicating that the device is ready for another command, operating the serial interface at the first clock frequency.

2. The method according to claim 1, wherein Sending the command includes: The command is sent to the memory device via a serial peripheral interface (SPI) or a quad SPI (QSPI).

3. The method according to claim 1, wherein Sending the command to the device includes: The command is sent to a NAND FLASH memory device or a NOR FLASH memory device.

4. The method according to claim 1, wherein Sending the command to the device includes: Send one of a read command, a write command, an erase command, and a reset command; as well as Operating the serial interface at the second clock frequency includes operating the serial interface at a clock frequency lower than the first clock frequency.

5. The method according to claim 4, wherein The second clock frequency is less than 3 / 20 of the first clock frequency.

6. An interface controller comprising: a serial interface configured to couple to a wired communication link; as well as A control system is coupled to the serial interface, the control system being configured to: operating the serial interface at a first clock frequency to send commands to a device via the wired communication link for execution by the device; in response to the command being sent, operating the serial interface at a second clock frequency; incrementing a counter value to track execution time of the command; comparing the counter value with an operational value determined based on a previous command execution time; polling a status of the device based on the counter value being equal to or greater than the operational value; as well as In response to the status indicating that the device is ready for another command, operating the serial interface at the first clock frequency.

7. The interface controller of claim 6, wherein the serial interface comprises a serial peripheral interface (SPI) or a quad SPI (QSPI), and the device comprises a memory device.

8. The interface controller of claim 6, wherein the device comprises a NAND FLASH memory device or a NORFLASH memory device.

9. The interface controller according to claim 6, wherein The command includes one of a read command, a write command, an erase command, and a reset command; and The second clock frequency is lower than the first clock frequency.

10. The interface controller according to claim 9, wherein the second clock frequency is less than 3 / 20 of the first clock frequency.

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