Method and system for address table cache management

Abstract

In a method for address table cache management, a first logical address associated with a first read command may be received. The first logical address may be associated with a first section of an address mapping table. A second logical address associated with a second read command may then be received. The second logical address may be associated with a second section of the address mapping table. A correlation metric associating the first section with the second section may be increased in response to receiving the first logical address before the second logical address. The first logical address and the second logical address may each be mapped to a physical address within the address mapping table, and a mapping table cache may be configured to store two or more sections. The mapping table cache may then be managed based on the correlation metric.

Description

Technical Field

[0001] The present application relates to an address table cache management method, an address table cache management device and an address table cache management system. Background Art

[0002] Mapping table cache management is a vital part of flash memory management. Mapping table cache is often used to improve read latency by avoiding the need to perform two read operations of NAND flash memory for each main read request due to the need to first perform logical to physical address translation. However, due to the limited size of the cache, it is necessary to manage the cache to maximize the cache hit rate and minimize the cache miss rate. In conventional systems, data can be introduced into the cache as needed, and a least recently used (LRU) eviction strategy can be implemented. However, these methods are suboptimal.

[0003] Optimization of mapping table cache usage is complicated by the fact that flash management related decisions (e.g., cache eviction) not only affect the immediate point in time when the decision is made, but can also have long-term effects that are more difficult to optimize. The cache contents of the mapping table cache need to be managed to improve longer-term performance. Summary of the invention

[0004] The present disclosure relates to a method for address table cache management. A first logical address associated with a first read command may be received. The first logical address may be associated with a first section of an address mapping table. A second logical address associated with a second read command may then be received. The second logical address may be associated with a second section of the address mapping table. A correlation metric associating the first logical address with the second logical address may increase in response to receiving the first logical address before the second logical address. The first logical address and the second logical address may each be mapped to a physical address within the address mapping table, and the mapping table cache may be configured to store two or more sections. The mapping table cache may then be managed based on the correlation metric.

[0005] The present disclosure further relates to a device for address table cache management. The device may include a processor and a memory. The memory may store instructions that, when executed by the processor, configure the device to receive a first read command including a first logical address, wherein a first segment of a mapping table cache includes the first logical address. The instructions may further configure the device to receive a second read command including a second logical address, wherein a second segment of the address mapping table includes the second logical address. The device may then increase a correlation metric associating the first segment with the second segment in response to the mapping table cache failing to include the second segment and in response to receiving the first read command before the second read command. The device may also be configured to manage the mapping table cache based on the correlation metric.

[0006] The present disclosure finally relates to a system for address table cache management. The system may include a non-volatile memory, a volatile memory, an input / output interface, a cache manager, a cache segment manager, a cache loader, and a storage controller. The non-volatile memory may be configured to store an address mapping table. The volatile memory may be configured to store a mapping table cache including a set of segments. Each segment may include an address mapping between a logical block address (LBA) and a physical block address. The input / output interface may be configured to receive a storage command. The storage command may include a logical address that uniquely identifies a set of data blocks stored on the non-volatile memory. The cache manager may be configured to load a segment from an address mapping table of the non-volatile memory into a mapping table cache of the volatile memory. The cache segment manager may be configured to manage an LBA correlation table. The LBA correlation table may include a correlation metric for each of a plurality of segments based on a read command request for an LBA of a segment in the plurality of segments. The cache loader may be configured to retrieve the non-cached segment from the address mapping table of the non-volatile memory in response to the non-cached segment having a higher coherence metric than one or more coherence metrics of the resident segment relative to other segments in the mapping table cache. The storage controller may also be configured to service a storage command using a physical address provided by the cache manager. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0008] Figure 1 is a block diagram of a storage system 100 according to one embodiment.

[0009] Figure 2 A block diagram of a host and a storage device according to one embodiment is shown.

[0010] Figure 3 A storage system 300 is shown according to one embodiment.

[0011] Figure 4 An address mapping table 400 is shown according to one embodiment.

[0012] Figure 5 A mapping table cache 500 is shown according to one embodiment.

[0013] Figure 6 An LBA correlation table 600 is shown according to one embodiment.

[0014] Figure 7Logical address request tracking or read command tracking 700 is shown according to one embodiment.

[0015] Figure 8 is a block diagram of a storage system 800 according to one embodiment.

[0016] Fig. 9 An address mapping table 900 is shown according to one embodiment.

[0017] Fig.10 A mapping table cache 1000 is shown according to one embodiment. DETAILED DESCRIPTION

[0018] In the present invention, Hebbian Learning rule can be used for flash memory management in storage devices, and more specifically for cache management. "Storage device" refers to any hardware, system, subsystem, circuit, component, module, non-volatile memory medium, hard drive, storage array, device or apparatus that is configured, programmed, designed or engineered to store data for a period of time and maintain the data in the storage device when the storage device does not use power from a power source. Examples of storage devices include, but are not limited to, hard drives, flash memories, MRAM memories, solid-state storage devices, Just a Bunch Of Disks (JBOD), Just a Bunch Of Flash (JBOF), external hard drives, internal hard drives, and the like.

[0019] Embodiments of the present disclosure propose devices, systems, and schemes for managing address caches based on real-time mapping of strongly correlated logical block addresses (LBAs) and / or LBA ranges using Hebbian learning rules as proposed below. (References to a single LBA or one or more LBA ranges are used interchangeably herein.) Hebbian learning rules identify how much weight to assign to an association between two concepts, objects, or things based on an activity or event that indicates an association / relationship.

[0020] Hebbian learning rules can be used to map strongly correlated LBAs on the fly during the device's lifetime. The LBA correlation map can then be used to improve storage device performance by improving the following flash management operations:

[0021] 1. Evict segments that have LBAs that are weakly correlated with LBAs of other segments.

[0022] 2. Upload the segments from the non-volatile storage media based on the learned LBA associations.

[0023] 3. Consolidate and update the management storage controller table based on the strongly associated LBAs.

[0024] 4. Activate NAND flash compaction operations based on strongly correlated LBAs and based on valid data counter (VC=0), where strongly correlated LBAs may be moved to common physical erase blocks and organized into common sectors by background operations.

[0025] "Segment" refers to a data structure configured to store a logical address and a physical address associated with the logical address. In one embodiment, the logical address may include an LBA range and the physical address may include a corresponding physical block address range. "Segment size" refers to the number of data bytes that together define a segment. In certain embodiments, a segment may include metadata associated with the segment. In such embodiments, the segment size may include metadata.

[0026] The dependencies between LBAs may be managed at the segment level. The segments may be initially organized by splitting the address mapping table into a number of segments. Although the number of segments may affect the efficiency of the LBA dependency table, splitting the address mapping table into a larger number of segments may provide better granularity and thus provide a higher hit rate. "Hit rate" refers to a measure of how often an LBA or LBA range is requested by a host and a segment, and the segment containing the requested LBA or LBA range is in the cache. The hit rate for each segment may be tracked. The hit rate may be expressed as an integer, a real number, a decimal number, or a percentage.

[0027] One formula for calculating the hit rate may include taking a count of the number of requests for LBAs of a segment in cache and dividing it by the total number of LBA requests serviced. For example, assume that out of 1000 LBA requests, 500 request LBAs within a given segment A. In this example, the hit rate is 0.5 or 50%.

[0028] The storage controller may maintain an LBA correlation table containing a "correlation metric". A "correlation metric" refers to a measurement, score or grade of the magnitude of a relationship, association or correlation of requesting, identifying or receiving a first logical address followed by a second logical address in a sequential order. In some embodiments, the correlation metric may be measured with respect to a period of time. In some embodiments, the higher the correlation metric, the stronger or higher the probability that the second logical address will be requested, identified or received immediately or soon after the first logical address. The correlation metric may be associated with any scale or unit of measurement that conveys an association, relationship or correlation at an appropriate level of granularity. For example, in one embodiment, the correlation metric is associated with a scale of real numbers between 0 and 1, where 0 on the scale represents a very low or non-existent correlation between the sequences and 1 on the scale represents a very high or possible correlation, where the first logical address will be requested after the request for the second logical address. This scale between 0 and 1 can be easily converted to a percentage representing the correlation metric. In another example, in one embodiment, the correlation metric is associated with a scale of all numbers between 1 and 10, where 1 on the scale represents a little or no correlation and 10 on the scale represents a maximum or high correlation. The storage controller may be able to identify a currently requested LBA and a previously requested LBA. In certain embodiments, the storage controller may be configured to maintain a history of how often a currently requested LBA was requested immediately after a particular previously requested LBA. Whenever a host system requests a storage operation (e.g., a read command) to a particular LBA and subsequently requests another LBA from a different segment, the storage controller may increase the correlation metric of the two cache segments within the LBA correlation table. In some embodiments, requesting an LBA from a different segment may reduce the correlation metric of the included LBA.

[0029] For data evenly distributed on a non-volatile storage medium, the average correlation metric may be -7 / 8*X, where X is equal to the number of LBA accesses serviced. Data accesses and associated logical addresses may not be completely random, and there may be correlations between LBAs, and the average score for each segment may be biased. In one embodiment, while very strong correlations may result in positive numbers, moderate correlations may result in small negative numbers, and weaker correlations may produce large negative numbers.

[0030] One embodiment of an LBA dependency table may be constructed and maintained so that the storage controller can "predict" which sectors should be pre-fetched volatile memory, such as an address mapping table cache, to increase the likelihood of a cache "hit." Another byproduct may be defragmentation of the cache and physical data stored in the non-volatile memory device.

[0031] Figure 11 is a schematic block diagram illustrating one embodiment of a storage system 100 including a partitioned storage device according to the disclosed solution. The storage system 100 includes a storage device 102, a storage controller 104, a memory die 106, a host 110, a user application 112, a storage client 114, a logical address space 116, metadata 118, a flash translation layer 120, an address mapping table 122, a data bus 124, a bus 126, at least one host 128, and a network 130.

[0032] The storage system 100 includes at least one storage device 102, which includes a storage controller 104 and one or more memory dies 106 connected by a bus 126. In some embodiments, the storage system 100 may include two or more storage devices. "Storage controller" refers to any hardware, device, component, element or circuit configured to manage data operations on non-volatile storage media, and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers or the like. In some embodiments, the storage controller is configured to store data on non-volatile storage media to transfer data to non-volatile storage devices and / or read data from non-volatile storage media to transfer data from non-volatile storage devices, etc. "Non-volatile memory" refers to the abbreviation of non-volatile storage media. In some embodiments, non-volatile storage media refers to non-volatile storage media and logic, controllers, processors, state machines and / or other peripheral circuits that manage non-volatile storage media and provide access to non-volatile storage media.

[0033] A "processor" refers to any circuit, component, chip, die, package, or module configured to receive, interpret, decode, and execute machine instructions. Examples of processors may include, but are not limited to, a central processing unit, a general-purpose processor, a special application processor, a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system on a chip (SoC), a virtual processor, a processor core, and the like.

[0034] "Memory" means any hardware, circuit, component, module, logic, device, or apparatus that is configured, programmed, designed, arranged, or engineered to retain data. Some types of memory require access to a constant power source to store and retain data. Other types of memory retain and / or store data when power is not available.

[0035] A "memory die" refers to a piece of semiconductor material made in such a way that one or more circuits are formed on, below, or within one or more layers of semiconductor material. Specifically, integrated circuits and memory circuits can be mass-produced on wafers of electronic grade silicon (EGS) or other semiconductor materials (e.g., GaAs). The wafer is divided into small segments, each containing an independent version of the integrated circuit. The segments are referred to herein as "die" or "memory die."

[0036] In one embodiment, a memory die is a die that includes functional circuitry for operating in the form of a nonvolatile memory medium and / or a nonvolatile memory array. "Nonvolatile memory medium" refers to any hardware, device, component, element, or circuit that is configured to retain a changeable physical characteristic for representing a binary value of zero or one after removal of main power. The nonvolatile memory medium may include an example of a nonvolatile storage medium. Examples of changeable physical characteristics include, but are not limited to, a threshold voltage of a transistor, a resistance level of a memory cell, a current level through a memory cell, a magnetic pole orientation, a spiral transfer torque, and the like.

[0037] A changeable physical characteristic is one that, once set, remains sufficiently fixed such that the changeable physical characteristic can be measured, detected, or sensed when reading, retrieving, or sensing a binary value when the main power supply for the nonvolatile memory medium is unavailable. In other words, nonvolatile memory media is a storage medium that is configured such that data stored on the nonvolatile memory media can be retrieved after power to the nonvolatile memory media is removed and subsequently restored. Nonvolatile memory media may include one or more nonvolatile memory elements, which may include, but are not limited to, chips, packages, panels, memory dies, and the like.

[0038] Examples of non-volatile memory media include, but are not limited to, ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, bidirectional universal memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon-oxide-based sub-10 nanometer process memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS), programmable metallization cell (PMC), conductive bridging RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, magnetic tape), optical storage media, or the like.

[0039] Although nonvolatile memory media are referred to herein as "memory media," in different embodiments, nonvolatile memory media may be more generally referred to as nonvolatile memory. Because nonvolatile memory media are able to store data when power is removed, nonvolatile memory media may also be referred to as recording media, nonvolatile recording media, storage media, memory, nonvolatile memory, volatile memory media, nonvolatile memory media, nonvolatile memory, or the like.

[0040] In some embodiments, data stored in the non-volatile memory medium may be addressed at a block level, which means that the data in the non-volatile memory medium is organized into blocks of data that each have a unique logical address (e.g., LBA). In other embodiments, data stored in the non-volatile memory medium may be addressed at a byte level, which means that the data in the non-volatile memory medium is organized into bytes of data (8 bits) that each have a unique address (e.g., logical address). One example of a byte-addressable non-volatile memory medium is a storage class memory (SCM).

[0041] “Non-volatile storage media” refers to any hardware, device, component, element, or circuit configured to retain a changeable physical characteristic representing a binary value of zero or one after the removal of primary power.

[0042] A "nonvolatile memory array" refers to a collection of nonvolatile memory cells (also referred to as memory cells or nonvolatile memory cells) organized into an array structure having rows and columns. The memory array is addressable using row and column identifiers.

[0043] Each storage device 102 may include two or more memory dies 106, such as flash memory, nano random access memory ("nano RAM or NRAM"), magnetoresistive RAM ("MRAM"), dynamic RAM ("DRAM"), phase change RAM ("PRAM"), etc. In further embodiments, the data storage device 102 may include other types of non-volatile and / or volatile data storage, such as dynamic RAM ("DRAM"), static RAM ("SRAM"), magnetic data storage, optical data storage, and / or other data storage technologies. The memory dies 106 may be configured into a memory array 108.

[0044] A "memory array" refers to a collection of storage units (also referred to as memory cells) organized into an array structure having rows and columns. A memory array may be addressed using row and column identifiers. A "memory cell" refers to a type of storage media configured to represent one or more binary values ​​by means of a determinable physical characteristic of the storage media when the storage media is sensed, read, or detected to determine which binary value was last stored in the memory cell. Memory cell and storage cell are used interchangeably herein.

[0045] The storage device 102, also referred to herein as a storage device, can be a component within the host 110 as depicted here and can be connected using a data bus 124, such as a Peripheral Component Interconnect Express ("PCI-e") bus, a Serial Advanced Technology Attachment ("serial ATA") bus, or the like. In another embodiment, the storage device 102 is external to the host 110 and connected to a Universal Serial Bus ("USB") connection, an Institute of Electrical and Electronics Engineers ("IEEE") 1394 bus ("FireWire"), or the like. In other embodiments, the storage device 102 is connected to the host 110 using a Peripheral Component Interconnect ("PCI") Express bus that uses an external electrical or optical bus extension or bus networking solution, such as InfiniBand or PCI Express Advanced Switching ("PCIe-AS"), or the like. "Host" refers to any computing device or computer device or computer system configured to send and receive storage commands. Examples of hosts include, but are not limited to, computers, laptops, mobile devices, home appliances, virtual machines, enterprise servers, desktops, tablets, mainframes, and the like.

[0046] In various embodiments, the memory device 102 may be in the form of a dual in-line memory module ("DIMM"), a daughter card, or a micromodule. In another embodiment, the memory device 102 is a component mounted within a rack-mounted blade. In another embodiment, the memory device 102 is contained within a package that is directly integrated onto a higher-level assembly (e.g., a backplane, a laptop, a graphics processor). In another embodiment, individual components comprising the memory device 102 are directly integrated onto a higher-level assembly without an intermediate package.

[0047] In another embodiment, instead of being directly connected to the host 110 in the form of a DAS, the data storage device 102 may be connected to the host 110 via a data network. For example, the data storage device 102 may include a storage area network ("SAN") storage device, a network attached storage ("NAS") device, a network share, or the like. In one embodiment, the storage system 100 may include a data network, such as the Internet, a wide area network ("WAN"), a metropolitan area network ("MAN"), a local area network ("LAN"), a token ring, a wireless network, a fiber channel network, a SAN, a NAS, an ESCON, or any combination of the like or networks. The data network may also include a network from the IEEE 802 family of network technologies, such as Ethernet, token ring, Wi-Fi, Wi-Max, and the like. The data network may include servers, switches, routers, cables, radios, and other devices for facilitating networking between the host 110 and the data storage device 102.

[0048] The storage system 100 includes at least one host 110 connected to a storage device 102. A plurality of hosts 110 may be used and may include: a server, a storage controller of a storage area network ("SAN"), a workstation, a personal computer, a laptop, a handheld computer, a supercomputer, a computer cluster, a network switch, a router or a home appliance, a database or storage device, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, or the like. In another embodiment, the host 110 may be a client and the storage device 102 autonomously operates on service data requests sent from the host 110. In this embodiment, the host 110 and the storage device 102 may be connected using a computer network, a system bus, a direct attached storage (DAS), or other communication means suitable for connection between a computer and an autonomous storage device 102.

[0049] The depicted embodiment shows a user application 112 as part of a host 110 in communication with a storage client 114. In one embodiment, the user application 112 is a software application that operates on or in conjunction with the storage client 114.

[0050] "Storage client" refers to any hardware, software, firmware, or logic component or module configured to communicate with a storage device to use a storage service. Examples of storage clients include, but are not limited to, operating systems, file systems, database applications, database management systems ("DBMS"), server applications, servers, volume managers, kernel-level processes, user-level processes, applications, mobile applications, threads, processes, and the like. "Hardware" refers to functional elements implemented as analog and / or digital circuits. "Software" refers to logic implemented as processor-executable instructions in machine memory (e.g., read / write volatile memory media or non-volatile memory media). "Firmware" refers to logic implemented as processor-executable instructions stored on volatile memory media and / or non-volatile memory media.

[0051] "Volatile memory" refers to shorthand for volatile memory media. In certain embodiments, volatile memory refers to volatile memory media and logic, controllers, processors, state machines, and / or other peripheral circuitry that manages the volatile memory media and provides access to the volatile memory media. "Volatile memory media" refers to mutable physical features configured to hold a binary value representing a zero or a one, wherein the mutable physical features revert to a default state that no longer represents the binary value when main power is removed or unless main power is used to refresh the presented binary value. Examples of volatile memory media include, but are not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), double data rate random access memory (DDR RAM), or other random access solid-state memory.

[0052] Although volatile memory media is referred to herein as "memory media," in different embodiments, volatile memory media may be more generally referred to as volatile memory.

[0053] In certain embodiments, data stored in the volatile memory medium may be addressed at a byte level, which means that the data in the volatile memory medium is organized into data bytes (8 bits) that each have a unique address (eg, a logical address).

[0054] "Logic" refers to machine memory circuits, non-transitory machine-readable media, and / or circuitry that, by virtue of its material and / or material energy configuration, includes control and / or program signals, and / or settings and values ​​(e.g., resistance, impedance, capacitance, inductance, current / voltage ratings, etc.) applicable to affect the operation of a device. Magnetic media, electronic circuits, electrical and optical memory (both volatile and non-volatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (but does not exclude machine memory that includes software and thereby forms a configuration of matter).

[0055] "Circuitry" refers to a circuit having at least one discrete circuit, a circuit having at least one integrated circuit, a circuit having at least one application-specific integrated circuit, a circuit forming a general-purpose computing device configured by a computer program (e.g., a general-purpose computer configured by a computer program that at least partially performs the processes or devices described herein, or a microprocessor configured by a computer program that at least partially implements the processes or devices described herein), a circuit forming a memory device (e.g., in the form of random access memory), or a circuit forming a communication device (e.g., a modem, a communications switch, or an optoelectronic device).

[0056] The storage clients 114 manage files and data and utilize the functions and features of the storage controller 104 and the associated memory die 106. Representative examples of storage clients include, but are not limited to, servers, file systems, operating systems, database management systems ("DBMS"), volume managers, and the like. The storage clients 114 communicate with the storage controller 104 within the storage device 102. In some embodiments, the storage clients 114 may include remote storage clients operating on a host 128 or otherwise accessible over a network 130. The storage clients may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

[0057] The storage client 114 may present a logical address space 116 to the host 110 and / or the user application 112. A "logical address space" refers to a logical representation of a memory resource. The logical address space may include a plurality (e.g., a series) of logical addresses. The logical address space 116 may include a plurality (e.g., a series) of logical addresses. As used herein, a logical address refers to any identifier used to reference a memory resource (e.g., data), including but not limited to a logical block address (LBA), a cylinder / head / sector (CHS) address, a file name, an object identifier, an index section, a universally unique identifier (UUID), a globally unique identifier (GUID), a hash code, a tag, an index entry, a range, an extent, or the like.

[0058] "Logical address" refers to any identifier used to reference a memory resource (e.g., data), including but not limited to a logical block address (LBA), a cylinder / header / sector (CHS) address, a file name, an object identifier, an index section, a universally unique identifier (UUID), a globally unique identifier (GUID), a hash code, a tag, an index entry, a range, an extent, or the like. A logical address does not indicate the physical location of data on a storage medium, but is an abstract reference to the data.

[0059] "Logical Block Address" refers to the value used in a block storage device to associate an address with each of the n logical blocks available for storage of user data throughout the storage media. In some block storage devices, the logical block address (LBA) may range from 0 to n per volume or partition. In a block storage device, each LBA maps directly to a specific data block, and each data block maps to a specific set of physical sectors on the physical storage device media.

[0060] A device driver for the host 110 (and / or storage client 114) may maintain metadata 118 within the storage client 114, such as a logical to physical address mapping structure to map logical addresses of the logical address space 116 to storage locations on the memory die 106. The device driver may be configured to provide storage services to one or more storage clients.

[0061] The storage client 114 may include a flash translation layer 120 and an address mapping table 122. "Flash translation layer" or "logical address to physical address (L2P) translation" refers to logic in a flash memory device that includes logical to physical address translation that provides an abstraction of logical block addresses used by the storage client and physical block addresses where the storage controller stores data. The logical to physical translation layer maps logical block addresses (LBAs) of data stored on a non-volatile storage medium to physical addresses. This mapping allows data to be referenced in a logical address space using a logical identifier, such as a logical block address. The logical identifier does not indicate the physical location of the data on the solid-state storage medium, but is an abstract reference to the data.

[0062] Flash translation layer 120 receives processed data and one or more control signals to determine the flash translation layer queue depth. Flash translation layer 120 can interact with address mapping table 122 through control signals to determine the appropriate physical address to send data and commands to memory die 106 and volatile memory. In one embodiment, flash translation layer 120 also receives data output from memory die 106.

[0063] An "address mapping table" refers to a data structure that associates a logical block address with a physical address of data stored on a non-volatile memory array. The table may be implemented as an index, a map, a b-tree, a content addressable memory (CAM), a binary tree, and / or a hash table, among others. The address mapping table 122 stores the address locations of blocks of data on the storage device 102 for use by the flash translation layer 120. Specifically, the flash translation layer 120 searches the address mapping table 122 to determine if the logical block address included in the storage command has an entry in the address mapping table 122. If so, the physical address associated with the logical block address is used to direct the storage operation on the memory die 106.

[0064] "Data block" refers to the smallest physical amount of storage space on a physical storage medium that is accessible and / or addressable using storage commands. The physical storage medium may be a volatile memory medium, a non-volatile memory medium, a permanent memory, a non-volatile memory, a flash memory storage medium, a hard disk drive, or the like. Some conventional storage devices divide the physical storage medium into volumes or logical partitions (also referred to as partitions). Each volume or logical partition may contain multiple sectors. One or more sectors are organized into blocks (also referred to as data blocks). In applications such as those related to In some storage systems that interface with operating systems, data blocks are referred to as clusters. In other storage systems, such as those that interface with UNIX, Linux, or similar operating systems, data blocks are simply referred to as blocks. A data block or cluster represents the smallest physical amount of storage space on a storage medium that is managed by a storage controller. A block storage device may associate n data blocks available for user data storage throughout the physical storage medium with logical block addresses (LBAs), numbered from 0 to n. In some block storage devices, the logical block addresses may vary from 0 to n per volume or logical partition. In conventional block storage devices, the logical block address maps directly to one and only one data block.

[0065] A "storage operation" refers to an operation performed on a memory cell to change or obtain a data value that is characteristic of the state of the memory cell. Examples of storage operations include, but are not limited to, reading data from a memory cell (or sensing the state of a memory cell), writing (or programming) data to a memory cell, and / or erasing data stored in a memory cell.

[0066] "Characteristic" refers to any property, trait, quality, or attribute of an object or thing. Examples of characteristics include, but are not limited to, condition, readiness for use, not ready for use, chemical composition, water content, temperature, relative humidity, particle count, data value, contaminant count, and the like.

[0067] In one embodiment, the storage system 100 includes one or more clients connected to one or more hosts 128 via one or more computer networks 130. The host 128 may be a server, a storage controller of a SAN, a workstation, a personal computer, a laptop, a handheld computer, a supercomputer, a computer cluster, a network switch, a router or a home appliance, a database or storage device, a data acquisition or data capture system, a diagnostic system, a test system, a robot, a portable electronic device, a wireless device, or the like. The network 130 may include the Internet, a wide area network ("WAN"), a metropolitan area network ("MAN"), a local area network ("LAN"), a token ring, a wireless network, a fiber channel network, a SAN, a network attached storage ("NAS"), ESCON, or any combination of the like or networks. The network 130 may also include a network from the IEEE 802 family of network technologies, such as Ethernet, token ring, WiFi, WiMax, and the like.

[0068] The network 130 may include servers, switches, routers, cabling, radios, and other devices for facilitating networking of the host 110 or multiple hosts with a host 128 or client. In one embodiment, the storage system 100 includes multiple hosts communicating as peers via the network 130. In another embodiment, the storage system 100 includes multiple storage devices 102 communicating as peers via the network 130. Those skilled in the art will recognize other computer networks including one or more computer networks and related devices having single or redundant connections between one or more clients or other computers and one or more storage devices 102 or one or more storage devices 102 connected to one or more hosts. In one embodiment, the storage system 100 includes two or more storage devices 102 connected to a host 128 instead of a host 110 via the network 130.

[0069] In one embodiment, storage client 114 communicates with storage controller 104 through a host interface including an input / output (I / O) interface. For example, storage device 102 may support the ATA interface standard maintained by the InterNational Committee for Information Technology Standards ("INCITS"), the ATA Packet Data Interface (ATAPacket Interface; "ATAPI") standard, the Small Computer System Interface (Small Computer System Interface; "SCSI") standard, and / or the Fibre Channel standard.

[0070] In one example embodiment, a data block contains eight sectors, and the block is 4KB. In some storage systems that interface with operating systems, data blocks are referred to as clusters. In other storage systems, such as those that interface with UNIX, Linux, or similar operating systems, data blocks are simply referred to as blocks. A block or data block or cluster represents the smallest physical amount of storage space on a storage medium that is managed by a storage manager, such as a storage controller, storage system, storage unit, storage device, or the like.

[0071] In some embodiments, the storage controller 104 may be configured to store data on one or more asymmetric write-once storage media, such as solid-state storage memory cells within the memory die 106. As used herein, a "write-once" storage media refers to a storage media that is reinitialized (e.g., erased) each time new data is written or programmed thereon. As used herein, an "asymmetric" storage media refers to a storage media that has different latencies for different storage operations. Many types of solid-state storage media (e.g., memory dies) are asymmetric; for example, a read operation may be much faster than a write / program operation, and a write / program operation may be much faster than an erase operation (e.g., reading a storage media may be hundreds of times faster than erasing, and tens of times faster than programming a storage media).

[0072] The memory die 106 can be divided into memory partitions (e.g., erase blocks) that can be erased as a group, in order to take into account the asymmetric nature of the memory die 106 or the like, in particular. An "erase block" refers to a logical erase block or a physical erase block. In one embodiment, a physical erase block represents the smallest storage unit that can be erased at a given time (e.g., due to the wiring of the storage cells on the memory die) within a given memory die. In one embodiment, a logical erase block represents the smallest storage unit or storage block that can be erased by a storage controller in response to receiving an erase command. In such embodiments, when the storage controller receives an erase command specifying a particular logical erase block, the storage controller can erase each physical erase block within the logical erase block at the same time. It should be noted that the physical erase blocks within a given logical erase block can be considered to be continuous within the physical address space, even if they reside in separate dies. Therefore, the term "continuous" can be applied not only to data stored in the same physical medium, but also to data stored in separate media.

[0073] Thus, modifying a single data segment in-place may require erasing the entire erase block including the data and rewriting the modified data to the erase block along with the original unchanged data. This may result in inefficient write amplification, which may excessively wear out the memory die 106. "Write amplification" refers to the measurement of write / programming operations performed on a non-volatile storage device that specifically cause any data and user data to be written more times than the data was originally written in the first case. In some embodiments, write amplification may count the number of write operations performed by the non-volatile storage device to manage and maintain the data stored on the non-volatile storage device. In other embodiments, write amplification measures the amount of data, the number of bits, the writing of data beyond the data initially stored on the non-volatile storage device.

[0074] Therefore, in some embodiments, the storage controller 104 may be configured to write data offsite. As used herein, writing data "offsite" refers to writing the data to a different media storage location, rather than overwriting the data "in place" (e.g., overwriting the original physical location of the data). Modifying data offsite can avoid write amplification because there is no need to erase and copy existing valid data on the erase block with the data to be modified. In addition, writing data offsite can remove erase from the latency path of many storage operations (e.g., erase latency is no longer part of the critical path of the write operation).

[0075] Managing data blocks by the storage manager specifically includes addressing a specific data block for a read operation, a write operation, or a maintain operation. A block storage device may associate n blocks available for user data storage throughout the storage medium with logical block addresses, numbered from 0 to n. In some block storage devices, the logical addresses may vary from 0 to n per volume or partition.

[0076] In conventional block storage devices, logical addresses are mapped directly to specific data blocks on the physical storage device media. In conventional block storage devices, each data block is mapped to a specific set of physical sectors on the physical storage media. However, some storage devices do not directly or necessarily associate logical addresses with specific physical data blocks. These storage devices may emulate conventional block storage interfaces to maintain compatibility with block storage clients 114.

[0077] In one embodiment, the storage controller 104 provides a block I / O emulation layer that acts as a block device interface or API. In this embodiment, the storage client 114 communicates with the storage device through this block device interface. In one embodiment, the block I / O emulation layer receives commands and logical addresses from the storage client 114 according to this block device interface. Therefore, the block I / O emulation layer provides storage device compatibility with the block storage client 114.

[0078] In one embodiment, the storage clients 114 communicate with the storage controller 104 through a host interface including a direct interface. In this embodiment, the storage devices directly exchange information specific to non-volatile storage devices. "Non-volatile storage device" refers to any hardware, device, component, element, or circuit configured to retain a changeable physical characteristic for representing a binary value of zero or one after the removal of main power. Examples of non-volatile storage devices include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), non-volatile memory media, and the like.

[0079] Storage devices using a direct interface may store data in the memory die 106 using a variety of organizational structures including, but not limited to, blocks, sectors, pages, logical blocks, logical pages, erase blocks, logical erase blocks, ECC code words, logical ECC code words, or any other format or structure that is conducive to the technical characteristics of the memory die 106.

[0080] The storage controller 104 receives logical addresses and commands from the storage clients 114 and performs corresponding operations associated with the memory die 106. The storage controller 104 may support block I / O emulation, direct interface, or both.

[0081] Figure 2 2 shows a non-volatile memory system suitable for implementing certain embodiments. A host system 200 stores data in and retrieves data from a non-volatile storage device 202. The non-volatile storage device 202 may be embedded in the host system 200 or may be in the form of a card or other removable drive, such as a solid state disk (SSD) that is removably connected to the host system 200 through mechanical and electrical connectors. The host system 200 may be any of a number of fixed or portable data generating devices, such as a personal computer, a mobile phone, a personal digital assistant (PDA), or the like. The host system 200 communicates with the storage device via a communication channel 204.

[0082] The non-volatile storage device 202 includes a storage controller 206 and a non-volatile memory 208. Figure 2, the storage controller 206 includes a processor 210 and a controller memory 212. The processor 210 may include a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array, a logic digital circuit, or other logic processing capabilities now known or later developed. The controller memory 212 may include volatile memory and / or non-volatile memory such as random access memory (RAM 214), and processor executable instructions 216 for handling memory management. The RAM 214 may include one or more of any of a variety of types of RAM, such as static RAM (SRAM) or dynamic RAM (DRAM).

[0083] As discussed in more detail below, the non-volatile storage device 202 may include functionality for memory management. In operation, the processor 210 may execute memory management instructions (which may reside in instructions 216) for operation of the memory management function. The memory management function may control the allocation of one or more portions of the non-volatile memory 208 within the non-volatile storage device 202.

[0084] The non-volatile memory 208 may include non-volatile memory media (e.g., flash memory). One or more memory types may be included in the non-volatile memory 208. The memory may include a memory array 108. In an embodiment where the non-volatile memory 208 includes flash memory as the non-volatile memory, the memory array 108 may be composed of the same type of flash memory cells or different types of flash memory cells. For example, the memory array 108 may be composed of both single-level cell (SLC) type flash memory and multi-level cell (MLC) type flash memory with two or more bits per cell capacity to take advantage of the higher write speed of SLC flash memory and the higher density of MLC flash memory. The memory array 108 also encompasses different combinations of flash memory types. In addition, the non-volatile memory 208 may also include volatile memory, such as any of a variety of forms of random access memory (RAM 232).

[0085] The memory array 108 of the non-volatile memory 208 may include physical blocks of flash memory each consisting of a group of pages, wherein a physical block of flash memory (also referred to as an erase block) is a group of pages and a page is the smallest write unit in the memory. The physical blocks in the memory include operation blocks represented as logical blocks for storage clients (e.g., file system 224). The non-volatile storage device 202 may be in the form of a portable flash drive, an integrated solid-state drive, or any of a variety of known flash drive formats. In yet other embodiments, the non-volatile storage device 202 may include only a single type of flash memory with one or more partitions.

[0086] See again Figure 2 , the host system 200 may include a processor 218 that runs one or more applications 220. When data is to be stored in or retrieved from the non-volatile storage device 202, the application 220 communicates with a file system 224 through one or more operating system application programming interfaces (APIs) 222. The file system 224 may be a software module executed on the processor 218 and manages files in the non-volatile storage device 202. The file system 224 manages data clusters in a logical address space. The file system 224 may be a circuit, software, or a combination of circuits and software. Therefore, the file system 224 may be a separate chip or software that can be executed by the processor of the host system 200. The storage device driver 226 on the host system 200 translates instructions from the file system 224 for transmission via the communication channel 204 between the host system 200 and the non-volatile storage device 202. The interface for communicating via the communication channel 204 may be any of a variety of known interfaces, such as SD, MMC, USB storage, SATA, and SCSI interfaces. The host system 200 utilizes a file system data structure to maintain a logical address range of all logical block addresses (LBAs) that have been assigned by the host system 200 to data.

[0087] In addition to user data and host generated file system data structures that may be stored in flash memory on the non-volatile storage device 202, the storage device itself stores and maintains an address mapping table 228, a logical to physical mapping table, or other data structure that tracks the logical addresses supplied by the host file system and the physical addresses of the data held by the storage device. A primary logical to physical mapping table, sometimes referred to as an address mapping table 228, may be stored in the memory array 108. A copy of a portion of the address mapping table 228 may be cached in the RAM 214 of the non-volatile storage device 202 as a mapping table cache 230 for faster access to the logical to physical mapping information. A "mapping table cache" refers to a data structure configured to associate LBAs and / or LBA ranges with physical block addresses and / or physical block address ranges.

[0088] Within the non-volatile storage device 202, the storage controller 206 may act as a processor of the disclosed apparatus. The controller memory 212 may store instructions 216 that, when executed by the storage controller 206, configure the apparatus to receive a first logical address associated with a first read command, wherein a first segment of a mapping table cache 230 includes the first logical address. The non-volatile storage device 202 may further receive a second logical address associated with a second read command, wherein a second segment of the address mapping table 228 includes the second logical address. The storage controller 206 may increase a correlation metric associating the first segment with the second segment in response to the mapping table cache 230 failing to include the second segment and in response to receiving the first logical address before the second logical address. The storage controller 206 may therefore manage the mapping table cache 230 based on the correlation metric.

[0089] Figure 3 A storage device 302 is shown as part of a storage system 300 configured to implement a cache management policy in accordance with the claimed solution. A "cache management policy" refers to a method, rules, and set of requirements for how many cache entries to have, how large to make a cache entry, when to load a cache entry, how many cache entries to load, when and how to evict a cache entry, and the like. In an embodiment, the segments disclosed herein include cache entries. The storage device 302 includes a storage controller 304 and a non-volatile memory 306. The non-volatile memory 306 includes at least one complete copy of user data 308 and an address mapping table 310. In some embodiments, the storage controller 304 may keep a copy of the address mapping table 310 to prevent possible corruption of the data in the address mapping table 310 from occurring. In some embodiments, the address mapping table 310 may also be referred to as a group allocation table (GAT table).

[0090] The storage controller 304 includes a cache manager 312, a volatile memory 314, and an input / output interface 316. The input / output interface 316 receives storage commands from the host and returns data and / or responses to the host for each command. The storage controller 304 services storage commands (e.g., read commands, write commands, storage device 302 maintenance operations) using physical addresses provided by the cache manager 312. The volatile memory 314 is typically limited in size and stores a mapping table cache 318.

[0091] A "storage command" refers to any command serviced by a storage controller, including commands issued by a storage device or host external to the storage controller and any command issued by a component or module internal to the storage controller. Examples of storage commands include (but are not limited to) read commands, write commands, status commands, test mode commands, garbage collection (data migration commands), read scrubbing (update of data values ​​stored in memory cells) commands, and the like. The mapping table cache 318 holds a portion of the data stored in the address mapping table 310 (e.g., a copy of the data organized into cache entries (e.g., sectors)).

[0092] The cache manager 312 handles loading, unloading, and replacing of segments within the mapping table cache 318. Unloading a segment or replacing a segment is called eviction. The cache manager 312 may use certain criteria to determine which segment to evict. The cache manager 312 may use an eviction threshold based on one or more correlation metrics that satisfy the eviction threshold. If the LBA of the segment has a correlation metric that satisfies the eviction threshold, then the segment is evicted from the mapping table cache. "Threshold" refers to a setting above or below which a condition is satisfied or a related event will occur. "Eviction threshold" refers to a threshold that defines a correlation metric so that when the correlation metric is at or below the eviction threshold, the correlation metric satisfies the eviction threshold. In one embodiment, a request for a first LBA followed by a specific second LBA increases the correlation metric by more times. In another embodiment, the correlation metric may only increase if the first LBA is requested by the second LBA within a specific time window.

[0093] The storage controller 304 further includes a volatile memory 314 configured to store a mapping table cache 318 including a set of sectors. The input / output interface 316 is configured to receive a read command including a logical address that uniquely identifies a set of data blocks stored on the non-volatile memory. In one embodiment, the storage device 302 may also include a non-volatile memory 306 consisting of an address mapping table 310 and user data 308.

[0094] Figure 4 One embodiment of an address mapping table 400 is depicted. In one embodiment, the address mapping table 400 may be maintained by the cache manager 312 of the storage controller 304 to map LBAs or other logical addresses to physical locations on the non-volatile memory 306. In the depicted embodiment, the address mapping table 400 is a B-tree having several entries. In the depicted embodiment, the nodes of the address mapping table 400 include direct references to physical locations in the non-volatile memory 306. For example, this is shown in a node 402 having two entries, each entry including an LBA range 404 and a physical block address 406 indicated by a letter designation (i.e., "A" and "M").

[0095] In the illustrated embodiment, LBA range 404 (i.e., "205" to "207") may correspond to a set of logical block addresses identified by consecutive all numbers from "205" to "207". Each of Segment 0 410 and Segment 1 412 includes one or more nodes 402 and thus also includes at least one LBA range 404 representing a portion of the address mapping table 400 stored on the non-volatile memory 306.

[0096] In other embodiments, the address mapping table 400 may include links or the like that map to entries in the reverse mapping. In different embodiments, the address mapping table 400 may or may not be used by the reverse mapping. In other embodiments, the references in the address mapping table 400 may include features of α-values, features of hexadecimal, indicators, links, and the like.

[0097] In the depicted embodiment, address mapping table 400 includes multiple nodes. In the depicted embodiment, each node can store two entries. In other embodiments, each node may be able to store a larger number of entries, and the number of entries at each level can be changed by using or the like with the growth or contraction of address mapping table 400.

[0098] In the depicted embodiment, each entry maps a variable length range of LBAs to a physical location in the non-volatile memory 306. Furthermore, while in the depicted embodiment, the variable length range of LBAs is represented by a starting address and an ending address, in other embodiments, the variable length range of LBAs may be represented by a starting address and a length, or the like. In another embodiment, instead of storing a variable length range of LBAs, the address mapping table 400 may store a single LBA or other logical address in an entry as the starting address for a data value and / or associated metadata.

[0099] In the example shown, the address mapping table 400 is represented by a tree data structure, and a similar tree data structure may be maintained within the cache manager 312 and / or on the non-volatile memory 306. In the tree structure, the node 402 on the left side may include all LBAs that are less than the starting address of the root node 408. For example, the starting LBA in this example is 205 within the range 205 to 207. The root node 408 also includes the LBA range 209 to 212. As shown, each node in the left subtree has an LBA value less than 205 and each node in the right subtree has an LBA value greater than 212.

[0100] Node 402 may store one or more LBA ranges 404. For example, each entry of node 402 may include the shown LBA range 404 and physical block address 406. Cache manager 312 may partition address mapping table 400 into segments, such as segment 0 410 and segment 1 412. Each segment may include one or more LBA ranges that together represent a portion of address mapping table 400 stored on a non-volatile storage medium.

[0101] In one embodiment, the initials 'A' through 'M' may represent logical or physical erase blocks in the non-volatile memory 306 that store data for the corresponding LBA range. A "physical erase block" refers to the smallest unit of storage within a given memory die that can be erased at a given time (e.g., due to the wiring of the storage cells on the memory die). In other embodiments, the initials may represent other physical addresses or locations of the non-volatile memory 306.

[0102] In the depicted embodiment, membership in address mapping table 400 represents membership (or storage) in nonvolatile memory 306. In another embodiment, an entry may further include an indicator of whether nonvolatile memory 306 stores data corresponding to a logical block within the LBA range, reverse-mapped data, and / or other data.

[0103] Figure 5 A mapping table cache 500 according to one embodiment is shown. The mapping table cache 500 may be populated with at least two sections, e.g. Figure 4 410 and segment 1 412 are shown in FIG. Each segment may include at least one logical address, such as an LBA or a range of LBAs; and a corresponding physical address for a block of data stored on the non-volatile storage medium. In one embodiment, a segment includes one or more nodes 402. The cache manager 312 may use the mapping table cache 500 to track the hit rate for the segments within the mapping table cache 500. In one embodiment, the hit rate is a value that is incremented each time an LBA is requested as part of a storage operation and a mapping between the LBA and the physical address is found in the segment. Figure 5 Segment 0 hit rate 502 and segment 1 hit rate 504 are shown.

[0104] In some embodiments, the cache manager 312 may load the segment into the mapping table cache 500 before the LBA referenced in the request segment is requested by the host or received by the cache manager 312. This process of loading the segment before the request receives the LBA of the segment is called prefetching. In one embodiment, the cache manager 312 may prefetch the segment into the mapping table cache 500 based on the relevance metric satisfying a prefetch threshold. "Prefetch threshold" refers to a threshold that defines the relevance metric such that the relevance metric satisfies the prefetch threshold when the relevance metric is at or above the prefetch threshold.

[0105] Additionally or alternatively, the cache manager 312 may evict a segment from the mapping table cache 500 in response to a logical address (e.g., an LBA range) having a correlation metric that satisfies an eviction threshold. The correlation metric is associated with a pair of logical addresses, such as an LBA range. In some embodiments, if the correlation metric is below the eviction threshold, the cache manager 312 may be configured to evict a segment from the mapping table cache 500. In such embodiments, a correlation metric for an LBA range pair that is below the eviction threshold may mean that the correlation between a requested first LBA range followed by a requested second LBA range is low or weak. Thus, when the correlation metric for an LBA range pair is below the eviction threshold, the cache manager 312 may evict a segment that includes the first LBA range in the LBA range pair.

[0106] For example, assume that the coherency metric is an integer and the eviction threshold is an integer, such as 10. When the coherency metric of the LBA range of a segment in the mapping table cache is less than 10, the cache manager 312 evicts that segment.

[0107] In addition, the cache manager 312 may use the correlation metric of the LBA range of the segment to perform other operations. For example, a high correlation metric may indicate a strong correlation or a high correlation. Therefore, the cache manager 312 may configure or adjust the storage controller management table based on one or more correlation metrics of the segments in the mapping table cache.

[0108] In one embodiment, the cache manager 312 may change how the segments are organized and what LBAs are included in the segments based on a correlation metric. For example, the correlation metric indicates how likely it is that a second LBA range will be requested after a first LBA range. If a first LBA range is included in a segment that is in the mapping table cache and a second LBA range is included in a second segment that is not in the mapping table cache, the cache manager 312 may determine that the LBA ranges in each of the two segments should be merged.

[0109] Candidate segments for such combination may be LBA ranges having a correlation metric above a certain threshold. For example, if LBA range A is in segment 0 410 and LBA range B is not in segment 0 410 or segment 1 412, but is instead in segment 4 (not shown) and is stored in address mapping table 310 and LBA range A has a correlation metric of 0.8 on a scale of 0 to 1, then cache manager 312 may merge segment 0 410 and segment 4 into a new segment and store the new segment in mapping table cache 500.

[0110] In another embodiment, the cache manager 312 may change the size of a segment so that it includes more or fewer LBA ranges. For example, if the LBA ranges of all (but one) segments include a correlation metric greater than 0.5 on a scale of 0 to 1, the cache manager 312 may reduce the size of all segments and remove the LBA ranges in a given segment that have a correlation metric less than 0.5 so that the segment only includes LBA ranges that have a correlation metric greater than 0.5. Conversely, the cache manager 312 may increase the segment size so that segments with LBA ranges with higher correlation metrics are stored in the mapping table cache 500.

[0111] In one embodiment, the instructions may configure the storage device to populate the mapping table cache 500 with at least two sectors, such as Segment 0 and Segment 1 as shown. Each sector may include one or more logical addresses, such as LBAs or LBA ranges, corresponding to one or more physical addresses of data blocks stored in the non-volatile storage medium. The mapping table cache 500 may further be used to track the hit rate for each sector in the mapping table cache 500, such as Segment 0 hit rate 502 and Segment 1 hit rate 504 as shown.

[0112] Figure 6 An LBA dependency table 600 is shown according to one embodiment. An "LBA dependency table" refers to a data structure configured to track, record, or monitor a relationship between a first LBA or LBA range and a second LBA or LBA range and a dependency metric indicating the strength or weight of the relationship between the two LBAs or LBA ranges. Those skilled in the art will recognize that an LBA dependency table need not be implemented as only one table structure but may include a variety of data structures, including arrays, lists, databases, files, register sets, table structures including rows and columns, and the like.

[0113] Columns of the LBA dependency table 600 may include a last LBA access 602, a current LBA access 604, and a dependency metric 606. The last LBA access 602 may be the last LBA or LBA range accessed or received for servicing or requested by the host. The current LBA access 604 may be the LBA or LBA range currently being accessed or serviced or requested by the host. The cache manager 312 may use the LBA dependency table 600 to track how often accesses of one LBA or LBA range (e.g., LBA range "A") are followed by accesses of particular other LBAs (e.g., LBA range "B"). The LBA dependency table 600 may also track the reverse order of requests, how often accesses of LBA range "B" are followed by accesses of LBA range "A", and so on. In one embodiment, the dependency metric 606 numerically represents the dependency of "A" accesses followed by "B" accesses, and so on, and may be described below. Figure 7 Describes increments and decrements.

[0114] Each row of LBA dependency table 600 stores a dependency metric for a pair of LBAs, last LBA access 602 and 604. In the example LBA dependency table 600, a pair of LBA "A" followed by LBA "B", LBA "B" followed by LBA "A", and LBA "D" followed by LBA "E" are shown. When referencing a particular row of dependency metrics, the other rows of LBA dependency table 600 each contain a last LBA access 602 and a current LBA access 604, which together are a pair of other logical addresses than the pair of the row of dependency metrics being referenced.

[0115] As in the illustrated embodiment, the correlation metric 606 may be a decimal value between 0 and 1, where a value of 0 indicates no correlation and a value of 1 indicates complete correlation. That is, an LBA pair (e.g., "A" and "B" in the diagram) having a correlation metric 606 of 1 may indicate that every access to LBA "A" is followed by an access to LBA "B." A correlation metric 606 value of 0.10, where accesses to LBA "D" are followed by accesses to LBA "E," may indicate that only 10% of accesses to LBA "D" are followed by accesses to LBA "E."

[0116] In other embodiments, the correlation measures may be calculated using different scales, and some correlation measures may be negative as well as positive.The illustrated embodiment is only an example and is not intended as a limitation of the disclosed solution.

[0117] In one embodiment, the cache manager 312 uses the LBA dependency table 600 to define, organize, and manage segments within the mapping table cache 318. For example, the cache manager 312 may organize the segments so that more LBA ranges with higher dependency metrics are grouped into the same segments. In this manner, the cache manager 312 may associate segments within the mapping table cache 318 using the dependency metric, while the dependency metric directly relates one LBA range (last LBA access 602) to another LBA range (current LBA access 604). For example, the cache manager 312 may organize the segments based on commonality among the values ​​of the dependency metric.

[0118] Figure 7 A read command trace 700 according to one embodiment is shown. The read command trace 700 shown includes four different cases: case 1: accessing B after A within a dependency window 702; case 2, accessing A after B within a dependency window 704; case 3, accessing B after A outside a dependency window 706; and case 4, accessing A after B within an anti-dependency window 708.

[0119] When B is accessed after A within the correlation window 702, the first logical address "A" associated with the first read command and the first segment of the address mapping table may be accessed at time t0, as shown by LBAA access 710. A "correlation window" refers to a time span that includes the receipt of a first logical address X, such as a single logical block address (LBA), a range of LBAs, or a storage command that references the first logical address X, followed by the receipt of a second logical address Y (e.g., a single LBA, a range of LBAs), or the receipt of another storage command that references the second logical address Y, such that in the sequence, the receipt of the first logical address X followed by the receipt of the second logical address Y indicates a sequential relationship between X and Y and the possibility of future repetition. The correlation window may be measured in any unit of time, including nanoseconds, microseconds, seconds, minutes, hours, days, weeks, or the like. A correlation window is a time span that is configured such that two logical addresses received, identified, or requested in a temporal sequence during the correlation window indicates an association or correlation in the sequence of requests for the two logical addresses. Specifically, the order in which the two logical addresses are received may depend on a predicted likelihood that the same two logical addresses will be received, requested or identified in the same order in the future.

[0120] At a later time t1, a second logical address "B" associated with a second read command and a second segment of the address mapping table may be received as an LBAB access 712. When the LBA A access 710 occurs before the LBA B access 712, the correlation metric associating the first segment with the second segment may increase. The first logical address and the second logical address may each be mapped to a physical address within the address mapping table, and the mapping table cache may be configured to store two or more segments, wherein the mapping table cache is managed based on the correlation metric. In one embodiment, an incremental weighting factor may be applied to the correlation metric such that the correlation metric increases in response to the LBA B access 712 occurring within a correlation window 714 spanning both the LBAA access 710 and the LBA B access 712. This is described by Equation 1 below:

[0121] W(A to B): W(A to B)+Δ

[0122] Equation 1

[0123] Where W(A to B) is the relevance metric for LBAA access 710 that occurs directly before LBAB access 712, and Δ is an incremental weighting factor. "Factor" refers to a defined quantity, variable, or formula such that applying the factor to a value or a relationship represented by a value increases or decreases the value. In one embodiment, the value combined with the factor is a relevance metric.

[0124] Factors may also be referred to as weights or weighting factors because their application / combination with a value increases or decreases the magnitude of the value. Where the value represents a relationship, this increase or decrease is analogous to increasing or decreasing the strength, connection, association of a relationship between two things. An "incremental weighting factor" refers to a factor that increases the magnitude of a measure of relevance.

[0125] When A is accessed after B within the correlation window 704, in some embodiments, the correlation metric may be reduced in response to LBA A access 710 occurring at t1 following LBA B access 712 at t0. Reducing the correlation metric may include applying a reduction weighting factor as described by Equation 2 below:

[0126] W(A to B): W(A to B) – Δ / 10

[0127] Equation 2

[0128] Where W(A to B) is the correlation metric of LBA A access 710 occurring directly before LBAB access 712, and Δ / 10 is the reduction weighting factor. "Reducing the weighting factor" refers to a factor that reduces the magnitude of the correlation metric. It should be noted that W(A to B) can be reduced in this manner even if the correlation metric of W(B to A) or LBA B access 712 occurring before LBA A access 710 increases, as shown in access B after A within the correlation window 702 for W(A to B). In some embodiments, the correlation metric can be reduced in response to the mapping table cache failing to include the first segment and in response to LBA B access 712 occurring before LBA A access 710. It should also be noted that reducing the weighting factor can be incorporated into tuning parameters. "Tuning parameters" refers to configurable parameters including weight parameters, segment size, mapping table cache size, size of the sliding lookback window, and the like.

[0129] When B is accessed after A outside of correlation window 706, a zero weighting factor may be applied to the correlation metric so that the correlation metric is unchanged in response to LBA B access 712 at t1 being outside of correlation window 714 as measured from the receipt of LBA A access 710 at t0. A "zero weighting factor" refers to a factor that, when applied to the correlation metric, does not cause a change in the magnitude of the correlation metric. The application of this zero weighting factor may be presented as shown below in Equation 3:

[0130] W(A to B): W(A to B)+0

[0131] Equation 3

[0132] Where A is accessed after B within anti-correlation window 708, in some embodiments, in response to receiving LBAB access 712 at t0 before LBAA access 710 at t1 within anti-correlation window 716 that spans the receipt of LBAB access 712 and LBAA access 710, the correlation metric may be reduced by applying a reducing weighting factor (as shown in Equation 2). The correlation window 714 described previously may be smaller than the anti-correlation window 716 for this case. An "anti-correlation window" refers to a type of correlation window that expresses the relative sequential relationship of two logical addresses as an order of the two logical addresses within the correlation window. Specifically, a "non-correlation window" refers to a time span that includes the receipt of a first logical address X, such as a single logical block address (LBA), a range of LBAs, or the receipt of a storage command that references a first logical address Y, followed by the receipt of a second logical address X (e.g., a single LBA, a range of LBAs), or the receipt of another storage command that references the second logical address X, such that in the sequence, the receipt of the first logical address Y followed by the receipt of the second logical address X represents a decreasing or weakening sequential relationship between logical address X and logical address Y, in which the sequence (X and then Y) has a likelihood of repeating in the future. The non-correlation window can be measured in any time unit, including nanoseconds, microseconds, seconds, minutes, hours, days, weeks, or the like. The non-correlation window is a time span that is configured such that two logical addresses received, identified, or requested in a time sequence during the non-correlation window indicate a decreasing or weakening association or correlation for the relative order of the receipt or request of the two logical addresses. Specifically, the order of receipt of two logical addresses within the anti-correlation window can be predicted based on reducing the likelihood that the same two logical addresses will be received, requested, or identified in a relatively same order in the future.

[0133] Figure 8 A storage device 802 is shown as part of a storage system 800 configured to manage a mapping table cache 816 according to the claimed solution. The storage device 802 includes a storage controller 804 and a non-volatile memory 806. The non-volatile memory 806 includes stored user data 808 and at least one complete copy of an address mapping table 810. In some embodiments, the address mapping table 810 may also be referred to as a group allocation table (GAT table). The storage controller 804 further includes a volatile memory 814 configured to store a mapping table cache 816 including a set of sectors.

[0134] The storage controller 804 includes a cache manager 812, a volatile memory 814, and an input / output interface 818. The input / output interface 818 receives storage commands 824 from the host and returns data and / or responses to the host for each command. The input / output interface 818 may be configured to receive storage commands 824, which include a logical address that uniquely identifies a set of data blocks stored on the non-volatile memory 806, and the storage controller 804 uses the physical address provided by the cache manager 812 to service the storage commands 824 (e.g., read commands 826, write commands 828, storage device maintenance operations, and the like). The volatile memory 814 is typically limited in size and stores a mapping table cache 816. The mapping table cache 816 may include a set of sections 834, each of which includes an address mapping between an LBA 830 and a physical block address 832.

[0135] The cache manager 812 is configured to load segments from the address mapping table 810 in the non-volatile memory 806 into the mapping table cache 816 in the volatile memory 814. The cache manager 812 is configured to store modified segments of the volatile memory 814 mapping table cache 816 in the non-volatile memory 806 address mapping table 810. The cache manager 812 includes a cache segment manager 820 and a cache loader 822.

[0136] "Cache loader" refers to any hardware, software, firmware, circuit, electronic component, module, logic, device, or apparatus that is configured, programmed, designed, arranged, or engineered to load data from a non-volatile storage medium into a cache, where the data may be stored in a volatile storage medium. The cache loader may load data in fixed or variable sized portions or blocks of data. In one embodiment, the cache loader loads data into a cache of fixed size, such as a segment. Additionally or alternatively, in one embodiment, the cache loader may retrieve a non-cache segment from an address mapping table stored on a non-volatile storage medium and load the non-cache segment into the cache. The cache loader 822 is configured to determine cache eviction candidates based on one or more relevance metrics and based on a logical address of a storage command (e.g., a read command or a write command) in response to a cache miss and filling the cache, and is configured to replace the cache eviction candidates in the mapping table cache 816 with a replacement segment that may correspond to the logical address of the storage command. In another embodiment, cache manager 812 may replace cache eviction candidates with replacement segments rather than cache loader 822. In one embodiment, cache loader 822 identifies cache eviction candidates based on one or more relevance metrics of segments that satisfy eviction thresholds.

[0137] "Storage command" refers to any command related to storage operations. Examples of storage commands include (but are not limited to) read commands, write commands, management commands, maintenance commands, diagnostic commands, test mode commands, and any other commands that a storage controller can receive from a host or issue to another component, device, or system. "Read command" refers to a type of storage command that reads data from a memory cell. "Write command" refers to a storage command configured to instruct a recipient to write or store one or more blocks of data on a permanent storage medium, such as a hard drive, a non-volatile storage medium, or the like. A write command may include any storage command that can cause data to be written to the physical storage medium of a storage device. A write command may include enough data to fill one or more data blocks, or a write command may include enough data to fill a portion of one or more data blocks. In one embodiment, a write command includes a count of the number of LBAs of data written to the storage medium, indicating the starting LBA.

[0138] The eviction threshold is a criterion that defines when a segment should be evicted from the mapping table cache. Specifically, in one embodiment, the eviction threshold defines a level above which the relevance metric should be maintained to avoid eviction from the mapping table cache. In a certain embodiment, the eviction threshold is the minimum number of times a segment is referenced by a storage command serviced by the storage device 802 to avoid eviction from the mapping table cache. In other words, in some embodiments, the eviction threshold can be a minimum level that the relevance metric should reach or exceed, otherwise the segment will be evicted from the mapping table cache.

[0139] In the disclosed system, cache segment manager 820 may be configured to manage LBA dependency tables, such as Figure 6 830 corresponding to the plurality of segments 834. The cache loader 822 may be configured to retrieve a non-cached segment 838 from the address mapping table 810 of the non-volatile memory 806 when the non-cached segment 838 has a higher correlation metric than one or more correlation metrics of the resident segment 836 and other segments 834 in the mapping table cache 816. A "non-cached segment" refers to a segment that is not resident in a cache, a non-dependent cache, a primary cache, or a cache layer in a cache hierarchy. A "resident segment" refers to a segment that is stored, loaded, or otherwise occupies a cache and / or cached memory.

[0140] Fig. 9 and Fig.10Additional embodiments of address mapping table 900 and mapping table cache 1000 are depicted. Based on the correlation metric, the cache manager may adjust the segment size, definition and / or composition to improve the performance of the memory device. The cache manager may make these adjustments dynamically "on the fly". For example, Figure 4 The segment 0 410 and segment 1 412 shown in FIG. 4 may be adjusted to form segment 0 902 and segment 1 904, wherein certain LBA ranges (eg, those LBA ranges having similar correlation metrics) are reallocated to the respective LBA ranges. Fig. 9 The new segment 2 906 is shown in FIG.

[0141] This may allow the mapping table cache 1000 to maintain new segments with higher hit rates, which may ensure that highly related address ranges are well represented within the cache. For example, when defined as shown in the address mapping table 400 and mapping table cache 500, segment 0 410 and segment 1 412 may have segment 0 hit rate 502 and segment 1 hit rate 504, respectively. However, the cache manager may determine that differently configured segments may result in segment 2 906 having segment 2 hit rate 1006, which is higher than the segment 0 hit rate 1002 and segment 1 hit rate 1004 for the newly configured segment 0 902 and segment 1 904, respectively.

[0142] In some embodiments, managing the mapping table cache 1000 may include prefetching a segment including a second logical address into the mapping table cache 1000, wherein the correlation metric satisfies a prefetch threshold. The mapping table cache 1000 management may also include evicting a segment from the mapping table cache, the evicted segment including a logical address having a correlation metric that satisfies the eviction threshold. The management of the mapping table cache 1000 may include changing the segment size of the segments of the mapping table cache, such as reducing segment 0 410 to segment 0 902 as reflected in the illustrated address mapping table 400 and address mapping table 900.

[0143] A storage controller management table may be configured based on a correlation metric that associates a logical address with a second logical address. A "storage controller management table" refers to a data structure configured to track, record, or monitor statistics, conditions, and / or settings regarding the operation of a storage controller. Those skilled in the art will recognize that a storage controller management table may include generic names to refer to a variety of data structures, including structures including rows and columns, and may be implemented using a variety of data structures including arrays, lists, databases, files, sets of registers, and the like.

[0144] Examples of storage controller management tables include, but are not limited to, lists of data blocks that are still open or physical or logical erase blocks (i.e., the user can write more data to them without erasing them), or physical or logical erase blocks that have a large number of failed data blocks (i.e., for example, the user deleted something, but the data is still in the block because you can only erase complete blocks and not partial blocks), and the like.

[0145] In some embodiments, the correlation metric may be used to make other storage controller management decisions. At least two segments of the mapping table cache may be merged based on the correlation metric between the first logical address and the second logical address and the correlation metric of a pair of other logical addresses contained in the at least two segments, as reflected by merging segments 0 410 and portions of segment 1 412 to form segment 2 906.

[0146] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as "configured to" perform one or more tasks or operations. This expression of [an entity] configured to [perform one or more tasks] is used herein to refer to a structure (i.e., a physical object such as an electronic circuit). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be referred to as "configured to" perform some tasks even if the structure is not currently being operated. "Credit allocation circuitry configured to allocate credits to multiple processor cores" is intended to cover, for example, an integrated circuit having circuitry that performs such a function during operation, even if the integrated circuit in question is not currently being used (e.g., not connected to a power source). Therefore, an entity described or recited as "configured to" perform some task refers to a physical object, such as a device, a circuit, a memory storing program instructions that can be executed to implement a task, etc. This phrase is not used herein to refer to an intangible object.

[0147] The term “configured to” does not mean “configurable to.” For example, an unprogrammed FPGA would not be considered “configured to” perform some specific function, although it may be “configurable to” perform that function after being programmed.

[0148] The recitation of a structure "configured to" perform one or more tasks in the appended claims is expressly not intended to invoke 35 U.S.C. §112(f) for said claim elements. Thus, claims in this application that do not otherwise include a "means for [performing a function]" structure should not be interpreted under 35 U.S.C. §112(f).

[0149] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on specified factors or on specified factors and other unspecified factors. Consider the phrase "determining A based on B." This phrase specifies B as a factor used to determine A or influence the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover embodiments in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0150] As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, the effect may be responsive to only those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." This phrase specifies B as the factor that triggers the performance of A. This phrase does not exclude that A may also be performed in response to some other factor, such as C. This phrase is also intended to cover embodiments in which A is performed only in response to B.

[0151] As used herein, unless otherwise stated, the terms "first", "second", etc. are used as noun markers preceding them and do not imply any type of order (e.g., spatial, temporal, logical, etc.). For example, in a register set having eight registers, the terms "first register" and "second register" may be used to refer to any two of the eight registers, rather than, for example, just logical registers 0 and 1.

[0152] When used in the claims, the term "or" is used as an inclusive rather than an exclusive or. For example, the phrase "at least one of x, y, or z" means any one of x, y, and z, and any combination thereof.

Claims

1. A method comprising: receiving a first logical address associated with a first read command, the first logical address being associated with a first section of an address mapping table; receiving a second logical address associated with a second read command, the second logical address being associated with a second section of the address mapping table; increasing a correlation metric associating the first logical address with the second logical address in response to receiving the first logical address before the second logical address; wherein the first logical address and the second logical address are each mapped to a physical address within the address mapping table, and a mapping table cache is configured to store two or more segments; as well as managing the mapping table cache using the relevance metric; In response to the correlation metric satisfying a prefetch threshold, prefetching a second segment including the second logical address into the mapping table cache; and The correlation metric is decreased in response to receiving the second logical address prior to the first logical address.

2. The method of claim 1, wherein reducing the correlation metric further comprises: A decreasing weighting factor is applied to the correlation metric such that the correlation metric also decreases in response to determining that the first logical address is received within an anti-correlation window that spans receipt of the first logical address and the second logical address, wherein the anti-correlation window is a time span.

3. The method according to claim 1, further comprising: reducing the correlation metric in response to receiving the second logical address before the first logical address within an anti-correlation window; and wherein increasing the correlation metric further comprises increasing the correlation metric in response to receiving the second logical address within a correlation window, The anti-correlation window is a time span, the correlation window is a time span, and the correlation window is smaller than the anti-correlation window.

4. The method of claim 1 , wherein increasing the correlation metric further comprises: An incremental weighting factor is applied to the correlation metric such that the correlation metric increases in response to receiving the second logical address within a correlation window that spans receipt of the first logical address and the second logical address, wherein the correlation window is a time span.

5. The method of claim 1 , wherein increasing the relevance metric further comprises: A zero weighting factor is applied to the correlation metric such that the correlation metric is unchanged in response to determining that the second logical address is received outside a correlation window measured from receipt of the first logical address, wherein the correlation window is a time span.

6. The method of claim 1 , wherein managing the mapping table cache comprises one of: evict a segment from the mapping table cache, the segment comprising a logical address having the coherency metric satisfying an eviction threshold; changing a segment size of a segment of the mapping table cache; configuring a storage controller management table based on the correlation metric associating the first logical address with the second logical address; as well as At least two sections of the mapping table cache are merged based on the correlation metric between the first logical address and the second logical address and another correlation metric for a pair of other logical addresses contained within the at least two sections of the mapping table cache.

7. The method according to claim 1, further comprising: populating the mapping table cache with at least two sections, each section including a logical address and a corresponding physical address of a data block stored on a non-volatile storage medium; as well as A hit rate for each segment in the mapping table cache is tracked.

8. The method of claim 1, wherein the first logical address and the second logical address comprise logical block addresses (LBAs) and each segment comprises one or more LBA ranges, the one or more LBA ranges together representing a portion of an address mapping table stored on a non-volatile storage medium.

9. A device comprising: processor; as well as a memory storing instructions that, when executed by the processor, configure the device to: receiving a first read command including a first logical address, wherein a first segment of a mapping table cache includes the first logical address; receiving a second read command including a second logical address, wherein a second section of the address mapping table includes the second logical address; increasing a correlation metric correlating the first segment with the second segment in response to the mapping table cache failing to include the second segment and in response to receiving the first read command including the first logical address before receiving a second read command including the second logical address; managing the mapping table cache based on the relevance metric; In response to the correlation metric satisfying a prefetch threshold, prefetching a second segment including the second logical address into the mapping table cache; and The coherency metric is decreased in response to the mapping table cache failing to include the first segment and in response to receiving the second read command including the second logical address prior to receiving the first read command including the first logical address.

10. The apparatus of claim 9, wherein reducing the correlation metric further comprises: A decreasing weighting factor is applied to the correlation metric such that the correlation metric is also decreased in response to determining that the first read command is received within an anti-correlation window that spans receipt of the first read command and the second read command, wherein the anti-correlation window is a time span.

11. The apparatus of claim 9, wherein the instructions further configure the apparatus to: reducing the correlation metric in response to receiving the second read command including the second logical address prior to receiving the first read command including the first logical address within an anti-correlation window, the anti-correlation window spanning receipt of the second read command and the first read command; and wherein increasing the correlation metric further comprises increasing the correlation metric in response to receiving the second read command within a correlation window, the correlation window spanning receipt of the first read command and the second read command, in, The anti-correlation window is a time span, the correlation window is a time span, and the correlation window is smaller than the anti-correlation window.

12. The apparatus of claim 9, wherein increasing the correlation metric further comprises: An incremental weighting factor is applied to the correlation metric such that the correlation metric increases in response to determining that the second read command is received within a correlation window that spans receipt of the first read command and the second read command, wherein the correlation window is a time span.

13. The apparatus of claim 9, wherein increasing the correlation metric further comprises: A zero weighting factor is applied to the correlation metric such that the correlation metric is unchanged in response to determining that the second read command is received outside of a correlation window measured from receipt of the first read command, wherein the correlation window is a time span.

14. The apparatus of claim 9, wherein managing the mapping table cache comprises one of: evicting a segment from the mapping table cache, the segment comprising a logical address having a coherency metric that satisfies an eviction threshold; configuring a storage controller management table based on the correlation metric associating the first logical address with the second logical address; and At least two sections of the mapping table cache are merged based on one or more of the correlation metric between the first logical address and the second logical address and the correlation metric of at least two sections of the mapping table cache.

15. The apparatus of claim 9, wherein the instructions further configure the apparatus to: populating the mapping table cache with at least two segments, each segment comprising one or more logical addresses and corresponding one or more physical addresses of a data block stored on a non-volatile storage medium; and A hit rate for each segment in the mapping table cache is tracked.

16. The apparatus of claim 9, wherein the first logical address and the second logical address comprise logical block addresses (LBAs) and each segment comprises one or more LBA ranges, the one or more LBA ranges together representing a portion of an address mapping table stored on a non-volatile storage medium.

17. A system comprising: a non-volatile memory configured to store an address mapping table; a volatile memory configured to store a mapping table cache comprising a set of sectors, each sector comprising an address mapping between a logical block address (LBA) and a physical block address; an input / output interface configured to receive a storage command including a logical address that uniquely identifies a set of data blocks stored on the non-volatile memory; a cache manager configured to load segments from the address mapping table of the non-volatile memory into the mapping table cache of the volatile memory; a cache segment manager configured to manage an LBA dependency table based on a read command request of an LBA of a segment of a plurality of segments, the LBA dependency table including a dependency metric for each of the plurality of segments; a cache loader configured to retrieve a non-cached segment from the address mapping table of the non-volatile memory in response to the non-cached segment having a higher coherency metric than one or more coherency metrics of resident segments relative to other segments in the mapping table cache; as well as a storage controller configured to service the storage command using a physical address provided by the cache manager; Wherein, the cache loader is further configured to prefetch a second segment including a second logical address into the mapping table cache in response to the correlation metric satisfying a prefetch threshold; and the storage controller is further configured to reduce the correlation metric in response to receiving the second logical address before the first logical address.

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